Heterogeneous integrated Si-SiC MOSFET device and preparation method thereof
By adopting a heterogeneous integrated structure and multi-stage P-zone design in Si-SiC MOSFET devices, the problem of low on-resistance in SiC MOSFET devices is solved, and lower channel resistance and higher voltage withstandability are achieved.
Patent Information
- Application Number
- CN202411222003.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-05-16
AI Technical Summary
The problem of low on-resistance in existing planar SiC MOSFET devices.
The heterogeneously integrated Si-SiC MOSFET device structure is adopted, including substrate, epitaxial layer, P region, JFET region, first N+ region, silicon layer, PN region, gate dielectric layer, gate, source and drain. The channel resistance is reduced through the design of multi-stage P region and PN region.
Effectively reduce the channel resistance of SiC plane MOSFET devices, improve voltage withstandability, and reduce reverse leakage current.
Smart Images
Figure CN120018533A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a heterogeneously integrated Si-SiC MOSFET device and a preparation method thereof. Background Art
[0002] Silicon carbide (SiC) material is a typical representative of the third generation of wide bandgap semiconductor materials. It has a wide bandgap width of 3.26eV, which is three times higher than that of silicon (Si). Therefore, SiC has a higher breakdown electric field strength. Under the same withstand voltage, the thickness of the withstand voltage layer required by the device is thinner, so the chip volume can be made smaller, which is more suitable for the production of high-power devices.
[0003] At present, the current bottleneck of planar gate SiC vertical structure metal oxide semiconductor field effect transistor (MOSFET) is to reduce its on-resistance, which is mainly composed of drift region resistance, JFET resistance and channel resistance. The drift region resistance is the pressure-bearing layer resistance, which is basically fixed, while the JFET resistance accounts for a relatively small proportion. Therefore, the main way to reduce the on-resistance is the channel resistance. The fundamental reason is that the mobility of carriers in 4H-SiC on the (0001) crystal plane is low.
[0004] At present, the main method to solve the channel resistance is to design trench MOSFET devices, but the reliability of the trench gate oxide of trench MOSFET is still a problem that needs to be solved. In 2017, Baoxing Duan proposed a heterogeneous integrated Si / SiCMOSFET structure, which can improve the withstand voltage and reduce the on-resistance compared to Si MOSFET, but there will be a potential barrier when the on-current flows from Si to SiC, and it still has a high on-resistance.
[0005] In view of the current development status of the prior art, the art is currently in urgent need of seeking an effective way to overcome the defect of low on-resistance in existing planar SiCMOSFET devices. The present invention provides a new heterogeneously integrated Si-SiCMOSFET device and a preparation method thereof. Summary of the invention
[0006] Based on the above description, the present invention provides a heterogeneously integrated Si-SiC MOSFET device and a method for preparing the same to solve the problem of low on-resistance in existing planar SiC MOSFET devices.
[0007] The technical solution of the present invention to solve the above technical problems is as follows:
[0008] In a first aspect, the present invention provides a heterogeneously integrated Si-SiC MOSFET device, comprising: a substrate, an epitaxial layer, a P region, a JFET region, a first N+ region, a silicon layer, a PN region, a gate dielectric layer, a gate, a source and a drain;
[0009] The epitaxial layer, the silicon layer, the gate dielectric layer and the gate are sequentially stacked on the substrate;
[0010] The P region, the JFET region and the N+ region are formed on one side of the epitaxial layer away from the substrate, wherein two P regions are formed at two side regions of the epitaxial layer, and any one of the P regions is in a step shape; the JFET region is located between the two P regions, and the first N+ region is formed in a partial region of the JFET region and is arranged close to the silicon layer;
[0011] The two PN regions are formed in the left and right side regions of the silicon layer, corresponding to the positions of the two P regions respectively; wherein any one of the PN regions includes a second N+ region, a P+ region and a P-well region, the second N+ region and the P+ region are arranged in the upper region of the P-well region and close to the outside, wherein the P+ region is located at the edge; the width of the P-well region is smaller than the width of the P region.
[0012] The bottom of the source contacts the second N+ region and the P+ region, and the drain is formed at the bottom of the substrate.
[0013] Based on the above technical solution, the present invention can also be improved as follows.
[0014] Furthermore, the source electrode is arranged on both sides of the gate electrode;
[0015] Bottom portions of both sides of the gate are in contact with two of the second N+ regions respectively.
[0016] Furthermore, the P region has a multi-step structure, and the width thereof decreases from top to bottom.
[0017] Furthermore, the doping concentration of the P region is 1E16 cm -3 ~1E20 cm -3 , the depth is 0.5μm~5μm.
[0018] Furthermore, the doping ion concentration of the JFET region is 5E15 cm -3 ~1E18 cm -3 The ion implantation depth is 0.1 μm to 2 μm deeper than the P region.
[0019] Furthermore, the first N+ region is a high-concentration N+ region with a doping ion concentration of 1E18 cm -3 ~1E21 cm -3 The ion implantation depth is 0.1μm to 2μm.
[0020] Furthermore, the N-type doping ion concentration of the silicon layer is 5E14 cm -3 ~1E18 cm -3 , thickness is 0.1μm~5μm.
[0021] Furthermore, the doping concentration of the second N+ region is 1E17 cm -3 ~1E21 cm -3 The doping concentration of the P-well is 1E16 cm -3 ~1E18 cm -3 The doping concentration of the P+ region is 1E17cm -3 ~1E21 cm -3 .
[0022] Furthermore, the substrate is N+ type SiC; the epitaxial layer is obtained by homogeneous epitaxy of the substrate, and the N-SiC concentration is 5E14at cm -3 ~5E16 at cm -3 ;
[0023] The gate dielectric layer is SiO2, Al2O3 or Hf2O3.
[0024] In a second aspect, the present invention further provides a method for preparing a heterogeneously integrated Si-SiC MOSFET device as described in the first aspect, comprising:
[0025] growing an epitaxial layer on a substrate;
[0026] Injecting multi-level P regions, JFET regions and N+ regions into the epitaxial layer by selective ion implantation, activating at high temperature, and protecting the surface with a carbon film;
[0027] Depositing a layer of polysilicon on the surface of the implanted epitaxial layer to obtain a silicon layer;
[0028] Implanting the N+ region, the P+ region and the P-well region of the silicon layer respectively, and annealing and activating them to obtain a PN region;
[0029] Fabricate a gate dielectric layer on the surface of the silicon layer, and fabricate a gate on the surface of the gate dielectric layer;
[0030] A source electrode is made at the N+ region and the P+ region on the surface of the silicon layer, and a metal is deposited at the bottom of the substrate to form a drain electrode, thereby obtaining a heterogeneously integrated Si-SiC MOSFET device.
[0031] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:
[0032] The heterogeneously integrated Si-SiC MOSFET device provided by the present invention is formed with a P region, a JFET region and an N+ region, wherein two P regions are formed at intervals on both sides of the epitaxial layer, and any P region is in a stepped shape; the JFET region is located between the two P regions, the first N+ region is formed in a partial region of the JFET region and is arranged close to the silicon layer, and two PN regions are formed at intervals on the left and right sides of the silicon layer, corresponding to the positions of the two P regions respectively; wherein any PN region includes a second N+ region, a P+ region and a P-well region. Compared with the prior art, it has the following beneficial effects:
[0033] (1) The present invention can effectively transfer electrons in Si to SiC, and can effectively reduce the channel resistance of SiC planar MOSFET devices.
[0034] (2) The P region in the epitaxial layer is implanted with deep P, which can better achieve the withstand voltage function and reduce the reverse leakage current effect;
[0035] (3) The P region in the epitaxial layer has a multi-level structure, which can reduce the electric field strength at the bottom corner of the P region and prevent voltage breakdown there. The wider P shielding layer can reduce the electric field strength at the gate oxide, especially the secondary P region can effectively disperse the electric field strength distribution. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 A schematic structural diagram of a heterogeneously integrated Si-SiC MOSFET device provided in an embodiment of the present invention;
[0037] Figure 2 Electric field distribution diagrams of different P shielding layer structures provided by embodiments of the present invention;
[0038] Figure 3 A schematic diagram of the preparation process of a heterogeneously integrated Si-SiC MOSFET device provided in an embodiment of the present invention;
[0039] In the accompanying drawings, the components represented by the reference numerals are listed as follows:
[0040] 1. Substrate;
[0041] 2. Epitaxial layer;
[0042] 3. P zone;
[0043] 4. JFET region;
[0044] 5. The first N+ region;
[0045] 6. Silicon layer;
[0046] 7, PN region; 701, second N+ region; 702, P+ region; 703, P-well region;
[0047] 8. Gate dielectric layer;
[0048] 9. Gate;
[0049] 10. Source;
[0050] 11. Drain. DETAILED DESCRIPTION
[0051] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0052] In the prior art, conventional Si / SiC heterogeneous integrated planar MOSFET devices include:
[0053] Method 1: epitaxially or bond a layer of Si on SiC, prepare CMOS process on the Si layer, and penetrate the P region into SiC, while taking advantage of the high channel mobility of Si and the voltage resistance of SiC to form a heterogeneous integrated MOSFET device. Compared with SiMOSFET, this device has higher voltage resistance and lower on-resistance. Its disadvantage is that since the bandgap width of Si is lower than that of SiC, there will be a potential barrier when the conducting electrons in the device move from Si to SiC, resulting in excessive on-resistance and large switching loss.
[0054] Method 2: Heterogeneous integration of SiC and Si structure. Compared with method 1, the advantages are: a layer of N+ region, namely ETL, is injected into the JFET region in SiC, which mainly reduces the barrier for electrons to enter SiC from Si and reduces the conduction barrier; in addition, the device also has a voltage resistance comparable to that of SiC MOSFET. Its disadvantages are: 1. The increase of ETL leads to an increase in the gate oxide electric field strength in Si, reducing the reliability of the device; 2. The single P region in SiC will be subject to a larger electric field strength.
[0055] The present invention provides a novel heterogeneously integrated Si-SiC MOSFET device.
[0056] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.
[0057] First, as Figure 1 As shown, an embodiment of the present invention provides a heterogeneously integrated Si-SiC MOSFET device, including: a substrate 1, an epitaxial layer 2, a P region 3, a JFET region 4, a first N+ region 5, a silicon layer 6, a PN region 7, a gate dielectric layer 8, a gate 9, a source 10 and a drain 11.
[0058] The epitaxial layer 2 , the silicon layer 6 , the gate dielectric layer 8 and the gate 9 are sequentially stacked on the substrate 1 .
[0059] Preferably, the substrate 1 is 4H-SiC, the epitaxial layer 2 is obtained by homogeneous epitaxy of the substrate 1, and the N-SiC concentration is 5E14at cm -3 ~5E16 at cm -3 .
[0060] The gate dielectric layer 8 is SiO2, Al2O3 or Hf2O3, which is a gate oxide layer, which is prepared by injecting a doped Si surface into a dielectric layer, and has a thickness of 20nm to 200nm.
[0061] A P region 3, a JFET region 4 and a first N+ region 5 are formed on the side of the epitaxial layer 2 away from the substrate 1. The P region 3 is an electric field shielding layer, the N-type JFET region 4 is for reducing the on-resistance, and the first N+ region 5 is an electron tunneling layer.
[0062] Among them, two P regions 3 are formed at two sides of the epitaxial layer 2, and any P region 3 is in a step shape; the JFET region 4 is located between the two P regions 3, and the first N+ region 5 is formed in a partial region of the JFET region 4 and is arranged close to the silicon layer. It should be noted that in the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0063] Among them, the P type of the P region 3 is implanted with Al atoms, and the N type of the N+ region can be implanted with N or P atoms.
[0064] The P region 3 is a multi-step structure, and the width thereof decreases from top to bottom.
[0065] In a specific embodiment, the doping concentration of the P region 3 is 1E16 cm -3 ~1E20 cm -3 , the depth is 0.5μm~5μm. The specific value is not limited and can be set according to actual needs.
[0066] The doping ion concentration of JFET region 4 is 5E15 cm -3 ~1E18 cm -3 The ion implantation depth is 0.1 μm to 2 μm deeper than the P region. The specific value is not limited and can be set according to actual needs.
[0067] The first N+ region 5 is a high-concentration N+ region with a doping ion concentration of 1E18 cm -3 ~1E21 cm -3 , the ion implantation depth is 0.1 μm to 2 μm. The specific value is not limited and can be set according to actual needs.
[0068] Two PN regions 7 are formed in the left and right regions of the silicon layer 6, respectively corresponding to the positions of the two P regions 3; wherein any PN region 7 includes a second N+ region 701, a P+ region 702 and a P-well region 703, wherein the second N+ region 701 and the P+ region 702 are arranged in the upper region of the P-well region 703 and close to the outer side, wherein the P+ region 702 is located at the edge, specifically, as Figure 1 As shown, in the PN region on the left, the second N+ region and the P+ region are located in the upper left area of the P-well region, and the P+ region is located on the left side of the P-well region; in the PN region 7 on the right, the second N+ region 701 and the P+ region 702 are located in the upper right area of the P-well region 703, and the P+ region 702 is located on the right side of the P-well region 703.
[0069] The width of the P-well region 703 is smaller than the width of the P region 3 .
[0070] The bottom of the source 10 contacts the second N+ region 701 and the P+ region 702 , and the drain 11 is formed at the bottom of the substrate 1 .
[0071] Specifically, the source electrode 10 is disposed on both sides of the gate electrode 9 to form an ohmic contact with the silicon layer 6 ; the bottoms of both sides of the gate electrode 9 are in contact with the two second N+ regions 701 , respectively.
[0072] In an optional embodiment, the N-type doping ion concentration of the silicon layer 9 is 5E14 cm -3 ~1E18 cm -3 , the thickness is 0.1μm to 5μm. The specific value is not limited and can be set according to actual needs.
[0073] The silicon layer 9 may be polycrystalline silicon or single crystal silicon.
[0074] Among them, polysilicon can be deposited by PECVD, ALD and other methods to form a layer of polysilicon, or amorphous silicon can be deposited and annealed to form polysilicon. The use of polysilicon MOS structure, compared with single crystal silicon, slightly sacrifices carrier mobility, but compared with heteroepitaxial and H injection stripping processes, its manufacturing cost is greatly reduced and the process is simpler.
[0075] Single crystal silicon can be grown by direct epitaxy or by Smartcut process, that is, by using H implantation, bonding and peeling through Smartcut to obtain a single crystal silicon film.
[0076] The PN region 7 is obtained by ion implantation to dope Si with P and N types. The doping concentration of the second N+ region 701 is 1E17 cm -3 ~1E21 cm -3, the doping concentration of the P-well region 703 is 1E16cm -3 ~1E18 cm -3 , the doping concentration of P+ region 702 is 1E17 cm -3 ~1E21 cm -3 There is no limit on the specific value, just set it according to actual needs.
[0077] Compared with the prior art, the heterogeneously integrated Si-SiC MOSFET device provided in this embodiment has the following beneficial effects:
[0078] (1) The present invention can effectively transfer electrons in Si to SiC, and can effectively reduce the channel resistance of SiC planar MOSFET devices.
[0079] (2) The P region in the epitaxial layer is implanted with deep P, which can better achieve the withstand voltage function and reduce the reverse leakage current effect;
[0080] (3) When using a polysilicon MOS structure, although the carrier mobility is slightly sacrificed compared to single-crystal silicon, its manufacturing cost is greatly reduced and the process is simpler compared to heteroepitaxial and H-injection stripping processes;
[0081] (4) The P region in the epitaxial layer has a multi-level structure, which can reduce the electric field strength at the bottom corner of the P region and prevent voltage breakdown there, such as Figure 2 As shown, a wider P shielding layer can reduce the electric field strength at the gate oxide, especially the secondary P region can effectively disperse the electric field strength distribution.
[0082] In a second aspect, an embodiment of the present invention further provides a method for preparing a heterogeneously integrated Si-SiC MOSFET device, such as Figure 3 As shown, the operation is as follows:
[0083] Step S1: growing an epitaxial layer on a substrate
[0084] Specifically, a conductive SiC substrate is selected, and a homoepitaxial N-SiC layer is used as the epitaxial layer. The N-SiC concentration is 5E14atcm -3 ~5E16 at cm -3 .
[0085] Step S2: Implantation to form P region, JFET region and first N+ region
[0086] Specifically, a multi-level P-type region, a JFET region, and a high-concentration N+ region are selectively implanted on the SiC epitaxial layer by ion implantation, followed by high-temperature activation, and a carbon film is used for surface protection.
[0087] The ion implantation may be a combination of channel implantation and non-channel implantation. The ion doping concentration and thickness of each region are detailed in the structural description of the heterogeneous integrated Si-SiC MOSFET device, which will not be described here.
[0088] Step S3: Deposition of silicon layer
[0089] A layer of N-type polysilicon is deposited on the surface of the implanted epitaxial layer to obtain a polysilicon layer.
[0090] In an optional embodiment, Si can be either polycrystalline silicon or single crystal silicon.
[0091] Polysilicon can be formed by depositing a layer of polysilicon using methods such as PECVD and ALD, or by depositing amorphous silicon and then annealing it to form polysilicon.
[0092] Single crystal silicon can be produced by direct epitaxy or by Smartcut process.
[0093] Step S4: Create PN area
[0094] The silicon layer is implanted into the N+ region, P+ region and P-well region respectively using a mask, and then annealed and activated to obtain the PN region. It should be noted that the width of the P-well region is smaller than that of the P region.
[0095] Step S5: Making a gate dielectric layer
[0096] A gate dielectric layer is formed on the surface of polysilicon.
[0097] Step S6: Making the gate
[0098] A gate is fabricated on the surface of the gate dielectric layer above the P-type doped silicon layer.
[0099] Step S7: Making source and drain
[0100] A source is made on the surface of the N+ region and the P+ region of the silicon layer, and a drain is made at the bottom of the SiC substrate. Both the source and the drain are ohmic contacts.
[0101] Since the preparation method is used to prepare a heterogeneously integrated Si-SiC MOSFET device, the beneficial effects of the heterogeneously integrated Si-SiC MOSFET device are also applicable to the preparation method. The beneficial effects can be referred to the above description of the effects and will not be elaborated here.
[0102] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.
[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A heterogeneously integrated Si-SiC MOSFET device, characterized in that: include: Substrate, epitaxial layer, P region, JFET region, first N+ region, silicon layer, PN region, gate dielectric layer, gate, source and drain; The epitaxial layer, the silicon layer, the gate dielectric layer and the gate are sequentially stacked on the substrate; The P region, the JFET region and the first N+ region are formed on the side of the epitaxial layer away from the substrate, wherein two P regions are formed at two side regions of the epitaxial layer, and any one of the P regions is in a step shape; the JFET region is located between the two P regions, and the first N+ region is formed in a partial region of the JFET region and is arranged close to the silicon layer; The two PN regions are formed in the left and right regions of the silicon layer, respectively corresponding to the positions of the two P regions; wherein any of the PN regions comprises a second N+ region, a P+ region and a P-well region, wherein the second N+ region and the P+ region are arranged in the upper region of the P-well region and close to the outer side, wherein the P+ region is located at the edge; and the width of the P-well region is smaller than the width of the P region; The bottom of the source contacts the second N+ region and the P+ region, and the drain is formed at the bottom of the substrate.
2. The heterogeneously integrated Si-SiC MOSFET device according to claim 1, characterized in that: The source electrode is arranged on both sides of the gate electrode; Bottom portions of both sides of the gate are in contact with two of the second N+ regions respectively.
3. The heterogeneously integrated Si-SiC MOSFET device according to claim 1, characterized in that: The P region is a multi-step structure, and the width thereof decreases from top to bottom.
4. The heterogeneously integrated Si-SiC MOSFET device according to claim 1, characterized in that: The doping concentration of the P region is 1E16 cm -3 ~1E20 cm -3 , the depth is 0.5μm~5μm.
5. The heterogeneously integrated Si-SiC MOSFET device according to claim 4, characterized in that: The doping ion concentration of the JFET region is 5E15 cm -3 ~1E18 cm -3 The ion implantation depth is 0.1 μm to 2 μm deeper than the P region.
6. The heterogeneously integrated Si-SiC MOSFET device according to claim 5, characterized in that: The first N+ region is a high-concentration N+ region with a doping ion concentration of 1E18 cm -3 ~1E21 cm -3 The ion implantation depth is 0.1μm to 2μm.
7. The heterogeneously integrated Si-SiC MOSFET device according to claim 1, characterized in that: The doping ion concentration of the N-type silicon layer is 5E14 cm -3 ~1E18 cm -3 , thickness is 0.1μm~5μm.
8. The heterogeneously integrated Si-SiC MOSFET device according to claim 7, characterized in that: The doping concentration of the second N+ region is 1E17 cm -3 ~1E21 cm -3 The doping concentration of the P-well is 1E16 cm -3 ~1E18 cm -3 The doping concentration of the P+ region is 1E17 cm -3 ~1E21 cm -3 .
9. The heterogeneously integrated Si-SiC MOSFET device according to claim 8, characterized in that: The substrate is N+ type SiC; the epitaxial layer is obtained by homogeneous epitaxy of the substrate, and the N-SiC concentration is 5E14at cm -3 ~5E16 at cm -3 ; The gate dielectric layer is SiO2, Al2O3 or Hf2O3.
10. A method for preparing a heterogeneously integrated Si-SiC MOSFET device as claimed in any one of claims 1 to 9, characterized in that: include: growing an epitaxial layer on a substrate; Injecting multi-level P regions, JFET regions and N+ regions into the epitaxial layer by selective ion implantation, activating at high temperature, and protecting the surface with a carbon film; Depositing a layer of polysilicon on the surface of the implanted epitaxial layer to obtain a silicon layer; Implanting the N+ region, the P+ region and the P-well region of the silicon layer respectively, and annealing and activating them to obtain a PN region; Fabricate a gate dielectric layer on the surface of the silicon layer, and fabricate a gate on the surface of the gate dielectric layer; A source electrode is made at the N+ region and the P+ region on the surface of the silicon layer, and a metal is deposited at the bottom of the substrate to form a drain electrode, thereby obtaining a heterogeneously integrated Si-SiC MOSFET device.