Low-power-consumption MOSFET cellular structure, preparation method and MOSFET device

Abstract

The invention discloses a low-power-consumption MOSFET cellular structure which comprises drain electrode metal and an epitaxial layer located on the upper surface of the drain electrode metal, a U-shaped longitudinal deep groove is formed in the epitaxial layer, a polycrystalline silicon separation gate is arranged in the deep groove, the lower middle portion of the polycrystalline silicon separation gate is wrapped by a thermal oxide layer, and the upper portion of the polycrystalline silicon separation gate is wrapped by a dielectric isolation layer. A dielectric isolation layer is arranged in the deep groove, two opposite grid electrodes are arranged above the dielectric isolation layer, a dielectric layer is filled between the two grid electrodes, a grid oxide layer is arranged between the grid electrodes and the groove wall of the deep groove, the dielectric layer extends to the upper part of the epitaxial layer, and a P-well region, an N + region and a P + region are also arranged in the epitaxial layer. A novel NG structure is adopted, stray capacitance caused by FP can be reduced, charge distribution of a device drift region can be improved, and meanwhile the stray capacitance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a low-power MOSFET cell structure, a preparation method and a MOSFET device. Background Art

[0002] Power MOSFET devices have now become key components in various power management applications, thanks to their simple manufacturing process, high device reliability, high current density, and high cell density. However, as social demand increases, higher requirements are placed on the switching speed, energy consumption, and efficiency of the devices. Therefore, how to improve device performance has become a hot topic in current research. Summary of the invention

[0003] The object of the present invention is to provide a low-power MOSFET cell structure, which effectively reduces the parasitic capacitance of the MOSFET, improves the switching speed of the product, and reduces the power consumption.

[0004] To achieve this purpose, the present invention adopts the following technical scheme: a low-power MOSFET cell structure, the structure includes a drain metal and an epitaxial layer located on the upper surface of the drain metal, a U-shaped longitudinal deep groove is arranged in the epitaxial layer, a polysilicon separation gate is arranged in the deep groove, the middle and lower parts of the polysilicon separation gate are wrapped by a thermal oxide layer, and the upper part is wrapped by a dielectric isolation layer, two back-to-back gates are arranged above the dielectric isolation layer, a dielectric layer is filled between the two gates, a gate oxide layer is arranged between the gate and the groove wall of the deep groove, the dielectric layer extends to the top of the epitaxial layer, and a P-well region, an N+ region and a P+ region are also arranged in the epitaxial layer.

[0005] As a specific implementation, the thickness of the epitaxial layer is 3.1-3.3 μm, the resistivity is 0.17-0.19 Ω·cm, and the epitaxial layer is doped with arsenic at a doping concentration of 3.27-3.78×10 16 cm -3 .

[0006] As a specific implementation manner, the thermal oxide layer and the gate oxide layer are both made of silicon dioxide material, and the dielectric layer is made of borophosphosilicate glass material.

[0007] As a specific implementation manner, the dielectric isolation layer is made of a low-k dielectric material, and the upper surface of the dielectric isolation layer is lower than the height of the trench surface of the deep trench.

[0008] Another object of the present invention is to provide a method for preparing the above-mentioned low-power MOSFET cell structure, comprising the following steps: 1) Prepare a substrate and grow an epitaxial layer on the substrate; 2) A longitudinal deep trench is etched in the cell region of the epitaxial layer, and a U-shaped thermal oxide layer is grown in the deep trench. The thermal oxide layer extends to the upper surface of the epitaxial layer, and a thick layer of polysilicon is deposited on the thermal oxide layer; 3) Using dry etching, the thick polysilicon is etched back to a preset depth to prepare a polysilicon separation gate structure, and the thermal oxide layer of the deep trench sidewall is isotropically etched to expose part of the polysilicon separation gate; 4) depositing a low-k dielectric material in the deep trench and above the thermal oxide layer, wherein the low-k dielectric material extends above the epitaxial layer; 5) Etching back the deposited low-k dielectric material to form a dielectric isolation layer; 6) A gate oxide layer is grown on the dielectric isolation layer and on the side of the deep trench, the gate oxide layer extends to the top of the epitaxial layer, and then a thin polysilicon layer with a thickness of 0.1-0.2 μm is deposited on the gate oxide layer and the dielectric isolation layer, and the thin polysilicon layer is U-shaped; 7) Anisotropic etching of polysilicon is used. The polysilicon in the middle is etched to the bottom to expose the dielectric isolation layer. The remaining polysilicon on both sides forms a narrow gate structure. Finally, the thickness of the narrow gate sidewall is 0.08~0.09μm; 8) Deposit a dielectric layer to fill the deep trench, form a p-well region, N+ region and P+ region on the epitaxial layer through ion implantation, and finally form a drain by thinning the back side of the substrate and evaporating the back side metal.

[0009] As a specific implementation manner, the substrate uses an N-type silicon substrate with a resistivity of 0.0011-0.0012 Ω·cm.

[0010] As a specific implementation, the thickness of the dielectric isolation layer is smaller than the thickness of the thermal oxide layer.

[0011] As a specific implementation manner, the depth of the deep groove is 0.75-0.85 μm.

[0012] As a specific implementation manner, the thickness of the gate oxide layer grown in step 6) is 0.045-0.050 μm.

[0013] The third object of the present invention is to provide a low-power MOSFET device, comprising a plurality of the above-mentioned low-power MOSFET cell structures, wherein the sources of all the cell structures are connected to form the source of the MOSFET device, the drains are connected to form the drain of the MOSFET device, and the gates are connected to form the gate of the MOSFET device.

[0014] Compared with the prior art, the technical solution of the present invention has the following advantages: The low-power MOSFET cell structure proposed in this patent adopts a new NG structure, which can reduce the parasitic capacitance caused by FP, improve the charge distribution in the drift region of the device, and improve the parasitic capacitance. In order to further reduce the parasitic capacitance of the device, an additional low-k dielectric layer (LDL) is introduced between the gate and the FP structure. Different from the complete gate polysilicon electrode structure in traditional MOSFET devices, the polysilicon in the middle of the gate of the NG structure MOSFET device is partially removed to form an NG structure distributed along the gate oxide layer. The NG structure is narrower than the traditional device, but does not affect the normal switching process and turn-on voltage of the gate. In addition, a low-k dielectric layer can be deposited between the gate and the FP structure to replace the oxide layer in the traditional structure to further reduce the parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1a-1g It is a schematic diagram of the device cross section at each step in the process of preparing the low-power MOSFET cell structure of the present invention; Among them: 1. Substrate; 2. Epitaxial layer; 3. Deep trench; 4. Thermal oxide layer; 5. Polysilicon separation gate (thick polysilicon); 6. Dielectric isolation layer; 7. Gate oxide layer; 8. Gate (thin polysilicon layer); 9. Drain metal; 10. P-well region; 11. N+ region; 12. P+ region; 13. Dielectric layer. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific embodiments.

[0017] The present invention provides a low power consumption MOSFET cell structure, see Figure 1g As shown, the structure includes a drain metal 9 and an epitaxial layer 2 located on the upper surface of the drain metal 9, a U-shaped longitudinal deep groove 3 is provided in the epitaxial layer 2, a polysilicon separation gate 5 is provided in the deep groove 3, the middle and lower parts of the polysilicon separation gate 5 are wrapped by a thermal oxide layer 4, and the top is wrapped by a dielectric isolation layer 6, two gates 8 arranged back to back are provided above the dielectric isolation layer 6, a dielectric layer 13 is filled between the two gates 8, a gate oxide layer 7 is provided between the gate 8 and the groove wall of the deep groove 3, the dielectric layer 13 extends to the top of the epitaxial layer, and a P-well region 10, an N+ region 11 and a P+ region 12 are provided in the dielectric layer.

[0018] Here, the thickness of the epitaxial layer 2 is 3.1-3.3 μm, the resistivity is in the range of 0.17-0.19 Ω·cm, and the epitaxial layer 2 is doped with arsenic at a doping concentration of 3.27-3.78×10 16 cm -3The depth of the deep groove 3 is 0.75 to 0.85 μm.

[0019] Here, the thermal oxide layer 4 and the gate oxide layer 7 are both made of silicon dioxide material, and the dielectric layer 13 is made of borophosphosilicate glass material.

[0020] The dielectric isolation layer 6 is made of a low-k dielectric material, and the upper surface of the dielectric isolation layer 6 is located at the height of the groove surface of the deep groove. Here, the low-k dielectric material is a fluorosilicate glass material.

[0021] The method for preparing the above-mentioned low-power MOSFET cell structure comprises the following steps: 1) If Figure 1a As shown, a substrate 1 is prepared, an n-type wafer with a resistivity of 0.0011-0.0012Ω.cm, and an epitaxial layer 2 with a thickness of 3.1-3.3μm is grown on the substrate 1, and the resistivity of the epitaxial layer 2 is 0.18Ω.cm; 2) If Figure 1a As shown, a longitudinal deep groove 3 is etched in the cell region of the epitaxial layer 2, and a U-shaped thermal oxide layer 4 is grown in the deep groove 3. The thermal oxide layer 4 extends to the upper surface of the epitaxial layer 2, and a thick polysilicon layer 5 is deposited on the thermal oxide layer 4; 3) If Figure 1b As shown, dry etching is used to etch back the thick polysilicon 5 to a preset depth to prepare a polysilicon separation gate structure, and the thermal oxide layer 4 on the side wall of the deep trench 3 is isotropically etched to expose part of the polysilicon separation gate 5; 4) If Figure 1c As shown, a low-k dielectric material is deposited in the deep trench 3 and above the thermal oxide layer 4. Here, the low-k dielectric material uses fluorosilicate glass, and the low-k dielectric material extends to above the epitaxial layer 2; 5) If Figure 1d As shown, the deposited low-k dielectric material is etched back to form a dielectric isolation layer 6, and the thickness of the dielectric isolation layer 6 is less than the thickness of the thermal oxide layer 5; 6) If Figure 1f As shown, a gate oxide layer 7 with a thickness of 0.045-0.050 μm is grown on the dielectric isolation layer 6 and on the side of the deep trench 3. The gate oxide layer 7 is made of silicon dioxide material. The gate oxide layer 7 extends to the top of the epitaxial layer 2. Then, a thin polysilicon layer 8 with a thickness of 0.1-0.2 μm is deposited on the gate oxide layer 7 and the dielectric isolation layer 6. The thin polysilicon layer 8 is U-shaped. 7) As shown in FIG. g, anisotropic etching of polysilicon is adopted, the polysilicon in the middle is etched to the bottom to expose the dielectric isolation layer 6, and the remaining polysilicon on both sides forms a narrow gate structure, the etching thickness is 0.2-0.3 μm, and finally the thickness of the narrow gate sidewall is 0.08-0.09 μm; 8) Deposit a dielectric layer 13 to fill the deep trench 3, and form a p-well region 10, an N+ region 11, and a P+ region 12 in the dielectric layer 13 by ion implantation. Here, the dielectric layer 13 uses borophosphosilicate glass material, and finally form a drain by thinning the back side of the substrate and evaporating the back side metal.

[0022] See also Figure 1g As shown, the low-power MOSFET device includes several of the above-mentioned low-power MOSFET cell structures, and the sources of all the cell structures are connected to form the source of the MOSFET device, the drains are connected to form the drain of the MOSFET device, and the gates are connected to form the gate of the MOSFET device. The MOSFET device using the above structure effectively reduces the parasitic capacitance of the MOSFET, improves the switching speed of the product, reduces the power consumption, and makes the product more able to meet the needs of the market.

[0023] The above contents are only preferred embodiments of the present invention. For ordinary technicians in this field, according to the concept of the present invention, there will be changes in the specific implementation methods and application scopes. The content of this specification should not be understood as limiting the present invention.

Claims

1. A low power MOSFET cell structure, characterized in that: The structure includes a drain metal and an epitaxial layer located on the upper surface of the drain metal, a U-shaped longitudinal deep groove is arranged in the epitaxial layer, a polysilicon separation gate is arranged in the deep groove, the middle and lower parts of the polysilicon separation gate are wrapped by a thermal oxide layer, and the upper part is wrapped by a dielectric isolation layer, and two gates arranged back to back are arranged above the dielectric isolation layer, a dielectric layer is filled between the two gates, a gate oxide layer is arranged between the gate and the groove wall of the deep groove, the dielectric layer extends to the top of the epitaxial layer, and a P-well area, an N+ area and a P+ area are also arranged in the epitaxial layer.

2. A low power MOSFET cell structure according to claim 1, characterized in that: The thickness of the epitaxial layer is 3.1-3.3 μm, the resistivity is 0.17-0.19 Ω·cm, and the epitaxial layer is doped with arsenic with a doping concentration of 3.27-3.78×10 16 cm -3 .

3. A low power MOSFET cell structure according to claim 1, characterized in that: The thermal oxide layer and the gate oxide layer are both made of silicon dioxide material, and the dielectric layer is made of borophosphosilicate glass material.

4. A low power MOSFET cell structure according to claim 1, characterized in that: The dielectric isolation layer is made of low-k dielectric material, and the upper surface of the dielectric isolation layer is lower than the groove surface height of the deep groove.

5. A method for preparing a low power MOSFET cell structure according to any one of claims 1 to 4, characterized in that: The following steps are involved: 1) Prepare a substrate and grow an epitaxial layer on the substrate; 2) A longitudinal deep trench is etched in the cell region of the epitaxial layer, and a U-shaped thermal oxide layer is grown in the deep trench. The thermal oxide layer extends to the upper surface of the epitaxial layer, and a thick layer of polysilicon is deposited on the thermal oxide layer; 3) Using dry etching, the thick polysilicon is etched back to a preset depth to prepare a polysilicon separation gate structure, and the thermal oxide layer of the deep trench sidewall is isotropically etched to expose part of the polysilicon separation gate; 4) depositing a low-k dielectric material in the deep trench and above the thermal oxide layer, wherein the low-k dielectric material extends above the epitaxial layer; 5) Etching back the deposited low-k dielectric material to form a dielectric isolation layer; 6) A gate oxide layer is grown on the dielectric isolation layer and on the side of the deep trench, the gate oxide layer extends to the top of the epitaxial layer, and then a thin polysilicon layer with a thickness of 0.1-0.2 μm is deposited on the gate oxide layer and the dielectric isolation layer, and the thin polysilicon layer is U-shaped; 7) Anisotropic etching of polysilicon is used. The polysilicon in the middle is etched to the bottom to expose the dielectric isolation layer. The remaining polysilicon on both sides forms a narrow gate structure. Finally, the thickness of the narrow gate sidewall is 0.08~0.09μm; 8) Deposit a dielectric layer to fill the deep trench, form a p-well region, N+ region and P+ region on the epitaxial layer through ion implantation, and finally form a drain through substrate back thinning and back metal evaporation technology.

6. The method for preparing a low power consumption MOSFET cell structure according to claim 4, characterized in that: The substrate adopts an N-type silicon substrate with a resistivity of 0.0011-0.0012Ω·cm.

7. The method for preparing a low power consumption MOSFET cell structure according to claim 4, characterized in that: The thickness of the dielectric isolation layer is less than the thickness of the thermal oxide layer.

8. The method for preparing a low power consumption MOSFET cell structure according to claim 4, characterized in that: The depth of the deep groove is 0.75~0.85μm.

9. The method for preparing a low power consumption MOSFET cell structure according to claim 4, characterized in that: The thickness of the gate oxide layer grown in step 6) is 0.045-0.050 μm.

10. A low power consumption MOSFET device, characterized in that: It comprises a plurality of low-power MOSFET cell structures as claimed in any one of claims 1 to 3, wherein the sources of all the cell structures are connected to form the source of the MOSFET device, the drains are connected to form the drain of the MOSFET device, and the gates are connected to form the gate of the MOSFET device.

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