Silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) cellular structure with stepped groove, device and preparation method
By adopting a stepped trench structure and an alternate conductivity shielding area in silicon carbide MOSFETs, the problems of low breakdown voltage and high on-resistance of existing MOSFETs are solved, and a higher breakdown voltage and lower on-resistance are achieved, which is suitable for high-frequency switching circuits of new energy vehicles.
Patent Information
- Application Number
- CN202510052512.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-05-16
AI Technical Summary
Existing trench type silicon carbide MOSFETs have problems such as low breakdown voltage and high on-resistance, which is difficult to apply to the high-frequency switching circuit requirements of new energy vehicles.
A silicon carbide MOSFET cell structure with step-type grooves is adopted. By setting three steps on the side wall of the groove and a middle and top shielding area are provided outside the side walls, the alternating structure of the columnar area and the junction area is combined with the alternating structure of the cylindrical area and the junction area, the electric field distribution and electric field compensation are optimized.
It effectively increases the breakdown voltage, reduces the on-resistance, enhances the on-conductivity and voltage withstandability of the MOSFET, reduces the electric field spike phenomenon and the breakdown risk of gate oxygen layer, improves the switching speed and reduces power consumption.
Smart Images
Figure CN120018559A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of silicon carbide MOSFET, and in particular to a silicon carbide MOSFET cell structure with a stepped groove, a device and a preparation method thereof. Background Art
[0002] There are two common types of silicon carbide MOSFETs, planar and trench. Trench MOSFETs are widely studied and applied due to their smaller cell area and higher channel mobility. However, trench MOSFETs in the prior art have defects such as low breakdown voltage and high on-resistance, making them difficult to meet the high-frequency switching circuit requirements of new energy vehicles. Therefore, further increasing the breakdown voltage and reducing the on-resistance have become technical issues that need to be solved urgently. Summary of the invention
[0003] Purpose of the invention: The purpose of the present invention is to provide a silicon carbide MOSFET cell structure, device and preparation method with a stepped groove, which can effectively improve the breakdown voltage and reduce the on-resistance, so as to solve the problems existing in the prior art.
[0004] Technical solution: The silicon carbide MOSFET cell structure with a stepped groove described in the present invention is provided with a drain metal, a substrate, a buffer layer, a drift layer and a current diffusion layer in order from bottom to top, a trench gate is provided in the current diffusion layer and the drift layer, the trench gate includes a stepped groove, a well region is provided on the left side of the groove, a first contact region and a second contact region are provided above the well region, the second contact region is provided on the right side of the first contact region, and a source metal is provided above the first contact region and the second contact region; the side wall of the groove has at least three steps, the lowest step is located at the bottom of the groove side wall, the highest step is located at the top of the groove side wall, and the middle steps are located at the groove side wall. In the middle, a bottom shielding area is provided outside the lowest step, a top shielding area is provided outside the highest step, and a middle shielding area is provided outside each step in the middle; the top shielding area is in parallel contact with the second contact area, and the whole composed of all the middle shielding areas is in parallel contact with the drift layer, the current diffusion layer, and the well area, and the ion concentrations of the bottom shielding area, the middle shielding area, and the top shielding area increase in sequence; the drain metal is connected to the drain, the source metal is connected to the source, and the trench gate is connected to the gate; wherein the substrate, the buffer layer, the drift layer, and the first contact area are all of the first conductivity type, and the current diffusion layer, the well area, the second contact area, the bottom shielding area, the middle shielding area, and the top shielding area are all of the second conductivity type.
[0005] Furthermore, the bottom of the top shielding area is flush with the bottom of the second contact area, and the top of the top shielding area is flush with the top of the groove. In this way, the top shielding area covers the sidewall of the groove more completely, which can further improve the conduction capability and voltage resistance of the MOSFET, reduce the electric field spike phenomenon, and reduce the breakdown risk of the gate oxide layer. In addition, the area of parallel overlap between the top shielding area and the second contact area is the largest, which can further optimize the electric field distribution, reduce the breakdown risk, increase the switching speed, and reduce power consumption.
[0006] Furthermore, the sidewall of the trench has three steps; the trench gate also includes gate polysilicon arranged in the trench, and a gate oxide layer arranged between the trench and the gate polysilicon; the gate oxide layer includes sidewall gate oxide layers arranged on both sides of the gate polysilicon and a bottom gate oxide layer arranged at the bottom of the gate polysilicon, and the thickness of the bottom gate oxide layer is greater than that of the sidewall gate oxide layer. In this way, the channel resistance can be reduced and the conduction efficiency can be improved through the thinner sidewall gate oxide layer; the electric field distribution at the bottom of the trench can be optimized through the thicker bottom gate oxide layer, and the failure of the bottom gate oxide layer caused by electric field concentration can be prevented.
[0007] Furthermore, a columnar region is provided in the drift layer, the columnar region is located below the bottom shielding region and connected to the bottom shielding region, and the columnar region is of the second conductive type. The role of the alternating region structure: Since the conductive types of the columnar region and the drift layer are different, a structure of alternating two conductive type regions is formed, which can form a longitudinal electric field distribution, balance the electric field strength, and avoid breakdown caused by excessive electric field in a single region; and, due to the electric field compensation effect of the alternating region, the doping concentration of the drift region can be reduced while maintaining the withstand voltage, so that the on-resistance of the MOSFET can be effectively reduced, the conduction efficiency can be improved, and the power consumption can be reduced; in addition, the alternating region structure can optimize the dynamic characteristics of the MOSFET, such as reducing the electric field spike and charge distribution, improving the switching response speed, and can also reduce the dynamic switching loss by reducing the dynamic parasitic capacitance and parasitic inductance. The role of the connection between the columnar area and the bottom shielding area: The connection between the columnar area and the bottom shielding area can, first, improve the uniformity of the electric field and avoid breakdown caused by excessive local electric field; second, the connection between the two can provide additional current shielding, especially when the MOSFET is turned off, it can reduce the conduction of the parasitic diode and improve the overall voltage resistance; third, the connection between the two can effectively adjust the threshold voltage to ensure that the MOSFET remains in the off state when needed to prevent leakage current or short circuit; fourth, the connection between the two can also reduce the reverse recovery loss of the parasitic body diode and increase the switching speed, which is particularly suitable for occasions with high switching speed requirements, such as the field of new energy vehicles; fifth, in silicon carbide materials, especially in high voltage situations, lateral stress may cause uneven electric field, and the connection between the columnar area and the bottom shielding area can help disperse the electric field and stress, reducing the risk of MOSFET aging or failure.
[0008] The silicon carbide MOSFET cell structure with a stepped groove of the present invention is provided with a drain metal, a substrate, a buffer layer, a drift layer and a current diffusion layer in order from bottom to top, a trench gate is provided in the current diffusion layer and the drift layer, the trench gate comprises a stepped groove, a well region is provided on the left side of the groove, a contact region is provided above the well region, and a source metal is provided above the contact region; the side wall of the groove has at least three steps, the lowest step is located at the bottom of the groove side wall, the highest step is located at the top of the groove side wall, and the middle steps are located at the groove side wall. In the middle, a top shielding area is provided outside the topmost step, and a middle shielding area is provided outside each step in the middle; the top shielding area is in parallel contact with the contact area, and the whole composed of all the middle shielding areas is in parallel contact with the drift layer, the current diffusion layer, and the well area, and the ion concentrations of the middle shielding area and the top shielding area increase successively; the drain metal is connected to the drain, the source metal is connected to the source, and the trench gate is connected to the gate; wherein the substrate, the buffer layer, the drift layer and the contact area are all of the first conductivity type, and the current diffusion layer, the well area, the middle shielding area and the top shielding area are all of the second conductivity type.
[0009] Furthermore, a bottom shielding area is provided outside the bottommost step, and the ion concentrations of the bottom shielding area, the middle shielding area and the top shielding area increase in sequence; the bottom of the top shielding area is flush with the bottom of the contact area, and the top of the top shielding area is flush with the top of the groove. In this way, the coating of the groove sidewall is more complete, which can further improve the conduction capability and voltage resistance of the MOSFET, reduce the electric field spike phenomenon, and reduce the breakdown risk of the gate oxide layer.
[0010] Furthermore, a columnar region is provided in the drift layer, the columnar region extends from the bottom of the drift layer to below the bottom shielding region and is connected to the bottom shielding region, and the columnar region is of the second conductive type. The role of the alternating region structure: Since the conductive types of the columnar region and the drift layer are different, a structure of alternating two conductive type regions is formed, which can form a longitudinal electric field distribution, balance the electric field strength, and avoid breakdown caused by excessive electric field in a single region; and, due to the electric field compensation effect of the alternating region, the doping concentration of the drift region can be reduced while maintaining the withstand voltage, so that the on-resistance of the MOSFET can be effectively reduced, the conduction efficiency can be improved, and the power consumption can be reduced; in addition, the alternating region structure can optimize the dynamic characteristics of the MOSFET, such as reducing the electric field spike and charge distribution, improving the switching response speed, and can also reduce the dynamic switching loss by reducing the dynamic parasitic capacitance and parasitic inductance. The role of the connection between the columnar area and the bottom shielding area: The connection between the columnar area and the bottom shielding area can, first, improve the uniformity of the electric field and avoid breakdown caused by excessive local electric field; second, the connection between the two can provide additional current shielding, especially when the MOSFET is turned off, it can reduce the conduction of the parasitic diode and improve the overall voltage resistance; third, the connection between the two can effectively adjust the threshold voltage to ensure that the MOSFET remains in the off state when needed to prevent leakage current or short circuit; fourth, the connection between the two can also reduce the reverse recovery loss of the parasitic body diode and increase the switching speed, which is particularly suitable for occasions with high switching speed requirements, such as the field of new energy vehicles; fifth, in silicon carbide materials, especially in high voltage situations, lateral stress may cause uneven electric field, and the connection between the columnar area and the bottom shielding area can help disperse the electric field and stress, reducing the risk of MOSFET aging or failure.
[0011] Furthermore, a junction region is provided in the drift layer, the bottom of the junction region is located at a position of half the height in the drift layer, the top of the junction region is in contact with the bottom of the trench, the bottom of the middle shielding region and the bottom of the current diffusion layer, and the junction region is of the second conductivity type; the trench gate also includes a gate polysilicon arranged in the trench, and a gate oxide layer arranged between the trench and the gate polysilicon; the gate oxide layer includes a sidewall gate oxide layer arranged on both sides of the gate polysilicon and a bottom gate oxide layer arranged at the bottom of the gate polysilicon, and the thickness of the bottom gate oxide layer is greater than the thickness of the sidewall gate oxide layer. In this way, unlike the columnar region extending from the bottom of the drift layer to the bottom of the bottom shielding region, the junction region has only about half the area of the columnar region, forming a "semi-super junction structure", which retains the advantages of the columnar region while simplifying the process and reducing the need for precise charge balance. The thinner sidewall gate oxide layer can reduce the channel resistance and improve the conduction efficiency; the thicker bottom gate oxide layer can optimize the electric field distribution at the bottom of the trench to prevent the failure of the bottom gate oxide layer due to electric field concentration.
[0012] The silicon carbide MOSFET device with stepped grooves described in the present invention includes any one of the silicon carbide MOSFET cell structures with stepped grooves described above.
[0013] The method for preparing the silicon carbide MOSFET cell structure with stepped grooves of the present invention comprises the following steps: sequentially growing a buffer layer and a drift layer on a silicon carbide substrate; Performing multiple ion implantations to form a current diffusion layer, a first contact region, a second contact region, and a well region; Etching to form a stepped trench, wherein the sidewall of the trench has three steps; Ion implantation is performed on the outer side of the lowest step of the trench sidewall to form a bottom shielding region; growing a bottom gate oxide layer at the bottom of the trench; Ion implantation is performed on the outer side of the middle step of the trench sidewall to form a middle shielding area; Growing a sidewall gate oxide layer on both side walls of the trench; Growing gate polysilicon in the trench to form a trench gate; Ion implantation is performed on the outer side of the uppermost step of the trench sidewall to form a top shielding region; Depositing a source metal over the first contact region and the second contact region, wherein the source metal forms an ohmic contact with the first contact region and the second contact region; A drain metal is deposited at the bottom of the substrate.
[0014] Beneficial effects: Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention proposes two silicon carbide MOSFET cell structures with stepped grooves. Based on the same inventive concept, both cell structures completely cover the sidewalls of the grooves through the middle shielding area and the top shielding area, which can effectively improve the conduction capability and voltage resistance of the MOSFET on the one hand, and effectively reduce the electric field spike phenomenon and the breakdown risk of the gate oxide layer on the other hand; the middle shielding areas of the two cell structures are in parallel contact with the drift layer, the current diffusion layer, and the well area, that is, they span the three areas / layers, which helps to optimize the electric field of the entire cell structure, ensure a smooth transition of the electric field between the areas / layers, and avoid electric field spikes and local breakdown risks; in addition, the ion concentrations of the middle shielding area and the top shielding area of the two cell structures are successively increased, so that shielding areas with different concentrations can be formed at different depths, which can optimize the electric field distribution and the breakdown voltage, and improve the reliability of the MOSFET; 2. The first silicon carbide MOSFET cell structure with stepped grooves proposed by the present invention has a top shielding area in parallel contact with the second contact area. Since both are of the second conductivity type, the parallel contact between the two can optimize the electric field distribution, reduce the local electric field strength, reduce the breakdown risk, and improve reliability on the one hand; on the other hand, it can optimize the electrical performance of the body diode, such as reducing the reverse recovery time and the forward voltage drop, thereby effectively improving the switching speed of the MOSFET and reducing the power consumption, and is particularly suitable for occasions with high switching speed requirements, such as the field of new energy vehicles; 3. The second silicon carbide MOSFET cell structure with a stepped groove proposed by the present invention has a contact area of the first conductivity type and a top shielding area of the second conductivity type, which is equivalent to merging another contact area of the second conductivity type with the top shielding area to form a continuous second conductivity type area along the side of the groove. On the one hand, it can reduce the electric field strength in the drift region, prevent premature breakdown, and improve the voltage blocking capability of the MOSFET; on the other hand, it can reduce the reverse recovery charge in the body diode, making the MOSFET more efficient when turned off, and is particularly suitable for occasions with high switching speed requirements, such as the field of new energy vehicles; 4. The preparation method of the silicon carbide MOSFET cell structure with stepped grooves proposed in the present invention performs ion implantation into the bottom shielding area, the middle shielding area and the top shielding area three times instead of implanting ions into the three shielding areas at one time. Such a step-by-step implantation method has the following beneficial effects: (1) Through three step-by-step implantations, the doping concentration and depth of the three shielding areas can be accurately controlled, so that the ion concentration of the shielding areas is more uniform, which helps to optimize the breakdown voltage and improve the reliability of the MOSFET; (2) The three step-by-step implantations can achieve a gradual change in the doping concentration, which helps to smooth the electric field distribution, reduce the risk of hot spots, and improve the performance of the MOSFET under high voltage conditions, while a one-time implantation may produce an uneven electric field and increase local electric field concentration; (3) The more accurate doping profile formed by the three step-by-step implantations helps to optimize the reverse recovery performance of the body diode and ensure that the MOSFET can work normally in high voltage applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is a schematic diagram of the structure of the cell of Example 1 in a specific implementation manner of the present invention; Figure 2 This is a schematic diagram of the structure of a cell according to Example 2 in a specific implementation manner of the present invention; Figure 3 It is a schematic diagram of the structure of the cell of Example 3 in a specific implementation manner of the present invention; Figure 4 It is a schematic diagram of the structure of a cell of Example 4 in a specific implementation manner of the present invention; Figure 5It is a schematic diagram of the structure of the cell of Example 5 in a specific implementation manner of the present invention; Figure 6 It is a schematic diagram of the structure of the cell of Example 6 in the specific implementation manner of the present invention. DETAILED DESCRIPTION
[0016] This specific embodiment discloses a silicon carbide MOSFET cell structure with a stepped trench, and there are 6 embodiments, as follows: Embodiment 1:
[0017] The cell structure of Example 1 is as follows Figure 1 As shown, from bottom to top, a drain metal 120, a substrate 121, a buffer layer 122, a drift layer 123 and a current diffusion layer 124 are provided in sequence, a trench gate 13 is provided in the current diffusion layer 124 and the drift layer 123, the trench gate 13 includes a trench 131 in a stepped shape, a well region 143 is provided on the left side of the trench 131, a first contact region 141 and a second contact region 142 are provided above the well region 143, the second contact region 142 is provided on the right side of the first contact region 141, and a source metal 16 is provided above the first contact region 141 and the second contact region 142.
[0018] The sidewall of the trench 131 has at least three steps, the lowest step is located at the bottom of the sidewall of the trench 131, the highest step is located at the top of the sidewall of the trench 131, and the middle steps are located in the middle of the sidewall of the trench 131. A bottom shielding area 151 is provided outside the lowest step, a top shielding area 153 is provided outside the highest step, and a middle shielding area 152 is provided outside each middle step. The top shielding area 153 is in parallel contact with the second contact area 142, and the whole formed by all the middle shielding areas 152 is in parallel contact with the drift layer 123, the current diffusion layer 124, and the well area 143. The bottom of the top shielding area 153 is flush with the bottom of the second contact area 142, and the top of the top shielding area 153 is flush with the top of the trench 131. The ion concentrations of the bottom shielding area 151, the middle shielding area 152, and the top shielding area 153 increase in sequence.
[0019] The drain metal 120 is connected to the drain 111, the source metal 16 is connected to the source 112, and the trench gate 13 is connected to the gate 113. Among them, the substrate 121, the buffer layer 122, the drift layer 123 and the first contact area 141 are all of the first conductivity type, and the current diffusion layer 124, the well area 143, the second contact area 142, the bottom shielding area 151, the middle shielding area 152 and the top shielding area 153 are all of the second conductivity type. Among them, the first conductivity type can be N-type or P-type, and the second conductivity type is the opposite. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
[0020] like Figure 1As shown, in this embodiment, the sidewall of the trench 131 has three steps. The trench gate 13 also includes a gate polysilicon 132 disposed in the trench 131, and a gate oxide layer 133 disposed between the trench 131 and the gate polysilicon 132. The gate oxide layer 133 includes a sidewall gate oxide layer 1331 disposed on both sides of the gate polysilicon 132 and a bottom gate oxide layer 1332 disposed at the bottom of the gate polysilicon 132, and the thickness of the bottom gate oxide layer 1332 is greater than the thickness of the sidewall gate oxide layer 1331. In this embodiment, the thickness of the sidewall gate oxide layer 1331 is 10-200nm, and the thickness of the bottom gate oxide layer 1332 is 100-1000nm.
[0021] The ion concentration ranges of each part are: Substrate 121: 1×10 18 ~1×10 19 cm -3 ; Buffer layer 122: 1×10 15 ~5×10 17 cm -3 ; Drift layer 123: 5×10 14 ~5×10 16 cm -3 ; Current diffusion layer 124: 1×10 15 ~1×10 16 cm -3 ; First contact area 141: 1×10 19 ~1×10 20 cm -3 ; Second contact area 142: 1×10 18 ~1×10 19 cm -3 ; Well region 143: 1×10 16 ~1×10 18 cm -3 ; Bottom shielding area 151: 1×10 16 ~1×10 17 cm -3 ; Middle shielding area 152: 1×10 17 ~1×10 18 cm -3 ; Top shielding area 153: 1×10 18 ~1×10 19 cm -3 . Embodiment 2:
[0022] The cell structure in Example 2 is based on Example 1 and adds a columnar region 17, such as Figure 2 As shown, a columnar region 17 is provided in the drift layer 123 . The columnar region 17 is located below the bottom shielding region 151 and connected to the bottom shielding region 151 . The columnar region 17 is of the second conductivity type. Embodiment 3:
[0023] The cell structure of Example 3 is as follows Figure 3 As shown, from bottom to top, a drain metal 220, a substrate 221, a buffer layer 222, a drift layer 223 and a current diffusion layer 224 are provided in sequence, a trench gate 23 is provided in the current diffusion layer 224 and the drift layer 223, the trench gate 23 includes a trench 231 with a stepped shape, a well region 242 is provided on the left side of the trench 231, a contact region 241 is provided above the well region 242, and a source metal 26 is provided above the contact region 241.
[0024] The side wall of the trench 231 has at least three steps, the lowest step is located at the bottom of the side wall of the trench 231, the highest step is located at the top of the side wall of the trench 231, and the middle steps are located in the middle of the side wall of the trench 231. A top shielding area 253 is provided outside the highest step, and a middle shielding area 252 is provided outside each middle step. The top shielding area 253 is in parallel contact with the contact area 241, and the whole formed by all the middle shielding areas 252 is in parallel contact with the drift layer 223, the current diffusion layer 224, and the well area 242. The bottom of the top shielding area 253 is flush with the bottom of the contact area 241, and the top of the top shielding area 253 is flush with the top of the trench 231. The ion concentrations of the middle shielding area 252 and the top shielding area 253 increase in sequence.
[0025] The drain metal 220 is connected to the drain 211, the source metal 26 is connected to the source 212, and the trench gate 23 is connected to the gate 213. Among them, the substrate 221, the buffer layer 222, the drift layer 223 and the contact area 241 are all of the first conductivity type, and the current diffusion layer 224, the well area 242, the middle shielding area 252 and the top shielding area 253 are all of the second conductivity type. Among them, the first conductivity type can be N-type or P-type, and the second conductivity type is the opposite. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
[0026] like Figure 3 As shown, in this embodiment, the sidewall of the trench 231 has three steps. The trench gate 23 also includes a gate polysilicon 232 disposed in the trench 231, and a gate oxide layer 233 disposed between the trench 231 and the gate polysilicon 232. The gate oxide layer 233 includes a sidewall gate oxide layer 2331 disposed on both sides of the gate polysilicon 232 and a bottom gate oxide layer 2332 disposed at the bottom of the gate polysilicon 232, and the thickness of the bottom gate oxide layer 2332 is greater than the thickness of the sidewall gate oxide layer 2331. In this embodiment, the thickness of the sidewall gate oxide layer 2331 is 10-200nm, and the thickness of the bottom gate oxide layer 2332 is 100-1000nm.
[0027] The ion concentration ranges of each part are: Substrate 221: 1×1018 ~1×10 19 cm -3 ; Buffer layer 222: 1×10 15 ~5×10 17 cm -3 ; Drift layer 223: 5×10 14 ~5×10 16 cm -3 ; Current diffusion layer 224: 1×10 15 ~1×10 16 cm -3 ; Contact area 241: 1×10 19 ~1×10 20 cm -3 Well region 242: 1×10 16 ~1×10 18 cm -3 ; Middle shielding area 252: 1×10 17 ~1×10 18 cm -3 ; Top shielding area 253: 1×10 18 ~1×10 19 cm -3 . Embodiment 4:
[0028] The cell structure in Example 4 is based on Example 3 and adds a bottom shielding area 251, such as Figure 4 As shown, a bottom shielding area 251 is provided outside the lowest step, and the ion concentrations of the bottom shielding area 251, the middle shielding area 252 and the top shielding area 253 increase in sequence. The ion concentration range of the bottom shielding area 251 is: 1×10 16 ~1×10 17 cm -3 . Embodiment 5:
[0029] The cell structure in Example 5 is based on Example 4 and adds a columnar region 27, such as Figure 5 As shown, a columnar region 27 is provided in the drift layer 223 . The columnar region 27 extends from the bottom of the drift layer 223 to below the bottom shielding region 251 and is connected to the bottom shielding region 251 . The columnar region 27 is of the second conductivity type. Embodiment 6:
[0030] The cell structure in Example 6 is based on Example 3 and adds a junction region 28, such as Figure 6As shown, a junction region 28 is provided in the drift layer 223, the bottom of the junction region 28 is located at half the height of the drift layer 223, the top of the junction region 28 is in contact with the bottom of the groove 231, the bottom of the middle shielding area 252 and the bottom of the current diffusion layer 224, and the junction region 28 is of the second conductivity type.
[0031] This specific embodiment also discloses a silicon carbide MOSFET device with a stepped trench, including any one of the above silicon carbide MOSFET cell structures with a stepped trench.
[0032] This specific embodiment also discloses a method for preparing the cellular structure in Example 1, comprising the following steps: A buffer layer 122 and a drift layer 123 are sequentially grown on a silicon carbide substrate 121; Perform multiple ion implantations to form a current diffusion layer 124 , a first contact region 141 , a second contact region 142 , and a well region 143 ; Etching to form a stepped trench 131, wherein the sidewall of the trench 131 has three steps; Ion implantation is performed on the outer side of the lowest step of the side wall of the trench 131 to form a bottom shielding region 151; Growing a bottom gate oxide layer 1332 at the bottom of the trench 131; Ion implantation is performed on the outer side of the middle step of the side wall of the trench 131 to form a middle shielding region 152; A sidewall gate oxide layer 1331 is grown on both side walls of the trench 131; Growing gate polysilicon 132 in the trench 131 to form a trench gate 13; Ion implantation is performed on the outer side of the topmost step of the side wall of the trench 131 to form a top shielding region 153; Depositing a source metal 16 on the first contact region 141 and the second contact region 142 , the source metal 16 forms an ohmic contact with the first contact region 141 and the second contact region 142 ; Drain metal 120 is deposited at the bottom of substrate 121 .
[0033] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.
Claims
1. A silicon carbide MOSFET cell structure with a stepped trench, characterized in that: A drain metal (120), a substrate (121), a buffer layer (122), a drift layer (123) and a current diffusion layer (124) are sequentially provided from bottom to top; a trench gate (13) is provided in the current diffusion layer (124) and the drift layer (123); the trench gate (13) comprises a trench (131) in a stepped shape; a well region (143) is provided on the left side of the trench (131); a first contact region (141) and a second contact region (142) are provided above the well region (143); The second contact area (142) is arranged on the right side of the first contact area (141), and a source metal (16) is arranged above the first contact area (141) and the second contact area (142); the side wall of the groove (131) has at least three steps, the lowest step is located at the bottom of the side wall of the groove (131), the highest step is located at the top of the side wall of the groove (131), and the middle steps are located in the middle of the side wall of the groove (131); a bottom shielding area (151) is arranged outside the lowest step, and the highest step is located at the top of the side wall of the groove (131). A top shielding region (153) is provided outside, and a middle shielding region (152) is provided outside each step in the middle; the top shielding region (153) is in parallel contact with the second contact region (142), and the whole formed by all the middle shielding regions (152) is in parallel contact with the drift layer (123), the current diffusion layer (124), and the well region (143), and the ion concentrations of the bottom shielding region (151), the middle shielding region (152), and the top shielding region (153) increase in sequence; the drain metal (120) The drain (111) is connected, the source metal (16) is connected to the source (112), and the trench gate (13) is connected to the gate (113); wherein the substrate (121), the buffer layer (122), the drift layer (123) and the first contact area (141) are all of the first conductivity type, and the current diffusion layer (124), the well area (143), the second contact area (142), the bottom shielding area (151), the middle shielding area (152) and the top shielding area (153) are all of the second conductivity type.
2. The silicon carbide MOSFET cell structure with stepped trenches according to claim 1, characterized in that: The bottom of the top shielding region (153) is flush with the bottom of the second contact region (142), and the top of the top shielding region (153) is flush with the top of the groove (131).
3. The silicon carbide MOSFET cell structure with stepped trenches according to claim 1, characterized in that: The side wall of the trench (131) has three steps; the trench gate (13) further comprises a gate polysilicon (132) arranged in the trench (131), and a gate oxide layer (133) arranged between the trench (131) and the gate polysilicon (132); the gate oxide layer (133) comprises a side wall gate oxide layer (1331) arranged on both sides of the gate polysilicon (132) and a bottom gate oxide layer (1332) arranged at the bottom of the gate polysilicon (132); the thickness of the bottom gate oxide layer (1332) is greater than the thickness of the side wall gate oxide layer (1331).
4. The silicon carbide MOSFET cell structure with stepped trenches according to claim 1, characterized in that: A columnar region (17) is provided in the drift layer (123); the columnar region (17) is located below the bottom shielding region (151) and is connected to the bottom shielding region (151); and the columnar region (17) is of the second conductivity type.
5. A silicon carbide MOSFET cell structure with a stepped trench, characterized in that: A drain metal (220), a substrate (221), a buffer layer (222), a drift layer (223) and a current diffusion layer (224) are sequentially provided from bottom to top; a trench gate (23) is provided in the current diffusion layer (224) and the drift layer (223); the trench gate (23) comprises a stepped trench (231); a well region (242) is provided on the left side of the trench (231); a contact region (241) is provided above the well region (242); and a source metal (26) is provided above the contact region (241); the side wall of the trench (231) has at least three steps, the lowest step is located at the bottom of the side wall of the trench (231), the highest step is located at the top of the side wall of the trench (231), a plurality of middle steps are located in the middle of the side wall of the trench (231), a top shielding region (253) is provided outside the highest step, and a plurality of middle steps are provided at the top of the side wall of the trench (231). A middle shielding region (252) is provided outside each step; the top shielding region (253) is in parallel contact with the contact region (241); the whole formed by all the middle shielding regions (252) is in parallel contact with the drift layer (223), the current diffusion layer (224), and the well region (242); the ion concentrations of the middle shielding region (252) and the top shielding region (253) increase in sequence; the drain metal (220) is connected to the drain (211), the source metal (26) is connected to the source (212), and the trench gate (23) is connected to the gate (213); wherein the substrate (221), the buffer layer (222), the drift layer (223), and the contact region (241) are all of the first conductivity type, and the current diffusion layer (224), the well region (242), the middle shielding region (252), and the top shielding region (253) are all of the second conductivity type.
6. The silicon carbide MOSFET cell structure with stepped trenches according to claim 5, characterized in that: A bottom shielding area (251) is provided outside the lowermost step, and the ion concentrations of the bottom shielding area (251), the middle shielding area (252), and the top shielding area (253) increase in sequence; the bottom of the top shielding area (253) is flush with the bottom of the contact area (241), and the top of the top shielding area (253) is flush with the top of the groove (231).
7. The silicon carbide MOSFET cell structure with stepped trenches according to claim 6, characterized in that: A columnar region (27) is provided in the drift layer (223), the columnar region (27) extends from the bottom of the drift layer (223) to below the bottom shielding region (251) and is connected to the bottom shielding region (251), and the columnar region (27) is of the second conductivity type.
8. The silicon carbide MOSFET cell structure with stepped trenches according to claim 5, characterized in that: The drift layer (223) is provided with a junction region (28), the bottom of the junction region (28) is located at a position half the height of the drift layer (223), the top of the junction region (28) is in contact with the bottom of the groove (231), the bottom of the middle shielding region (252) and the bottom of the current diffusion layer (224), and the junction region (28) is of the second conductivity type; the groove gate (23) further comprises a gate polysilicon (232) arranged in the groove (231), and a gate oxide layer (233) arranged between the groove (231) and the gate polysilicon (232); the gate oxide layer (233) comprises a sidewall gate oxide layer (2331) arranged on both sides of the gate polysilicon (232) and a bottom gate oxide layer (2332) arranged at the bottom of the gate polysilicon (232), and the thickness of the bottom gate oxide layer (2332) is greater than the thickness of the sidewall gate oxide layer (2331).
9. A silicon carbide MOSFET device having a stepped trench, characterized in that: The invention comprises a silicon carbide MOSFET cell structure with a stepped trench as claimed in any one of claims 1 to 8.
10. The method for preparing the silicon carbide MOSFET cell structure with stepped trenches according to claim 3, characterized in that: The following steps are involved: A buffer layer (122) and a drift layer (123) are sequentially grown on a silicon carbide substrate (121); Performing multiple ion implantations to form a current diffusion layer (124), a first contact region (141), a second contact region (142), and a well region (143); Etching to form a stepped groove (131), wherein the side wall of the groove (131) has three steps; Performing ion implantation on the outer side of the lowest step of the side wall of the trench (131) to form a bottom shielding region (151); Growing a bottom gate oxide layer (1332) at the bottom of the trench (131); Performing ion implantation on the outer side of the middle step of the side wall of the trench (131) to form a middle shielding region (152); Growing sidewall gate oxide layers (1331) on both side walls in the trench (131); Growing gate polysilicon (132) in the trench (131) to form a trench gate (13); Performing ion implantation on the outer side of the topmost step of the side wall of the trench (131) to form a top shielding region (153); Depositing a source metal (16) above the first contact region (141) and the second contact region (142), wherein the source metal (16) forms an ohmic contact with the first contact region (141) and the second contact region (142); A drain metal (120) is deposited at the bottom of the substrate (121).