Memory controller, memory system including same, and operating method thereof

Abstract

The invention relates to a memory controller, a memory system including the same and an operating method thereof. The memory controller includes: a response buffer configured to store a response provided from the memory device; a congestion monitoring circuit configured to monitor a degree of congestion at an exit port of the memory controller; a priority control circuit configured to adjust a priority of commands based on a degree of congestion at the egress port and a fill level of the response buffer to process a second command corresponding to an internal operation prior to a first command corresponding to an operation requested by the host; and a command generation circuit configured to schedule the first command and the second command according to the priority, and output the scheduled commands to the memory device.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0160616, filed on November 20, 2023, which is hereby incorporated by reference in its entirety. Technical field

[0003] Various embodiments of the present disclosure relate to semiconductor design technologies, and more particularly to a storage system including a memory controller for scheduling commands and issuing commands to a memory device. Background art

[0004] An electronic device for storing data may include a host device and a storage system including a memory device. The host device and the storage system may be connected through various standard interface protocols. With the requirements for high - speed and large - capacity data processing of electronic devices, the high - speed operation of the interface protocol for connecting the host device and the storage system or the interface device adopting the interface protocol becomes increasingly important. Summary of the invention

[0005] Embodiments of the present disclosure relate to a memory controller capable of scheduling commands according to the congestion level of an output port and the filling level of a response buffer, and a storage system including the memory controller.

[0006] According to an embodiment of the present disclosure, a memory controller includes: a response buffer configured to store responses provided from a memory device; a congestion monitoring circuit configured to monitor the congestion level at an output port of the memory controller; a priority control circuit configured to adjust the priority of commands based on the congestion level at the output port and the filling level of the response buffer to process a second command corresponding to an internal operation before a first command corresponding to an operation requested by a host; and a command generation circuit configured to schedule the first command and the second command according to the priority and output the scheduled commands to the memory device.

[0007] According to an embodiment of the present disclosure, a storage system includes: a memory device; and a memory controller configured to: schedule a second command corresponding to an internal operation to be processed before a first command corresponding to an operation requested by a host according to the congestion level at an output port of the storage system and the filling level of a response buffer, the response buffer being configured to store responses provided from the memory device.

[0008] According to an embodiment of the present disclosure, a method for operating a memory controller includes: determining a throughput based on a congestion level at an output port of the memory controller; determining a time window according to the throughput and a filling level of a response buffer storing responses provided by a memory device; and scheduling a second command corresponding to an internal operation and a first command corresponding to an operation requested by a host, while adjusting a priority of the second command according to a comparison result between the time window and an execution time of the second command.

[0009] In addition, according to an embodiment of the present disclosure, a storage system may calculate an available time window according to a congestion level at an output port and a number of responses to be sent to a host device, and perform an internal operation not requested by the host device within the available time window. Therefore, performance can be improved by preemptively executing an internal operation that causes deterioration of quality of service (QoS). BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a data processing system according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram for describing congestion occurring in a data processing system using a CXL interface.

[0012] Figure 3 is a detailed block diagram showing a memory controller according to an embodiment of the present disclosure.

[0013] Figure 4 is a diagram showing Figure 3 a detailed block diagram of a congestion monitoring circuit.

[0014] Figure 5 is for describing Figure 4 a table of backpressure conditions.

[0015] Figure 6 is for describing Figure 4 a flowchart of operations of a congestion monitoring circuit.

[0016] Figure 7 is a diagram showing Figure 3 a detailed block diagram of a priority control circuit.

[0017] Figure 8 is a diagram showing Figure 3 a detailed block diagram of a command generation circuit.

[0018] Figure 9 and Figure 10 are flowcharts for describing operations of a memory controller according to an embodiment of the present disclosure.

[0019] Figure 11 is a block diagram showing a data processing system according to another embodiment of the present disclosure. Detailed Embodiments

[0020] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the present disclosure, the same reference numerals refer to the same components in multiple drawings and embodiments of the present disclosure.

[0021] It can be understood that when an element is referred to as being "coupled" or "connected" to another element, it may mean that the two are directly coupled or electrically connected to each other, and another circuit is inserted therebetween. It should be further understood that the terms "comprising", "including", "having", etc. used in this specification indicate the presence of the described features, numbers, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components and / or combinations thereof. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0022] Figure 1 is a block diagram showing a data processing system 1 according to an embodiment of the present disclosure.

[0023] Referring to Figure 1 , the data processing system 1 may include a host device 300 and a storage system 50.

[0024] The storage system 50 may include a memory controller 100 and a memory device 200. The storage system 50 can store data under the control of the host device 300 (such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, a television, a tablet computer, or an in-vehicle infotainment system). The host device 300 may be an external device of the storage system 50.

[0025] Depending on the host interface as a communication method with the host device 300, the storage system 50 can be manufactured as any one of various types of storage modules. The storage system 50 can be configured using any one of various types of storage modules, such as SSD; multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC; secure digital cards in the form of SD, mini SD, and micro SD; universal serial bus (USB) storage modules, universal flash storage (UFS) devices, personal computer memory card international association (PCMCIA) card-type storage modules, peripheral component interconnect (PCI) card-type storage modules, PCI Express (PCI-E) card-type storage modules, compact flash (CF) cards, smart media cards, and memory sticks.

[0026] The memory device 200 may store data. The memory device 200 may operate under the control of the memory controller 100. The memory device 200 may include a memory cell array that includes a plurality of memory cells storing data. In an embodiment, the memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in or reading data stored in the memory device 200.

[0027] In one embodiment, the memory device 200 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), spin transfer torque RAM (STT-RAM), etc.

[0028] The memory device 200 is configured to receive commands and addresses from the memory controller 100 and access a region selected by an address of the memory cell array. That is, the memory device 200 may perform an operation indicated by a command on the region selected by the address. For example, the memory device 200 may perform a write operation (e.g., a programming operation) to write data to the region selected by the address. During a read operation, the memory device 200 may read data from the region selected by the address.

[0029] The memory controller 100 may control the overall operation of the storage system 50. The memory controller 100 may control the memory device 200 to perform a write operation, a read operation, or other operations according to a request of the host device 300. The memory controller 100 may provide the memory device 200 with commands, addresses, and / or data for performing the operations directly requested from the host device 300. For example, during a write operation, the memory controller 100 may provide the memory device 200 with a write command, an address, and data. During a read operation, the memory controller 100 may provide the memory device 200 with a read command and an address. Additionally, whether or not there is a request from the host device 300, the memory controller 100 may generate commands and addresses by itself and send them to the memory device 200. That is, the memory controller 100 may provide the memory device 200 with commands, addresses, and / or data for performing operations that are not directly requested from the host device 300. For example, whether or not there is a request from the host device 300, the memory controller 100 may generate a write queue flush command for performing a write queue flush operation, a flush command for performing a flush operation, and an erase-write command for performing an erase-write operation.

[0030] The host device 300 may communicate with the storage system 50 using a communication standard or protocol, such as Universal Serial Bus (USB), Serial ATA Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Compute Express Link (CXL), Universal Flash Storage (UFS), Secure Digital Card (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low-Rank DIMM (LRDIMM).

[0031] In an embodiment, the host device 300 may communicate with the storage system 50 through a first interface 10. The first interface 10 may be referred to as a host interface. The first interface 10 may include an interface implemented based on the Compute Express Link (CXL) protocol. The CXL protocol may use a serial interface. The memory controller 100 and the memory device 200 may communicate through a second interface 20. The second interface 20 may include an interface implemented based on the Dual In-line Memory Module (DIMM) protocol. The second interface 20 may be referred to as a memory interface.

[0032] In the case of a data processing system that supports a CXL interface, multiple host devices and multiple logical devices (i.e., storage systems) may be coupled to each other through the CXL interface.

[0033] Figure 2 It is a diagram for describing congestion occurring in the data processing system 1A using the CXL interface.

[0034] Referring to Figure 2 , the data processing system 1A may include multiple host devices 300A, 300B, 300C, and 300D and multiple storage systems 50A, 50B, 50C, 50D, and 50E. The multiple host devices 300A, 300B, 300C, and 300D and the multiple storage systems 50A, 50B, 50C, 50D, and 50E may be coupled through a network fabric 60. The multiple host devices 300A, 300B, 300C, and 300D may correspond to the Figure 1 host device 300, and each of the multiple storage systems 50A, 50B, 50C, 50D, and 50E may correspond to the Figure 1 storage system 50. The network fabric 60 may also be referred to as a CXL switch.

[0035] The network fabric 60 may include the infrastructure of a computer network that provides communication between network devices. The network fabric 60 may provide a scalable and flexible framework for forming a network by interconnecting several devices such as switches, routers, and servers. The network fabric 60 may determine the data transmission method and the overall operation of the network. The configuration and operation of the network fabric 60 may affect the performance, scalability, and reliability of the network. According to an embodiment, the network fabric 60 may provide high-speed data transmission, efficient use of network resources, and robust error handling and recovery mechanisms. For example, the network fabric 60 may couple the multiple host devices 300A, 300B, 300C, and 300D to the multiple storage systems 50A, 50B, 50C, 50D, and 50E through the CXL interface.

[0036] As Figure 2 shown, the data corresponding to multiple host devices may be stored in one storage system, and the data corresponding to one host device may be distributed and stored in multiple storage systems. For example, the data corresponding to the first to third host devices 300A, 300B, and 300C may be stored in the second storage system 50B. The data corresponding to the first host device 300A may be distributed and stored in the first storage system 50A and the second storage system 50B.

[0037] Multiple storage systems 50A, 50B, 50C, 50D, and 50E can send a response signal RSP notifying the completion of a read operation or a write operation to a host device that requests a read operation or a write operation through an out-port E_P. For example, the first storage system 50A and the second storage system 50B can send a response signal RSP notifying the completion of the requested operation to the first host device 300A. In this case, due to the response signals RSP sent from the first storage system 50A and the second storage system 50B, a bottleneck occurs in the in-port I_P of the first host device 300A. The first host device 300A performs backpressure (i.e., backpressure conversion) on the first storage system 50A and the second storage system 50B due to the bottleneck, which may cause congestion at the out-port E_P of each storage system.

[0038] Next, a memory controller capable of scheduling commands based on the congestion level of an out-port according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0039] Figure 3 is a detailed block diagram showing a memory controller 100 according to an embodiment of the present disclosure.

[0040] Referring to Figure 3 , the memory controller 100 may include a response buffer 110, a transmitter 120, a congestion monitoring circuit 130, a priority control circuit 140, and a command generation circuit 150.

[0041] The response buffer 110 may store a response ACK provided from a memory device ( Figure 1 200). The response buffer 110 may sequentially output the stored response RESP in response to a ready signal RDY output from the transmitter 120. The ready signal RDY may be a signal indicating that the transmitter 120 is ready to send a response. The response buffer 110 may send a valid signal VD indicating that the response RESP is valid together with the response RESP. In an embodiment of the present disclosure, the response buffer 110 includes a plurality of fields for storing the response ACK respectively, and may output information on the number of fields storing valid responses as a fill level BF_LVL. The fill level BF_LVL may be determined according to the product of the number of fields storing valid responses and the field width of the response buffer 110. According to an embodiment, the memory controller 100 may include a response counter R_CNTR 112, and the response counter R_CNTR 112 generates the fill level BF_LVL by counting the number of fields storing valid responses. Next, a case where both the ready signal RDY and the valid signal VD are signals activated to a logic high level will be described as an example.

[0042] The transmitter 120 can receive the response RESP provided from the response buffer 110 when the valid signal VD is activated, convert the response RESP into a format suitable for the host interface, and send the response signal RSP to the host device 300 through the output port E_P ( Figure 1 of 300). The transmitter 120 can output a ready signal RDY indicating its readiness to send the response. According to an embodiment, the transmitter 120 can receive the congestion level C_LVL from the congestion monitoring circuit 130 and send the response signal RSP to the host device 300, and the response signal RSP incorporates information about the congestion level C_LVL as part of it.

[0043] The congestion monitoring circuit 130 can monitor the degree of congestion at the output port E_P (hereinafter referred to as the congestion degree). The congestion monitoring circuit 130 can calculate the average congestion rate C_AVG and the congestion level C_LVL by tracking the congestion degree at the output port E_P for each monitoring period. The congestion monitoring circuit 130 can calculate the average congestion rate C_AVG by sampling the cases where the backpressure condition has occurred for each monitoring period based on the ready signal RDY and the valid signal VD input to / output from the response buffer 110, and generate the congestion level C_LVL by dividing the calculated average congestion rate C_AVG based on multiple thresholds.

[0044] The priority control circuit 140 can adjust the priority of the commands based on the congestion degree at the output port E_P and the fill level BF_LVL of the response buffer 110 to process the second command corresponding to the internal operation before the first command corresponding to the operation requested by the host. For example, the priority control circuit 140 can generate a priority control signal group P_CTRLG for adjusting the priority according to the average congestion rate C_AVG and the fill level BF_LVL of the response buffer 110. The priority control signal group P_CTRLG can include multiple rate control signals and multiple selection signals for controlling the command generation circuit 150. In an embodiment of the present disclosure, the priority control circuit 140 can calculate the throughput based on the average congestion rate C_AVG and determine the time window according to the fill level BF_LVL of the response buffer 110 and the throughput. The priority control circuit 140 can adjust the priority to process the second command before the first command by increasing the priority of the second command according to the comparison result between the time window and the execution time of the second command.

[0045] The command generation circuit 150 may provide a command CMD to the memory device 200 by scheduling a first command corresponding to an operation requested by the host and a second command corresponding to an internal operation according to a priority control signal group P_CTRLG. In this case, the first command may be a command for performing an operation directly requested from the host device 300 according to a request REQ from the host device 300, and may include, for example, a read command, a write command, etc. On the other hand, the second command may be a command for performing an internal operation that is not directly requested from the host device 300, and may include, for example, a write queue flush command, a flush command, and an erase-write command.

[0046] When a write request is input from the host device 300, the memory controller 100 may send a response signal RSP to the host device 300, then store the corresponding write command in the write queue of the request queue, and perform a delayed write operation by internally scheduling the commands stored in the request queue. Therefore, an improved operation speed can be achieved through the early response characteristic while maintaining reliability. The write queue flush command may be a command for performing a delayed write operation according to the write commands stored in the write queue of the request queue after an early response. The flush command may be a command issued periodically or aperiodically to flush multiple rows of the memory device 200. The erase-write command may be a command for reading data from the memory device 200, checking and correcting errors in the data, and rewriting the error-corrected data to the memory device 200, and may include an erase-write read command and an erase-write write command.

[0047] As described above, in an embodiment of the present disclosure, the memory controller 100 may calculate an average congestion rate C_AVG by monitoring the congestion degree at the out port E_P, schedule a second command corresponding to an internal operation to be processed before a first command corresponding to an operation requested by the host according to the average congestion rate C_AVG and the fill level BF_LVL of the response buffer 110, and provide the scheduled command to the memory device 200.

[0048] Hereinafter, each configuration of the Figure 2 memory controller 100 will be described in detail with reference to the drawings.

[0049] Figure 4 is a diagram showing Figure 3 a detailed block diagram of the congestion monitoring circuit 130. Figure 5 is a table for describing Figure 4 the backpressure conditions.

[0050] Referring to Figure 4 , the congestion monitoring circuit 130 may include a backpressure history buffer 132, an average value calculator 134, and a level determiner 136.

[0051] The backpressure history buffer 132 can store a plurality of sampled signals SAM_B# obtained by sampling the ready signal RDY and the valid signal VD at a preset sampling interval. The backpressure history buffer 132 can generate a sampled signal composed of 2 bits by sampling the logic levels of the ready signal RDY and the valid signal VD at each sampling interval, and sequentially store the sampled signals as the plurality of sampled signals SAM_B#. In this case, the least significant bit LSB of each sampled signal SAM_B# corresponds to the ready signal RDY, and the most significant bit MSB corresponds to the valid signal VD. For example, the sampled signal "01" is a signal generated by sampling the ready signal RDY with a logic high level and the valid signal VD with a logic low level.

[0052] The average value calculator 134 can generate a backpressure count value by counting the number of sampled signals SAM_B# that meet the backpressure condition among the sampled signals input during the monitoring period. As Figure 5 shown, the average value calculator 134 can determine that the sampled signal sampled when the ready signal RDY is deactivated to a logic low level and the valid signal VD is activated to a logic high level (i.e., when the sampled signal is "10") meets the backpressure condition. The monitoring period can be set to an integer multiple of the sampling interval.

[0053] In addition, the average value calculator 134 can generate an average congestion rate C_AVG expressed as a percentage by tracking the backpressure count value for each monitoring period. That is, depending on the congestion level, the average congestion rate C_AVG can have a value between 0 and 1 (or between 0% and 100%). The average value calculator 134 can calculate the average congestion rate C_AVG by averaging the backpressure count value tracked for each monitoring period and the backpressure count value tracked for the previous monitoring period.

[0054] The level determiner 136 can output a congestion level C_LVL composed of one or more bits by dividing the average congestion rate C_AVG based on a plurality of thresholds TH.

[0055] Figure 6 is a flowchart for describing Figure 4 the operation of the congestion monitoring circuit 130.

[0056] Refer to Figure 6, the backpressure history buffer 132 can store a plurality of sampled signals SAM_B# obtained by sampling the ready signal RDY and the valid signal VD at a sampling interval (at S510). For example, when the sampling interval is set to 1 ns, the backpressure history buffer 132 can generate a plurality of sampled signals SAM_B# by sampling the logic levels of the ready signal RDY and the valid signal VD every 1 ns and sequentially storing sampled signals of 2 bits having one of "00", "01", "10", and "11".

[0057] The average value calculator 134 can generate a backpressure count value by counting the number of sampled signals SAM_B# that satisfy the backpressure condition (i.e., "10") during a monitoring period (at S520). For example, if the sampling interval is 1 ns and the monitoring period is set to 100 ns, the average value calculator 134 can receive 100 sampled signals SAM_B# within a 100 ns period and generate a backpressure count value by counting the number of sampled signals of "10" among the 100 sampled signals SAM_B#.

[0058] The average value calculator 134 can generate an average congestion rate C_AVG expressed as a percentage by tracking the backpressure count value for each monitoring period (at S530). For example, the average value calculator 134 can calculate the backpressure count value 10 by counting the number of sampled signals that satisfy the backpressure condition among 100 sampled signals SAM_B# during a first monitoring period, and calculate the congestion rate of the first monitoring period as 0.1 (or 10%). Thereafter, the average value calculator 134 can calculate the backpressure count value 50 by counting the number of sampled signals that satisfy the backpressure condition among 100 sampled signals SAM_B# during a second monitoring period, and calculate the congestion rate of the second monitoring period as 0.5 (or 50%). In this case, the average value calculator 134 can calculate the average congestion rate C_AVG as 0.3 (or 30%) by averaging the congestion rate 0.1 (or 10%) of the first monitoring period and the congestion rate 0.5 (or 50%) of the second monitoring period. In this way, the average value calculator 134 can track the backpressure count value for each monitoring period to generate an average congestion rate C_AVG expressed as a percentage.

[0059] The level determiner 136 may output a congestion level C_LVL by dividing the average congestion rate C_AVG based on multiple thresholds TH (at S540). For example, when setting four thresholds TH of 0.25, 0.5, 0.75, and 1, the level determiner 136 may output the average congestion rate C_AVG between 0 and 0.25 as the congestion level C_LVL of "00", output the average congestion rate C_AVG between 0.25 and 0.5 as the congestion level C_LVL of "01", output the average congestion rate C_AVG between 0.5 and 0.75 as the congestion level C_LVL of "10", and output the average congestion rate C_AVG between 0.75 and 1.0 as the congestion level C_LVL of "11".

[0060] As described above, the congestion monitoring circuit 130 may sample the backpressure situation for each monitoring period based on the ready signal RDY and the valid signal VD, calculate the average congestion rate C_AVG, and output the congestion level C_LVL by classifying the calculated average congestion rate C_AVG according to the threshold.

[0061] Figure 7 is a detailed block diagram showing Figure 3 of the priority control circuit 140.

[0062] Referring to Figure 7 , the priority control circuit 140 may include a window determination circuit 142 and a scheduling control circuit 144.

[0063] The window determination circuit 142 may calculate the throughput based on the average congestion rate C_AVG, and determine the time window T_WIN according to the ratio of the fill level BF_LVL of the response buffer 110 to the throughput.

[0064] The window determination circuit 142 may calculate the throughput based on the average congestion rate C_AVG according to the following [Equation 1]. That is, the throughput may have a value obtained by reducing the average congestion rate C_AVG from the maximum throughput. When the average congestion rate C_AVG is 0.3 and the maximum throughput is 8 GByte / s, the throughput may have a value obtained by reducing 30% from the maximum throughput, that is, the throughput may become 5.6 GB / s.

[0065] [Equation 1]

[0066] Throughput = Maximum throughput * (1 - Average congestion rate)

[0067] In addition, the window determination circuit 142 can determine the time window T_WIN according to the following [Equation 2], based on the ratio of the fill level BF_LVL of the response buffer 110 to the throughput. When the fill level BF_LVL is 7 * 64 bytes and the throughput is 5.6 GB / s, the time window T_WIN can be set to 7 * 64 / 5.6G = 80 ns. When the fill level BF_LVL is large and the throughput is low, that is, when the number of responses to be sent is large and the congestion level is high, the window determination circuit 142 can increase the width of the time window T_WIN. On the other hand, when the fill level BF_LVL is low and the throughput is large, that is, when the congestion level is low and the number of responses to be sent is small, the window determination circuit 142 can decrease the width of the time window T_WIN.

[0068] [Equation 2]

[0069] Time window T_WIN = Fill level BF_LVL * (Field width of the response buffer) / Throughput

[0070] The scheduling control circuit 144 can adjust the priority control signal group P_CTRLG according to the comparison result between the time window T_WIN and the execution time of the second command to increase the priority of the second command.

[0071] According to an embodiment, the scheduling control circuit 144 can arrange the execution times of the second commands in descending order from the longest time to the shortest time, and sequentially compare the arranged execution times with the time window T_WIN to increase the priority of the second commands. When the execution time with the shortest time is equal to or greater than the time window T_WIN, the scheduling control circuit 144 can maintain the priority of the second command without increasing the priority.

[0072] As an example, the execution times increase in the order of the execution time Ta of the erase / write / read or write operation, the execution time Tb of the write queue flush operation, and the execution time Tc of the flush operation, that is, Tc > Tb > Ta. In this case, when the time window T_WIN is greater than the execution time Tc of the flush operation, the scheduling control circuit 144 can increase the priority of the flush command. When the time window T_WIN is equal to or less than the execution time Tc of the flush operation and greater than the execution time Tb of the write queue flush operation, the scheduling control circuit 144 can increase the priority of the write queue flush command. When the time window T_WIN is equal to or less than the execution time Tb of the write queue flush operation and greater than the execution time Ta of the erase / write / read or write operation, the scheduling control circuit 144 can increase the priority of the erase / write / read or write command.

[0073] According to an embodiment, the scheduling control circuit 144 may include a look-up table (LUT) having a plurality of fields obtained by combining the execution times of two or more of the second commands. The scheduling control circuit 144 may increase the priority of the second commands stored in the field corresponding to the time window T_WIN. For example, when 80 ns, which is the sum of the execution time Tb of the write queue flush operation and the execution time Tc of the flush operation, is stored in the first field of the look-up table LUT and a time window T_WIN of 80 ns is input, the scheduling control circuit 144 may increase the priority of both the write queue flush command and the flush command.

[0074] As described above, the priority control circuit 140 may adjust the priority such that, according to the average congestion rate C_AVG and the fill level BF_LVL of the response buffer 110, the second commands corresponding to internal operations are processed before the first commands corresponding to the operations requested by the host.

[0075] Figure 8 is a detailed block diagram of Figure 3 the command generation circuit 150.

[0076] Referring to Figure 8 , the command generation circuit 150 may include a first command generator 151, second command generators 152 and 153, a request queue 154, and an output control circuit 155.

[0077] The first command generator 151 may generate first commands RD and WT in response to a request REQ input from the host device 300. The first command generator 151 may generate a read command RD or a write command WT for performing an operation directly requested by the host device (i.e., the operation requested by the host). That is, the first command generator 151 may be a host command generator.

[0078] The second command generators 152 and 153 may generate second commands ScrRD, ScrWT, and REF on their own regardless of whether there is a request REQ from the host device 300, while adjusting the generation rates of the second commands ScrRD, ScrWT, and REF according to a plurality of rate control signals S_RATE and R_RATE.

[0079] The second command generators 152 and 153 may include a scrub command generator 152 and a flush command generator 153. The scrub command generator 152 may generate a scrub read command ScrRD and a scrub write command ScrWT according to the first rate control signal S_RATE. The flush command generator 153 may generate a flush command REF according to the second rate control signal R_RATE.

[0080] The request queue 154 may include a read queue RD_Q and a write queue WT_Q. The read queue RD_Q may sequentially store a read command RD and a scrub read command ScrRD related to a read operation. The write queue WT_Q may sequentially store a write command WT and a scrub write command ScrWT related to a write operation. In this case, a write queue flush command WT_D for performing a delayed write operation after an early response may also be stored in the write queue WT_Q. That is, the write command WT may be defined as a first command corresponding to an operation requested by a host, and the scrub write command ScrWT and the write queue flush command WT_D may be defined as second commands corresponding to internal operations.

[0081] The output control circuit 155 may schedule the first commands RD and WT, and the second commands ScrRD, ScrWT, REF, and WT_D output from the read queue RD_Q, the write queue WT_Q, and the flush command generator 153 according to a plurality of selection signals R_SEL, W_SEL, RW_SEL, and REF_D.

[0082] The output control circuit 155 may include first to fourth selectors 155A, 155B, 155C, and 155D. The first selector 155A may select and output the read command RD and the scrub read command ScrRD stored in the read queue RD_Q according to the first selection signal R_SEL. The second selector 155B may select and output the write command WT, the write queue flush command WT_D, and the scrub write command ScrWT stored in the write queue WT_Q according to the second selection signal W_SEL. The third selector 155C may select and output one of the outputs of the first selector 155A and the second selector 155B according to the third selection signal RW_SEL. The fourth selector 155D may finally output a command CMD to the memory device 200 by selecting one of the output of the third selector 155C and the flush command REF output from the flush command generator 153 according to the fourth selection signal REF_SEL. That is, the output control circuit 155 may adjust the priorities of the first commands RD and WT and the second commands ScrRD, ScrWT, REF, and WT_D according to the selection signals R_SEL, W_SEL, RW_SEL, and REF_SEL.

[0083] As a reference, the priority control signal group P_CTRLG may include the above rate control signals S_RATE and R_RATE, and selection signals R_SEL, W_SEL, RW_SEL, and REF_SEL. That is, the priority control circuit 140 may generate the rate control signals S_RATE and R_RATE, and the selection signals R_SEL, W_SEL, RW_SEL, and REF_SEL according to the average congestion rate C_AVG and the fill level BF_LVL of the response buffer 110. For example, the priority control circuit 140 may adjust the second rate control signal R_RATE and the fourth selection signal REF_SEL to increase the priority of the refresh command REF. The priority control circuit 140 may adjust the first rate control signal S_RATE and the first selection signal R_SEL to increase the priority of the scratch read command ScrRD, and adjust the first rate control signal S_RATE and the second selection signal W_SEL to increase the priority of the scratch write command ScrWT. The priority control circuit 140 may adjust the first to fourth selection signals R_SEL, W_SEL, RW_SEL, and REF_SEL to increase the priority of the write queue flush command WT_D.

[0084] Figure 9 And Figure 10 is a flowchart for describing the operation of the memory controller 100 according to an embodiment of the present disclosure.

[0085] Referring Figure 9 , the congestion monitoring circuit 130 may calculate the throughput based on the congestion degree at the out port E_P (at S900).

[0086] More specifically, the congestion monitoring circuit 130 may calculate the average congestion rate C_AVG by monitoring the congestion degree at the out port E_P (at S910). The congestion monitoring circuit 130 may calculate the average congestion rate C_AVG by sampling the occurrence of the backpressure condition for each monitoring period based on the ready signal RDY and the valid signal VD input to / output from the response buffer 110.

[0087] The window determination circuit 142 may calculate the throughput based on the average congestion rate C_AVG (at S920). The window determination circuit 142 may calculate the throughput after reducing the average congestion rate C_AVG from the maximum throughput.

[0088] Further, the window determination circuit 142 may determine a time window T_WIN (at S930) based on the fill level BF_LVL of the response buffer 110 and the throughput. When the fill level BF_LVL is large and the throughput is low, that is, when the number of responses to be sent is large and the congestion level is high, the window determination circuit 142 may increase the width of the time window T_WIN. On the other hand, when the fill level F_LVL is low and the throughput is large, that is, the congestion level is low and the number of responses to be sent is small, the window determination circuit 142 may decrease the width of the time window T_WIN.

[0089] The scheduling control circuit 144 may adjust the priority according to the time window T_WIN to increase the priority of the second command corresponding to the internal operation (at S940).

[0090] According to an embodiment, the scheduling control circuit 144 may arrange the execution times of the second commands in descending order from the longest time to the shortest time, and sequentially compare the arranged execution times with the time window T_WIN to increase the priority of the second commands.

[0091] Referring to Figure 10 , when the time window T_WIN is greater than the execution time Tc of the refresh operation (i.e., "Yes" in S941), the scheduling control circuit 144 may increase the priority of the refresh command REF (at S942). For example, the scheduling control circuit 144 may adjust the second rate control signal R_RATE and the fourth selection signal REF_SEL in the priority control signal group P_CTRLG to increase the priority of the refresh command REF.

[0092] When the time window T_WIN is equal to or less than the execution time Tc of the refresh operation (i.e., "No" in S941) and greater than the execution time Tb of the write queue refresh operation (i.e., "Yes" in S943), the scheduling control circuit 144 may increase the priority of the write queue refresh command WT_D (at S944). In this case, the scheduling control circuit 144 may adjust the first to fourth selection signals R_SEL, W_SEL, RW_SEL, and REF_SEL to increase the priority of the write queue refresh command WT_D.

[0093] When the time window T_WIN is equal to or less than the execution time Tb of the write queue flush operation (i.e., "No" in S943) and greater than the execution time Ta of the scrub read or write operation (i.e., "Yes" in S945), the scheduling control circuit 144 can increase the priorities of the scrub read command ScrRD and the scrub write command ScrWT (in S946). In this case, the scheduling control circuit 144 can adjust the first rate control signal S_RATE and the first selection signal R_SEL to increase the priority of the scrub read command ScrRD, and can adjust the first rate control signal S_RATE and the second selection signal W_SEL to increase the priority of the scrub write command ScrWT.

[0094] When the execution time Ta of the scrub read or write operation with the shortest time is equal to or greater than the time window T_WIN (i.e., "No" in S945), the scheduling control circuit 144 can maintain the priority of the second command without increasing the priority.

[0095] According to an embodiment, the scheduling control circuit 144 can include a look-up table (LUT) that has fields obtained by combining the execution times of two or more second commands, and increases the priority of the second command stored in the field corresponding to the time window T_WIN.

[0096] Return reference Figure 9 ., the command generation circuit 150 can schedule the first command corresponding to the operation requested by the host and the second command corresponding to the internal operation according to the priority control signal group P_CTRLG, and output the scheduled commands as command CMD to the memory device 200 (in S950).

[0097] As described above, according to an embodiment of the present disclosure, the memory controller 100 and the storage system 50 including the same can calculate the available time window according to the congestion degree at the out-port and the number of responses to be transmitted to the host device, and perform internal operations that are not requested from the host device within the time window. Therefore, by preemptively executing internal operations (such as flush operations, scrub operations, write queue flush operations, etc.) that cause a decrease in quality of service (QoS), performance can be improved.

[0098] Figure 11 is a block diagram showing a data processing system 1000 according to another embodiment of the present disclosure.

[0099] Reference Figure 11 ., the data processing system 1000 can include a host device 1300 and a storage system 1050. The storage system 1050 can include a memory controller 1100 and a memory device 1200.

[0100] The memory controller 1100 may include a host interface circuit 1120, a link controller 1140, a media controller 1160, and a memory interface circuit 1180.

[0101] The host interface circuit 1120 may communicate with the host device 1300 through the host interface 1010. The host interface circuit 1120 may receive a request REQ from the host device 1300 and provide a corresponding response signal RSP to the host device 1300. The host interface circuit 1120 may send and receive host data HDATA to and from the host device 1300.

[0102] The link controller 1140 may control the host interface circuit 1120 to communicate with the host device 1300 using the Compute Express Link (CXL) protocol.

[0103] The memory interface circuit 1180 may communicate with the memory device 1200 through the memory interface 1020. The memory interface circuit 1180 may transmit a command CMD and an address ADDR to the memory device 1200 and receive a corresponding response ACK. The memory interface circuit 1180 may send and receive data DQ to and from the memory device 1200.

[0104] The media controller 1160 is connected to the memory device 1200 through the memory interface circuit 1180 and controls the overall operation of the memory device 1200.

[0105] When the memory device 1200 is formed by multiple memory modules, the memory interface circuit 1180 may include multiple physical layers corresponding to the memory modules and communicate with the corresponding memory modules through dedicated channels. Additionally, the media controller 1160 may include multiple media controllers corresponding to the multiple physical layers and control the corresponding memory modules.

[0106] In an embodiment of the present disclosure, Figure 3 the transmitter 120 and the congestion monitoring circuit 130 included in the memory controller 100 may be provided in Figure 11 the link controller 1140, and Figure 3 the response buffer 110, the priority control circuit 140, and the command generation circuit 150 included in the memory controller 100 may be provided in Figure 11 the media controller 1160. That is, the link controller 1140 may monitor the congestion degree of the outport, calculate the average congestion rate, and provide it to the media controller 1160, while the media controller 1160 may adjust the priority according to the average congestion rate and the filling level of the response buffer, such that a second command corresponding to an internal operation is processed before a first command corresponding to an operation of a host request.

[0107] However, embodiments of the present disclosure are not limited thereto, and Figure 3 the configuration of the memory controller 100 of can be arranged according to various embodiments. For example, the response buffer 110, the transmitter 120, and the congestion monitoring circuit 130 can be arranged in the link controller 1140, while the priority control circuit 140 and the command generation circuit 150 can be arranged in the media controller 1160.

[0108] A variety of embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to describe the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above embodiments, and there can be many variations within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can be made based on the technical scope of the present disclosure. These embodiments can be combined to form additional embodiments.

[0109] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with the embodiments of the present disclosure, this is only for descriptive purposes and should not be construed as a limitation. Those of ordinary skill in the art should understand that various changes can be made without departing from the technical spirit of the present disclosure and the appended claims.

[0110] For example, for the logic gates and transistors provided as examples in the above embodiments, different positions and types can be implemented according to the polarity of the input signal.

Claims

1. A memory controller, comprising: a response buffer that stores a response provided from the memory device; a congestion monitoring circuit that monitors a level of congestion at an egress port of the memory controller; a priority control circuit that adjusts the priority of commands based on the congestion level at the egress port and the fill level of the response buffer to process a second command corresponding to an internal operation before a first command corresponding to an operation requested by a host; as well as A command generation circuit, which: schedules the first command and the second command according to the priority; and outputting the scheduled commands to the memory device.

2. The memory controller according to claim 1, in, The first command includes a command for performing an operation requested from the host device, and The second command includes a command for executing the internal operation, and the internal operation is not requested from the host device.

3. The memory controller according to claim 1, wherein: The second command includes at least one of a write queue refresh command, a refresh command, or an erase command.

4. The memory controller according to claim 1, in, The congestion monitoring circuit determines an average congestion rate by tracking the congestion level at the egress port for each monitoring period, Wherein, the priority control circuit: determines the throughput based on the average congestion rate; determines the time window according to the fill level of the response buffer and the throughput; and adjusts the priority to process the second command before the first command by increasing the priority of the second command according to the comparison result of the time window with the execution time of the second command.

5. The memory controller according to claim 4, wherein: The priority control circuit determines the throughput based on the average congestion rate according to the following equation 1: Throughput = maximum throughput * (1-average congestion rate).

6. The memory controller according to claim 4, in, The priority control circuit: Arrange the execution time of the second command in descending order; and The arranged execution times are compared with the time window in sequence to increase the priority of the second command when a specific execution time is less than the time window, or to maintain the priority of the second command without increasing the priority when the execution time with the shortest time is equal to or greater than the time window.

7. The memory controller according to claim 4, in, The priority control circuit includes a lookup table having a plurality of fields obtained by combining two or more execution times of the second command, and The priority control circuit increases the priority of the second command stored in the field corresponding to the time window.

8. The memory controller according to claim 1, in, The response buffer sends a response and a valid signal indicating that the response is valid in response to the ready signal, and The congestion monitoring circuit determines an average congestion rate corresponding to the congestion level at the egress port by sampling the occurrence of a back pressure condition in each monitoring period based on the ready signal and the valid signal.

9. The memory controller according to claim 8, wherein: The congestion monitoring circuit comprises: a back pressure history buffer storing a plurality of sampled signals obtained by sampling the ready signal and the valid signal at a preset sampling interval; and An average value calculator is provided for: generating a back pressure count value by counting the number of sampled signals satisfying the back pressure condition among the sampled signals; and generating the average congestion rate by tracking the back pressure count value for each monitoring period.

10. The memory controller according to claim 9, wherein: The average calculator determines that a sampled signal sampled when the ready signal is deactivated and the valid signal is activated satisfies the backpressure condition.

11. The memory controller according to claim 1, wherein: The priority control circuit comprises: a window determination circuit, which: determines a throughput based on the congestion level at the egress port; and determines a time window according to a ratio of the filling level of the response buffer to the throughput; and A scheduling control circuit is configured to increase the priority of the second command according to a comparison result between the time window and the execution time of the second command.

12. The memory controller according to claim 1, wherein: The command generation circuit comprises: a first command generator that generates the first command in response to a request from a host device; a second command generator that: generates the second command corresponding to the internal operation based on the priority regardless of the request from the host device; a request queue storing the first command and the second command; and An output control circuit schedules the first command and the second command stored in the request queue according to the priority.

13. The memory controller according to claim 1, further comprising: a response counter that generates the fill level by counting the number of valid responses stored in the response buffer; as well as A transmitter provides a ready signal to the response buffer according to a valid signal provided from the response buffer, and provides a response signal to a host device through the output port.

14. A storage system comprising: Memory device; as well as Memory controller, The method further comprises: scheduling a second command corresponding to an internal operation to be processed before a first command corresponding to an operation requested by a host according to a congestion level at an egress port of the storage system and a fill level of a response buffer storing a response provided from the memory device.

15. The storage system according to claim 14, wherein: The memory controller: storing a plurality of sampled signals obtained by sampling a ready signal and a valid signal input to and output from the response buffer at a preset sampling interval; Generate a back pressure count value by counting the number of sampling signals satisfying the back pressure condition among the sampling signals; as well as By tracking the backpressure count value for each monitoring period, an average congestion rate corresponding to the congestion level at the egress port is generated.

16. The storage system according to claim 14, wherein: The memory controller: determining an average congestion rate by tracking the congestion level at the egress port; determining a throughput according to the average congestion rate; determining a time window according to a ratio of the fill level of the response buffer to the throughput; as well as The priority is adjusted by increasing the priority of the second command according to a comparison result between the time window and the execution time of the second command.

17. An operating method of a memory controller, the operating method comprising: determining a throughput based on a level of congestion at an egress port of the memory controller; determining a time window based on the throughput and a fill level of a response buffer storing responses provided from a memory device; as well as A second command corresponding to the internal operation and a first command corresponding to the operation requested by the host are scheduled, and a priority of the second command is adjusted according to a comparison result of the time window and an execution time of the second command.

18. The operating method according to claim 17, further comprising: storing a plurality of sampled signals obtained by sampling a ready signal and a valid signal input to and output from the response buffer at a preset sampling interval; Generate a back pressure count value by counting the number of sampling signals satisfying the back pressure condition among the sampling signals; as well as By tracking the back pressure count value for each monitoring period, an average congestion rate corresponding to the congestion level at the egress port is generated.

19. The operating method according to claim 17, wherein: Determining the time window includes: increasing the width of the time window based on determining that the fill level is large and the throughput is low; and The time window is reduced based on determining that the fill level is low and the throughput is high.

20. The operating method according to claim 17, wherein adjusting the priority of the second command comprises: Arrange the execution time of the second command in descending order; as well as The arranged execution times are compared with the time window in sequence to increase the priority of the second command with the specific execution time based on determining that the specific execution time is less than the time window, or to maintain the priority of the second command without increasing the priority based on determining that the execution time with the shortest time is equal to or greater than the time window.

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