Electronic device for optimizing semiconductor characteristics and method of operating same

Abstract

An electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuitry is configured to generate an initial experimental design (DOE) set that includes a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device. The GA execution circuitry is configured to convert a previous generation of DOE set to a next generation of DOE set. The control circuit is configured to transmit the initial DOE set to an external device, receive an initial characteristic evaluation from the external device, generate an initial DOE set based on the initial characteristic evaluation, and control the genetic algorithm to be executed with an experimental result of the initial DOE set as an input. Each initial case of the plurality of initial cases corresponds to a combination of a plurality of setting values that affect semiconductor characteristics.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0161436 filed in the Korean Intellectual Property Office on November 20, 2023, and Korean Patent Application No. 10-2024-0033324 filed in the Korean Intellectual Property Office on March 8, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to optimization of semiconductor characteristics, and more particularly, to an electronic device and an operating method thereof, which optimize semiconductor characteristics based on Plackett-Burman design and genetic algorithm. Background Art

[0004] With the emergence of high-speed systems and the diversification of applications (such as but not limited to mobile device applications, server applications, autonomous driving, etc.), problems related to semiconductor characteristics may continue to occur, and therefore, the need to ensure signal integrity may be increasing.

[0005] In the development stage, the operational stability of the signal can be performed. However, due to the increase in evaluation cases, it may be difficult to complete the optimization at a relatively high level within a limited time period. Therefore, the importance of the experimental plan for evaluation time and selection of test cases may be increasing, and therefore, it may be necessary to effectively ensure the semiconductor characteristic optimization conditions by introducing an evaluation condition optimization algorithm. Summary of the invention

[0006] One or more example embodiments of the present disclosure provide an electronic device and an operating method thereof, which optimize semiconductor characteristics based on Plackett-Burman Design (PBD) and a genetic algorithm.

[0007] According to one aspect of the present disclosure, an electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuit is configured to generate an initial design of experiment (DOE) set, which includes multiple initial cases about semiconductor characteristics of a memory device included in an external device. The GA execution circuit is configured to convert the previous generation DOE set into the next generation DOE set based on a genetic algorithm. The control circuit is configured to send the initial DOE set to an external device, receive an initial characteristic evaluation performed based on the initial DOE set from the external device, generate a starting DOE set based on the initial characteristic evaluation, and control the genetic algorithm to be executed with the experimental results of the starting DOE set as input. Each of the multiple initial cases corresponds to a combination of multiple setting values ​​that affect semiconductor characteristics.

[0008] According to one aspect of the present invention, an operating method of an electronic device includes: generating an initial DOE set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device, sending the initial DOE set to the external device, receiving an initial characteristic evaluation performed based on the initial DOE set from the external device, generating the starting DOE set based on the initial characteristic evaluation, and generating an output DOE set by executing a genetic algorithm with an experimental result of the starting DOE set as input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values ​​affecting the semiconductor characteristics.

[0009] According to one aspect of the present disclosure, a system includes a first electronic device and a second electronic device. The first electronic device is configured to generate an initial DOE set including a plurality of initial cases about semiconductor characteristics of a memory device of the second electronic device, send the initial DOE set to the second device, receive an initial characteristic evaluation corresponding to the initial DOE set from the second device, generate a starting DOE set based on the initial characteristic evaluation, and execute a genetic algorithm with an experimental result of the starting DOE set as input. The second electronic device is configured to receive an initial DOE set including a plurality of initial cases from the first electronic device, perform a semiconductor characteristic evaluation by setting a memory device based on corresponding setting values ​​of the plurality of initial cases, and send an initial characteristic evaluation corresponding to the result of the performed semiconductor characteristic evaluation to the first electronic device. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values ​​affecting semiconductor characteristics. The first electronic device is also configured to perform a linear analysis on each of the plurality of setting values ​​based on the initial characteristic evaluation, determine a plurality of setting values ​​based on the result of the linear analysis, generate an optimal case including a plurality of determined setting values, and generate a starting DOE set by merging a plurality of initial cases, an optimal case, and a base case in which a plurality of setting values ​​are set to off.

[0010] Additional aspects may be set forth in part in the description which follows and, in part, may be obvious from the description, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of certain embodiments of the present disclosure may be more apparent from the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 A system according to an embodiment is shown;

[0013] Figure 2A is a block diagram of a first electronic device according to an embodiment;

[0014] Figure 2B is a block diagram of a second electronic device according to an embodiment;

[0015] Figure 3 is a flowchart illustrating a method of operating a first electronic device according to an embodiment;

[0016] Figure 4 is a table showing an example of an initial Plackett-Burman Design (PBD) Design of Experiments (DOE) set according to an embodiment;

[0017] Figure 5 is a table showing an example of determining a best case according to an embodiment;

[0018] Figure 6 is a table showing an example of a starting PBD DOE set according to an embodiment;

[0019] Figure 7 An example of a genetic algorithm according to an embodiment is shown;

[0020] Figure 8 shows a signal exchange diagram according to an embodiment;

[0021] Fig. 9 is a block diagram showing an electronic device according to an embodiment;

[0022] Fig.10 is a block diagram showing an electronic device according to an embodiment;

[0023] Fig.11A is a graph showing improvement of semiconductor characteristics according to generation repetition according to an embodiment; and

[0024] Fig. 11B An improved eye diagram according to an embodiment is shown. DETAILED DESCRIPTION

[0025] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, it will be appreciated by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and structures have been omitted for clarity and conciseness.

[0026] With respect to the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that, unless otherwise clearly stated in the relevant context, the singular form of the noun corresponding to the project may include one or more things. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B or C" may include any one or all possible combinations of the items listed together in the corresponding phrase. As used herein, terms such as "1st" and "2nd" or "first" and "second" may be used to simply distinguish the corresponding component from another component, and do not limit the component in other aspects (e.g., importance or order). It should be understood that if an element (e.g., a first element) is referred to as "coupled with another element (e.g., a second element)", "coupled to another element", "connected to another element" or "connected to another element" with or without the term "operably" or "communicatively", it means that the element can be coupled to another element directly (e.g., wired), wirelessly or via a third element.

[0027] The terms "first", "second", "third" may be used to describe various elements, but the elements are not limited by the terms, and the "first element" may be referred to as the "second element". Alternatively or additionally, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. may not necessarily refer to any form of order or numerical meaning.

[0028] References throughout this disclosure to "one embodiment," "an embodiment," "an example embodiment," or similar language may indicate that a particular feature, structure, or characteristic described in conjunction with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment," "in an embodiment," "in an example embodiment," and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and therefore, the disclosure is not limited thereto, and may be implemented in various other forms.

[0029] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is an illustration of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged. In addition, some blocks can be combined or omitted. The attached claims present the elements of the various blocks in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0030] As shown in the accompanying drawings, the embodiments herein may be described and illustrated in terms of blocks that perform one or more functions described. These blocks (which may be referred to herein as units or modules, etc., or by names such as devices, logic, circuits, controllers, counters, comparators, generators, converters, etc.) may be physically implemented by analog and / or digital circuits, including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0031] In this disclosure, the articles "a" and "an" are intended to include one or more items and can be used interchangeably with "one or more". Figure 1 In the case of multiple items, the term "a" or similar language is used. For example, the term "processor" can refer to a single processor or multiple processors. When a processor is described as performing an operation and the processor is referred to as performing additional operations, the multiple operations can be performed by any one or combination of the single processor or multiple processors.

[0032] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0033] Figure 1 A system 10 according to an embodiment is shown.

[0034] refer to Figure 1 , the system 10 may include a first electronic device 110 and a second electronic device 120 .

[0035] According to an embodiment, the first electronic device 110 may optimize the semiconductor characteristics of the second electronic device 120. The first electronic device 110 may be referred to using various terms, such as, but not limited to, a test device, an optimization device, etc. For example, the first electronic device 110 may provide a design of experiments (DOE) set to the second electronic device 120. The DOE set may be and / or may include data for evaluating the semiconductor characteristics of a memory (e.g., at least one of a volatile memory or a non-volatile memory) included in the second electronic device 120. For example, the DOE set may include a plurality of cases. Each of the plurality of cases may include a plurality of test mode register settings (TMRS) values ​​for evaluating the semiconductor characteristics of the memory included in the second electronic device 120. Depending on whether the TMRS value is set to ON (e.g., POSITIVE, “+”, high, “1”, etc.) or set to OFF (e.g., NEGTIVE, “-”, low, “0”, etc.), the TMRS value may include factors that may affect the semiconductor characteristics of the memory of the second electronic device 120 (e.g., input / output (I / O) margin in the case of dynamic random access memory (DRAM), eye size of an eye diagram, etc.).

[0036] According to an embodiment, the second electronic device 120 may evaluate semiconductor characteristics and provide the first electronic device 110 with the characteristic evaluation result. The second electronic device 120 may receive the DOE set from the first electronic device 110, and may provide the first electronic device 110 with the characteristic evaluation result for each of the multiple cases included in the DOE set. For example, the DOE set may include eight (8) cases, and each of the eight (8) cases may include a combination of seven (7) TMRS values. The second electronic device 120 may set the memory of the second electronic device 120 according to the TMRS value corresponding to each of the eight (8) cases, and evaluate the semiconductor characteristics. For example, the second electronic device 120 may set the memory according to the combination of the TMRS values ​​of each of the eight (8) cases, and evaluate the I / O margin and / or the eye size of the eye diagram. For example, when the DOE set includes eight (8) cases, the second electronic device 120 may perform eight (8) evaluations of semiconductor characteristics, and provide eight (8) results of the characteristic evaluation to the first electronic device 110.

[0037] According to an embodiment, the first electronic device 110 may execute a genetic algorithm and / or identify a best case based on a characteristic evaluation result received from the second electronic device 120. For example, when the characteristic evaluation result satisfies the termination condition of the genetic algorithm (e.g., the I / O margin exceeds a threshold margin and / or the child size exceeds a threshold size), the generation repetition based on the genetic algorithm may be stopped, and one case with a preferred (e.g., highest) evaluation result among the DOE sets provided to the second electronic device 120 may be identified as the best case and provided to the second electronic device 120. The second electronic device 120 may provide optimal performance by receiving the best case and setting the memory device according to a combination of TMRS values ​​included in the best case. As another example, when the characteristic evaluation result does not satisfy the termination condition of the genetic algorithm, the first electronic device 110 may generate and provide a new DOE set (e.g., child) to the second electronic device 120 by performing generation repetitions of the DOE set (e.g., parent generation). Reference Figure 2A and 2B The first electronic device 110 and the second electronic device 120 are further described.

[0038] Figure 2A is a block diagram of a first electronic device 110 according to an embodiment.

[0039] refer to Figure 2A , the first electronic device 110 may include a control circuit 210 , a Plackett-Burman design (PBD) execution circuit 220 , and a genetic algorithm (GA) execution circuit 230 .

[0040] The control circuit 210 may control the overall operation of the first electronic device 110. For example, the control circuit 210 may generate an initial PBD DOE set by providing a control signal to the PBD execution circuit 220. The initial PBD DOE set may be a DOE set for identifying initial characteristics of a memory included in the second electronic device 120. As another example, the control circuit 210 may perform generation repetition of the DOE set by providing a control signal to the GA execution circuit 230.

[0041] According to an embodiment, the control circuit 210 may determine whether to continue to perform the generation repetition of the DOE set based on the characteristic evaluation result received from the second electronic device 120. For example, the control circuit 210 may determine whether the characteristic evaluation result received from the second electronic device 120 exceeds a threshold value and satisfies the termination condition of the genetic algorithm. When the termination condition of the genetic algorithm is met, the control circuit 210 may provide a control signal to the GA execution circuit 230 to stop the generation repetition based on the genetic algorithm, and may determine the case with the preferred (e.g., highest) characteristic evaluation result among the finally generated DOE set as the best case, and provide the case to the second electronic device 120. When the termination condition of the genetic algorithm is not met, the control circuit 210 may provide a control signal to the GA execution circuit 230 to instruct the GA execution circuit 230 to continue to perform the generation repetition based on the genetic algorithm. The control circuit 210 may provide the next generation DOE set generated from the GA execution circuit 230 to the second electronic device 120.

[0042] The PBD execution circuit 220 can generate an initial PBD DOE set based on PBD. PBD can refer to a design method in which various independent factors can be examined for factors that may affect experimental results. Based on PBD, factors that affect memory characteristics (e.g., I / O margin, eye size in an eye diagram, etc.) can be explored while minimizing the number of experiments by selecting multiple factors to evenly divide the entire experimental space. The initial PBD DOE set can be used to search for initial settings of the memory in the second electronic device 120. The second electronic device 120 can respond to the first electronic device 110 with a characteristic evaluation result based on the initial PBD DOE set, and the first electronic device 110 can determine a starting DOE set for starting a genetic algorithm based on the characteristic evaluation result corresponding to the initial PBD DOE set. Reference Figure 5 An example of determining the best case is further described.

[0043] The GA execution circuit 230 can execute a genetic algorithm based on the DOE set. That is, the GA execution circuit 230 can generate a new DOE set of the next generation using the DOE set that has been provided to the second electronic device 120 as the previous generation based on at least one of various selection operators (e.g., roulette wheel selection, ranking selection, tournament selection, elite preserving selection, etc.), various crossover operators (e.g., single-point crossover, two-point crossover, uniform crossover, arithmetic crossover, etc.) and / or various mutation operators (e.g., scrambling mutation, inversion mutation, insertion mutation, etc.). Refer to later Figure 7An example of generation repetition based on the genetic algorithm of the GA execution circuit 230 is described.

[0044] Figure 2B is a block diagram of the second electronic device 120 according to an embodiment.

[0045] refer to Figure 2B , the second electronic device 120 may include a processing circuit 215 and a memory device 225 .

[0046] The processing circuit 215 may control the overall operation of the second electronic device 120. The processing circuit 215 may correspond to a central processing unit (CPU). For example, the processing circuit 215 may perform startup by loading a boot loader into a DRAM in response to power-on of the second electronic device 120. As another example, the processing circuit 215 may change a setting value of the memory device 225.

[0047] According to an embodiment, the processing circuit 215 may obtain the characteristic evaluation result of the memory device 225 by receiving the DOE set from the first electronic device 110 and changing the setting value of the memory device 225 based on the DOE set. For example, when the DOE set includes eight (8) cases, the processing circuit 215 may change the setting value of the memory device 225 eight (8) times and evaluate the semiconductor characteristics (e.g., I / O margin, eye size of an eye diagram, etc.) of the memory device 225 each time the setting value is changed. The processing circuit 215 may provide the characteristic evaluation result of the memory device 225 to the first electronic device 110.

[0048] The memory device 225 may include at least one of a non-volatile memory or a volatile memory. Examples of non-volatile memory may include, but are not limited to, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), NAND flash memory, vertical NAND (V-NAND or 3D NAND) flash memory, NOR flash memory, resistive random access memory (RRAM or ReRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), etc. Examples of volatile memory may include, but are not limited to, random access memory (RAM), static RAM (SRAM), DRAM, etc.

[0049] Figure 3 is a flowchart illustrating a method of operating the first electronic device 110 according to an embodiment.

[0050] refer to Figure 3In operation S310, the first electronic device 110 may generate an initial PBD DOE set. The initial PBD DOE set may be a set for identifying initial semiconductor characteristics of the memory device 225 in the second electronic device 120. For example, the initial PBD DOE set may correspond to Figure 4 Table 400.

[0051] Reference together Figure 4 , Table 400 shows eight (8) cases (e.g., first case Case1, second case Case2, third case Case3, fourth case Case4, fifth case Case5, sixth case Case6, seventh case Case7, and eighth case Case8) and seven (7) TMRS factors (e.g., first TRMS factor TMRS1, second TRMS factor TMRS2, third TRMS factor TMRS3, fourth TRMS factor TMRS4, fifth TRMS factor TMRS5, sixth TRMS factor TMRS6, and seventh TRMS factor TMRS7). The first factor TMRS1 to the seventh factor TMRS7 may correspond to factors that may affect the semiconductor characteristics of the memory device 225. Each of the first case Case1 to the eighth case Case8 may be determined according to a combination of the first TMRS factor TMRS1 to the seventh TMRS factor TMRS7. For example, as shown in Table 400, when the first TMRS factor TMRS1 to the seventh TMRS factor TMRS7 are set to ON (or POSITIVE), the first case Case1 may evaluate the semiconductor characteristics of the memory device 225. As another example, when the first TMRS factor TMRS1, the second TMRS factor TMRS2, and the seventh TMRS factor TMRS7 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the third TMRS factor TMRS3, the fourth TMRS factor TMRS4, the fifth TMRS factor TMRS5, and the sixth TMRS factor TMRS6) are set to OFF (or NEGTIVE), the second case Case2 may evaluate the semiconductor characteristics of the memory device 225.

[0052] As another example, when the first TMRS factor TMRS1, the third TMRS factor TMRS3, and the fourth TMRS factor TMRS4 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the second TMRS factor TMRS2, the fifth TMRS factor TMRS5, the sixth TMRS factor TMRS6, and the seventh TMRS factor TMRS7) are set to OFF (or NEGTIVE), the third case Case3 may evaluate the semiconductor characteristics of the memory device 225.

[0053] As another example, when the first TRMS factor TMRS1, the fifth TRMS factor TMRS5, and the sixth TRMS factor TMRS6 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the second TRMS factor TMRS2, the third TRMS factor TMRS3, the fourth TRMS factor TMRS4, and the seventh TRMS factor TMRS7) are set to OFF (or NEGTIVE), the fourth case Case4 can evaluate the semiconductor characteristics of the memory device 225.

[0054] As another example, when the second TRMS factor TMRS2, the third TRMS factor TMRS3, and the fifth TRMS factor TMRS5 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the fourth TRMS factor TMRS4, the sixth TRMS factor TMRS6, and the seventh TRMS factor TMRS7) are set to OFF (or NEGTIVE), the fifth case Case5 may evaluate the semiconductor characteristics of the memory device 225.

[0055] As another example, when the second TRMS factor TMRS2, the fourth TRMS factor TMRS4, and the sixth TRMS factor TMRS6 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the third TRMS factor TMRS3, the fifth TRMS factor TMRS5, and the seventh TRMS factor TMRS7) are set to OFF (or NEGTIVE), the sixth case Case6 may evaluate the semiconductor characteristics of the memory device 225.

[0056] As another example, when the third TRMS factor TMRS3, the sixth TRMS factor TMRS6, and the seventh TRMS factor TMRS7 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the second TRMS factor TMRS2, the fourth TRMS factor TMRS4, and the fifth TRMS factor TMRS5) are set to OFF (or NEGTIVE), the seventh case Case7 may evaluate the semiconductor characteristics of the memory device 225.

[0057] As another example, when the fourth TRMS factor TMRS4, the fifth TRMS factor TMRS5 and the seventh TRMS factor TMRS7 are set to ON (or POSITIVE) and the remaining TMRS factors (e.g., the first TRMS factor TMRS1, the second TRMS factor TMRS2, the third TRMS factor TMRS3 and the sixth TRMS factor TMRS6) are set to OFF (or NEGTIVE), the eighth case Case8 can evaluate the semiconductor characteristics of the memory device 225.

[0058] Although Table 400 describes an example of an initial PBD DOE set having eight (8) cases and seven (7) TMRS factors, the invention is not limited in this respect. For example, the initial PBD DOE set may include additional cases (e.g., more than eight (8)), may include fewer cases (e.g., less than eight (8)), may include additional TMRS factors (e.g., more than seven (7)), may include fewer TMRS factors (e.g., less than seven (7)), or any combination thereof. Alternatively or additionally, in these cases, the initial PBD DOE set may include the same and / or different combinations of TMRS factors.

[0059] The first electronic device 110 may generate a PBD execution circuit 220 Figure 4 An initial PBD DOE set of Table 400.

[0060] In operation S320, the first electronic device 110 may receive an initial characteristic evaluation of an initial PBD DOE set. The second electronic device 120 may receive the initial PBD DOE set from the first electronic device 110 and perform a semiconductor characteristic evaluation on the memory device 225. For example, the second electronic device 120 may perform a semiconductor characteristic evaluation for each of the first case Case1 to the eighth case Case8 of the initial PBD DOE set. That is, the second electronic device 120 may measure the I / O margin and / or the eye size of the eye diagram by changing the settings of the memory device 225 according to the first TMRS factor TMRS1 to the seventh TMRS factor TMRS7 mapped to the first case Case1, applying an input signal to the memory device 225 that has completed the setting change, and receiving an output signal. The second electronic device 120 may send the characteristic evaluation result measured for the first case Case1 to the first electronic device 110. For the remaining second case Case2 to the eighth case Case8, the second electronic device 120 may repeatedly evaluate the semiconductor characteristics of the memory device 225 and send the measured characteristic evaluation results to the first electronic device 110. The result of the semiconductor characteristic evaluation of the memory device 225 set according to the initial PBD DOE set may correspond to the initial characteristic evaluation.

[0061] In operation S330, the first electronic device 110 may generate a starting DOE set using the correlation identified based on the initial characteristic evaluation. The starting DOE set may refer to a set provided as an input to the GA execution circuit 230. That is, the starting DOE set may correspond to a first generation DOE set (or first parent DOE) in which the genetic algorithm starts.

[0062] To determine the starting DOE set, the first electronic device 110 may identify correlations based on the initial characteristic evaluation. Figure 5 , Table 500 can be used with Figure 4 Table 400 is substantially similar and / or identical, and may further include an additional row of linear analysis results. The additional row may indicate a case newly added according to the linear analysis result, and may be referred to as a best case. The first electronic device 110 may derive the best case using the characteristic evaluation results of each case of the initial PBD DOE. The first electronic device 110 may perform linear analysis by determining whether the semiconductor characteristics are improved when each TMRS factor is ON (or POSITIVE) or whether the semiconductor characteristics are further improved when each TMRS factor is OFF (or NEGTIVE). In an embodiment, the first electronic device 110 may determine whether the result of summing the evaluation results when a specific TMRS factor is ON and subtracting the evaluation results when the specific TMRS factor is OFF is greater than 0. For example, in the case of performing a linear analysis on the first TMRS factor TMRS1, the evaluation results of the cases when the first TMRS factor TMRS1 is ON (e.g., the first case Case1 to the fourth case Case4) may be summed, and the evaluation results of the cases when the first TMRS factor TMRS1 is OFF (e.g., the fifth case Case5 to the eighth case Case8) may be subtracted. In this example, the result of the linear analysis may be approximately 1.001464, and therefore, the linear analysis result of the first TMRS factor TMRS1 may be determined to be ON (or POSITIVE). The first electronic device 110 may repeat the same process for the second TMRS factor TMRS2 to the seventh TMRS factor TMRS7 to determine the combination of the best case TMRS factors.

[0063] The first electronic device 110 can obtain a starting DOE set to be used as an input to the genetic algorithm by adding the best case and the base case to the existing initial PBD DOE set. The base case may refer to a case in which the first TMRS factor TMRS1 to the seventh TMRS factor TMRS7 are OFF (or NEGTIVE). When executing the genetic algorithm, adding the base case to the generation of the starting DOE can increase the possibility of reaching the global optimum without falling into the local optimum. Figure 6 , the table 600 may correspond to the starting DOE set. That is, the table 600 may include both the best case determined according to the linear analysis result and the basic (or default) case in which the first TMRS factor TMRS1 to the seventh TMRS factor TMRS7 are OFF in the initial case generated by the PBD execution circuit 220.

[0064] In operation S340, the first electronic device 110 may execute a genetic algorithm using the starting DOE set as input. For example, the first electronic device 110 may provide the generated starting DOE set as input to the GA execution circuit 230. The GA execution circuit 230 may generate a next generation DOE set by executing a genetic algorithm using the starting DOE set as the previous generation.

[0065] Reference together Figure 7 , the first electronic device 110 can execute a genetic algorithm based on the starting DOE set. For ease of description, Figure 7 The starting DOE set is shown to include five (5) parent cases (e.g., a first parent case Parent1, a second parent case Parent2, a third parent case Parent3, a fourth parent case Parent4, and a fifth parent case Parent5). However, the present disclosure is not limited thereto. The first electronic device 110 may evaluate the score of each case included in the starting DOE set before executing the genetic algorithm. The score may adopt the above-mentioned characteristic evaluation result, or may be obtained according to an equation for converting the characteristic evaluation result in proportion to the characteristic evaluation result, and is not limited to a specific embodiment. For example, as a result of evaluating the score of the starting DOE set, the score of the first parent case Parent1 may be 26, the score of the second parent case Parent2 may be 13, the score of the third parent case Parent3 may be 34, the score of the fourth parent case Parent4 may be 8, and the score of the fifth parent case Parent5 may be 19. The first electronic device 110 may generate the next generation DOE set based on various selection operators, crossover operators, and mutation operators. The next generation DOE set may include five (5) child cases (eg, a first child case Child1, a second child case Child2, a third child case Child3, a fourth child case Child4, and a fifth child case Child5).

[0066] According to an embodiment, the first electronic device 110 may cross the cases with high scores in the starting DOE set. The first electronic device 110 may cross the TMRS factors of the first parent case Parent1 and the third parent case Parent3 in the starting DOE set. Figure 7 In the case of , only one intersection point may be set as the middle point, however, the present disclosure is not limited thereto. Figure 7 , the first child case Child1 can be obtained by crossing to include the first half four TMRS factors TMRS1 to TMRS4 of the first parent case Parent1 and the second half four TMRS factors TMRS5 to TMRS8 of the third parent case Parent3.

[0067] According to an embodiment, the first electronic device 110 may cross the cases with low scores in the starting DOE set. The first electronic device 110 may cross the TMRS factors of the second parent case Parent2 and the fourth parent case Parent4 in the starting DOE set. Figure 7 , the second child case Child2 can be obtained by crossing to include the first half four TMRS factors TMRS1 to TMRS4 of the second parent case Parent2 and the second half four TMRS factors TMRS5 to TMRS8 of the fourth parent case Parent4.

[0068] According to an embodiment, the first electronic device 110 may cross-start adjacent cases in the DOE set. Figure 7 , the third child case Child3 can be obtained by crossing to include the first half of the four TMRS factors TMRS1 to TMRS4 of the fifth parent case Parent5 and the second half of the four TMRS factors TMRS5 to TMRS8 of the fourth parent case Parent4. The fourth child case Child4 can be obtained by crossing to include the first half of the four TMRS factors TMRS1 to TMRS4 of the third parent case Parent3 and the second half of the four TMRS factors TMRS5 to TMRS8 of the second parent case Parent2.

[0069] According to an embodiment, the first electronic device 110 may crossover and mutate any case in the starting DOE set. Figure 7 , the fifth child case Child5 can be obtained by crossing to include the first half four TMRS factors TMRS1 to TMRS4 of the fifth parent case Parent5 and the second half four TMRS factors TMRS5 to TMRS8 of the first parent case Parent1, and then changing OFF to ON by generating a mutation in the third TMRS factor TMRS3.

[0070] However, the embodiment in which the first electronic device 110 executes the genetic algorithm is not limited thereto, and the next generation of new DOE sets may be generated based on at least one of various selection operators (e.g., roulette selection, ranking selection, tournament selection, elite retention selection, etc.), various crossover operators (e.g., single-point crossover, two-point crossover, uniform crossover, arithmetic crossover, etc.), and various mutation operators (e.g., scrambling mutation, inversion mutation, insertion mutation, etc.). The first electronic device 110 may send the next generation of new DOE sets to the second electronic device 120 to evaluate semiconductor characteristics, and obtain characteristic evaluation results of the next generation of new DOE sets. When the characteristic evaluation results of the next generation of new DOE sets do not meet the termination condition of the genetic algorithm, the next generation of new DOE sets may be repeatedly generated by executing the genetic algorithm for generating repetitions again.

[0071] In operation S350, when the termination condition of the genetic algorithm is met, the first electronic device 110 may send the best case among the termination DOE set. The first electronic device 110 may send the new DOE set of the next generation to the second electronic device 120 to evaluate the semiconductor characteristics, and obtain the characteristic evaluation results of the new DOE set of the next generation. When the characteristic evaluation results of the new DOE set of the next generation meet the termination condition of the genetic algorithm, the genetic algorithm for generating repetitions may be terminated without further executing the genetic algorithm. The termination condition may be based on, for example, whether there are cases exceeding a threshold score, or whether there are characteristic evaluation results exceeding a threshold. However, the above-mentioned termination condition is not limited thereto, and even if the above-mentioned threshold score or termination condition exceeding the threshold is not reached, if the generation repetitions exceeding the threshold number of times are performed, it can also be determined that the termination condition is met to prevent excessive delays in the startup process.

[0072] Figure 8 A signal exchange diagram according to an embodiment is shown.

[0073] Hereinafter, for convenience of description, description is made based on the case where the memory device 225 is a DRAM. However, as described above, the memory device 225 is not limited to the DRAM, and may be various volatile memories or nonvolatile memories including a NAND flash memory.

[0074] refer to Figure 8 In operation 810, the processing circuit 215 may perform booting. That is, the booting process may be performed by loading a boot loader into the DRAM in response to power-on of the second electronic device 120.

[0075] In operation 815, the first electronic device 110 may generate an initial PBD DOE. The PBD execution circuit 220 may generate a DOE based on TMRS factors (eg, 31 TMRS factors) that affect the performance evaluation of the DRAM. For example, the initial PBD DOE may include 32 cases. Figure 8 , it is shown that operation 810 is before operation 815, but the embodiment is not limited thereto. Operations 810 and 815 may be performed in parallel, and / or operation 815 may be performed first.

[0076] In operation 820, the first electronic device 110 may send Figure 1 The first electronic device 110 may provide the initial PBD DOE to the second electronic device 120. For example, the first electronic device 110 may provide 32 cases included in the initial PBD DOE to the processing circuit 215 of the second electronic device 120. Each of the 32 cases may correspond to a combination of 31 different TMRS factors.

[0077] In operation 825, the processing circuit 215 may provide a plurality of case setting values ​​to the memory device 225. The processing circuit 215 may sequentially change the setting value of the memory device 225 according to the combination of TMRS factors of the 32 cases, and evaluate the I / O margin value of the set case in operation 830. For example, the processing circuit 215 may evaluate the I / O margin by setting the memory device 225 according to the TMRS factor combination of the first case among the 32 cases provided from the first electronic device 110 and applying the input signal to the memory device 225. Thereafter, the processing circuit 215 may sequentially evaluate the respective characteristics up to the I / O margin according to the TMRS factor combination of the 32nd case.

[0078] In operation 835, the first electronic device 110 may receive a plurality of I / O margin evaluation values. Figure 8 It is shown that the memory device 225 provides a plurality of I / O margin evaluation values ​​to the processing circuit 215 at one time, and the processing circuit 215 sends the plurality of I / O margin evaluation values ​​to the first electronic device 110, but the embodiment is not limited thereto. As described above, the memory device 225 can output an I / O margin evaluation value for each case, and whenever the characteristic evaluation of each case is completed, the processing circuit 215 can send the I / O margin evaluation value to the first electronic device 110. At the time point of operation 835, the first electronic device 110 can obtain 32 I / O margin evaluation values ​​corresponding to 32 cases.

[0079] In operation 840, the first electronic device 110 may determine a linear coefficient based on a plurality of I / O margin evaluation values. For example, the first electronic device 110 may determine whether the I / O margin evaluation value improves when the first TMRS factor among the 31 TMRS factors is ON or OFF. For example, the first electronic device 110 may determine whether the linear coefficient is ON, OFF, or NULL (empty) (e.g., it may indicate that there is no correlation) by summing the evaluation values ​​of the 32 cases corresponding to the first TMRS factor. The first electronic device 110 may determine 31 linear coefficients by performing the same process for each of the 31 TMRS factors.

[0080] In operation 845 , the first electronic device 110 may generate a best case according to the linear coefficient. The best case may refer to a case in which each of the 31 TMRS factors is set to match the linear coefficient determined in operation 840 .

[0081] In operation 850, the first electronic device 110 may provide information about the best case to the second electronic device 120. For example, the first electronic device 110 may provide the processing circuit 215 with the best case in which each of the 31 TMRS factors is set to match the linear coefficient.

[0082] In operation 855, the processing circuit 215 may provide the best case setting value to the memory device 225. The processing circuit 215 may change the setting value of the memory device 225 according to the combination of 31 TMRS factors indicated by the best case, and may evaluate the I / O margin value of the memory device 225 in operation 860. For example, the processing circuit 215 may set the memory device 225 according to the TMRS factor combination of the best case provided from the first electronic device 110, and apply the input signal to the memory device 225 to evaluate the I / O margin.

[0083] In operation 865 , the first electronic device 110 may receive an I / O margin evaluation value. The received I / O margin evaluation value may be an I / O margin evaluation value corresponding to the best case generated in operation 845 .

[0084] In operation 870, the first electronic device 110 may generate a starting DOE set. The first electronic device 110 may generate a starting DOE set by additionally merging the best case and the base case with the initial PBD DOE. The base case may correspond to a case in which all TMRS factors are OFF. Accordingly, the starting DOE set may include 34 cases. However, the above embodiment is not limited thereto, and the starting DOE set may be generated by additionally merging a case in which all TRMS factors are ON.

[0085] In operation 875, the first electronic device 110 may generate a next generation DOE set based on a genetic algorithm. The first electronic device 110 may randomly select at least two cases from the 34 parent cases, and generate a single child case based on various selection operators, crossover operators, and mutation operators for the selected cases. The first electronic device 110 may generate a next generation DOE set according to a genetic algorithm by randomly generating 34 child cases.

[0086] In operation 880, the first electronic device 110 may perform an I / O margin assessment whenever a generation-specific DOE set is generated. For example, when a next-generation DOE set is generated based on the starting DOE set in operation 875, a second-generation DOE set may have been generated. The first electronic device 110 may obtain an I / O margin assessment value for each case by providing 34 cases of the second-generation DOE set to the second electronic device 120.

[0087] In operation 885, the first electronic device 110 may determine whether the I / O margin evaluation satisfies the termination condition. For example, in operation 880, the first electronic device 110 may have obtained the I / O margin evaluation value of the second-generation DOE set. The first electronic device 110 may determine whether the termination condition of the genetic algorithm is met based on the I / O margin evaluation value of the second-generation DOE set. For example, the first electronic device 110 may determine whether there is a case exceeding the threshold value among the 34 I / O margin evaluation values ​​corresponding to the 34 cases of the second-generation DOE set. When there is a case exceeding the threshold value among the 34 I / O margin evaluation values ​​of the second-generation DOE set, the first electronic device 110 may determine that the termination condition is met and proceed to operation 890. If no case exceeds the threshold value among the 34 I / O margin evaluation values ​​corresponding to the 34 cases of the second-generation DOE set, it can be determined that the termination condition is not met and can return to operation 875. In this case, the first electronic device 110 can generate a third-generation DOE set by re-executing the genetic algorithm on the input of the second-generation DOE set. In operation 880, the first electronic device 110 may provide the third generation DOE set to Figure 1 The second electronic device 120 of the third generation DOE set performs characteristic evaluation and obtains 34 I / O margin evaluation values ​​corresponding to the 34 cases of the third generation DOE set. The first electronic device 110 can determine whether the 34 I / O margin evaluation values ​​corresponding to the 34 cases of the third generation DOE set meet the termination condition, and perform generation repetition until the termination condition is met by returning to operation 875 according to the determination result.

[0088] In operation 890, the first electronic device 110 may determine a final case of the termination DOE set. The termination DOE set may refer to a DOE set of a generation that satisfies the termination condition of the genetic algorithm. The first electronic device 110 may determine the case with the highest score or the case with the highest I / O evaluation margin value among the 34 cases included in the termination DOE set as the final case.

[0089] In operation 895, the first electronic device 110 may send Figure 1 The second electronic device 120 of the present invention provides the final case. For example, the first electronic device 110 may provide the final case to the processing circuit 215. The processing circuit 215 may change the setting value of the memory device 225 according to the 34 TMRS factors included in the final case. The memory device 225 may provide an improved I / O margin or semiconductor characteristics by changing the setting to the TMRS factor value according to the final case before completing the boot process of the processing circuit 215.

[0090] Fig. 9 is a block diagram showing an electronic device 130 according to an embodiment.

[0091] refer to Fig. 9 , the electronic device 130 may include a processing circuit 910 and a memory device 920. Figures 1 to 8 A redundant description of the embodiments is given.

[0092] The processing circuit 910 may include a PBD execution circuit 912 and a GA execution circuit 914. That is, Fig. 9 The electronic device 130 may not need to include a separate electronic device (eg, Figure 1 For example, the PBD execution circuit 912 may generate an initial PBD DOE set. The initial PBD DOE set may be a DOE set for identifying initial characteristics of the memory device 920. The GA execution circuit 914 may generate a next generation DOE set from a previous generation DOE set based on a genetic algorithm.

[0093] In an embodiment, the processing circuit 910 may not include the PBD execution circuit 912. In such an embodiment, instead of generating the initial PBD DOE set by the PBD execution circuit 912, the electronic device 130 may pre-store the initial PBD DOE set in a ROM area accessible at startup, and load the initial PBD DOE set to identify the initial characteristics of the memory device 920.

[0094] Fig.10 is a block diagram showing an electronic device 140 according to an embodiment.

[0095] refer to Fig.10 , the electronic device 130 may include a processing circuit 1010 and a high bandwidth memory (HBM) 1020. Figures 1 to 9 A redundant description of the embodiments is given.

[0096] The HBM 1020 may include a plurality of stacked memory dies, and through a plurality of channels, data may be written to the plurality of memory dies in parallel and / or data may be read from the plurality of memory dies in parallel. The HBM 1020 may include a process in memory (PIM) circuit 1022. The PIM circuit 1022 may perform arithmetic processing through a core loaded by a CPU of the processing circuit 215. For example, the PIM circuit 1022 may generate an initial PBD DOE set based on the PBD. The PIM circuit 1022 may include an internal block and / or circuit capable of executing a genetic algorithm, and the genetic algorithm performs generation repetition by randomly changing each element. For example, the PIM circuit 1022 may execute a genetic algorithm based on the DOE set. The PIM circuit 1022 may use the initial PBD DOE set as the previous generation to generate a new DOE set for the next generation.

[0097] Fig.11A is a graph showing improvement of semiconductor characteristics according to generation repetition according to an embodiment. Fig. 11B An improved eye diagram according to an embodiment is shown.

[0098] refer to Fig.11A , a first graph 1110 represents the degree of improvement of semiconductor characteristics when only a genetic algorithm is used according to a comparative example, and a second graph 1120 represents the degree of improvement of semiconductor characteristics when based on both PBD and a genetic algorithm according to an embodiment.

[0099] According to an embodiment, the default value may represent an I / O margin evaluation value when all TMRS factors affecting the I / O margin of the memory device are OFF. As shown in the first graph 1110, as the TMRS factors affecting the I / O margin of the memory device are repeatedly generated using a genetic algorithm, the I / O margin evaluation value may increase. However, in the case of the first graph 1110, the TMRS factors are not selected so that the entire experimental space is evenly divided because all TMRS factors are OFF in the base case, which is the input to the genetic algorithm. For example, after repeated generation "a" times, according to the genetic algorithm, the I / O margin evaluation value may not be significantly improved. That is, the input of the genetic algorithm may not evenly divide the entire experimental space, and therefore may have reached a local optimum.

[0100] According to the second graph 1120, as the TMRS factors affecting the I / O margin of the memory device are repeatedly generated using the genetic algorithm, the I / O margin evaluation value may increase. However, compared to the first graph 1110, a relatively rapid increase in the I / O margin evaluation value starting from the initial time point of the generation repetition may be observed. The rapid increase may be the result of a linear analysis based on the initial PBD DOE, according to Figure 3 , which includes the best case. In addition, unlike the first graph 1110, it can be observed that the second graph 1120 can continue to improve the I / O evaluation margin even after the repetition "a" has been repeatedly generated. That is, the global optimum can be achieved because the TMRS factors have been selected so that the entire experimental space is equally divided based on the PBD without applying the input of the genetic algorithm to the base case.

[0101] refer to Fig. 11B , the first graph 1130 may correspond to an eye diagram when all TMRS factors affecting the I / O margin of the memory device are OFF. According to an embodiment, the second graph 1140 may correspond to an eye diagram when the settings of the memory device are changed according to the TMRS factors of the final case that satisfies the termination condition using PBD and GA. Fig. 11BAs shown, in the case of the second graph 1140, the size of the noise margin may also be improved compared to the first graph 1130, and the left and right widths of the eye may be increased, indicating that the overall eye size is improved.

[0102] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An electronic device for optimizing semiconductor characteristics, comprising: a Plackett-Burman design PBD execution circuit configured to generate an initial design of experiments DOE set including a plurality of initial cases regarding semiconductor characteristics of a memory device included by an external device; A genetic algorithm GA execution circuit, wherein the GA execution circuit is configured to transform a previous generation DOE set into a next generation DOE set based on a genetic algorithm; as well as A control circuit, the control circuit being configured to: sending the initial DOE set to the external device; receiving, from the external device, an initial characteristic evaluation performed based on the initial DOE set; generating a starting DOE set based on the initial property assessment; as well as A control genetic algorithm is executed with the experimental results of the starting DOE set as input, wherein each initial case of the plurality of initial cases corresponds to a combination of a plurality of setting values ​​affecting the semiconductor characteristic.

2. The electronic device according to claim 1, wherein: The PBD execution circuit is further configured to: The plurality of initial cases are generated by combining the plurality of setting values ​​to evenly divide an experimental space.

3. The electronic device according to claim 1, wherein: The GA execution circuit is further configured to: A plurality of child cases to be included in the next generation DOE set are generated by selecting at least two parent cases from among a plurality of parent cases included in the previous generation DOE set based on at least one of a plurality of selection operators, a plurality of crossover operators, or a plurality of mutation operators.

4. The electronic device according to claim 3, wherein: The plurality of selection operators include at least one of a roulette selection method, a ranking selection method, a tournament selection method, and an elite reserve selection method, The multiple crossover operators include at least one of a single-point crossover, a two-point crossover, a uniform crossover, or an arithmetic crossover, and The multiple mutation operators include at least one of scrambling mutation, inversion mutation or insertion mutation.

5. The electronic device according to claim 1, wherein: The initial characteristic evaluation corresponds to a result of setting the memory device based on the setting value of each of the plurality of initial cases and evaluating the semiconductor characteristic.

6. The electronic device according to claim 1, wherein: The control circuit is further configured to: performing a linear analysis on each of the plurality of setting values ​​based on the initial characteristic evaluation; determining the plurality of setting values ​​based on a result of the linear analysis; generating a best case including a plurality of determined setting values; as well as generating the starting DOE set by merging the plurality of initial cases, the best case and a base case, and The base case corresponds to a case in which all setting values ​​among the plurality of setting values ​​are set to off.

7. The electronic device according to claim 1, wherein: The control circuit is further configured to: sending the next generation DOE set output by the GA execution circuit to the external device; receiving, from the external device, a characteristic evaluation result corresponding to the next generation DOE set; as well as It is determined whether the characteristic evaluation result satisfies a termination condition of the genetic algorithm.

8. The electronic device according to claim 7, wherein: The control circuit is further configured to: Determining that the termination condition is satisfied based on the characteristic evaluation result exceeding the threshold evaluation value; Determine a case having a highest evaluation value among a plurality of sub-cases included in the next-generation DOE set as a final case; as well as The final case is sent to the external device.

9. The electronic device according to claim 7, wherein: The control circuit is further configured to: Determining to repeat the genetic algorithm based on the characteristic evaluation result being less than a threshold evaluation value; and The next generation DOE set is provided to the GA execution circuit.

10. An operating method of an electronic device, the operating method comprising: generating an initial design of experiments (DOE) set, the DOE set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device; sending the initial DOE set to the external device; receiving, from the external device, an initial characteristic evaluation performed based on the initial DOE set; generating a starting DOE set based on the initial property assessment; as well as generating an output DOE set by executing a genetic algorithm with the experimental results of the starting DOE set as input, Each of the plurality of initial cases corresponds to a combination of a plurality of setting values ​​affecting the semiconductor characteristics.

11. The operating method according to claim 10, further comprising: The plurality of initial cases are generated by combining the plurality of setting values ​​to evenly divide the experimental space based on a Plackett-Burman design (PBD).

12. The operating method according to claim 10, wherein: The execution of the genetic algorithm includes: A plurality of child cases to be included in the next generation DOE set are generated by selecting at least two parent cases from among the plurality of parent cases included in the starting DOE set based on at least one of a plurality of selection operators, a plurality of crossover operators, or a plurality of mutation operators.

13. The operating method according to claim 12, wherein: The plurality of selection operators include at least one of a roulette selection method, a ranking selection method, a tournament selection method, or an elite reserve selection method, The multiple crossover operators include at least one of a single-point crossover, a two-point crossover, a uniform crossover, or an arithmetic crossover, and The multiple mutation operators include at least one of scrambling mutation, inversion mutation or insertion mutation.

14. The operating method according to claim 10, wherein: The initial characteristic evaluation corresponds to a result of setting the memory device based on the setting value of each of the plurality of initial cases and evaluating the semiconductor characteristic.

15. The operating method according to claim 10, further comprising: performing a linear analysis on each of the plurality of setting values ​​based on the initial characteristic evaluation; determining the plurality of setting values ​​based on a result of the linear analysis; generating a best case including a plurality of determined setting values; as well as generating the starting DOE set by merging the plurality of initial cases, the best case and a base case, The base case corresponds to a case in which all setting values ​​among the plurality of setting values ​​are set to off.

16. The operating method according to claim 10, further comprising: sending a next generation DOE set to the external device; receiving, from the external device, a characteristic evaluation result corresponding to the next generation DOE set; as well as It is determined whether the characteristic evaluation result satisfies a termination condition of the genetic algorithm.

17. The operating method according to claim 16, further comprising: Determining that the termination condition is satisfied based on the characteristic evaluation result exceeding the threshold evaluation value; Determine a case having the highest evaluation value among the plurality of sub-cases included in the next-generation DOE set as a final case; as well as The final case is sent to the external device.

18. The operating method according to claim 16, further comprising: Determining that the termination condition is not satisfied based on that the characteristic evaluation result is less than a threshold evaluation value; as well as The genetic algorithm is repeated based on the next generation DOE set.

19. A system for optimizing semiconductor characteristics, comprising: A first electronic device, wherein the first electronic device is configured as: generating an initial design of experiments (DOE) set, the DOE set including a plurality of initial cases regarding semiconductor characteristics of a memory device of a second electronic device; sending the initial DOE set to the second electronic device; receiving, from the second electronic device, an initial characteristic evaluation corresponding to the initial DOE set; generating a starting DOE set based on the initial property assessment; as well as executing a genetic algorithm using the experimental results of the starting DOE set as input; and the second electronic device, the second electronic device being configured to: receiving, from the first electronic device, the initial DOE set including the plurality of initial cases; performing semiconductor characteristic evaluation by setting the memory device based on respective setting values ​​of the plurality of initial cases, and transmitting the initial characteristic evaluation corresponding to the result of the performed semiconductor characteristic evaluation to the first electronic device, wherein each of the plurality of initial cases corresponds to a combination of a plurality of setting values ​​affecting the semiconductor characteristics, and Wherein, the first electronic device is further configured as: performing a linear analysis on each of the plurality of setting values ​​based on the initial characteristic evaluation; determining the plurality of setting values ​​based on a result of the linear analysis; generating a best case scenario including a plurality of determined setting values; and The starting DOE set is generated by merging the plurality of initial cases, the best case, and a base case in which the plurality of setting values ​​are set to off.

20. The system of claim 19, wherein: The first electronic device is further configured to: sending a next generation DOE set to the second electronic device; receiving, from the second electronic device, a characteristic evaluation result corresponding to the next generation DOE set; Determining whether the characteristic evaluation result satisfies the termination condition of the genetic algorithm; Determining that the termination condition is satisfied based on the characteristic evaluation result exceeding the threshold evaluation value; Determine a case having a highest evaluation value among a plurality of sub-cases included in the next-generation DOE set as a final case; as well as sending the final case to the second electronic device; as well as Based on the characteristic evaluation result being less than the threshold evaluation value, the genetic algorithm is repeated based on the next generation DOE set.

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