Combined correction method for electron beam proximity effect and etching load effect and mask plate

Abstract

The invention provides an electron beam proximity effect and etching load effect combined correction method and a mask plate, and relates to the technical field of semiconductor manufacturing. The electron beam proximity effect and etching load effect combined correction method comprises the steps that a to-be-corrected layout is corrected based on the electron beam proximity effect, a first correction layout is obtained, and the first correction layout is a layout obtained after the to-be-corrected layout is compensated for first contour offset caused by the electron beam proximity effect; the to-be-corrected layout is corrected based on the etching load effect, a second corrected layout is obtained, and the second corrected layout is obtained after the to-be-corrected layout is compensated for second contour offset caused by the etching load effect; performing intersection processing on the first correction layout and the second correction layout to obtain a combined correction layout; and preparing a mask plate based on the combined correction layout, wherein the size of each pattern element in the mask pattern of the mask plate is within a preset size range.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and more specifically, to a joint correction method for electron beam proximity effect and etching load effect and a mask. Background Art

[0002] The progress of integrated circuit technology has promoted the development of technologies such as 5G, the Internet of Things, and artificial intelligence, making electronic devices faster, smarter, and more efficient, and has had a revolutionary impact on economic development and social progress. Over the past 50 years, the progress of lithography technology has been crucial to maintaining Moore's Law. However, as the minimum feature size of integrated circuits has shrunk to far below the wavelength of light used in the lithography process, the semiconductor industry faces the challenge of continuing to increase the density of transistors. In particular, as the size of transistors decreases and the density increases, the electron beam proximity effect (PE) and the etching loading effect (LE) are easily generated during the mask manufacturing process. The electron beam proximity effect occurs in the electron beam lithography (EBL) process. Due to the forward scattering and backscattering of electrons, the patterns of different areas and densities receive inconsistent doses at the same exposure dose. After the mask is finally etched, defects such as shrinkage of line endpoints, arc-shaped corners of the pattern, and increased line width appear. The etching load effect occurs during the plasma etching process. Due to the different sizes and densities of the patterns in different regions on the layout, the etching rate is inconsistent during the etching process, and the final pattern size of the mask after etching deviates from the target layout. Therefore, how to optimize the defects caused by the electron beam proximity effect and the etching load effect during the mask manufacturing process has become an urgent problem to be solved. Summary of the invention

[0003] In view of this, the present disclosure provides a joint correction method for electron beam proximity effect and etching load effect and a mask, which are used to at least partially solve the above technical problems.

[0004] The first aspect of the present disclosure provides a method for joint correction of electron beam proximity effect and etching load effect, comprising: correcting a layout to be corrected based on the electron beam proximity effect to obtain a first corrected layout, the first corrected layout being a layout obtained after compensating the layout to be corrected for a first contour offset caused by the electron beam proximity effect; correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout, the second corrected layout being a layout obtained after compensating the layout to be corrected for a second contour offset caused by the etching load effect; performing intersection processing on the first corrected layout and the second corrected layout to obtain a joint corrected layout; preparing a mask plate based on the joint corrected layout, the size of each graphic element in the mask pattern of the mask plate being within a preset size range.

[0005] According to an embodiment of the present disclosure, the method also includes: when the size of each graphic element in the mask pattern of the mask plate is outside a preset size range, supplementary correction is performed on the joint correction layout based on the etching load effect, and the supplementary corrected joint correction layout is intersected with the first correction layout to generate a new joint correction layout; iterate in this way until the size of each graphic element in the mask pattern of the mask plate prepared based on the new joint correction layout is within the preset size range.

[0006] According to an embodiment of the present disclosure, a layout to be corrected is corrected based on an electron beam proximity effect to obtain a first corrected layout, including: gridding the layout to be corrected to determine a point spread function of energy distribution in the electron beam resist and an initial electron beam exposure dose of each grid when the electron beam resist is subjected to a unit dose of electron beam direct writing exposure; determining a first offset pixel block in a non-patterned area of ​​the layout to be corrected based on the point spread function and the initial electron beam exposure dose of each grid to compensate for a first contour offset caused by the electron beam proximity effect; and generating a first corrected layout based on the layout to be corrected and the first offset pixel block.

[0007] According to an embodiment of the present disclosure, a layout to be corrected is corrected based on an etching load effect to obtain a second corrected layout, including: sequentially forming a light-shielding layer and an electron beam resist on a surface of a mask substrate; performing electron beam direct writing exposure and development on the electron beam resist based on the layout to be corrected, and etching the light-shielding layer to obtain an initial mask; obtaining a second offset pixel block between an etched contour of each graphic element in the mask pattern of the initial mask and a contour of each corresponding graphic element in the layout to be corrected, so as to compensate for a second contour offset caused by the etching load effect; and generating a second corrected layout according to the layout to be corrected and the second offset pixel block.

[0008] According to an embodiment of the present disclosure, obtaining a second offset pixel block between the etched outline of each graphic element in the mask pattern of the initial mask plate and the outline of each corresponding graphic element in the layout to be corrected includes: determining the coordinates of the first pixel point of each first graphic element according to the outline of each first graphic element in the layout to be corrected; determining the coordinates of the second pixel point of each second graphic element according to the etched outline of each second graphic element in the mask pattern of the initial mask plate; wherein one first graphic element corresponds to one second graphic element; for each first graphic element, determining the second offset pixel block of the first graphic element according to the coordinates of the first pixel point of the first graphic element and the coordinates of the second pixel point corresponding to the first pixel point.

[0009] According to an embodiment of the present disclosure, for each first graphic element, determining a second offset pixel block of the first graphic element according to the coordinates of a first pixel point of the first graphic element and the coordinates of a second pixel point corresponding to the first pixel point includes: for each first pixel point on the boundary of the first graphic element in the same to-be-corrected layout, determining a first offset of an etching contour of the second graphic element in a first direction according to the coordinates of the first pixel point and the coordinates of a second pixel point corresponding to the first pixel point; determining a second offset of an etching contour of the second graphic element in a first direction according to the coordinates of a first pixel point adjacent to the first pixel point and the coordinates of a second pixel point corresponding to the first pixel point adjacent to the first pixel point; calculating a size in the first direction corresponding to the second offset pixel block according to the first offset, the second offset, and a preset gradient value; taking the first pixel point as a starting pixel point, determining the number of first pixels of the same size and continuous in the first direction, and determining the second offset based on the number The size of the second direction corresponding to the pixel block; the first direction intersects with the second direction, and the second direction is parallel to the tangent direction of the boundary; based on the coordinates of the first pixel point, the size of the first direction and the size of the second direction corresponding to the second offset pixel block, determine the area of ​​the second offset pixel block corresponding to the first pixel point; repeatedly determine the first offset of the etching outline of the second graphic element in the first direction according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point; determine the second offset of the etching outline of the second graphic element in the first direction according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point to determine the area of ​​the second offset pixel block corresponding to the first pixel point based on the coordinates of the first pixel point, the size of the first direction and the size of the second direction corresponding to the second offset pixel block, and determine all second offset pixel blocks on the boundary, wherein each second offset pixel block is adjacent to each other.

[0010] According to an embodiment of the present disclosure, the size of the first direction corresponding to the second offset pixel block is calculated based on the first offset, the second offset and the preset gradient value, including: when the difference between the first offset and the second offset is less than or equal to the preset gradient value, the first offset is determined as the size of the second offset pixel block corresponding to the first direction; when the difference between the first offset and the second offset is greater than the preset gradient value, the difference between the first offset and the preset gradient value is determined as the size of the second offset pixel block corresponding to the first direction.

[0011] According to an embodiment of the present disclosure, a second correction layout is generated based on the layout to be corrected and the second offset pixel block, including: using the boundary line in the layout to be corrected adjacent to the second offset pixel block as the axis of symmetry to perform an inversion operation on the second offset pixel block to obtain a mirrored second offset pixel block; the difference between the layout to be corrected and the mirrored second offset pixel block of each graphic element is the second correction layout.

[0012] The second aspect of the present disclosure provides a large-scale electron beam proximity effect and etching load effect joint correction method, including: based on the electron beam proximity effect, respectively correcting initial layouts with different density distributions to obtain multiple first corrected layouts, the first corrected layout is a layout after compensating the initial layout for a first contour offset caused by the electron beam proximity effect; based on the etching load effect, respectively correcting the initial layouts with different density distributions to obtain multiple second corrected layouts, the second corrected layout is a layout after compensating the initial layout for a second contour offset caused by the etching load effect; respectively performing intersection processing on the first corrected layout and the second corrected layout corresponding to the initial layout with the same density distribution to obtain multiple joint corrected layouts; inputting the initial layouts with different density distributions and the multiple joint corrected layouts into a generative adversarial network for multiple iterative training until the convergence condition is met, and obtaining a trained generative adversarial network; inputting the layout to be corrected into the trained generative adversarial network, and outputting a target joint corrected layout.

[0013] A third aspect of the present disclosure provides a mask plate, which is prepared based on a joint correction layout, wherein the size of each graphic element in the mask pattern of the mask plate is within a preset size range, and the joint correction layout is obtained using the above-mentioned joint correction method.

[0014] The method for jointly correcting the electron beam proximity effect and the etching load effect provided by the embodiments of the present disclosure has at least the following beneficial effects:

[0015] This method can accurately predict and compensate for the profile deviation caused by the electron beam proximity effect by calculating the energy distribution of each grid based on the point spread function of the layout to be corrected. At the same time, by analyzing the difference between the actual etching profile and the designed profile, the profile deviation caused by the etching load effect is determined and compensated. This method takes into account the influence of the electron beam proximity effect and the etching load effect at the same time, and optimizes the mask pattern of the mask. It can accurately compensate for the errors caused by the two effects, thereby improving the quality of the mask. Compared with the traditional single effect correction method, this method not only solves the error accumulation caused by ignoring the potential problems caused by another effect, but also ensures that the final mask is as close to the design specifications as possible.

[0016] This method uses joint correction layouts with different density distributions as sample sets to iteratively train the generative adversarial network to obtain a trained generative adversarial network model. This model can automatically learn complex patterns and relationships in a large number of data sets, intelligently integrate the correction results of the electron beam proximity effect and the etching load effect, and generate an optimal layout that comprehensively considers the influence of the two effects. In this way, not only can large-scale layout data be processed quickly and accurately, improving work efficiency, but it can also adapt to different design requirements and changes in process conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0018] Figure 1 Schematically shows a flowchart of a method for jointly correcting electron beam proximity effect and etching load effect according to an embodiment of the present disclosure;

[0019] Figure 2 Schematically shows a flowchart of a method for jointly correcting electron beam proximity effect and etching load effect according to another embodiment of the present disclosure;

[0020] Figure 3 Schematically shows a flowchart of a method for generating a first corrected layout according to an embodiment of the present disclosure;

[0021] Figure 4 Schematically shows a flowchart of a method for generating a second corrected layout according to an embodiment of the present disclosure;

[0022] Figure 5 Schematically shows a flowchart of a method for generating a second offset pixel according to an embodiment of the present disclosure;

[0023] Figure 6 Schematically shows a schematic diagram of a local area of a layout to be corrected and a corresponding etching area according to an embodiment of the present disclosure;

[0024] Figure 7 Schematically shows a schematic diagram of an etching deviation of a graphic element according to an embodiment of the present disclosure;

[0025] Figure 8 Schematically shows a schematic diagram of an etching deviation inversion operation of a graphic element according to an embodiment of the present disclosure;

[0026] Fig. 9 Schematically shows a schematic diagram of a graphic element correction according to an embodiment of the present disclosure;

[0027] Fig.10 Schematically shows a schematic diagram of a jointly corrected layout according to an embodiment of the present disclosure;

[0028] Fig.11 Schematically shows a comparison diagram of a mask pattern etched based on an original layout and a jointly corrected layout according to an embodiment of the present disclosure;

[0029] Fig.12 Schematically shows a schematic diagram of a method for jointly correcting a large-scale layout according to an embodiment of the present disclosure;

[0030] Fig.13The figure schematically shows a structure diagram of a generative adversarial network according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known systems and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0032] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0033] pass Figures 1 to 13 The joint correction method of the embodiment of the present disclosure is described in detail.

[0034] Figure 1 The flowchart of the joint correction method of the electron beam proximity effect and the etching load effect according to an embodiment of the present disclosure is schematically shown.

[0035] like Figure 1 As shown, the joint correction method of this embodiment includes steps S110 to S140.

[0036] Step S110: Correcting the layout to be corrected based on the electron beam proximity effect to obtain a first corrected layout, where the first corrected layout is a layout obtained after compensating the layout to be corrected for a first contour offset caused by the electron beam proximity effect.

[0037] Step S120: Correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout, where the second corrected layout is a layout obtained after compensating the layout to be corrected for a second contour offset caused by the etching load effect.

[0038] Step S130: performing intersection processing on the first correction layout and the second correction layout to obtain a joint correction layout.

[0039] Step S140: preparing a mask based on the joint correction pattern, wherein the size of each graphic element in the mask pattern of the mask is within a preset size range.

[0040] In the embodiments of the present disclosure, the electron beam proximity effect refers to the phenomenon that when using electron beam direct writing technology for lithography, due to electron scattering, the resist around the design pattern is also affected by exposure. This effect can cause a deviation between the actual pattern and the design pattern. The etching load effect refers to the pattern distortion phenomenon caused by the difference in etching rates in different density areas during the etching process. For example, in high-density areas, etching liquid or gas is difficult to reach, which may lead to insufficient etching; while in low-density areas, over-etching may occur.

[0041] At present, the commonly used method for the above-mentioned electron beam proximity effect is to compensate for the influence of the electron beam proximity effect by adjusting the exposure dose, or to compensate for the electron beam proximity effect by changing the pattern shape. The commonly used method for the above-mentioned etching load effect is to change the etching process parameters or deposit a barrier layer to weaken the influence of the load effect. However, these methods fail to comprehensively consider the pattern distortion problem caused by the simultaneous action of the electron beam proximity effect and the etching load effect. In fact, these two effects often exist simultaneously in the mask preparation process, and treating one of the effects alone cannot completely eliminate the distortion defects of the final prepared mask.

[0042] Based on this, in order to effectively solve the problem of mask pattern distortion caused by the electron beam proximity effect and the etching load effect, the present disclosure proposes a joint correction method. The method first corrects the layout to be corrected based on the electron beam proximity effect to generate a first correction layout. Then, the layout to be corrected is corrected again based on the etching load effect to obtain a second correction layout. Then, by performing intersection processing on the first correction layout and the second correction layout, a joint correction layout that comprehensively considers the influence of the two effects is generated. And a mask is made according to this joint correction layout to ensure that the size of each graphic element in the mask pattern is within the preset size range, and the optimization of the layout to be corrected is completed.

[0043] Among them, profile deviation refers to the position deviation between the designed pattern and the actual formed pattern due to the influence of the electron beam proximity effect or the etching load effect in the actual manufacturing process. Specifically, the first profile deviation caused by the electron beam proximity effect is due to the change in the exposure amount of the resist around the designed pattern caused by electron scattering, which causes the position of the actual pattern to move relative to the designed pattern. The second profile deviation caused by the etching load effect is due to the difference in etching rates in different regions, such as the difference between high-density areas and low-density areas, which causes changes in the actual pattern size or shape.

[0044] According to the embodiments of the present disclosure, this joint correction method can achieve efficient correction of electron beam proximity effect and etching load effect without changing the electron beam exposure dose and plasma etching process conditions used for the same mask, and effectively solves the limitations of traditional methods caused by not comprehensively considering multiple effects.

[0045] Figure 2 A flow chart of a method for jointly correcting electron beam proximity effect and etching load effect according to another embodiment of the present disclosure is schematically shown.

[0046] like Figure 2 As shown, the joint correction method of this embodiment also includes steps S150 to S160.

[0047] Step S150: When the size of each graphic element in the mask pattern of the mask plate is outside the preset size range, the joint correction layout is supplemented based on the etching load effect, and the supplemented joint correction layout is intersected with the first correction layout to generate a new joint correction layout.

[0048] Step S160: iterate in this way until the size of each graphic element in the mask pattern of the mask plate prepared based on the new joint correction pattern is within a preset size range.

[0049] In an embodiment of the present disclosure, if it is checked that the sizes of all graphic elements on the mask plate generated based on the current joint correction layout do not meet the requirements of the preset size range, the current joint correction layout is corrected based on the etching load effect to generate a new second correction layout. The new second correction layout is intersected with the first correction layout to generate a new joint correction layout. Step S150 is repeated until the size of each graphic element in the mask pattern of the mask plate generated based on the new joint correction layout is within the preset size range.

[0050] In some possible embodiments, the size deviation between each graphic element in the mask pattern of the mask plate generated based on the new joint correction layout and each graphic element designed in the layout to be corrected is ±5%.

[0051] According to the embodiments of the present disclosure, through continuous evaluation and optimization, this method effectively solves the limitations that may be caused by single effect correction and provides strong support for modern semiconductor manufacturing.

[0052] Figure 3 The flowchart of the method for generating a first correction layout according to an embodiment of the present disclosure is schematically shown.

[0053] like Figure 3 As shown, the method of this embodiment includes steps S210 to S230.

[0054] Correcting the layout to be corrected based on the proximity effect of the electron beam to obtain a first corrected layout, including:

[0055] Step S210: Gridding the layout to be corrected, etc., to determine the point spread function of the energy distribution in the electron beam resist and the initial electron beam exposure dose of each grid when the electron beam resist is subjected to electron beam direct writing exposure of a unit dose.

[0056] Step S220: determining a first offset pixel block in the non-patterned area based on the point spread function and the electron beam initial exposure dose of each grid, so as to compensate for the first contour offset caused by the electron beam proximity effect.

[0057] Step S230: generating a first correction layout according to the layout to be corrected and the first offset pixel block.

[0058] In the embodiment of the present disclosure, the layout to be corrected is divided according to preset rules to form a series of grids of equal size. The acceleration voltage, beam spot diameter, number of simulated electrons, material thickness of the electron beam resist and substrate, and material properties of the electron beam direct writing exposure are set, and the electron beam Monte Carlo simulation is performed according to the above parameters to obtain the forward scattering range α (nm) and back scattering range β (nm) of the electron beam, as well as the energy ratio η of the forward scattering to the back scattering.

[0059] Based on the double Gaussian function, the point spread function F(r) of the energy distribution in the electron beam resist is calculated when the unit dose of electron beam direct writing exposure is used. It can be used to express the relationship between the energy generated by a single electron beam exposure point in the electron beam resist and the attenuation of the energy with the distance. The expression is as follows:

[0060]

[0061] Through the point spread function, the energy contribution of each grid to other surrounding grids can be calculated, so as to evaluate the energy superposition caused by the electron beam proximity effect in the entire pattern area. Based on the above energy analysis, the point spread function and the initial exposure dose information of each grid are used to predict and quantify the impact of the electron beam proximity effect on the non-patterned area, and then determine the displacement of these areas caused by electron beam scattering, that is, the first offset pixel block.

[0062] For each first offset pixel block identified as being affected by the electron beam proximity effect, the size, shape or relative position of the graphic elements around it is adjusted accordingly to ensure that the final pattern is as close as possible to the design specifications under the ideal state.

[0063] According to the embodiments of the present disclosure, by systematically analyzing and correcting the layout to be corrected, this method effectively solves the proximity effect problem commonly seen in electron beam lithography technology and improves the accuracy and reliability of the micro-nano manufacturing process.

[0064] Furthermore, the total effective exposure dose E of any grid p is calculated based on the point spread function and the initial exposure dose of the electron beam of each grid: p , which is expressed as follows:

[0065]

[0066] in, is the energy distribution point spread function at a distance r from the grid p, is the initial exposure dose at a distance r from grid p, N is the number of grids in the x direction of the layout, M is the number of grids in the y direction of the layout, the initial exposure dose of each grid is the same and is the minimum exposure dose that can ensure that all graphics in the layout can reach the development threshold.

[0067] The total effective exposure dose E of any grid p is calculated by p The energy distribution of the entire layout to be corrected can be obtained.

[0068] Further, determine the position of the non-graphic area in the layout to be corrected , which is expressed as follows:

[0069]

[0070] The total effective exposure dose E based on the position of the non-pattern area and any grid p p Calculate the energy distribution E in the non-graphic area q , which is expressed as follows:

[0071]

[0072] According to the development threshold E th , determine the area that needs to be corrected for proximity effects , which is expressed as follows:

[0073]

[0074] Will The grid is used as the offset pixel block for the electron beam proximity effect. The offset pixel block is inverted with the boundary line of the adjacent original layout as the symmetry axis. The initial layout for electron beam proximity effect correction is obtained by subtracting the offset pixel block from the original layout. .

[0075] Figure 4 The flowchart of the method for generating a second correction layout according to an embodiment of the present disclosure is schematically shown.

[0076] like Figure 4 As shown, the method for generating a second correction layout in this embodiment includes steps S310 to S330.

[0077] Correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout, including:

[0078] Step S310: forming a light shielding layer and an electron beam resist in sequence on the surface of the mask substrate.

[0079] Step S320: performing electron beam direct writing exposure and development on the electron beam resist based on the layout to be corrected, and etching the light shielding layer to obtain an initial mask.

[0080] Step S330: obtaining a second offset pixel block between the etched contour of each graphic element in the mask pattern of the initial mask and the contour of each corresponding graphic element in the layout to be corrected, so as to compensate for the second contour offset caused by the etching load effect.

[0081] Step S340: Generate a second correction layout according to the layout to be corrected and the second offset pixel block.

[0082] In an embodiment of the present disclosure, an initial mask is obtained by preparing a pattern on a quartz glass deposited with a light-shielding material based on the layout to be corrected using electron beam direct writing exposure and plasma etching technology. The etching profile of each graphic element in the initial mask is extracted by a contour extraction method, and the extracted etching profile is compared with the profile of the corresponding graphic element in the layout to be corrected to determine the etching deviation, that is, the second offset pixel block. Finally, combined with the original layout to be corrected, an accurate second correction layout is generated, which can effectively compensate for the profile deviation caused by the etching load effect.

[0083] Furthermore, a scanning electron microscope image of each graphic element in the initial mask is collected, and the collected image is processed into equal grids to facilitate quantification of etching deviations. Among them, the offset pixel block refers to the offset of a single graphic element from the corresponding graphic element in the layout to be corrected after etching is completed, and is composed of multiple grids.

[0084] Further, the light shielding material may include chromium, molybdenum, tantalum or molybdenum silicide.

[0085] According to the embodiments of the present disclosure, by introducing the second offset pixel block and adjusting the correction layout accordingly, the influence of the etching load effect on the final product can be significantly reduced, thereby improving the accuracy of pattern transfer.

[0086] Figure 5 The flowchart of the method for generating the second offset pixel according to the embodiment of the present disclosure is schematically shown.

[0087] like Figure 5 As shown, the method for generating the second offset pixel in this embodiment includes steps S410 to S430.

[0088] Obtaining a second offset pixel between an etched outline of each graphic element in the mask pattern of the initial mask and a corresponding graphic element outline in the layout to be corrected, comprising:

[0089] Step S410: determining the coordinates of the first pixel points of each first graphic element according to the contour of each first graphic element in the layout to be corrected.

[0090] Step S420: determining the second pixel coordinates of each second graphic element according to the etching profile of each second graphic element in the mask pattern of the initial mask; wherein one first graphic element corresponds to one second graphic element.

[0091] Step S430: For each first graphic element, determine a second offset pixel block of the first graphic element according to the coordinates of a first pixel point of the first graphic element and the coordinates of a second pixel point corresponding to the first pixel point.

[0092] In the embodiments of the present disclosure, a pixel point refers to a point constituting the outline of a single image element.

[0093] On the basis of determining the coordinates of the second pixel points of the etching profile of each second graphic element in the initial mask, the profile of the corresponding first graphic element in the to-be-corrected layout is placed in the same coordinate system as the etching profile based on each second graphic element. The offset of the etching profile of each second graphic element relative to the design expectation is calculated, that is, the second offset pixel block.

[0094] According to the embodiments of the present disclosure, based on each first graphic element, by comparing the difference between the etching profile and the design target, the offset is accurately quantified, thereby improving the accuracy of correction.

[0095] Further, step S430: for each first graphic element, determining a second offset pixel block of the first graphic element according to the coordinates of a first pixel point of the first graphic element and the coordinates of a second pixel point corresponding to the first pixel point, includes:

[0096] For each first pixel point on the boundary of the first graphic element in the layout to be corrected, a first offset of the etching profile of the second graphic element in the first direction is determined according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point.

[0097] A second offset of the etching profile of the second graphic element in the first direction is determined according to the coordinates of a first pixel point adjacent to the first pixel point and the coordinates of a second pixel point corresponding to the first pixel point adjacent to the first pixel point.

[0098] The size of the second offset pixel block in the first direction is calculated according to the first offset, the second offset and the preset gradient value.

[0099] Further, when the difference between the first offset and the second offset is less than or equal to a preset gradient value, the first offset is determined as the size of the second offset pixel block corresponding to the first direction.

[0100] When the difference between the first offset and the second offset is greater than the preset gradient value, the difference between the first offset and the preset gradient value is determined as the size of the second offset pixel block corresponding to the first direction.

[0101] Taking the first pixel point as the starting pixel point, the number of first pixel points with the same size and continuous in the first direction is determined, and the size of the second direction corresponding to the second offset pixel block is determined based on the number; the first direction intersects with the second direction, and the second direction is parallel to the tangent direction of the boundary.

[0102] Based on the coordinates of the first pixel point, the size of the second offset pixel block in the first direction and the size of the second direction corresponding to the first pixel point, the area of ​​the second offset pixel block corresponding to the first pixel point is determined.

[0103] Repeat the process of determining the first offset of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point. Determine the second offset of the etching profile of the second graphic element in the first direction according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point. Based on the coordinates of the first pixel point, the size of the first direction and the size of the second direction corresponding to the second offset pixel block, determine the area operation of the second offset pixel block corresponding to the first pixel point, and determine all the second offset pixel blocks on the boundary, wherein each second offset pixel block is adjacent to each other.

[0104] In the embodiment of the present disclosure, based on each first graphic element in the layout to be corrected, the second graphic element in the mask pattern of the initial mask after etching is compared with the first graphic element in the layout to be corrected, wherein each first graphic element corresponds to each second graphic element one by one. An algorithm is used to search for the maximum offset point in the first direction between the etching profile and the same position in the layout to be corrected, that is, the second pixel point, and calculate the first offset h 1At this time, the first offset is the maximum offset in the graphic elements at the same position. And according to the first offset point, the second offset point adjacent to the grid corresponding to the first offset point is determined, that is, the second pixel point adjacent to the second pixel point, and the offset between the second offset point and the contour at the same position in the layout to be corrected, that is, the second offset h 2 The preset gradient value is set to t, and the gradient value can be nanometer level. Then the size D of the second offset pixel block in the first direction is v The expression is as follows:

[0105]

[0106] The size D of the second offset pixel block in the second direction h The expression is as follows:

[0107]

[0108] Among them, x i is the grid size, N is the size D in the first direction v The number of horizontal grids included. And so on, until all offset pixel blocks in the same direction are calculated.

[0109] For example, when calculating a second offset pixel block adjacent to a second offset pixel block on the boundary, the last first pixel point of the second offset pixel block in the second direction is used as the starting pixel point. Based on the starting pixel point, the size of the adjacent second offset pixel block in the first direction and the size of the adjacent second offset pixel block in the second direction are recalculated to further determine the area of ​​the adjacent second offset pixel block.

[0110] According to the embodiments of the present disclosure, it is possible to ensure that even in the presence of large local deviations, the impact of these deviations can be reduced through appropriate compensation mechanisms, thereby improving the accuracy and consistency of the final product. At the same time, it is also possible to more accurately capture significant deviations within a small range that occur during the actual manufacturing process and make targeted corrections. And by setting a preset gradient value t, the strength of the correction can be controlled to a certain extent to avoid new problems caused by overcorrection.

[0111] On the basis of the above embodiment, generating a second correction layout according to the layout to be corrected and the second offset pixel block includes:

[0112] An inversion operation is performed on the second offset pixel block using a boundary line in the to-be-corrected layout adjacent to the second offset pixel block as a symmetry axis to obtain a mirrored second offset pixel block.

[0113] The difference between the layout to be corrected and the second offset pixel block of the mirror image of each graphic element is the second corrected layout.

[0114] In an embodiment of the present disclosure, the boundary lines of each graphic element in the layout to be corrected are identified, and these boundary lines will serve as the axis of symmetry in the inversion operation. For each determined second offset pixel block, a mirror transformation is performed with its corresponding boundary line as the axis. This means that if a design error deviates in a certain direction in a certain graphic element, the inversion operation will generate a corresponding compensation amount in the opposite direction to offset this deviation. Finally, the difference between the layout to be corrected and the mirrored second offset pixel block of each graphic element is calculated. This difference actually represents the amount of adjustment that needs to be made to compensate for the etching load effect. In this way, a new layout, namely the second corrected layout, can be obtained.

[0115] According to the embodiments of the present disclosure, by accurately calculating and applying the inversion operation, the dimensional deviation caused by the etching load effect can be effectively compensated. Using the above correction method, potential manufacturing errors can be taken into account in the design stage, thereby reducing the need for later adjustments.

[0116] Figure 6 The schematic diagram schematically shows the local region of the layout to be corrected and the corresponding etching region according to an embodiment of the present disclosure. Figure 6 a is a schematic diagram of a sparse area in the layout to be corrected. Figure 6 b is Figure 6 a Schematic diagram of the corresponding etching area. Figure 6 c is a schematic diagram of a dense area in the layout to be corrected. Figure 6 d is Figure 6 c Schematic diagram of the corresponding etching area.

[0117] In some possible embodiments, the layout to be corrected is gridded, and the size of each grid can be set according to the process node and the optimization accuracy requirement, such as 1nm-10nm, wherein the size of the layout to be corrected is 3.5mm×3.5mm.

[0118] like Figure 6 As shown in a, 1 is a rectangular element with a size of 130nm×50nm. 2 is a non-graphic area. 3 is a square hole element with a size of 50nm×50nm. Figure 6 As shown in c, 4 is a square element with a period of 130nm and a size of 50nm×50nm.

[0119] The initial exposure dose of each grid can be set to 380μC / cm 2 , which can ensure that all graphic elements in the layout to be corrected can reach the development threshold. Among them, the development threshold is affected by the photoresist material, exposure parameters, development conditions, film characteristics, etc., and can be obtained through experiments.

[0120] The energy distribution of the non-graphic area in the layout to be corrected is calculated according to the above parameters. According to the energy development threshold of the electron beam resist, the area where the energy distribution in the non-graphic area reaches the development threshold is determined, and the adjacent layout elements of the graphic area are optimized to generate the first correction layout. .

[0121] Based on the layout to be corrected, a 38nm chromium layer can be deposited on a 6.35mm thick quartz substrate using chromium as a light shielding material. After subsequent spin-on, electron beam direct writing, development and plasma etching processes, the final pattern is formed on the quartz substrate to obtain the initial mask. Among them, the minimum etching time is to ensure that the etching of the graphic element with the slowest etching rate in the mask layout reaches the corresponding size of the target layout. Figure 6 As shown in b and d, where b is Figure 6 The image of a after etching, d is Figure 6 Image of c after etching. Due to the etching load effect, the rectangular elements and dense hole elements have increased line width and rounded corners after etching.

[0122] Figure 7 A schematic diagram schematically illustrates an etching deviation of a graphic element according to an embodiment of the present disclosure.

[0123] like Figure 7 As shown, Figure 6 Take the rectangular element 1 in b as an example. By designing a contour extraction algorithm, the edge contour of the pattern after etching is extracted and the coordinates of the contour pixel points are assigned. Then the corresponding position of the original layout is placed in the same coordinate system for comparison. Among them, 1-1 is the corresponding pattern of the original layout, 1-2 is the pixel point of the edge contour of the pattern etching, and 1-3 is the second offset pixel block.

[0124] Specifically, the outline of the graphic elements in the initial mask after etching is compared with the graphic elements at the same position in the original layout. Figure 7 As shown in the figure, taking the horizontal edge as an example, the innermost pixel point of the contour is calculated, and the algorithm is used to search for the maximum offset point x1 at the same position of the contour and the layout. According to the x1 point of the etched contour and the corresponding x2 point on the layout to be corrected, the first offset h is calculated. 1 And calculate the second offset h according to the next corresponding grid x3 and the corresponding x4 2 , setting the minimum optimization gradient to t, the size D of the second offset pixel block in the first direction v , that is, the longitudinal dimension D v as follows:

[0125]

[0126] The size of the second offset pixel block in the second direction, i.e., the horizontal size Dh for , where x i is the grid size, N is the same longitudinal dimension D v The number of second direction grids included below.

[0127] This process is repeated until all offset pixel blocks in the same direction are calculated (e.g. Figure 7 (as shown in 1-34, 1-33, 1-32, and 1-31).

[0128] Figure 8 A schematic diagram of an etching bias inversion operation of a graphic element according to an embodiment of the present disclosure is schematically shown.

[0129] like Figure 8 As shown, the offset pixel block is inverted with the boundary line of the adjacent to-be-corrected layout as the symmetry axis. The pixel block after symmetric inversion is as follows Figure 8 As shown, 1-4 are the second mirror image offset pixel blocks. Similarly, for the longitudinal edge of the rectangular element, and the transverse and longitudinal edges of the dense hole element, referring to the above steps, all the offset pixel blocks of the transverse and longitudinal edges of each element can be calculated.

[0130] Fig. 9 A schematic diagram of graphic element correction according to an embodiment of the present disclosure is schematically shown.

[0131] like Fig. 9 As shown, the corrected graphic element 1-6 is obtained by subtracting the corresponding second mirror offset pixel block 1-4 from the original graphic element 1-1 in the layout to be corrected, wherein the original second mirror offset pixel block 1-4 is converted into a non-graphic area 1-5 in the generated corrected layout after correction. Similarly, for each graphic element, the second corrected layout with etching load effect correction is obtained by subtracting the offset pixel block from the layout to be corrected. .

[0132] Fig.10 A schematic diagram of a joint correction layout according to an embodiment of the present disclosure is schematically shown.

[0133] First calibration layout and the second calibration layout Perform intersection processing to obtain the first joint correction map. Fig.10 As shown, Fig.10 The a in Figure 6 The layout of the rectangular element 1 in a after joint correction. Fig.10 b in Figure 6 c is the layout after the joint correction of the square hole 4. Among them, the edges of the rectangular elements and square elements in the layout to be corrected show a step morphology after the electron beam proximity effect and the etching load effect are jointly corrected.

[0134] Plasma etching is performed based on the first optimized layout to prepare the mask after the first optimization, and it is determined whether the etching size of each graphic element in the mask pattern of the mask reaches the design size of the graphic element in the layout to be corrected. If it has reached the design size, the optimization is completed. If it has not reached the design size, the second correction layout is updated, and a new joint correction layout is generated based on the updated second correction layout and the first correction layout. Until the error between the size of the graphic element in the mask prepared based on the new joint correction layout and the size of the design pattern is less than the deviation tolerance limit of ±5%.

[0135] Fig.11 The figure schematically shows a comparison of mask patterns etched based on the original layout and based on the joint correction layout according to an embodiment of the present disclosure. Fig.11 a is based on the original version Figure 1 Mask pattern for etching sparse areas, Fig.11 b is the mask pattern etched based on the same sparse area of ​​the joint correction layout. Fig.11 c is based on the original version Figure 1 Mask pattern for dense area etching, Fig.11 d is the mask pattern etched based on the same dense area of ​​the joint correction layout. Fig.11 e is based on the original version Figure 1 Mask pattern for etching of sparse square hole areas, Fig.11 f is the mask pattern etched based on the same sparse square hole area of ​​the joint correction pattern.

[0136] like Fig.11 As shown in the figure, after the joint correction and optimization of the electron beam proximity effect and the etching load effect, the mask has significant improvements in pattern line width, edge flatness, and line end corner rounding after plasma etching compared to before optimization, so that patterns of different densities and areas in the same mask can reach the target layout design size after etching under the same electron beam exposure dose and plasma etching conditions.

[0137] For comparison, only the long edges of the rectangular elements are optimized, while the short edges and hole elements are not optimized. Fig.11 As shown in a and b in the figure, the line width and edge flatness of the long side of the rectangular element are significantly improved after optimization, while the short edge and the edge of the hole element are still in an arc shape. After optimizing both the long and short edges of the rectangular element, the arc shape and line width of the line end are significantly improved, as shown in Fig.11 As shown in the embedded dotted line diagram in b.

[0138] like Fig.11As shown in c and d, the four edges of the dense square holes are optimized. Before optimization, the holes are etched in a circular shape with a larger size, while after optimization, they are shaped like square holes. The rounding of the corners is significantly improved, and the size of the holes reaches the target layout design value.

[0139] like Fig.11 As shown in Figures e and f, the four edges of the sparse square hole are optimized. After optimization, the edge morphology, flatness, corner rounding and hole size are significantly improved.

[0140] Fig.12 A schematic diagram of a method for large-scale layout joint correction according to an embodiment of the present disclosure is schematically shown.

[0141] like Fig.12 As shown, the large-scale layout joint correction method of this embodiment includes steps S510 to S540.

[0142] Step S510: Based on the electron beam proximity effect, the initial layouts with different density distributions are corrected respectively to obtain multiple first corrected layouts, where the first corrected layout is a layout after compensating the initial layout for the first contour offset caused by the electron beam proximity effect. The principle of this step is the same as step S110 and will not be repeated here.

[0143] Step S520: Based on the etching load effect, the initial layouts with different density distributions are corrected to obtain multiple second corrected layouts, where the second corrected layouts are layouts after compensating the initial layout for the second contour offset caused by the etching load effect. The principle of this step is the same as step S120 and will not be repeated here.

[0144] Step S530: Perform intersection processing on the first correction layout and the second correction layout corresponding to the initial layout with the same density distribution to obtain multiple joint correction layouts. The principle of this step is the same as that of step S110, and will not be repeated here.

[0145] Step S540: Inputting the initial layout with different density distributions and multiple joint correction layouts into the generative adversarial network for multiple iterative training until the convergence condition is met to obtain a trained generative adversarial network.

[0146] Step S550: input the to-be-corrected layout into the trained generative adversarial network, and output the target joint-corrected layout.

[0147] In the embodiments of the present disclosure, in a large-scale mask layout, there are graphic elements of different sizes and different density distributions. Under the same electron beam exposure dose, if the graphic with the smallest area or sparse distribution is guaranteed to obtain the best exposure dose, the exposure dose obtained by the graphic elements with large area or dense distribution will be excessive, which will eventually lead to an increase in the line width of the graphic. In addition, during the plasma etching process, due to the inconsistent etching rates of graphic elements with different sizes and different density distributions during the etching process, under the same etching conditions, if the graphic with the smallest area or sparse distribution is guaranteed to be etched to the target layout design size, the graphic elements with large area or dense distribution will deviate from the target layout design size after etching.

[0148] Based on this, the initial layouts with different density distributions and multiple joint correction layouts generated based on the initial layouts with different density distributions are input into the generative adversarial network for multiple iterative training to obtain the trained generative adversarial network. Finally, according to the specified input method, the generative adversarial network can generate a joint correction layout for the electron beam proximity effect and the etching load effect of any large-scale mask layout.

[0149] Fig.13 The figure schematically shows a structure diagram of a generative adversarial network according to an embodiment of the present disclosure.

[0150] Specifically, if Fig.13As shown in Figure 1, the generative adversarial network includes a generator and a discriminator. The generator uses convolutional layers and deconvolutional layers to construct an encoder-decoder structure, designs a U-Net jump connection structure, and fuses the feature map of the encoder with the feature map of the decoder through jump connections to retain more detailed information; residual blocks are added to the encoder and decoder to improve the network's expressiveness; LeakyReLU or ReLU is used as the activation function, and the output layer uses Sigmoid or Tanh functions. The discriminator uses multiple convolutional layers to extract features, gradually reduces the size of the feature map, and uses global average pooling instead of the fully connected layer in the last layer to reduce the number of parameters; LeakyReLU is used as the activation function, and the output layer uses the Sigmoid function. The initial layout with different density distributions is input into the generator, and the graphic elements in the layout are encoded through a series of convolutional layers and activation functions, and then the graphic elements are decoded through a series of deconvolutional layers and activation functions. The potential space vector is mapped to the data space to obtain a generated layout and input into the discriminator. At the same time, the layout corresponding to the initial layout after joint correction is rotated, flipped and other enhancement operations are performed, and then input into the discriminator as the optimized sample set. Through a series of convolutional layers and activation functions, the features of the input samples are extracted for comparison, and the binary cross entropy loss is used to distinguish the layout generated by the generator from the real optimized layout. The discriminator determines the difference between the layout generated by the generator network and the optimized sample set, calculates the loss function and updates the parameters, and provides feedback to the generator network. The generator adjusts its own parameters according to the feedback of the discriminator, and finally achieves the effect that the layout generated by the generator is difficult to distinguish from the real sample set, and obtains the trained generative adversarial network.

[0151] The present disclosure also provides a mask, which is prepared based on a joint correction layout, wherein the size of each graphic element in the mask pattern of the mask is within a preset size range, and the joint correction layout is obtained using the above-mentioned joint correction method. The principle of the joint correction method is the same as the above expression, and will not be repeated here.

[0152] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A joint correction method for electron beam proximity effect and etching loading effect, characterized in that: include: Correcting the layout to be corrected based on the electron beam proximity effect to obtain a first corrected layout, wherein the first corrected layout is a layout obtained after compensating the layout to be corrected for a first contour offset caused by the electron beam proximity effect; Correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout, wherein the second corrected layout is a layout obtained after compensating the layout to be corrected for a second contour offset caused by the etching load effect; Performing intersection processing on the first correction map and the second correction map to obtain a joint correction map; A mask is prepared based on the joint correction pattern, and the size of each graphic element in the mask pattern of the mask is within a preset size range.

2. The method according to claim 1, characterized in that Also includes: When the size of each graphic element in the mask pattern of the mask is outside the preset size range, supplementary correction is performed on the joint correction layout based on the etching load effect, and the supplementary corrected joint correction layout is intersected with the first correction layout to generate a new joint correction layout; The process is iterated in this way until the size of each graphic element in the mask pattern of the mask plate prepared based on the new joint correction pattern is within a preset size range.

3. The method according to claim 1, characterized in that The method of correcting the layout to be corrected based on the proximity effect of the electron beam to obtain a first corrected layout includes: Gridding the to-be-corrected layout, etc., to determine the point spread function of energy distribution in the electron beam resist and the initial electron beam exposure dose of each grid when the electron beam resist is subjected to electron beam direct writing exposure of a unit dose; Determine a first offset pixel block in the non-patterned area of ​​the to-be-corrected layout based on the point spread function and the initial exposure dose of the electron beam of each grid, so as to compensate for the first profile offset caused by the proximity effect of the electron beam; A first correction layout is generated according to the layout to be corrected and the first offset pixel block.

4. The method according to claim 1, characterized in that: The method of correcting the layout to be corrected based on the etching load effect to obtain a second corrected layout includes: forming a light shielding layer and an electron beam resist in sequence on a surface of a mask substrate; Based on the layout to be corrected, the electron beam resist is subjected to electron beam direct writing exposure and development, and the light shielding layer is subjected to etching processing to obtain an initial mask; Obtaining a second offset pixel block between the etched contour of each graphic element in the mask pattern of the initial mask and the contour of each corresponding graphic element in the to-be-corrected layout, so as to compensate for the second contour offset caused by the etching load effect; A second correction layout is generated according to the layout to be corrected and the second offset pixel block.

5. The method according to claim 4, characterized in that The second offset pixel block between the etched outline of each graphic element in the mask pattern of the initial mask and the outline of each corresponding graphic element in the to-be-corrected layout comprises: Determine the coordinates of the first pixel points of each first graphic element according to the outline of each first graphic element in the to-be-corrected layout; Determining the coordinates of the second pixel points of each second graphic element according to the etching profile of each second graphic element in the mask pattern of the initial mask; wherein one first graphic element corresponds to one second graphic element; For each first graphic element, a second offset pixel block of the first graphic element is determined according to coordinates of a first pixel point of the first graphic element and coordinates of a second pixel point corresponding to the first pixel point.

6. The method according to claim 5, characterized in that The step of determining, for each first graphic element, a second offset pixel block of the first graphic element according to a coordinate of a first pixel point of the first graphic element and a coordinate of a second pixel point corresponding to the first pixel point comprises: For each first pixel point on the boundary of the first graphic element in the to-be-corrected layout, a first offset of the etching contour of the second graphic element in the first direction is determined according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point; a second offset of the etching contour of the second graphic element in the first direction is determined according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point; Calculate a size in a first direction corresponding to the second offset pixel block according to the first offset, the second offset and a preset gradient value; Taking the first pixel point as a starting pixel point, determining the number of first pixel points of the same size and continuous in a first direction, and determining the size of the second offset pixel block in a second direction based on the number; the first direction intersects the second direction, and the second direction is parallel to the tangent direction of the boundary; Determine, based on the coordinates of the first pixel point, the size of the second offset pixel block in the first direction and the size of the second offset pixel block in the second direction corresponding to the first pixel point; Repeat the process of determining the first offset of the etching outline of the second graphic element in the first direction according to the coordinates of the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point; determining the second offset of the etching outline of the second graphic element in the first direction according to the coordinates of the first pixel point adjacent to the first pixel point and the coordinates of the second pixel point corresponding to the first pixel point adjacent to the first pixel point; and determining the area operation of the second offset pixel block corresponding to the first pixel point based on the coordinates of the first pixel point, the size of the first direction and the size of the second direction corresponding to the second offset pixel block, and determining all the second offset pixel blocks on the boundary, wherein each second offset pixel block is adjacent to each other.

7. The method according to claim 6, characterized in that The calculating, according to the first offset, the second offset and a preset gradient value, a size in the first direction corresponding to the second offset pixel block comprises: When the difference between the first offset and the second offset is less than or equal to the preset gradient value, the first offset is determined as the size of the second offset pixel block corresponding to the first direction; In a case where the difference between the first offset and the second offset is greater than the preset gradient value, the difference between the first offset and the preset gradient value is determined as the size of the second offset pixel block corresponding to the first direction.

8. The method according to claim 4, characterized in that The step of generating a second correction layout according to the layout to be corrected and the second offset pixel block includes: Taking the boundary line in the to-be-corrected layout adjacent to the second offset pixel block as the axis of symmetry, an inversion operation is performed on the second offset pixel block to obtain a mirrored second offset pixel block; The difference between the to-be-corrected layout and the mirrored second offset pixel block of each graphic element is a second corrected layout.

9. A large-scale electron beam proximity effect and etching loading effect joint correction method, characterized in that: include: Based on the electron beam proximity effect, initial layouts with different density distributions are corrected respectively to obtain a plurality of first corrected layouts, wherein the first corrected layouts are layouts after compensating the initial layout for a first contour offset caused by the electron beam proximity effect; Based on the etching load effect, the initial layouts with different density distributions are corrected respectively to obtain a plurality of second corrected layouts, wherein the second corrected layouts are layouts after compensating the initial layout for the second contour offset caused by the etching load effect; Performing intersection processing on the first correction layout and the second correction layout corresponding to the initial layout with the same density distribution respectively to obtain a plurality of joint correction layouts; Inputting the initial layout with different density distributions and the multiple joint correction layouts into a generative adversarial network for multiple iterative training until convergence conditions are met, thereby obtaining a trained generative adversarial network; The to-be-corrected layout is input into the trained generative adversarial network, and a target joint-corrected layout is output.

10. A mask, characterized in that: The mask is prepared based on a joint correction pattern, wherein the size of each graphic element in the mask pattern of the mask is within a preset size range, and the joint correction pattern is obtained by the method described in any one of claims 1-9.

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