Storage device and operating method of storage device

Abstract

The invention provides a storage device and an operation method of the storage device. The storage device includes: a multifunction controller configured to control a plurality of functions requested by a host; a power-off protection (PLP) capacitor configured to provide auxiliary power to the storage device; and a PLP controller configured to periodically monitor a state of the PLP capacitor and manage a performance list according to the state of the PLP capacitor, the performance list including a plurality of pieces of performance information supportable by the plurality of functions. The PLP controller is further configured to provide the performance list to the host in response to a first command received from the host, and to set a performance level for at least one function among the plurality of functions by adjusting internal resources of the storage device in response to a second command received from the host.

Description

Technical Field

[0001] The inventive concept relates to memory devices, and more particularly, to memory devices and methods of operating such memory devices. Background Art

[0002] Generally, a storage device including a nonvolatile memory and a controller operates by receiving power from the outside. A sudden power outage (SPO) in which the power supply is suddenly cut off may occur while the storage device is operating. In this case, because the controller buffers data by using a volatile memory, the data buffered in the volatile memory may be lost, or an erase operation or a write operation performed in the nonvolatile memory may not be completed. To solve this problem, the storage device completes the operation being performed by using an auxiliary power supply device including a capacitor, and backs up the data in the nonvolatile memory. Summary of the invention

[0003] The inventive concept provides a storage device, an operating method of such a storage device, and / or an operating method of a host, which support flexible power loss protection (PLP) by dynamically adjusting performance levels of multiple functions according to capacitor states.

[0004] According to an example embodiment conceived in the present invention, a storage device may include: a multi-function controller, which is configured to control multiple functions requested by a host; a power-loss protection (PLP) capacitor, which is configured to provide auxiliary power to the storage device; and a PLP controller, which is configured to periodically monitor the state of the PLP capacitor and manage a performance list based on the state of the PLP capacitor, the performance list including multiple performance information that the multiple functions can support, wherein the PLP controller is further configured to: provide the performance list to the host in response to a first command received from the host, and set a performance level for at least one of the multiple functions by adjusting internal resources of the storage device in response to a second command received from the host.

[0005] According to an example embodiment conceived in the present invention, a method for operating a storage device may include: periodically monitoring a state of a power-loss protection (PLP) capacitor included in the storage device; managing a performance list based on the state of the PLP capacitor, the performance list including multiple performance information supportable by multiple functions; receiving a first command for requesting the performance list from a host; sending the performance list to the host in response to the first command; receiving a second command from the host for setting a performance level for at least one function among the multiple functions; and setting the performance level for the at least one function by adjusting internal resources of the storage device in response to the second command.

[0006] According to an example embodiment conceived by the present invention, a host operation method may include: sending a first command for requesting a performance list to a storage device, the performance list including multiple performance information that can be supported by multiple functions; receiving the performance list from the storage device; setting a performance level for at least one of the multiple functions based on the performance list; and sending a second command including the performance level of the at least one function to the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram illustrating a storage system according to an example embodiment;

[0009] Figure 2 is a block diagram illustrating a storage controller according to an example embodiment;

[0010] Figure 3 An internal table representing the status of a power loss protection (PLP) capacitor is shown according to an example embodiment;

[0011] Figure 4A shows a performance table according to an example embodiment; Figure 4B shows an updated performance list according to an example embodiment;

[0012] Figure 5 is a diagram illustrating internal resource adjustments of various functions according to an example embodiment;

[0013] Fig. 6A and Figure 6B is a diagram illustrating a method of adjusting a PLP data size according to an exemplary embodiment;

[0014] Fig. 7A and Figure 7B is a diagram illustrating a method of adjusting a flushing cycle according to an example embodiment;

[0015] Figure 8 is a block diagram illustrating a storage system according to an example embodiment;

[0016] Figures 9 to 11 is a flowchart illustrating a method of operating a storage device according to some example embodiments;

[0017] Figure 12 to Figure 14 is a flow chart illustrating a method of operating a host according to some example embodiments;

[0018] Fig.15 is a diagram illustrating operations between a host and a storage device according to an example embodiment;

[0019] Fig.16 is a diagram illustrating operations between a host and a storage device according to an example embodiment;

[0020] Fig.17 is a diagram illustrating operations between a host, a memory controller, and a nonvolatile memory device according to an example embodiment;

[0021] Fig.18 is a block diagram illustrating a nonvolatile memory according to example embodiments;

[0022] Fig.19 is a diagram illustrating a system to which a storage device according to an example embodiment is applied;

[0023] Fig. 20 is a block diagram illustrating a solid state drive (SSD) system according to an example embodiment; and

[0024] Fig.21 is a diagram illustrating a data center to which a storage device according to example embodiments is applied. DETAILED DESCRIPTION

[0025] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same elements are represented by the same reference numerals, and repeated description thereof will be omitted.

[0026] As used herein, expressions such as "at least one" when used before a list of elements modify the entire list of elements, rather than the individual elements in the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0027] Figure 1 is a block diagram illustrating a storage system 10 according to an example embodiment.

[0028] refer to Figure 1, the storage system 10 may include a storage device 100 and a host 200, and therefore, the storage system 10 may be referred to as a host storage system. The storage device 100 may include a storage controller 110 and a non-volatile memory (NVM) 120. According to example embodiments, the storage controller 110 may be referred to as a controller, a memory controller, or an NVM controller.

[0029] In an example embodiment, multiple commands may be generated according to requests generated by multiple users of the host 200, and the generated multiple commands may be sent to the storage device 100. The storage device 100 may provide multiple responses corresponding to the multiple commands to the multiple users, respectively. For example, the host 200 may generate multiple virtual machines based on virtualization, and the multiple virtual machines may be assigned to multiple users. In the example, any one virtual machine may be assigned to a corresponding user among the multiple users, and each of the multiple users may provide commands to the storage device 100 through the assigned virtual machine. In this way, multiple users may share the storage device 100.

[0030] Recently, multi-host storage systems have been developed in which a single storage medium supports multiple hosts or multiple tenants (such as multiple virtual machines). For example, multifunctional technologies have been developed in which a single storage medium can operate with multiple devices. Multifunctional technologies can include technologies that provide multiple physical functions and single root input output virtualization (SR-IOV) technologies that provide multiple physical functions and multiple virtual functions by implementing multiple virtual functions with one physical function. When SR-IOV technology provides the same number of functions, it can reduce the implementation cost compared to multiple physical functions.

[0031] In this example embodiment, the storage controller 110 may include a multi-function controller 111, a power-off protection (PLP) capacitor 112, and a PLP controller 113. The multi-function controller 111 may generally control the operation of the storage controller 110, and may be implemented as, for example, a controller chip. In an example embodiment, the multi-function controller 111 may control a plurality of functions requested by the host 200. For example, the plurality of functions may include at least one physical function and / or at least one virtual function, which will be referred to as Figure 8 A more detailed description is given.

[0032] The PLP capacitor 112 may provide auxiliary power to the storage device 100. When a sudden power outage (SPO) occurs in the storage system 10, the PLP capacitor 112 may provide auxiliary power to the storage device 100, and thus may store write data received from the host 200 in the NVM 120. For example, the PLP capacitor 112 may include a plurality of capacitors. Figure 1The memory controller 110 includes the PLP capacitor 112 , but the inventive concept is not limited thereto. In some example embodiments, the PLP capacitor 112 may include at least one capacitor module having a plurality of capacitors and may be located outside the memory controller 110 .

[0033] The PLP controller 113 may periodically monitor the state of the PLP capacitor 112, and may manage a performance list including a plurality of pieces of performance information that may be supported by a plurality of functions according to the monitoring result (i.e., the state of the PLP capacitor 112). The storage device 100 may send the performance list to the host 200, and the host 200 may dynamically determine performance standards or performance levels corresponding to the plurality of functions, respectively, according to the state of the PLP capacitor 112 based on the performance list. The PLP controller 113 may adjust the internal resources of the storage device 100 according to the performance level of each function determined by the host 200, thereby setting the performance level of each function.

[0034] For example, when the first performance information corresponding to the first function among the multiple functions is equal to or greater than the reference value, the host 200 may increase the first performance level of the first function. In this case, the PLP controller 113 may increase the internal resources corresponding to the first function according to the first performance level determined by the host 200. For example, when the second performance information corresponding to the second function among the multiple functions is less than the reference value, the host 200 may reduce the second performance level of the second function. In this case, the PLP controller 113 may reduce the internal resources corresponding to the second function according to the second performance level determined by the host 200.

[0035] The host 200 may send a first command for requesting a performance list stored in the storage device 100 to the storage device 100. The storage device 100 may send the performance list to the host 200 in response to the first command received from the host 200. In this case, the performance list may include information about a performance level that the storage device 100 can support according to the current state of the PLP capacitor 112.

[0036] The host 200 may set a performance level for at least one of the multiple functions based on the performance list. For example, the host 200 may determine the performance level of each function by considering the priority or importance of the multiple functions. For example, the host 200 may determine the performance level of each function according to the characteristics of the tenants or users corresponding to the multiple functions respectively. In this case, the host 200 may determine the performance level of each function so that the sum of the performance levels of the multiple functions does not exceed the level that the storage device 100 can support.

[0037] The host 200 may send a second command to the storage device 100 to set a performance level for at least one function in the storage device 100. In response to the second command, the storage device 100 may set a performance level for the at least one function by adjusting internal resources of the storage device 100. For example, the storage device 100 may set a data size or a write buffer size for the at least one function by adjusting internal resources.

[0038] The host 200 may send an event notification request (e.g., an asynchronous event request (AER)) to the storage device 100 to receive notification according to the state change of the PLP capacitor 112. The storage device 100 may send an event notification response, such as an asynchronous event notification (AEN), to the host 200 according to the capacitor 112 state change.

[0039] In this way, the storage device 100 can update the performance list by regularly monitoring the state of the PLP capacitor 112, and can support flexible PLP by dynamically adjusting the multiple levels of multiple functions according to the settings of the host 200. In addition, the host 200 can adjust the performance levels of multiple functions respectively based on the updated performance list and the priorities of the multiple functions. Therefore, the storage system 10 can guarantee or ensure data integrity according to the current state of the PLP capacitor, thereby improving the reliability of the storage device 100.

[0040] The host 200 may include a host controller 210 and a host memory 220. The host controller 210 may manage an operation of storing data in a buffer of the host memory 220 in the NVM 120 or storing data in the NVM 120 in a buffer of the host memory 220. The host memory 220 may be used as a buffer memory for temporarily storing write data to be sent to the storage device 100 or read data to be sent from the storage device 100. In an example, the host controller 210 may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 220 may be an embedded memory provided in the application processor, or may be an NVM or memory module located outside the application processor.

[0041] In an example embodiment, the host 200 and the storage device 100 may communicate with each other based on an expected (or predetermined) interface. The expected (or predetermined) interface may support at least one of the following interfaces, such as, but not limited to, Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCI), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Universal Flash Storage (UFS), NVM Express (NVMe), or Compute Express Link (CXL).

[0042] The storage device 100 may include a storage medium for storing data according to a request from the host 200. For example, the storage device 100 may include at least one of a solid state drive (SSD), an embedded memory, or a removable external memory. When the storage device 100 is an SSD, the storage device 100 may be a device that complies with the NVMe standard. When the storage device 100 is an embedded memory or an external memory, the storage device 100 may be a device that complies with the universal flash memory (UFS) or embedded multimedia card (eMMC) standard. Both the host 200 and the storage device 100 may generate a data packet according to the adopted standard protocol, and may send the data packet.

[0043] When the NVM 120 of the storage device 100 includes a flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) vertical NAND (VNAND) memory array. In another example, the storage device 100 may include various other types of NVM. For example, the storage device 100 may include any of a magnetic random access memory (MRAM), a spin-transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, and various other types of memory. According to some example embodiments, the NVM 120 may include a plurality of memory chips, a plurality of memory dies, or a plurality of memory planes.

[0044] Figure 2 is a block diagram illustrating a memory controller 110 according to example embodiments.

[0045] refer to Figure 2, the storage controller 110 may include a multi-function controller 111, a PLP capacitor 112, a PLP controller 113, a buffer memory 114, a host interface (I / F) 115, and an NVM I / F 116. The multi-function controller 111, the PLP capacitor 112, the PLP controller 113, the buffer memory 114, the host I / F 115, and the NVM I / F 116 may communicate with each other via a bus 117. Hereinafter, the elements of the storage controller 110 will be described in detail.

[0046] The multi-function controller 111 may control a plurality of functions requested by the host 200. The multi-function controller 111 may include, for example, a central processing unit (CPU) or a microprocessor, and may control the overall operation of the storage controller 110. For example, the multi-function controller 111 may be implemented as a multi-core processor such as a dual-core processor or a quad-core processor.

[0047] The PLP controller 113 may periodically monitor the state of the PLP capacitor 112, and may manage a performance list including a plurality of pieces of performance information corresponding to a plurality of functions, respectively, according to the monitoring result (i.e., the state of the PLP capacitor 112). In this case, the performance list may include a data size and / or a write buffer size that is ensured or permitted for each function PLP. The PLP controller 113 may include a capacitor monitor 113a and a performance manager 113b.

[0048] When power is supplied to the storage controller 110, the capacitor monitor 113a may periodically monitor the state of the PLP capacitor 112. For example, the capacitor monitor 113a may periodically monitor the total capacitance of the PLP capacitor 112. For example, the capacitor monitor 113a may be implemented as a hardware module that performs a capacitor health monitoring (CHM) function. However, the inventive concept is not limited thereto, and the capacitor monitor 113a may be implemented by using software and / or firmware.

[0049] The performance manager 113b may manage a performance list including a plurality of pieces of performance information corresponding to a plurality of functions according to the state of the PLP capacitor 112. In this case, the performance manager 113b may manage the performance list so that the sum of the plurality of pieces of performance information corresponding to the plurality of functions is equal to or less than the range that the storage device 100 can support. The performance manager 113b may classify the state of the PLP capacitor 112 into an ultra-healthy state, an unhealthy state, and an unsecured state. For example, the performance manager 113b may be implemented as software. However, the inventive concept is not limited thereto, and the performance manager 113b may be implemented by using hardware and / or firmware. Reference will be made to Figures 3 to 7B The operation of capacitor monitor 113a and the operation of performance manager 113b are described in more detail.

[0050] The buffer memory 114 may temporarily store write data to be written to the NVM 120 or read data to be read from the NVM 120. According to the present example embodiment, the write buffer size of each function may be dynamically adjusted according to the state of the PLP capacitor 112. For example, when the state of the PLP capacitor 112 is equal to or greater than a reference value, the write buffer size may be increased, and when the state of the PLP capacitor 112 is less than the reference value, the write buffer size may be decreased. The buffer memory 114 may be an element provided in the storage controller 110, or may be an element located outside the storage controller 110. For example, the storage controller 110 may further include a buffer memory manager (not shown) or a buffer memory interface (not shown) for communicating with the buffer memory 114.

[0051] The host I / F 115 may transmit and receive data packets to and from the host 200. The data packets transmitted from the host 200 to the host I / F 115 may include commands or write data to be written to the NVM 120, etc., and the data packets transmitted from the host I / F 115 to the host 200 may include responses to commands or read data read from the NVM 120. The NVM I / F 116 may transmit write data to be written to the NVM 120, or may receive read data read from the NVM 120. The NVM I / F 116 may be implemented to comply with a standard protocol such as switching or an open NAND flash interface (ONFI).

[0052] In an example embodiment, the host I / F 115 may receive a first command (e.g., a get log page command) for requesting a performance list from the host 200, and may send the performance list to the host 200 in response to the first command. In an example embodiment, the host I / F 115 may receive a second command (e.g., a set feature command) for setting a performance level of each function from the host 200, and may send a response message to the host 200 in response to the second command. In an example embodiment, the host I / F 115 may receive a third command (e.g., a get feature command) for requesting the set performance level from the host 200, and may send a response for the performance level of each function to the host 200 in response to the third command, as described below with reference to FIG. Fig.15 and Fig.16 Described in detail.

[0053] In an example embodiment, the host I / F 115 may receive an event notification request (e.g., AER) from the host 200, and may send an event notification response (e.g., AEN) in response to a change in the state of the PLP capacitor 112 in response to the event notification request, as described below with reference to Fig.15 Described in detail.

[0054] Figure 3 An internal table IT representing the status of the PLP capacitors according to an example embodiment is shown.

[0055] Reference together Figure 2 and Figure 3 , the capacitor monitor 113a may monitor the state of the PLP capacitor 112 based on, for example, the total capacitance of the PLP capacitor 112. The performance manager 113b may manage an internal table IT representing the relationship between the PLP data size and the performance information according to the state of the PLP capacitor 112. The PLP data size may correspond to the data size that the PLP can ensure or permit. When a sudden power outage (SPO) occurs, write data corresponding to the PLP data size may be flushed from the buffer memory 114 to the NVM 120.

[0056] The internal table IT may divide the PLP data size based on the state of the PLP capacitor 112 into S0 to S10, and divide the performance information corresponding to the PLP data size into PI_0 to PI_10. For example, when the total capacitance of the PLP capacitor 112 corresponds to the reference capacitance, the state of the PLP capacitor 112 may correspond to the reference state. In this case, the PLP data size may be S2, and the performance information may correspond to PI_2 to ensure or achieve maximum performance. In an example embodiment, the maximum performance may vary according to the function. However, the inventive concept is not limited thereto, and in some example embodiments, the maximum performance may be the same for multiple functions.

[0057] For example, when the total capacitance of the PLP capacitor 112 is higher than the reference capacitance, the state of the PLP capacitor 112 may correspond to an ultra-healthy state. In this case, the PLP data size may be S0 or S1, and the performance information may correspond to PI_0 (ensuring or allowing performance to be 10% higher than the maximum performance) or PI_1 (ensuring or allowing performance to be 5% higher than the maximum performance).

[0058] For example, when the total capacitance of the PLP capacitor 112 is lower than the reference capacitance, the state of the PLP capacitor 112 may correspond to an unhealthy state. In this case, the PLP data size may be S3 or S4, and the performance information may correspond to PI_3 (ensuring or allowing performance to be 5% lower than the maximum performance) or PI_4 (ensuring or allowing performance to be 10% lower than the maximum performance). For example, when the total capacitance of the PLP capacitor 112 is much lower than the reference capacitance, the PLP data size may be S10, and the performance information may correspond to PI_10, which ensures or allows performance to be X% lower than the maximum performance (where X>10).

[0059] Figure 4AA performance list PL1 according to an example embodiment is shown.

[0060] Reference together Figures 1 to 4A , the performance list PL1 may include multiple pieces of performance information that can be supported by multiple functions. For example, the performance manager 113b may assign a standard index or an index to each of the multiple functions. For example, the performance manager 113b may assign an index to each of the multiple controllers. For example, the performance manager 113b may assign an index to each of the multiple virtual functions or the multiple physical functions.

[0061] The performance manager 113b may set a valid bit corresponding to each index based on the state of the PLP capacitor 112. In this case, the valid bit indicates whether the corresponding standard index is valid. For example, when the storage device 100 can support the function corresponding to the standard index, the valid bit may be set to 1, and when the storage device 100 does not support the function corresponding to the standard index, the valid bit may be reset to 0. For example, the performance manager 113b may initially set the valid bit to 1, and may change the valid bit to 0 or may maintain the valid bit to 1 according to the change in the state of the PLP capacitor 112.

[0062] The performance manager 113b may manage the PLP data size and performance information of each function according to the state of the PLP capacitor 112. The performance manager 113b may determine the PLP data size of each function so that the sum of the PLP data sizes respectively corresponding to the plurality of indexes does not exceed the level supportable by the PLP capacitor 112. The performance manager 113b may determine the performance level of each function so that the sum of the performance levels respectively corresponding to the plurality of indexes does not exceed the level supportable by the PLP capacitor 112.

[0063] For example, the performance manager 113b may determine the PLP data size corresponding to index 0 as S0, and may determine the performance information as PI_0 that ensures or permits performance to be 10% higher than the maximum performance. For example, the performance manager 113b may determine the PLP data size corresponding to index 1 as S1, and may determine the performance information as PI_1 that ensures or permits performance to be 5% higher than the maximum performance.

[0064] The host 200 may send a first command for requesting the performance list PL1 to the storage device 100, such as a get log page command. The storage device 100 may send the performance list PL1 to the host 200 in response to the first command. The host 200 may set a performance level for at least one function among the multiple functions based on the performance list PL1, and may send a second command (e.g., a set feature command) for setting the performance level for the at least one function to the storage device 100. The storage device 100 may set the performance level for the at least one function by adjusting internal resources in response to the second command. The storage device 100 may continue to monitor the state of the PLP capacitor 112 regularly, and may update the performance list PL1 when the state of the PLP capacitor 112 changes.

[0065] Figure 4B An updated performance list PL2 according to an example embodiment is shown.

[0066] Reference together Figures 1 to 4B Even after the performance list PL1 is generated, the capacitor monitor 113a may periodically monitor the state of the PLP capacitor 112, and the performance manager 113b may generate an updated performance list PL2 based on the state change of the PLP capacitor 112. For example, when the total capacitance of the PLP capacitor 112 decreases, the performance manager 113b may reset the valid bit corresponding to index 0 and the valid bit corresponding to index 1 to 0.

[0067] When the state of the PLP capacitor 112 changes, the storage device 100 may send an event notification to the host 200. The host 200 may send a first command including a request for an updated performance list PL2, such as a get log page command, to the storage device 100. The storage device 100 may send the updated performance list PL2 to the host 200 in response to the first command.

[0068] The host 200 may reset the performance level of each function based on the updated performance list PL2. For example, the host 200 may reset the performance level of the function corresponding to index 0 or index 1. The host 200 may send a command for resetting the performance level of each function, such as a set feature command, to the storage device 100. The storage device 100 may, in response to the second command, reset the performance level for each function by adjusting internal resources. For example, the storage device 100 may, in response to the second command, reset the performance level of the function corresponding to index 0 or index 1.

[0069] Figure 5 is a diagram illustrating internal resource adjustments of each function according to an example embodiment.

[0070] Reference together Figure 1 and Figure 5, the storage device 100 may adjust the internal resources RS for the multiple functions according to the settings of the host 200. For example, the host 200 may set the performance levels of the multiple functions respectively according to the priorities of the multiple functions. The storage device 100 may allocate the internal resources RS corresponding to the multiple functions to correspond to the performance levels respectively set by the host 200. The internal resources RS may include the PLP data size and / or the flushing cycle.

[0071] For example, the host 200 may set the performance level corresponding to the first function F1 to be higher than the performance level corresponding to the second function F2. In this case, the storage device 100 may allocate more internal resources RS corresponding to the first function F1 than to the internal resources RS corresponding to the second function F2. For example, the PLP data size corresponding to the first function F1 may be larger than the PLP data size corresponding to the second function F2. For example, the flushing period corresponding to the first function F1 may be longer than the flushing period corresponding to the second function F2. In addition, the storage device 100 may allocate internal resources RS to multiple functions respectively, and may manage the remaining internal resources RS as spare resources.

[0072] Fig. 6A is a diagram illustrating a method 61 of adjusting a PLP data size according to an example embodiment. Figure 6B is a diagram illustrating a method 62 of adjusting a PLP data size according to an example embodiment.

[0073] Reference together Figure 1 , Figure 5 and Fig. 6A , the host 200 may be based on a performance list (e.g., Figure 4A PL1 or Figure 4B The first performance level corresponding to the first function F1 is set in the PLP 611 of the storage device 100, and the PLP data size corresponding to the first function F1 can be set to the first PLP data size DS1 according to the first performance level. Therefore, the buffered data D1 corresponding to the first data size DS1 can be flushed from the buffer memory 611 to the NVM 612, and thus can be stored as the write data D11 in the NVM 612. Therefore, even when SPO occurs, the PLP can ensure or permit the buffered data D1 corresponding to the first data size DS1.

[0074] Reference together Figure 1 , Figure 5 and Figure 6B , the host 200 may be based on a performance list (e.g., Figure 4A PL1 or Figure 4BThe storage device 100 may set the second performance level corresponding to the second function F2 according to the second performance level (PL2), and the storage device 100 may set the PLP data size corresponding to the second function F2 to the second PLP data size DS2 according to the second performance level. Therefore, the buffered data D2 corresponding to the second data size DS2 may be flushed from the buffer memory 621 to the NVM 622, and thus may be stored as write data D21 in the NVM 622. Therefore, even when SPO occurs, the PLP may ensure or permit the buffered data D2 corresponding to the second data size DS2.

[0075] Fig. 7A is a schematic diagram illustrating a method 71 of adjusting a flush cycle according to an example embodiment. Figure 7B is a schematic diagram illustrating a method 72 of adjusting a flush cycle according to an example embodiment.

[0076] Reference together Figure 1 , Figure 5 and Fig. 7A , the host 200 may be based on a performance list (e.g., Figure 4A PL1 or Figure 4B The first performance level corresponding to the first function F1 is set according to the first performance level PL2 of the memory device 100, and the flushing period corresponding to the first function F1 can be set to the first period tP1 according to the first performance level. Therefore, data can be flushed from the buffer memory to the NVM according to the first period tP1. For example, the first flushing operation FOP11 to the fourth flushing operation FOP14 can be sequentially performed according to the first period tP1.

[0077] Reference together Figure 1 , Figure 5 and Figure 7B , the host 200 may be based on a performance list (e.g., Figure 4A PL1 or Figure 4B The second performance level corresponding to the second function F2 is set according to the second performance level PL2 of the memory device 100, and the flushing period corresponding to the second function F2 can be set to the second period tP2 according to the second performance level. Therefore, data can be flushed from the buffer memory to the NVM according to the second period tP2. For example, the first flushing operation FOP21 to the third flushing operation FOP23 can be sequentially performed according to the second period tP2.

[0078] Figure 8 is a block diagram illustrating a storage system 10a according to an example embodiment.

[0079] refer to Figure 8, the host 200a may include a physical function manager PM, a hypervisor HP, and first to fourth virtual machines VM1 to VM4. The storage device 100a may include a storage controller 110a and an NVM 120. The storage controller 110a may include a physical function PF, first to fourth virtual functions VF1 to VF4, a PLP capacitor 112, and a PLP controller 113. For ease of description, the description of the PLP capacitor 112 and the PLP controller 113 will not be described again. Figure 1 The same elements as those described.

[0080] For example, the physical function PF and the first virtual function VF1 to the fourth virtual function VF4 may be hardware, software, or a combination thereof configured to provide functions defined in the PCI-express interface standard. In some example embodiments, the physical function PF and the first virtual function VF1 to the fourth virtual function VF4 may be PCI-express functions supporting SR-IOV. In some example embodiments, the physical function PF and the first virtual function VF1 to the fourth virtual function VF4 may be sub-storage controllers. The sub-storage controller may be implemented as software, hardware, or a combination thereof. For example, the physical function PF may be a primary controller, and the first virtual function VF1 to the fourth virtual function VF4 may be an auxiliary controller.

[0081] For example, the host 200a may be configured to drive a plurality of virtual machines including a first virtual machine VM1 to a fourth virtual machine VM4. The first virtual machine VM1 to the fourth virtual machine VM4 may all be independently driven on the host 200a. For example, the first virtual machine VM1 to the fourth virtual machine VM4 may correspond to a corresponding user among a plurality of users including a first user to a fourth user or a corresponding tenant among a plurality of tenants including a first tenant to a fourth tenant. The hypervisor HP may be a logical platform configured to drive the first virtual machine VM1 to the fourth virtual machine VM4 on the host 200a. The first virtual machine VM1 to the fourth virtual machine VM4 may all be driven in the host 200a.

[0082] In an example embodiment, the physical function manager PM may communicate with the physical function PF, and the first virtual machine VM1 to the fourth virtual machine VM4 may communicate with the corresponding virtual functions of the first virtual function VF1 to the fourth virtual function VF4, respectively. In this case, the physical function manager PM may be a management host, and the first virtual machine VM1 to the fourth virtual machine VM4 may be a user host. For example, the physical function manager PM may send a management command to the physical function PF. Each of the first virtual machine VM1 to the fourth virtual machine VM4 may send a general command to the corresponding virtual function of the first virtual function VF1 to the fourth virtual function VF4.

[0083] The physical function PF can receive a general command or a management command generated by the physical function manager PM, and can process the general command or the management command. Each of the first virtual function VF1 to the fourth virtual function VF4 can receive a general command generated by a corresponding virtual machine among the first virtual machine VM1 to the fourth virtual machine VM4, and can process the general command. In this case, the first virtual function VF1 to the fourth virtual function VF4 can share physical resources, such as a link to the physical function PF and other virtual functions associated with the physical function PF. The first virtual function VF1 to the fourth virtual function VF4 can be a lightweight PCIe function, which can be directly accessed by the first virtual machine VM1 to the fourth virtual machine VM4, respectively.

[0084] The physical function manager PM and the first virtual machine VM1 to the fourth virtual machine VM4 may all be configured to access the storage device 100a. The first virtual machine VM1 may correspond to the first virtual function VF1, the second virtual machine VM2 may correspond to the second virtual function VF2, the third virtual machine VM3 may correspond to the third virtual function VF3, and the fourth virtual machine VM4 may correspond to the fourth virtual function VF4. In other words, the first virtual machine VM1 may communicate with the first virtual function VF1, the second virtual machine VM2 may communicate with the second virtual function VF2, the third virtual machine VM3 may communicate with the third virtual function VF3, and the fourth virtual machine VM4 may communicate with the fourth virtual function VF4.

[0085] In an example embodiment, the first user or the first tenant may access the storage device 100a through the first virtual machine VM1, and therefore, the storage device 100a may process the first virtual function VF1 in response to a request of the host 200a. For example, the first user or the first tenant may dynamically select a desired performance level, such as the first performance level, through the first virtual machine VM1, and the host 200a may dynamically adjust the performance level of the first virtual function VF1 to the first performance level. For example, the first user or the first tenant may dynamically select a desired reliability, such as the first reliability, through the first virtual machine VM1, and the host 200a may dynamically adjust the reliability of the first virtual function VF1 to the first reliability.

[0086] Likewise, the second user or second tenant may access the storage device 100a through the second virtual machine VM2, and therefore, the storage device 100a may process the second virtual function VF2 in response to a request from the host 200a. For example, the second user or second tenant may dynamically select a performance level (e.g., a second performance level) and / or a desired reliability (e.g., a second reliability) through the second virtual machine VM2, and the host 200a may dynamically adjust the performance level of the second virtual function VF2 to the second performance level, or may dynamically adjust the reliability of the second virtual function VF2 to the second reliability.

[0087] Likewise, a third user or a third tenant may access the storage device 100a through the third virtual machine VM3, and therefore, the storage device 100a may process the third virtual function VF3 in response to a request from the host 200a. For example, the third user or the third tenant may dynamically select a desired performance level (e.g., a third performance level) and / or a desired reliability (e.g., a third reliability) through the third virtual machine VM3, and the host 200a may dynamically adjust the performance level of the third virtual function VF3 to the third performance level, or may dynamically adjust the reliability of the third virtual function VF3 to the third reliability.

[0088] Likewise, a fourth user or a fourth tenant may access the storage device 100a through the fourth virtual machine VM4, and therefore, the storage device 100a may process the fourth virtual function VF4 in response to a request from the host 200a. For example, the fourth user or the fourth tenant may dynamically select a desired performance level (e.g., a fourth performance level) and / or a desired reliability (e.g., a fourth reliability) through the fourth virtual machine VM4, and the host 200a may dynamically adjust the performance level of the fourth virtual function VF4 to the fourth performance level, or may dynamically adjust the reliability of the fourth virtual function VF4 to the fourth reliability.

[0089] For example, the physical function PF may be a sub-storage controller corresponding to the physical function manager PM, and the first virtual function VF1 to the fourth virtual function VF4 may be sub-storage controllers corresponding to the first virtual machine VM1 to the fourth virtual machine VM4, respectively. However, the scope of the inventive concept is not limited thereto. In addition, for ease of explanation, although the terms "physical function" and "virtual function" are used, the physical function and the virtual function may be used interchangeably with the term "sub-storage controller". According to some example embodiments, Figure 1 The multi-function controller 111 may include a physical function PF and first to fourth virtual functions VF1 to VF4 .

[0090] In an example embodiment, the storage device 100a may support an SR-IOV function. SR-IOV may refer to a function in which a physical function supports one or more subordinate virtual functions. The storage device 100a may include a first virtual function VF1 to a fourth virtual function VF4, and may support multiple functions. For example, the physical function PF and the first virtual function VF1 to the fourth virtual function VF4 may be configured to process a command of a corresponding host (e.g., a virtual machine) or a command in a transmission queue managed by the corresponding host.

[0091] Fig. 9 is a flowchart illustrating an operating method of a storage device according to an example embodiment.

[0092] refer to Fig. 9 The operation method of the storage device according to this example embodiment may correspond to a method in which the storage device for providing multiple functions sets a performance level for each of the multiple functions according to the setting of the host. The operation method of the storage device according to this example embodiment may include: Figure 1 Operations performed in a time series manner in the storage device 100. Figures 1 to 8 The description made may be applicable to this exemplary embodiment.

[0093] In operation S110, the storage device 100 may periodically monitor the state of the PLP capacitor 112. In operation S120, the storage device 100 may manage the performance list according to the state of the PLP capacitor 112. In operation S130, the storage device 100 may receive a first command for requesting a performance list from the host 200. In operation S140, the storage device 100 may send the performance list to the host 200 in response to the first command.

[0094] In operation S150, the storage device 100 may receive a second command for setting a performance level for at least one function from the host 200. In operation S160, the storage device 100 may set a performance level for at least one function by adjusting internal resources in response to the second command. For example, the host 200 may generate a second command for setting a performance level and / or reliability for each tenant, and the storage device 100 may set a performance level or reliability of a function corresponding to a specific tenant in response to the second command. When a performance level is set for at least one function according to the second command and the sum of the performance levels of the plurality of functions exceeds a level that the PLP capacitor 112 can support, the storage device 100 may send an error message to the host 200. When operation S160 ends, operation S110 may be performed.

[0095] Fig.10 is a flowchart illustrating an operating method of a storage device according to an example embodiment.

[0096] refer to Fig.10 , the operating method of the storage device according to this example embodiment may correspond to Fig. 9 A modified example of the run method of Fig. 9 The operating method may further include operation S170 and operation S180. Fig. 9 The description made may be applicable to this example embodiment. In operation S170, the storage device 100 may receive a third command for requesting a performance level set for at least one function in the storage device 100 from the host 200. In operation S180, the storage device 100 may send the performance level set for at least one function to the host 200. When operation S180 ends, the storage device 100 may periodically monitor the state of the PLP capacitor 112 again (operation S110).

[0097] Fig.11 is a flowchart illustrating an operating method of a storage device according to an example embodiment.

[0098] refer to Fig.11 , the operating method of the storage device according to this example embodiment may correspond to the operating method of the storage device when the state of the PLP capacitor changes. The operating method of the storage device according to this example embodiment may include Figure 1 Operations performed in a time series manner in the storage device 100. Figures 1 to 8 The description made may be applicable to this exemplary embodiment.

[0099] In operation S210, the memory device 100 may periodically monitor the state of the PLP capacitor 112. For example, Fig. 9 Operation S210 is performed after operation S160. For example, Fig.10 Operation S210 is performed after operation S160 or operation S180. In operation S220, the storage device 100 may update the performance list according to the state of the PLP capacitor 112. For example, the storage device 100 may Figure 4A The performance list PL1 is updated to Figure 4B Performance list PL2.

[0100] In operation S230, the storage device 100 may determine whether the state of the PLP capacitor 112 has changed. When it is determined that the state of the PLP capacitor 112 has changed, in operation S240, the storage device 100 may send a state change event indicating that the state of the PLP capacitor 112 has changed to the host 200. When it is determined that the state of the PLP capacitor 112 has not changed, in operation S210, the storage device 100 may continue to periodically monitor the state of the PLP capacitor 112.

[0101] Fig.12 is a flowchart illustrating an operating method of a host according to an example embodiment.

[0102] refer to Fig.12 , the operation method according to this example embodiment may correspond to a method in which the host controls various functions of the storage device based on the monitoring result generated in the storage device according to the state of the PLP capacitor included in the storage device. For example, the operation method according to this example embodiment may include Figure 1 Operations performed in a time series manner in the host 200. Figures 1 to 8 The description made may be applicable to this exemplary embodiment.

[0103] In operation S310, the host 200 may send a first command for requesting a performance list stored in the storage device 100 to the storage device 100. In operation S320, the host 200 may receive the performance list from the storage device 100. In operation S330, the host 200 may set a performance level for at least one function among the multiple functions based on the performance list. For example, the host 200 may determine the performance level of each function by considering the priority or importance of the multiple functions. For example, the host 200 may determine the performance level of each function according to the characteristics of the tenants or users corresponding to the multiple functions respectively. For example, the host 200 may determine the performance level and / or reliability of each user or tenant. In this case, the host 200 may determine the performance level of each function so that the sum of the performance levels of the multiple functions does not exceed the level that the storage device 100 can support. In operation S340, the host 200 may send a second command including the performance level of at least one function to the storage device 100.

[0104] Fig.13 is a flowchart illustrating an operating method of a host according to an example embodiment.

[0105] refer to Fig.13 The operating method of the host according to this example embodiment may correspond to Fig.12 A modified example of the run method of Fig.12 Compared with the operating method of the present invention, the method may further include operation S350 and operation S360. Fig.12 In operation S350, the host 200 may send a third command for requesting a performance level set for at least one function in the storage device 100 to the storage device 100. In operation S360, the host 200 may receive the performance level set for at least one function from the storage device 100.

[0106] Fig.14 is a flowchart illustrating an operating method of a host according to an example embodiment.

[0107] refer to Fig.14 The operating method of the host according to this example embodiment may correspond to Fig.12 A modified example of the run method of Fig.12 Compared with the operation method of the present invention, the method may further include operation S370. Fig.12 The description may be applicable to the present exemplary embodiment. In operation S370, the host 200 may receive a state change event from the storage device 100. For example, the state change event may be an event indicating a state change of the PLP capacitor 112. For example, the state change event may be an event indicating that performance information of each function is changed due to a state change of the PLP capacitor 112. For example, the state change event may be an event indicating that an internal resource of each function is changed due to a state change of the PLP capacitor 112.

[0108] Fig.15 is a diagram illustrating operations between a host 200 and a storage device 100 according to an example embodiment.

[0109] Reference together Figure 1 and Fig.15 In operation S410, the storage device 100 may monitor the capacitor health status and manage a performance list. For example, the storage device 100 may periodically monitor the status of the PLP capacitor 112 through a capacitor health monitoring (CHM) function, and may manage a performance list including a plurality of performance information that may be ensured or permitted for a plurality of functions according to the monitoring result.

[0110] In operation S420, the host 200 may issue a get log page command for requesting a performance list stored in the storage device 100. For example, the get log page command may correspond to Fig.12 In operation S430, the host 200 may send a get log page command to the storage device 100. In operation S435, the storage device 100 may send a performance list to the host 200 in response to the get log page command.

[0111] In operation S440, the host 200 may issue a set feature command for setting a performance level for each function. For example, the set feature command may correspond to Fig.12For example, the host 200 may issue a set feature command for setting the performance level and / or reliability for each tenant. In operation S450, the host 200 may send the set feature command to the storage device 100. In operation S460, the storage device 100 may set the standard of each function (i.e., the performance level of each function) in response to the set feature command. In operation S470, the storage device 100 may send a response message to the host 200 indicating the result of the operation of setting the performance level for each function.

[0112] When the performance level is set for each function according to the set feature command and the sum of the performance levels of the plurality of functions exceeds the level that the PLP capacitor 112 can support, the storage device 100 may send an error message to the host 200. In addition, when the host 200 requests to set a performance level for a function that the storage device 100 may not support through the set feature command, the storage device 100 may send an error message to the host 200. For example, in Figure 4B In the performance list PL2, when a set feature command corresponding to a function corresponding to index 0 or index 1 whose valid bit is 0 is received, the storage device 100 may send an error message to the host 200.

[0113] In operation S480, the storage device 100 may monitor the capacitor health status and may update the performance list. For example, the storage device 100 may continue to periodically monitor the status of the PLP capacitor 112 through the CHM function, and may update the performance list by changing the performance information, valid bits, or PLP data size corresponding to at least one of the multiple functions according to the monitoring result.

[0114] In operation S485, the storage device 100 may determine whether the state of the capacitor has changed. When it is determined that the state of the capacitor has changed, in operation S490, the storage device 100 may send an asynchronous event notification (AEN) corresponding to the state change event to the host 200. When it is determined that the state of the capacitor has not changed, operation S480 may be performed.

[0115] Fig.16 is a diagram illustrating operations between a host 200 and a storage device 100 according to an example embodiment.

[0116] refer to Fig.16 , the operating method according to this example embodiment may correspond to Fig.15 Therefore, refer to Fig.15The description made may be applicable to this example embodiment. In operation S440a, the host 200 may issue a set feature command for setting the standard of each function (i.e., setting the performance level for each function). In operation S450, the host 200 may send the set feature command to the storage device 100. In operation S460, the storage device 100 may set the performance level for each function in response to the set feature command. In operation S470, the storage device 100 may send a response message indicating the result of the operation of setting the performance level for each function to the host 200.

[0117] In operation S471, the host 200 may issue a get feature command for checking feature values ​​set in the storage device 100. For example, the get feature command may correspond to Fig.13 The host 200 may send a get feature command to the storage device 100. In operation S475, the storage device 100 may send a response message including the feature value requested by the host 200 to the host 200 in response to the get feature command.

[0118] Fig.17 is a diagram illustrating operations among the host 200 , the storage controller 110 , and the NVM 120 according to an example embodiment.

[0119] refer to Fig.17 In operation S510, the storage controller 110 may periodically monitor the capacitor health status. In operation S520, the storage controller 110 may manage the performance list based on the capacitor health status. In operation S530, the host 200 may issue a write command. In operation S540, the host 200 may send write data and the write command to the storage controller 110. In operation S550, the storage controller 110 may buffer the write data in a buffer memory.

[0120] In operation S560, the storage controller 110 may determine whether an SPO has occurred. When it is determined that an SPO has not occurred, operation S510 may be performed. When it is determined that an SPO has occurred, in operation S570, the storage controller 110 may generate a write command. In operation S580, the storage controller 110 may send write data and a write command to the NVM 120. In operation S590, the NVM 120 may perform a write operation on the write data. In operation S595, the NVM 120 may send a response message including an operation result of performing the write operation to the storage controller 110. In this case, operations S570 to S590 may correspond to a flush operation.

[0121] Fig.18 is a block diagram illustrating the NVM 120 according to example embodiments.

[0122] refer to Fig.18 , NVM 120 may include a control logic circuit 121, a memory cell array 122, a page buffer circuit 123, a voltage generator 124, and a row decoder 125. NVM 120 may correspond to Figure 1 The NVM 120 of FIG. 120. The memory cell array 122 may include a plurality of memory blocks BLK1 to BLKz, each of which may include a plurality of cell strings, and each of which may include a plurality of memory cells connected in series. The memory cell array 122 may be connected to the page buffer circuit 123 through the bit lines BL, and connected to the row decoder 125 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0123] In example embodiments, the memory cell array 122 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of cell strings. Each cell string may include a memory cell connected to a word line vertically stacked on a substrate.

[0124] In example embodiments, the memory cell array 122 may include a flash memory, and the flash memory may include a 2D NAND memory array or a 3D vertical NAND (VNAND) memory array. In example embodiments, the memory cell array 122 may include any of a magnetic RAM (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, and various other types of memory.

[0125] The control logic circuit 121 may generally control various operations in the NVM 120. The control logic circuit 121 may output various control signals in response to the command CMD and / or the address ADDR. For example, the control logic circuit 121 may output a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR. According to the present example embodiment, the control logic circuit 121 may control the flushing operation according to the PLP data size and / or the flushing cycle set for each function.

[0126] The voltage generator 124 can generate various types of voltages for performing programming, reading and erasing operations based on the voltage control signal CTRL_vol. For example, the voltage generator 124 can generate a programming voltage, a reading voltage, a programming verification voltage and an erasing voltage as a word line voltage VWL. The row decoder 125 can select at least one word line of a plurality of word lines WL in response to the row address X_ADDR and can select a string selection line of a plurality of string selection lines SSL. For example, during a programming operation, the row decoder 125 can apply the word line voltage VWL to the selected word line during a search operation or a read operation. The page buffer circuit 123 can select at least one bit line among the bit lines BL in response to the column address Y-ADDR. The page buffer circuit 123 can be used as a write driver or a sense amplifier according to the operation mode.

[0127] Fig.19 is a diagram illustrating a system 1000 to which a storage device according to an example embodiment is applied.

[0128] Fig.19 The system 1000 may be a mobile system such as a mobile phone, a smart phone, a tablet computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, Fig.19 The system 1000 is not limited to a mobile system and may include a personal computer, a laptop, a server, a media player, or an automotive device such as a navigation device.

[0129] refer to Fig.19 , system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may further include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0130] The main processor 1100 may control the overall operation of the system 1000, and more specifically, control operations of other elements constituting the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0131] The main processor 1100 may include at least one CPU core 1110, and may further include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to some example embodiments, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data calculations such as artificial intelligence data calculations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other elements of the main processor 1100.

[0132] Memories 1200a and 1200b may be used as main memory devices of system 1000, respectively, and may include volatile memory such as SRAM and / or DRAM, but may also include NVM such as flash memory, PRAM and / or RRAM. Memories 1200a and 1200b may be implemented in the same package as main processor 1100.

[0133] The storage devices 1300a and 1300b may each be used as a non-volatile storage device that stores data regardless of whether power is supplied, and may have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and NVMs 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. The NVMs 1320a and 1320b may include flash memories having a 2D structure or a 3D vertical NAND (V-NAND) structure, but may include other types of NVMs such as PRAM and / or RRAM.

[0134] The storage devices 1300a and 1300b may be included in the system 1000 while being physically separated from the main processor 1100, or may be implemented in the same package as the main processor 1100. In addition, because the storage devices 1300a and 1300b have a form such as an SSD or a memory card, the storage devices 1300a and 1300b may be detachably coupled to other elements of the system 1000 via an interface (such as the connection interface 1480 described below). The storage devices 1300a and 1300b may be devices to which a standard protocol such as, but not limited to, universal flash memory (UFS), embedded multimedia card (eMMC), or non-volatile memory express (NVMe) is applied. Reference Figures 1 to 18 The described example embodiments may be implemented in storage devices 1300a and 1300b.

[0135] The image capture device 1410 can capture still images or moving images, and can be a camera, a video camera, and / or a webcam. The user input device 1420 can receive various types of data input from a user of the system 1000, and can be a touch pad, a keypad, a keyboard, a mouse, and / or a microphone. The sensor 1430 can detect various types of physical quantities obtained from the outside, and can convert the detected physical quantities into electrical signals. The sensor 1430 can be a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope sensor.

[0136] The communication device 1440 may transmit and receive signals to and from other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, and / or a modem. The display 1450 and the speaker 1460 may be used as output devices for outputting visual information and auditory information to a user of the system 1000, respectively. The power supply device 1470 may appropriately convert power supplied from a battery (not shown) included in the system 1000 and / or an external power source, and may supply power to each element of the system 1000.

[0137] The connection interface 1480 may provide a connection between the system 1000 and an external device connected to the system 1000 to transmit and receive data to and from the system 1000. The connection interface 1480 may be implemented in any of various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, MultiMediaCard (MMC), eMMC, UFS, Embedded Universal Flash (eUFS), or Compact Flash (CF) card interface.

[0138] Fig. 20 is a block diagram illustrating an SSD system 2000 according to example embodiments.

[0139] refer to Fig. 20, the SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 may send and receive signals to and from the host 2100 through a signal connector, and receive power through a power connector. The SSD 2200 may include an SSD controller 2210, an auxiliary power supply device 2220, and storage devices 2230, 2240, and 2250. The storage devices 2230, 2240, and 2250 may be vertically stacked NAND flash memory devices. Figures 1 to 18 The described example embodiments may be implemented in SSD 2200 .

[0140] The auxiliary power supply device 2220 may include Figure 1 , Figure 2 and Figure 8 In an example embodiment, the auxiliary power supply device 2220 may include a first capacitor module 2221 to an Nth capacitor module 222N. When SPO occurs in which the power PWR supplied from the host to the SSD 2200 is suddenly disconnected, the auxiliary power supply device 2220 may continue to perform the operation being performed by the SSD 2200 through the capacitors stored in the first capacitor module 2221 to the Nth capacitor module 222N, so that the operation is completed. Therefore, when SPO occurs, the auxiliary power supply device 2220 may prevent the loss of data to be stored in the SSD 2200.

[0141] Fig.21 is a diagram illustrating a data center 3000 to which a storage device according to example embodiments is applied.

[0142] refer to Fig.21 , the data center 3000 is a facility that collects various data and provides services, and may be referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used in a company such as a bank or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to some example embodiments, the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected in various ways, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0143] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. When the storage server 3200 is described as an example, the processor 3210 may control the overall operation of the storage server 3200, and may access the memory 3220 and may execute commands and / or data loaded into the memory 3220. The memory 3220 may be a DDR double data rate synchronous DRAM (SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an optane DIMM, and / or a non-volatile DIMM (NVMDIMM). According to some example embodiments, the number of processors 3210 and the number of memories 3220 included in the storage server 3200 may be selected in various ways. In an example embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an example embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The description of the storage server 3200 may be applicable to the application server 3100. According to some example embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. According to some example embodiments, the number of storage devices 3250 included in the storage server 3200 may be selected in various ways. Figures 1 to 18 The described example embodiments may be implemented in the application server 3100 or the storage server 3200 .

[0144] Any functional blocks shown in the figure and described above can be implemented in a processing circuit such as: hardware including logic circuits, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0145] Some example embodiments have been described with reference to the drawings and the specification. Although some example embodiments have been described by using specific terms, these terms are only used to explain the technical ideas of the inventive concept and should not be interpreted as limiting the scope of the inventive concept defined by the claims.

[0146] While the inventive concept has been particularly shown and described with reference to some example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A storage device, comprising: a multi-function controller configured to control a plurality of functions requested by a host; a power-off protection capacitor configured to provide auxiliary power to the storage device; as well as a power failure protection controller, the power failure protection controller being configured to periodically monitor a state of the power failure protection capacitor and manage a performance list according to the state of the power failure protection capacitor, the performance list including a plurality of pieces of performance information that the plurality of functions can support, Wherein, the power-off protection controller is further configured to: provide the performance list to the host in response to a first command received from the host, and set a performance level for at least one of the multiple functions by adjusting internal resources of the storage device in response to a second command received from the host.

2. The storage device according to claim 1, wherein: The power failure protection controller is further configured as: when first performance information corresponding to the at least one function is equal to or greater than a reference value, increasing the internal resource in response to the second command; and When the first performance information corresponding to the at least one function is less than the reference value, the internal resource is reduced in response to the second command.

3. The storage device according to claim 1, wherein: The power-off protection controller comprises: a capacitor monitor configured to periodically monitor the state of the power failure protection capacitor; and A performance manager is configured to manage the performance list according to the state of the power-off protection capacitor.

4. The storage device according to claim 1, further comprising: A host interface, the host interface being configured to: receive the first command for requesting the performance list from the host, send the performance list to the host in response to the first command, and receive the second command for setting the performance level for the at least one function from the host.

5. The storage device according to claim 4, wherein: The host interface is further configured to receive write data from the host, and The storage device also includes: a buffer memory configured to buffer the write data, and A nonvolatile memory configured to store the write data buffered in the buffer memory.

6. The storage device according to claim 5, wherein: The power failure protection controller is further configured to: determine a power failure protection data size permitted by power failure protection for each of the plurality of functions, and update performance information corresponding to each of the plurality of functions based on the power failure protection data size, and The power-off protection data size corresponds to the size of data flushed from the buffer memory to the nonvolatile memory.

7. The storage device according to claim 6, wherein: The internal resources include at least one of the following: The power-off protection data size, or A flush cycle to flush the write data from the buffer memory to the non-volatile memory.

8. The storage device according to claim 6, wherein: The storage device is configured to store the write data corresponding to the power-off protection data size and buffered in the buffer memory in the nonvolatile memory when a sudden power off occurs.

9. The storage device according to claim 4, wherein: The host interface is also configured to: receiving from the host a third command for checking the performance level of the at least one function, In response to the third command, the performance level is sent to the host.

10. The storage device according to claim 4, wherein: The power-off protection controller is further configured to: when the state of the power-off protection capacitor changes, update the performance list based on the changed state of the power-off protection capacitor, and The host interface is further configured to send a state change event to the host indicating that the state of the power-off protection capacitor has changed.

11. The storage device according to claim 10, wherein: The host interface is also configured to: receiving a fourth command from the host for requesting an updated capability list; and An updated performance list is sent to the host in response to the fourth command.

12. The storage device according to claim 1, wherein: The performance list also includes valid bits corresponding to the multiple functions, each of which indicates whether a corresponding piece of performance information is valid, and The power-off protection controller is further configured to send an error message to the host when a piece of performance information corresponding to the at least one function included in the second command is invalid.

13. A method for operating a storage device, the method comprising: periodically monitoring the status of a power-off protection capacitor included in the storage device; managing a performance list according to the state of the power-off protection capacitor, the performance list including a plurality of pieces of performance information that can be supported by a plurality of functions; receiving a first command from a host for requesting the performance list; sending the performance list to the host in response to the first command; receiving from the host a second command for setting a performance level for at least one function among the plurality of functions; as well as In response to the second command, the performance level is set for the at least one function by adjusting internal resources of the storage device.

14. The operating method according to claim 13, wherein: Managing the performance list includes: determining a power-off protection data size corresponding to each of the plurality of functions according to the state of the power-off protection capacitor, and updating performance information corresponding to each of the plurality of functions based on the power-off protection data size, and The power-off protection data size corresponds to a size of data flushed from a buffer memory to a nonvolatile memory included in the storage device.

15. The operating method according to claim 14, wherein: The internal resources include at least one of the following: The power-off protection data size, or A flush cycle to flush write data received from the host from the buffer memory to the non-volatile memory.

16. The operating method according to claim 15, further comprising: When a sudden power failure occurs, the write data corresponding to the power failure protection data size and buffered in the buffer memory is stored in the nonvolatile memory.

17. The operating method according to claim 13, further comprising: receiving from the host a third command for checking the performance level of the at least one function; as well as The performance level is sent to the host in response to the third command.

18. The operating method according to claim 13, further comprising: When the state of the power-off protection capacitor changes, updating the performance list based on the changed state of the power-off protection capacitor; as well as A state change event is sent to the host indicating that the state of the power failure protection capacitor has changed.

19. The operating method according to claim 18, further comprising: receiving a fourth command from the host for requesting an updated capability list; as well as An updated performance list is sent to the host in response to the fourth command.

20. The operating method according to claim 13, wherein: The performance list also includes valid bits corresponding to the multiple functions, each of which indicates whether a corresponding piece of performance information is valid, and The operation method further includes: when a piece of performance information corresponding to the at least one function included in the second command is invalid, sending an error message to the host.

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