A memory error detection method, device, apparatus, medium and product

Abstract

The present application relates to the technical field of computers, and discloses a memory error detection method, device, equipment, medium and product, the memory error detection method comprising: obtaining the intermediate representation of target compiled code, analyzing the intermediate representation to obtain a current memory access operation; obtaining a memory region corresponding to the current memory access operation, performing static analysis on the current memory access operation based on the memory region to obtain first memory error information; when the memory region corresponding to the current memory access operation is not obtained, performing dynamic analysis on the current memory access operation to obtain second memory error information; and performing memory access error processing based on the first memory error information or the second memory error information. The present application ensures comprehensive detection and positioning of memory errors in the compilation stage, can help users quickly find and repair memory problems, and significantly improves software development efficiency and code quality.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and specifically to a method, apparatus, device, medium, and product for detecting memory errors. Background Technology

[0002] As software development becomes increasingly complex, memory management errors have become one of the main problems affecting system stability and security. Common memory errors include memory leaks, buffer overflows, and illegal memory accesses. These errors can not only cause software crashes but may even threaten hardware security.

[0003] Limited memory inspection tools make it difficult to quickly detect and fix memory problems during software development, which in turn affects software development efficiency and code quality, and makes it difficult to ensure hardware security. Summary of the Invention

[0004] In view of this, the present invention provides a memory error detection method, apparatus, device, medium and product to solve the problem that memory problems cannot be quickly detected and repaired during software development, which affects software development efficiency and code quality and makes it difficult to ensure hardware security.

[0005] In a first aspect, the present invention provides a memory error detection method, the method comprising:

[0006] Obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation;

[0007] Obtain the memory region corresponding to the current memory access operation, perform static analysis on the current memory access operation based on the memory region, and obtain the first memory error information;

[0008] If the memory region corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain the second memory error information.

[0009] Memory access error handling is performed based on either the first or second memory error information.

[0010] This embodiment provides a memory error detection method that analyzes the intermediate representation of the target compiled code to obtain the current memory access operation. Static analysis of the current memory access operation based on the memory region yields first memory error information. If the memory region corresponding to the current memory access operation is not found, dynamic analysis is performed to obtain second memory error information. Memory access error handling is then performed based on either the first or second memory error information. By performing static and dynamic analysis on memory access operations during multi-threaded compilation, comprehensive detection and localization of memory errors during the compilation stage are ensured. This helps users quickly discover and fix memory problems, significantly improving software development efficiency and code quality, and assisting users in conducting high-quality software engineering.

[0011] In one optional implementation, the memory region corresponding to the current memory access operation is obtained, and static analysis is performed on the current memory access operation based on the memory region to obtain first memory error information, including:

[0012] Perform dependency analysis on the current memory access operation to obtain the memory region corresponding to the current memory access operation;

[0013] The memory access operation information corresponding to the current memory access operation is compared with the memory information corresponding to the memory region, and the first memory error information is determined based on the comparison result.

[0014] This embodiment provides a memory error detection method that determines the first memory error by comparing the memory access operation information corresponding to the current memory access operation with the memory information corresponding to the memory region. This achieves accurate detection of memory access operation errors with existing memory definitions during the compilation stage, helping users to quickly discover and fix memory problems.

[0015] In one optional implementation, when the memory region corresponding to the current memory access operation is not found, the current memory access operation is dynamically analyzed to obtain second memory error information, including:

[0016] The compilation multi-threaded memory space corresponding to the target compiled code is divided into a main memory space and multiple shadow memory spaces, and the main memory space is mapped to the multiple shadow memory spaces;

[0017] Obtain the detection code and instrument the detection code in the shadow memory space;

[0018] Run the target compiled code after instrumentation of the detection code to detect memory errors and obtain the second memory error information.

[0019] This embodiment provides a memory error detection method that divides the compilation multi-threaded memory space into a main memory space and multiple shadow memory spaces, maps the main memory space to the multiple shadow memory spaces, and instrumentes detection code in the shadow memory spaces. Then, it runs the target compiled code after the detection code instrumentation to detect memory errors. This method can ensure that there is enough shadow memory space for memory checking, and also ensure that each thread can perform independent checks without conflict.

[0020] In one optional implementation, the compilation multi-threaded memory space corresponding to the target compiled code is divided into a main memory space and multiple shadow memory spaces, and the main memory space is mapped to the multiple shadow memory spaces, including:

[0021] The compilation multi-threaded memory space is divided into a common memory space and a raw shadow memory space;

[0022] The common memory space is divided into the main memory space and the independent shadow memory space. The independent shadow memory space is used to store multi-threaded memory access information.

[0023] Multiple shadow memory spaces are established based on the original shadow memory space and independent shadow memory spaces;

[0024] Map the main memory space to multiple shadow memory spaces.

[0025] This embodiment provides a memory error detection method that divides the common memory space into a main memory space and an independent shadow memory space for storing multi-threaded memory access information, thereby establishing multiple shadow memory spaces and mapping the main memory space to the multiple shadow memory spaces. This achieves the goal of storing memory access information of all threads in the main memory space while ensuring that access to each thread does not conflict.

[0026] In one optional implementation, the detection code is obtained, and the detection code is instrumented in the shadow memory space, including:

[0027] Obtain the thread number corresponding to the current memory access operation, and determine the shadow memory address of each thread based on the current thread number;

[0028] The detection code is instrumented based on the shadow memory address of each thread to obtain the target compiled code after the detection code instrumentation.

[0029] This embodiment provides a memory error detection method that determines the shadow memory address of each thread by using the thread number of the current thread, ensuring that there is enough shadow memory space for memory checking. Furthermore, during the compilation stage, detection code instrumentation is performed based on the shadow memory address of each thread, thereby achieving accurate location and detection of memory errors and improving the efficiency of writing high-quality code.

[0030] In one optional implementation, memory access error handling is performed based on a first memory error message or a second memory error message, including:

[0031] Mark the error type for either the first or second memory error message;

[0032] If the error type corresponding to the first memory error message or the second memory error message is an alarm type, a warning message is generated and recorded in the software running code;

[0033] If the error type corresponding to the first or second memory error message is an interrupt type, then the code compilation process or the software execution process will be interrupted.

[0034] This embodiment provides a memory error detection method that can immediately interrupt code compilation or software operation when a code execution error that may threaten hardware security is detected, thereby preventing serious accidents and ensuring hardware security.

[0035] Secondly, the present invention provides a memory error detection device, which includes:

[0036] The acquisition module is used to acquire an intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation.

[0037] The static analysis module is used to obtain the memory region corresponding to the current memory access operation, perform static analysis on the current memory access operation based on the memory region, and obtain the first memory error information.

[0038] The dynamic analysis module is used to perform dynamic analysis on the current memory access operation and obtain the second memory error information when the memory region corresponding to the current memory access operation is not obtained.

[0039] The memory access error handling module is used to handle memory access errors based on either the first memory error information or the second memory error information.

[0040] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform a memory error detection method according to the first aspect or any corresponding embodiment described above.

[0041] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute a memory error detection method according to the first aspect or any corresponding embodiment described above.

[0042] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute a memory error detection method according to the first aspect or any corresponding embodiment described above. Attached Figure Description

[0043] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 This is a flowchart illustrating a memory error detection method according to an embodiment of the present invention;

[0045] Figure 2 This is a flowchart illustrating another memory error detection method according to an embodiment of the present invention;

[0046] Figure 3 This is a flowchart illustrating another memory error detection method according to an embodiment of the present invention;

[0047] Figure 4 This is a flowchart illustrating another memory error detection method according to an embodiment of the present invention;

[0048] Figure 5 This is a flowchart illustrating the memory error detection process using a static + dynamic analysis method according to an embodiment of the present invention.

[0049] Figure 6 This is a structural block diagram of a memory error detection device according to an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] In software development, memory management errors are a significant issue affecting system stability and security. Many-core architecture places even higher demands on memory inspection tools. In a many-core architecture, each core group can be considered an independent thread. Multithreaded programming models can better utilize all threads to improve program performance. Each independent thread can access both its own independent memory space and a shared memory space, and errors can occur during memory access. Therefore, designing a mechanism to simultaneously check for memory access errors from multiple threads at different memory levels is a problem that memory inspection tools need to solve.

[0053] Memory checking tools and methods can be categorized as follows:

[0054] (1) Static analysis tools:

[0055] Static analysis tools detect memory errors during the compilation phase by analyzing source code. Relevant static analysis tools include Clang Static Analyzer (a static code analysis tool) for LLVM (Low Level Virtual Machine) and Coverity (a static analysis software). These tools can detect potential memory leaks, out-of-bounds accesses, and other problems before code execution. However, a drawback of static analysis tools is that they rely on the static nature of the code and cannot detect dynamically generated problems at runtime.

[0056] (2) Dynamic analysis tools:

[0057] Dynamic analysis tools monitor and detect memory errors during program runtime. Valgrind is a widely used dynamic analysis tool that can detect issues such as memory leaks and illegal memory accesses. Another dynamic analysis tool is AddressSanitizer (a fast memory error detection tool), which monitors memory operations by inserting detection code. Although dynamic analysis tools can catch runtime errors, they often introduce additional runtime overhead, thus impacting program performance.

[0058] (3) Hardware-supported memory checks:

[0059] Some advanced hardware platforms offer built-in memory error detection mechanisms. For example, MPX (Memory Protection Extensions) technology detects and prevents out-of-bounds memory accesses through hardware support. However, these technologies require hardware support and may be limited by hardware compatibility in practical applications.

[0060] (4) Operating system-level protection:

[0061] Operating systems also provide some memory protection mechanisms, such as memory paging and virtual memory technology to prevent illegal memory access. However, operating system-level protection is often insufficient for fine-grained detection and repair of memory errors in applications.

[0062] In summary, there is no technology that can apply memory checking to many-core architectures. Due to the special hardware characteristics of many-core architectures, such as the small independent memory space of each thread that cannot be used to store memory access information, and the large shared memory space that is accessed simultaneously, it is difficult to guarantee that memory access errors of each thread in a multi-threaded programming model can be accurately detected.

[0063] To address the aforementioned technical problems, this invention provides a memory error detection method. By assisting users in locating code errors during multi-threaded programming, this method improves the efficiency of writing high-quality code and helps users conduct high-quality software engineering. When a code execution error that may threaten hardware security is detected, the tool can forcibly interrupt software operation, thereby ensuring hardware security.

[0064] This invention provides a method for detecting memory errors. It should be noted that the execution subject of this method can be a memory error detection device, which can be implemented as part or all of an electronic device through software, hardware, or a combination of both. The electronic device can be a server or a terminal. In this embodiment, the server can be a single server or a server cluster composed of multiple servers. The terminal can be a smartphone, personal computer, tablet computer, wearable device, or other intelligent hardware device such as a smart robot. The following method embodiments all use an electronic device as the execution subject for illustration.

[0065] According to an embodiment of the present invention, a memory error detection method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0066] This embodiment provides a memory error detection method, which can be used in the aforementioned electronic device. Figure 1 This is a flowchart of a memory error detection method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0067] Step S101: Obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation.

[0068] Specifically, during the compilation phase, the intermediate representation (IR) of the target compiled code is analyzed to obtain the current memory access operations (such as memory allocation, release, reading, writing, etc.).

[0069] Step S102: Obtain the memory region corresponding to the current memory access operation, perform static analysis on the current memory access operation based on the memory region, and obtain the first memory error information.

[0070] Specifically, memory error messages include out-of-bounds (OOB) memory access, access to unallocated memory, memory leaks, multiple frees, stack overflows, and other information.

[0071] Furthermore, static analysis of the current memory access operation aims to identify illegal memory operations during the compilation phase, and the relevant information corresponding to the illegal memory operation is used as the first memory error information for memory access error handling; for memory operations identified as legal, other memory operations are analyzed further.

[0072] Step S103: When the memory region corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain the second memory error information.

[0073] Specifically, if the definition of a memory location cannot be obtained, the current memory access operation is dynamically analyzed. For example, if function A has a memory access operation that reads a certain address addr, but addr is a parameter of A, this parameter is only passed in at runtime, and thus dynamic analysis is performed.

[0074] Furthermore, for memory access operations whose legitimacy cannot be analyzed during the compilation stage, dynamic analysis is performed using shadow memory technology and compile-time instrumentation methods.

[0075] Step S104: Perform memory access error handling based on the first memory error information or the second memory error information.

[0076] This embodiment provides a memory error detection method that analyzes the intermediate representation of the target compiled code to obtain the current memory access operation. Static analysis of the current memory access operation based on the memory region yields first memory error information. If the memory region corresponding to the current memory access operation is not found, dynamic analysis is performed to obtain second memory error information. Memory access error handling is then performed based on either the first or second memory error information. By performing static and dynamic analysis on memory access operations during multi-threaded compilation, comprehensive detection and localization of memory errors during the compilation stage are ensured. This helps users quickly discover and fix memory problems, significantly improving software development efficiency and code quality, and assisting users in conducting high-quality software engineering.

[0077] This embodiment provides a memory error detection method that can be used in the aforementioned electronic device. Figure 2 This is a flowchart of a memory error detection method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0078] Step S201: Obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0079] Step S202: Obtain the memory region corresponding to the current memory access operation, perform static analysis on the current memory access operation based on the memory region, and obtain the first memory error information.

[0080] Specifically, step S202 includes:

[0081] Step S2021: Perform dependency analysis on the current memory access operation to obtain the memory region corresponding to the current memory access operation.

[0082] Specifically, the compiler uses the source operations that the current memory access operation depends on to obtain the memory region corresponding to the current memory access operation; for example, if the current memory access operation is to read a memory address, the compiler uses that memory address to find the defined memory region and then obtains the various parameters defined at the time of definition.

[0083] Furthermore, common compilation techniques such as single IR analysis, alias analysis (AA), and definition-use (DU) analysis can be used to locate the memory region of the current memory access operation.

[0084] Step S2022: Compare the memory access operation information corresponding to the current memory access operation with the memory information corresponding to the memory region, and determine the first memory error information based on the comparison result.

[0085] Specifically, for a memory access operation, obtain relevant information about the current memory access operation (size of memory access, whether it is an allocation / release operation, etc.) and the memory information corresponding to the memory region (whether it is allocated / released memory, the defined memory size, whether it is initialized, etc.). Compare the above two pieces of information. If they match, the current memory access operation is determined to be a legal operation; otherwise, the current memory access operation is an illegal operation.

[0086] Step S203: If the memory region corresponding to the current memory access operation is not found, the current memory access operation is dynamically analyzed to obtain the second memory error information. For details, please refer to [link to relevant documentation]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0087] Step S204: Perform memory access error handling based on either the first or second memory error information. For details, please refer to [link to relevant documentation]. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0088] This embodiment provides a memory error detection method that determines the first memory error by comparing the memory access operation information corresponding to the current memory access operation with the memory information corresponding to the memory region. This achieves accurate detection of memory access operation errors with existing memory definitions during the compilation stage, helping users to quickly discover and fix memory problems.

[0089] This embodiment provides a memory error detection method, which can be used in the aforementioned electronic device. Figure 3 This is a flowchart of a memory error detection method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps:

[0090] Step S301: Obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation. For details, please refer to [link to relevant documentation]. Figure 2 Step S201 of the illustrated embodiment will not be described again here.

[0091] Step S302: Obtain the memory region corresponding to the current memory access operation, and perform static analysis on the current memory access operation based on the memory region to obtain the first memory error information. For details, please refer to [link to relevant documentation]. Figure 2 Step S202 of the illustrated embodiment will not be described again here.

[0092] Step S303: When the memory region corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain the second memory error information.

[0093] Specifically, step S303 includes:

[0094] Step S3031: Divide the multi-threaded memory space corresponding to the target compiled code into a main memory space and a multiple shadow memory space, and map the main memory space into the multiple shadow memory space.

[0095] Specifically, shadow memory technology allocates an additional memory region, called the "shadow memory region," for each monitored memory address. The shadow memory records and maintains status information corresponding to the actual memory, including whether it has been initialized and whether it is accessible. Each time memory is accessed (read or write), the shadow memory performs a synchronization operation; for example, when accessing an actual memory address, the shadow memory synchronously updates or queries the corresponding status information. Shadow memory is created at compile time, generated into binary code along with normal code, and dynamically read and written at runtime.

[0096] In some optional implementations, step S3031 above includes:

[0097] Step a1: Divide the compilation multi-threaded memory space into a common memory space and a raw shadow memory space.

[0098] Specifically, the public memory space belongs to the program process and is used by the program process. The original shadow memory space is used to store metadata needed to detect memory errors. That is, the original shadow memory stores metadata that can reflect the normal memory state information, while the normal memory stores the data that the program actually needs.

[0099] Step a2: Divide the common memory space into the main memory space and the independent shadow memory space. The independent shadow memory space is used to store multi-threaded memory access information.

[0100] Specifically, since the independent memory space of a single thread is small, it is impossible to allocate additional space to store large memory access information. Therefore, the memory access information of multiple threads can only be stored in the common memory space. However, another problem is that the common memory space can be accessed by multiple threads at the same time. It is necessary to ensure that each thread can access the memory space without conflict. Therefore, a shadow memory space (i.e., an independent shadow memory space) is reserved in the common memory space to store the memory access information of all threads.

[0101] Furthermore, the independent shadow memory space is divided into equal parts according to the number of threads. Each thread can only access its corresponding memory space. The formula for calculating the total size of the independent shadow memory space is as follows:

[0102] shadowMemorySize=threadNum*threadShadowMemorySize

[0103] Where shadowMemorySize is the total memory space size of the independent shadow memory space, threadNum is the fixed total number of threads in the hardware, and threadShadowMemorySize is the shadow memory space size required by each thread.

[0104] Step a3: Establish a multi-shadow memory space based on the original shadow memory space and the independent shadow memory space.

[0105] Step a4: Map the main memory space to the multiple shadow memory space.

[0106] Step S3032: Obtain the detection code and instrument the detection code in the shadow memory space.

[0107] Specifically, compile-time instrumentation is a method of inserting additional code into a program during the compilation process, with the aim of monitoring, analyzing, and optimizing the program. This method differs from dynamic instrumentation because instrumentation is performed during the compilation phase of the program, rather than during runtime. That is, additional detection code is inserted before memory access operations, including collecting relevant information about memory access operations, memory access detection, and error handling.

[0108] In some optional implementations, step S3032 above includes:

[0109] Step b1: Obtain the thread number corresponding to the current memory access operation, and determine the shadow memory address of each thread based on the current thread number.

[0110] Specifically, the thread ID of the current thread is obtained during compile-time instrumentation, and the shadow memory address threadShadowMemoryAddress of each thread is calculated as follows:

[0111] threadShadowMemoryAddress

[0112] =threadID*threadShadowMemorySize+shadowMemoryAddress

[0113] Where threadID is the thread number of the current thread, threadShadowMemorySize is the size of the shadow memory space required by each thread, and shadowMemoryAddress is the starting address of the total shadow memory, which needs to be dynamically obtained at runtime.

[0114] Step b2 involves instrumenting detection code based on the shadow memory address of each thread to obtain the target compiled code after the detection code instrumentation.

[0115] Specifically, it identifies all assignment, copy, and other code locations in the program and inserts detection code to update the target object's metadata.

[0116] Step S3033: Run the target compiled code after instrumentation of the detection code to detect memory errors and obtain the second memory error information.

[0117] Specifically, the detection code and the original code are compiled together into a binary file, and the detection code and the original code are executed sequentially during the runtime phase. Before the memory access operation is executed, a memory access detection method is used, and the detection result is passed to the user after memory access error handling.

[0118] Step S304: Perform memory access error handling based on either the first or second memory error information. For details, please refer to [link to relevant documentation]. Figure 2 Step S204 of the illustrated embodiment will not be described again here.

[0119] This embodiment provides a memory error detection method that divides the compilation multi-threaded memory space into a main memory space and multiple shadow memory spaces, maps the main memory space to the multiple shadow memory spaces, and instrumentes detection code in the shadow memory spaces. Then, it runs the target compiled code after the detection code instrumentation to detect memory errors. This method can ensure that there is enough shadow memory space for memory checking, and also ensure that each thread can perform independent checks without conflict.

[0120] This embodiment provides a memory error detection method, which can be used in the aforementioned electronic device. Figure 4 This is a flowchart of a memory error detection method according to an embodiment of the present invention, such as... Figure 4 As shown, the process includes the following steps:

[0121] Step S401: Obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation. For details, please refer to [link to relevant documentation]. Figure 3 Step S301 of the illustrated embodiment will not be described again here.

[0122] Step S402: Obtain the memory region corresponding to the current memory access operation, and perform static analysis on the current memory access operation based on the memory region to obtain the first memory error information. For details, please refer to [link to relevant documentation]. Figure 3 Step S302 of the illustrated embodiment will not be described again here.

[0123] Step S403: If the memory region corresponding to the current memory access operation is not found, the current memory access operation is dynamically analyzed to obtain the second memory error information. For details, please refer to [link to relevant documentation]. Figure 3 Step S303 of the illustrated embodiment will not be described again here.

[0124] Step S404: Perform memory access error handling based on the first memory error information or the second memory error information.

[0125] Specifically, step S404 includes:

[0126] Step S4041: Mark the error type of the first memory error message or the second memory error message.

[0127] Specifically, memory errors can be marked as either warnings or aborts.

[0128] Furthermore, the specific distinction between error types is based on different hardware architectures, adopting a relatively lenient strategy to avoid causing excessive code development difficulties for users. Specifically, for software errors that may threaten hardware boards, such as causing hardware crashes requiring a restart that could take several hours to recover, these memory errors need to be interrupted and are marked as interrupt types. For memory access errors that may lead to incorrect calculation results, only the memory access error is output to the user, who then decides how to handle it—whether to modify or retain it—and these are marked as alarm types. In the software, the distinction is made based on the specific address value accessed; accessing addresses within a certain range or at address zero will cause hardware errors, while accessing addresses within a certain range will not have a serious impact.

[0129] Step S4042: If the error type corresponding to the first memory error message or the second memory error message is an alarm type, then a warning message is generated and recorded in the software running code.

[0130] Specifically, for minor memory errors such as alarms, a warning message is generated and alerted to the developers by logging it to the log or printing it to the command line.

[0131] Step S4043: If the error type corresponding to the first memory error message or the second memory error message is an interrupt type, then interrupt the code compilation process or the software execution code process.

[0132] Specifically, for interrupt-type memory errors, the compilation process or code execution is forcibly interrupted to avoid causing hardware crashes.

[0133] This embodiment provides a memory error detection method that can immediately interrupt code compilation or software operation when a code execution error that may threaten hardware security is detected, thereby preventing serious accidents and ensuring hardware security.

[0134] The following specific embodiment illustrates the steps of a memory error detection method.

[0135] Example 1:

[0136] On a domestically produced chip with a many-core architecture, this memory testing tool was implemented based on a self-developed compiler, targeting a multi-threaded programming model. After extensive code testing, it identified numerous test case errors, such as... Figure 5 As shown, the memory testing tool uses a combination of static and dynamic analysis. The memory testing steps include:

[0137] During the compilation phase, the intermediate representation of the code is analyzed, and in this process, all memory access operations (such as memory allocation, deallocation, reading, and writing) are identified.

[0138] By performing static analysis on memory access operations, illegal memory operations are identified as early as possible during the compilation stage. For memory access operations identified as legal, other memory access operations will be analyzed further; for memory access operations identified as illegal, error handling will be performed on the results.

[0139] For memory access operations that cannot be identified during static analysis, a dynamic checking method is adopted, using instrumentation technology to detect them at runtime and handle errors in the results.

[0140] In the above embodiment 1, for code that is difficult to locate, the user can efficiently locate some memory access errors by using a memory detection tool, fix the problem, and then resolve the issue. In addition, for the processing of different threads, the memory access error information of the thread that malfunctions can also be accurately identified. If an unallocated null address is accessed, it will cause the hardware to restart, and it will recover after several hours. After using this tool, such memory access errors will be identified before execution and the program will be interrupted to prevent hardware crashes. In summary, it can be seen that this tool has a relatively effective function of improving user development efficiency and protecting hardware.

[0141] This embodiment also provides a memory error detection device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0142] This embodiment provides a memory error detection device, such as... Figure 6 As shown, it includes:

[0143] The acquisition module 601 is used to acquire the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation;

[0144] The static analysis module 602 is used to obtain the memory region corresponding to the current memory access operation, perform static analysis on the current memory access operation based on the memory region, and obtain the first memory error information.

[0145] The dynamic analysis module 603 is used to perform dynamic analysis on the current memory access operation and obtain the second memory error information when the memory region corresponding to the current memory access operation is not obtained.

[0146] The memory access error handling module 604 is used to handle memory access errors based on the first memory error information or the second memory error information.

[0147] In some alternative implementations, the static analysis module 602 includes:

[0148] The dependency analysis unit is used to perform dependency analysis on the current memory access operation to obtain the memory region corresponding to the current memory access operation.

[0149] The comparison unit is used to compare the memory access operation information corresponding to the current memory access operation with the memory information corresponding to the memory region, and determine the first memory error information based on the comparison result.

[0150] In some alternative implementations, the dynamic analysis module 603 includes:

[0151] The partitioning unit is used to divide the multi-threaded memory space corresponding to the target compiled code into a main memory space and multiple shadow memory spaces, and to map the main memory space to the multiple shadow memory spaces;

[0152] The instrumentation unit is used to acquire detection code and instrument the detection code in the shadow memory space;

[0153] The detection unit is used to run the target compiled code after the detection code is instrumented, to detect memory errors, and to obtain the second memory error information.

[0154] In some alternative implementations, the partitioning unit includes:

[0155] The first partitioning subunit is used to divide the compilation multithreaded memory space into a common memory space and a raw shadow memory space;

[0156] The second partitioning subunit is used to divide the common memory space into the main memory space and the independent shadow memory space. The independent shadow memory space is used to store multi-threaded memory access information.

[0157] Establish sub-units to create multiple shadow memory spaces based on the original shadow memory space and independent shadow memory spaces;

[0158] The mapping subunit is used to map the main memory space to multiple shadow memory spaces.

[0159] In some alternative implementations, the piling unit includes:

[0160] The sub-unit is determined to obtain the thread number corresponding to the current memory access operation and determine the shadow memory address of each thread based on the current thread number.

[0161] The instrumentation subunit is used to perform detection code instrumentation based on the shadow memory address of each thread, and obtain the target compiled code after the detection code instrumentation.

[0162] In some alternative implementations, the memory access error handling module 604 includes:

[0163] A marking unit is used to mark the error type of the first memory error message or the second memory error message;

[0164] An alarm unit is used to generate a warning message and record the warning message in the software running code if the error type corresponding to the first memory error message or the second memory error message is an alarm type.

[0165] The interrupt unit is used to interrupt the code compilation process or the software execution process if the error type corresponding to the first memory error message or the second memory error message is an interrupt type.

[0166] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0167] In this embodiment, a memory error detection device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.

[0168] This invention also provides a computer device having the above-described features. Figure 6 The image shows a memory error detection device.

[0169] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0170] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0171] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0172] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0173] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0174] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0175] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0176] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0177] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0178] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A memory error detection method, characterized in that, The method includes: Obtain an intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation; If the memory region corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain the second memory error information. Memory access error handling is performed based on the second memory error information; When the memory region corresponding to the current memory access operation is not found, the current memory access operation is dynamically analyzed to obtain a second memory error message, including: The compilation multi-threaded memory space corresponding to the target compiled code is divided into a main memory space and multiple shadow memory spaces, and the main memory space is mapped to the multiple shadow memory spaces; Obtain the detection code and instrument the detection code in the shadow memory space; Run the target compiled code after instrumentation of the detection code to detect memory errors and obtain the second memory error information; The step of dividing the multi-threaded compilation memory space corresponding to the target compiled code into a main memory space and multiple shadow memory spaces, and mapping the main memory space to the multiple shadow memory spaces, includes: The compiled multi-threaded memory space is divided into a common memory space and a raw shadow memory space; the common memory space belongs to the program process and is used by the program process, while the raw shadow memory space is used to store metadata required for detecting memory errors. The common memory space is divided into a main memory space and an independent shadow memory space. The independent shadow memory space is used to store multi-threaded memory access information. The multiple shadow memory spaces are established based on the original shadow memory space and the independent shadow memory space; The main memory space is mapped to the multiple shadow memory spaces.

2. The method according to claim 1, characterized in that, Also includes: Obtain the memory region corresponding to the current memory access operation, and perform static analysis on the current memory access operation based on the memory region to obtain the first memory error information; Memory access error handling is performed based on the first memory error information.

3. The method according to claim 2, characterized in that, The step of obtaining the memory region corresponding to the current memory access operation, and performing static analysis on the current memory access operation based on the memory region to obtain first memory error information includes: Perform dependency analysis on the current memory access operation to obtain the memory region corresponding to the current memory access operation; The memory access operation information corresponding to the current memory access operation is compared with the memory information corresponding to the memory region, and the first memory error information is determined based on the comparison result.

4. The method according to claim 1, characterized in that, The step of obtaining the detection code and instrumenting the detection code in the shadow memory space includes: Obtain the thread number corresponding to the current memory access operation, and determine the shadow memory address of each thread based on the thread number corresponding to the current memory access operation; Based on the shadow memory address of each thread, detection code instrumentation is performed to obtain the target compiled code after the detection code instrumentation.

5. The method according to claim 1, characterized in that, The memory access error handling based on the second memory error information includes: The second memory error message is marked with an error type. If the error type corresponding to the second memory error information is an alarm type, then a warning message is generated and the warning message is recorded in the software running code; If the error type corresponding to the second memory error information is an interrupt type, then the code compilation process or the software execution process will be interrupted.

6. A memory error detection device, characterized in that, The device includes: The acquisition module is used to acquire an intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation. The dynamic analysis module is used to perform dynamic analysis on the current memory access operation and obtain the second memory error information when the memory region corresponding to the current memory access operation is not obtained. The memory access error handling module is used to handle memory access errors based on the second memory error information. The dynamic analysis module includes: The partitioning unit is used to divide the multi-threaded memory space corresponding to the target compiled code into a main memory space and multiple shadow memory spaces, and to map the main memory space to the multiple shadow memory spaces; The instrumentation unit is used to acquire detection code and instrument the detection code in the shadow memory space; The detection unit is used to run the target compiled code after the detection code is instrumented, detect memory errors, and obtain the second memory error information; The division units include: The first partitioning subunit is used to divide the compilation multi-threaded memory space into a common memory space and a raw shadow memory space; the common memory space belongs to the program process and is used by the program process, while the raw shadow memory space is used to store metadata required for detecting memory errors; The second partitioning subunit is used to divide the common memory space into the main memory space and the independent shadow memory space. The independent shadow memory space is used to store multi-threaded memory access information. Establish sub-units to create multiple shadow memory spaces based on the original shadow memory space and independent shadow memory spaces; The mapping subunit is used to map the main memory space to multiple shadow memory spaces.

7. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the memory error detection method according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the memory error detection method according to any one of claims 1 to 5.

9. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the memory error detection method according to any one of claims 1 to 5.

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