FPGA-based homomorphic encryption hardware accelerator and data processing method thereof

Abstract

The application discloses a homomorphic encryption hardware accelerator based on FPGA, which comprises an FPGA end, wherein the FPGA end comprises a data transmission module, a control module, a homomorphic encryption module, a homomorphic decryption module, a number theory transformation module and a small-to-large modulus conversion module; the data transmission module is used for realizing data transmission between the FPGA end and an upper computer; the control module is used for controlling the flow direction of data among various modules according to encryption or decryption operation; the number theory transformation module is used for carrying out number theory transformation or inverse number theory transformation on input data to obtain transformed data or inverse number theory transformed data; the homomorphic encryption module is used for encrypting the transformed data to obtain ciphertext data; the homomorphic decryption module is used for decrypting the transformed data to obtain plaintext data; and the small-to-large modulus conversion module is used for converting the ciphertext data or plaintext data of multiple small-bit-width moduli into data of one large-bit-width modulus. The calculation efficiency of homomorphic encryption and decryption is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit encryption technology, specifically to an FPGA-based homomorphic encryption hardware accelerator and its data processing method. Background Technology

[0002] In the internet age, data processing and management are core business operations for enterprises. Before the advent of cloud computing, enterprises needed to build data centers for data processing and storage, which undoubtedly increased operating costs significantly. Cloud computing services offer these enterprises a new solution. However, from the perspective of cloud service delivery, security is the primary issue hindering its development. Once users choose to use cloud computing services, it means their data is no longer under their control, and their privacy is at risk of leakage. Traditional encryption methods can ensure the security of data storage and transmission during cloud computing. However, when the cloud provider needs to process and compute the data, it still needs to decrypt it. Thus, private data is still exposed to the cloud provider.

[0003] Homomorphic encryption perfectly aligns with the privacy and data protection needs of cloud computing. Homomorphic encryption refers to encrypting plaintext; the result of addition or multiplication operations performed on the ciphertext is identical to the result of the same operations performed on the plaintext after decryption. In September 2009, Gentry proposed the first fully homomorphic encryption scheme supporting arbitrary additions and multiplications, possessing complete homomorphic support properties and supporting homomorphic computations of arbitrary numbers of additions and multiplications. Since 2009, the field of cryptography has witnessed a surge in research on fully homomorphic encryption schemes, resulting in three generations of construction schemes.

[0004] However, homomorphic encryption involves polynomial operations, which significantly increases the time consumed in software implementation. Furthermore, homomorphic encryption increases the bit length and dimensionality of the ciphertext data, making it computationally inefficient when processing large amounts of data. Therefore, proposing efficient and feasible homomorphic encryption schemes is a research hotspot in the field of homomorphic encryption and an essential step towards its practical application. Summary of the Invention

[0005] The purpose of this invention is to provide an FPGA-based homomorphic encryption hardware accelerator and its data processing method, which can improve the computational efficiency of homomorphic encryption and decryption.

[0006] This invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention provides an FPGA-based homomorphic encryption hardware accelerator, comprising an FPGA terminal, wherein the FPGA terminal includes a data transmission module, a control module, a homomorphic encryption module, a homomorphic decryption module, a number theory transformation module, and a small-to-large analog-to-digital conversion module;

[0008] The data transmission module is used to realize data transmission between the FPGA and the host computer.

[0009] The control module is used to control the flow of data between various modules according to encryption or decryption operations;

[0010] The number theory transformation module is used to perform number theory transformation or inverse number theory transformation on the input data to obtain the transformed data or the data after inverse number theory transformation.

[0011] The homomorphic encryption module is used to encrypt the transformed data to obtain ciphertext data;

[0012] The homomorphic decryption module is used to decrypt the transformed data to obtain plaintext data;

[0013] The small-to-large analog-to-digital converter module is used to convert multiple small-width analog-to-digital encrypted or plaintext data into one large-width analog-to-digital data.

[0014] The control module controls the input data to the number theory transformation module for number theory transformation, transmits the transformed data to the homomorphic encryption module or homomorphic decryption module for encryption or decryption, transmits the encrypted ciphertext data or decrypted plaintext data to the number theory transformation module for inverse number theory transformation, transmits the transformed data to the small-to-large modulus conversion module for conversion processing, and transmits the converted data to the data transmission module.

[0015] Secondly, another embodiment of the present invention provides a data processing method for an FPGA-based homomorphic encryption hardware accelerator, applicable to the FPGA-based homomorphic encryption hardware accelerator described in the above embodiments, comprising:

[0016] Receive the public key and plaintext data required for encryption or the private key and ciphertext data required for decryption sent by the host computer;

[0017] Convert the received data into signed binary data;

[0018] The signed binary data is subjected to number theory transformation to obtain the number theory transformed data;

[0019] According to the functional requirements, the data after the number theory transformation is encrypted or decrypted to obtain ciphertext data or plaintext data;

[0020] Perform an inverse number theory transformation on either ciphertext or plaintext data to obtain the data after the inverse number theory transformation.

[0021] The data after inverse number theory transformation is converted from small-bit-width modulus to large-bit-width modulus data, and the converted data is transmitted to the host computer.

[0022] Thirdly, another embodiment of the present invention provides an FPGA capable of hardware acceleration for homomorphic encryption, comprising a processor and a memory, wherein the memory is used to store a computer program, the computer program comprising program instructions, and the processor is configured to invoke the program instructions to execute the method described in the above embodiments.

[0023] Fourthly, another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the methods described in the above embodiments.

[0024] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0025] This invention provides an FPGA-based homomorphic encryption hardware accelerator and its data processing method. On one hand, it reduces the complexity of finite-field polynomial multiplication calculations in homomorphic encryption, eliminates the polynomial multiplication order reduction process, reduces the difficulty of polynomial coefficient reduction, and allows the circuit to be synthesized into a higher-frequency structure, thus improving the efficiency of polynomial calculations. On the other hand, through modulo conversion technology, it converts large-number modulo operations into multiple sets of small-number modulo operations, and designs parallel and pipelined processing schemes, thereby improving the overall throughput of the accelerator. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0027] Figure 1 A structural block diagram of a homomorphic encryption hardware accelerator based on FPGA provided in the first embodiment of the present invention;

[0028] Figure 2 This is a structural block diagram of the data transmission module in the first embodiment of the present invention;

[0029] Figure 3 This is a structural block diagram of the homomorphic encryption module in the first embodiment of the present invention;

[0030] Figure 4 This is a structural block diagram of the homomorphic decryption module in the first embodiment of the present invention;

[0031] Figure 5 This is a structural block diagram of the number theory transformation module in the first embodiment of the present invention;

[0032] Figure 6 This is a structural block diagram of the small-to-large analog-to-digital conversion module in the first embodiment of the present invention;

[0033] Figure 7 This is a structural block diagram of the Montgomery simple element in the first embodiment of the present invention;

[0034] Figure 8 This is a flowchart of the data processing method of the FPGA-based homomorphic encryption hardware accelerator in the second embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0036] Example 1

[0037] like Figure 1 As shown, this embodiment of the invention is designed using a combination of hardware and software based on the BGV homomorphic encryption scheme. The first embodiment of the invention provides an FPGA-based homomorphic encryption hardware accelerator, comprising a host computer and an FPGA terminal. In this embodiment, the host computer is a PC, which assists in verifying the calculation results of the FPGA terminal. Python is used to implement functions such as key generation, homomorphic computation, plaintext computation, and result comparison. The FPGA terminal is the core of the entire accelerator, used to implement homomorphic encryption and decryption to achieve acceleration. Communication between the PC and the FPGA terminal is accomplished via a serial port.

[0038] The FPGA side includes a data transmission module, a control module, a homomorphic encryption module, a homomorphic decryption module, a number theory transformation module, and a small-to-large analog-to-digital conversion module. The system comprises the following modules: a data transmission module for data transmission between the FPGA and the host computer; a control module for controlling the flow of data between modules based on encryption or decryption operations; a number theory transformation module for performing number theory or inverse number theory transformations on the input data to obtain the transformed data; a homomorphic encryption module for encrypting the transformed data to obtain ciphertext data; a homomorphic decryption module for decrypting the transformed data to obtain plaintext data; a small-to-large analog-to-digital converter module for converting multiple small-bit-width analog-to-digital (ADC) ciphertext or plaintext data into one large-bit-width ADC data; and a control module for controlling the input data to the number theory transformation module for number theory transformation, transmitting the transformed data to the homomorphic encryption or decryption module for encryption or decryption, transmitting the encrypted ciphertext or decrypted plaintext data to the number theory transformation module for inverse number theory transformation, transmitting the inverse number theory transformation data to the small-to-large analog-to-digital converter module for conversion processing, and transmitting the converted data back to the data transmission module.

[0039] like Figure 2 As shown, the data transmission module includes a UART data transmission unit, a string to binary conversion unit, a large-to-small analog-to-digital conversion unit, and a first data storage unit.

[0040] The UART data transmission unit uses the UART protocol to complete the communication between the host computer and the slave computer. A frame of data in the sending or receiving process consists of 3 parts: 1 start bit, 8 data bits and 1 stop bit, with a baud rate of 115200. It concatenates the 32 frames of data transmitted from the PC into 256-bit ASCII code data and transmits the 256-bit ASCII code data to the string to binary conversion unit.

[0041] The string-to-binary unit removes the high 4 bits of every 8 bits of the received 256-bit ASCII data to obtain 128-bit BCD code with values ​​ranging from 0 to 9. It then converts the 128-bit BCD code into 128-bit signed binary code through iterative operations. Each iteration multiplies 4 bits of data by 10 and accumulates the result.

[0042] The large-to-small analog-to-digital converter performs modulo operations on 128-bit signed binary data based on the remainder system, converting one 128-bit data stream into four 17-bit data streams modulo q0, q1, q2, and q3. A parallel architecture is used to compute the four data streams simultaneously. Each data stream is processed serially, processing 17 bits of data from low to high, then accumulating the results, performing eight operations to obtain the final result.

[0043] The first data storage unit consists of four 17-bit wide, 256-bit deep single-port RAMs (RAM0-RAM3) and one 256-bit wide, 256-bit deep single-port RAM (RAM4). RAM0-RAM3 are used to store the final results obtained from the four channels. RAM4 is used to store the plaintext or ciphertext data to be sent to the PC.

[0044] The control module controls the data flow according to its functions. When encryption is required, the control module first performs a number-theoretical transformation on the data. Then, the transformed data is transmitted to the homomorphic encryption module for encryption. Next, the encrypted ciphertext is transmitted back to the number-theoretical transformation module for inverse number-theoretical transformation. Finally, the data after inverse number-theoretical transformation is transmitted to the small-to-large analog-to-digital converter module to merge the four data streams into one. Finally, the data is transmitted to the data transmission module. Similarly, when decryption is required, the control module first performs a number-theoretical transformation on the data. Then, the transformed data is transmitted to the homomorphic decryption module for decryption. Next, the decrypted plaintext is transmitted back to the number-theoretical transformation module for inverse number-theoretical transformation. Finally, the data after inverse number-theoretical transformation is transmitted to the small-to-large analog-to-digital converter module to merge the four data streams into one. Finally, the merged data is transmitted to the data transmission module.

[0045] like Figure 3 As shown, the homomorphic encryption module includes an encryption control unit, an encryption calculation unit, and a second data storage unit.

[0046] The encryption control unit is responsible for storing the six data points, which have undergone number theory transformations and are required for encryption calculations, into the second data storage module in sequence. After all the data has been stored for encryption, the six parameters are read out and transmitted to the encryption calculation module. Then, the encrypted ciphertext data is transmitted to the second data storage module for storage.

[0047] The encryption computing unit is responsible for encrypting the number-theoretic transformed data into ciphertext. It generates three random numbers required by the encryption algorithm using Python and then stores these random numbers in ROM. To improve throughput, the encryption computing module adopts a pipelined structure, performing multiplication and addition operations sequentially.

[0048] The second data storage unit includes eight single-port RAMs, six of which are used to store the parameters required for homomorphic encryption, and the remaining two are used to store the encrypted ciphertext data. Each RAM group contains four single-port RAMs with a width of 17 bits and a depth of 256.

[0049] Similar to the homomorphic encryption module, the homomorphic decryption module includes a decryption control unit, a decryption calculation unit, and a third data storage unit, such as... Figure 4 As shown.

[0050] The decryption control unit stores the three data required for decryption calculations sequentially into the third data storage unit. After all the data has been stored in one decryption, the three parameters are read out and transmitted to the decryption calculation unit. Then, the plaintext data obtained from the decryption is transmitted to the third data storage unit for storage.

[0051] The decryption unit is responsible for decrypting the number-theoretic transformed data into plaintext data. It also employs a pipelined structure, performing multiplication and addition operations sequentially. The third data storage unit includes four single-port RAMs: three RAMs store the parameters required for homomorphic decryption, and the remaining RAM stores the decrypted plaintext data. Each RAM group contains four single-port RAMs with a width of 17 bits and a depth of 256.

[0052] like Figure 5 As shown, the number theory transformation module includes a butterfly operation unit, a control unit, a preprocessing module, a postprocessing unit, and a fourth data storage unit.

[0053] The butterfly operation unit is the core unit of the number theory transformation module. Butterfly operations include addition, subtraction, and multiplication, all performed over a finite field. First, data is read from RAM1 for butterfly operations, and the result is stored in RAM2. After all operations in this layer are completed, data is read from RAM2 for butterfly operations, and the result is stored in RAM1, continuing this ping-pong operation. The butterfly operation uses frequency decimation. The process involves adding the first 128 data points to the last 128 data points to obtain even-numbered terms, subtracting the last 128 data points from the first 128 data points, and then multiplying by a rotation factor to obtain odd-numbered terms. After the calculation, a modulo operation is performed.

[0054] The fourth data storage unit consists of four dual-port RAMs with a bit width of 17 bits and a depth of 256. RAM0 and RAM1 are used to store the preprocessing calculation results and the postprocessing calculation results, while RAM2 and RAM3 are used to store the intermediate results in the NTT (number theory transformation) process.

[0055] The control unit is used to control the entire module to perform ping-pong operations. First, it reads data from RAM2 to perform NTT calculations, and then stores the calculation results in RAM3. When all NTT calculations in this layer are completed, it reads data from RAM3 to perform NTT calculations again, and stores the calculation results in RAM2. This process is repeated until the entire NTT calculation is completed.

[0056] The preprocessing and postprocessing units are used to perform preprocessing and postprocessing of the polynomial parameters. Before the NTT operation, the polynomial needs preprocessing, i.e., the scaling factor is multiplied by the polynomial coefficients. After the INTT (Inverse Number Theory Transform) operation, postprocessing is performed, i.e., the inverse scaling factor is multiplied by the coefficients of the resulting polynomial. By applying the negative-packet convolution theorem, it is unnecessary to multiply the polynomial coefficients, and the process of taking the modulus of the resulting polynomial order is reduced.

[0057] like Figure 6 As shown, a large-to-small analog-to-digital converter module is designed using parallel processing and a pipelined architecture, including a multiplication unit, a Montgomery simplex element, and a modular addition unit. The Montgomery simplex element is shown below. Figure 7 As shown, this unit uses simple shift and multiplication operations to complete the modulo operation, avoiding the time-consuming division operation in the modulo process. In this embodiment of the invention, all modular multiplication operations are completed using the Montgomery simple element with a pipeline structure.

[0058] The BGV homomorphic encryption and decryption algorithm is based on polynomials. An encryption operation requires two polynomial multiplications and three polynomial additions, while a decryption operation requires one polynomial multiplication and one polynomial addition. Polynomial operations are among the most critical and time-consuming operations in the encryption and decryption process. Number theory transformations are used to optimize polynomial operations, thereby reducing their computational complexity.

[0059] The design method of number theory transformation is as follows: butterfly operation is performed by frequency decimation. The butterfly operation includes modular addition, modular subtraction and modular multiplication. The process is to add the first 128 data to the last 128 data to get the even-numbered terms, subtract the last 128 data from the first 128 data and then multiply by the rotation factor to get the odd-numbered terms. These operations are all performed on a finite field. After the calculation is completed, the modulo operation needs to be performed.

[0060] Modular multiplication consists of two parts: integer multiplication and modulo operation. First, integer multiplication is performed, with the two inputs being the rotation factor and the result of the modular subtraction operation. Then, the product is modulo-operated to obtain the final result with the same bit width as the input. To obtain both odd and even terms simultaneously, the result of the modular addition is processed by register scalarization during the modular multiplication calculation. The performance bottleneck of modular multiplication lies in the modulo operation. The modulo operation is defined as the remainder when a number is divided by the modulus. To achieve efficient modulo operation, the Montgomery modular reduction algorithm is used as the basic algorithm for hardware design. This algorithm uses simple shift and multiplication operations to complete the modulo calculation, avoiding the time-consuming division calculation during the modulo operation, making it very suitable for hardware implementation.

[0061] The butterfly operation, as the core unit of number theory transformation, is used for iterative operations of number theory transformation. First, data is read from RAM1 to perform butterfly operations, and then the calculation result is stored in RAM2. After all the operations in this layer are completed, data is read from RAM2 to perform butterfly operations, and the calculation result is stored in RAM1. This ping-pong operation is performed in this way.

[0062] Homomorphic encrypted polynomial multiplication differs from ordinary polynomial multiplication. Homomorphic encrypted polynomial multiplication operates within a polynomial ring R. q =Z q [x] / (x n The polynomial multiplication in +1) requires modulo x of the result of the polynomial multiplication. n +1 reduction. Applying the theory of negative-package convolution in polynomial multiplication can effectively optimize this problem. It only requires preprocessing before the number-theoretical transformation (i.e., the dot product of the scaling factor and the polynomial coefficients) and postprocessing after the inverse number-theoretical transformation (i.e., the dot product of the scaling factor and the coefficients of the resulting polynomial), thus reducing the modulus x of the final polynomial. n The +1 operation.

[0063] The specific methods for homomorphic encryption and homomorphic decryption are as follows: The BGV encryption algorithm uses the public key (pk0, pk1) to encrypt the plaintext m, and obtains the ciphertext c = (c0, c1).

[0064] The specific algorithm for homomorphic encryption is as follows:

[0065] The ciphertexts c0 and c1 are calculated by selecting n-dimensional vectors e0 and e1 from a discrete Gaussian distribution and selecting an n-dimensional vector r from a uniform distribution {-1, 0, 1}. The calculation formulas are as follows:

[0066] c0 = pk0*r + 2e0 + m,

[0067] c1 = pk1*r + 2e1.

[0068] The BGV decryption algorithm uses the private key sk to decrypt the ciphertext c, obtaining the plaintext m. The specific calculation formula is as follows:

[0069] m = (c0 + c1 * sk) mod 2.

[0070] Here, mod2 indicates modulo 2 operation. For the three random numbers required in the encryption algorithm, Python generates suitable random numbers and stores them in ROM. The public key and plaintext needed for encryption, and the private key and ciphertext needed for decryption, are generated by the host computer and stored in RAM via the data transmission module. All computations in homomorphic encryption and decryption are polynomial calculations, which are performed using number theory transformations before addition or multiplication.

[0071] To reduce the complexity of modulo operations, the data transmission module design employs a remainder system to convert one large-width modulo-Q data stream into four smaller-width data streams with modulo q0, q1, q2, and q3. After the calculation, the ciphertext or plaintext data from the four smaller-width modulo streams needs to be converted back into one large-width modulo stream. The design method for the modulo-digital conversion is as follows: the remainder base q can be converted using the Chinese Remainder Theorem. i The coefficients under the given condition are converted to polynomial coefficients modulo Q, and the calculation formula is as follows:

[0072]

[0073] Among them, t i For Q i Mod q i Inverse in a meaningful sense. t is pre-calculated using Python. i and Q i Defined in the FPGA as parameters, a i This provides ciphertext or plaintext data for four small-bit-width modulo operations, where modQ indicates modulo-Q operations. Pipeline and parallel processing are employed in the circuit design to improve the module's operational efficiency.

[0074] This invention proposes an FPGA-based homomorphic encryption hardware accelerator. Analysis of the main time-consuming points in the homomorphic encryption and decryption process reveals that a large number of operations are performed on polynomial rings. Polynomial multiplication is one of the most critical and time-consuming operations in encryption and decryption, and its computation time increases significantly when processing large-scale data. The invention reduces the computational complexity of polynomial multiplication by utilizing number theory transformations and the negative package convolution theorem, and transforms the modulo operation into multiplication and shift operations using the Montgomery reduction algorithm, thereby improving the computational efficiency of polynomial operations. Simultaneously, the bit width of the polynomial coefficients also affects the efficiency of the modulo operation. By utilizing the remainder system and the Chinese Remainder Theorem, high-bit-width modulo operations are transformed into low-bit-width modulo operations, and parallel processing is employed to increase parallelism and reduce the execution time required for encryption and decryption.

[0075] This invention proposes an FPGA-based homomorphic encryption hardware accelerator. On one hand, it reduces the complexity of finite-field polynomial multiplication in homomorphic encryption by eliminating the polynomial multiplication order reduction process, reducing the difficulty of polynomial coefficient reduction, and allowing the circuit to be synthesized into a higher-frequency structure, thus improving the efficiency of polynomial computation. On the other hand, through modulo conversion technology, it converts large-number modulo operations into multiple sets of small-number modulo operations, and designs parallel and pipelined processing schemes to improve the overall throughput of the accelerator.

[0076] Example 2

[0077] like Figure 8As shown, this invention proposes a data processing method for an FPGA-based homomorphic encryption hardware accelerator, applicable to the FPGA-based homomorphic encryption hardware accelerator described in the above embodiments. The method includes the following steps:

[0078] The host computer generates the public key and plaintext data required for encryption or the private key and ciphertext data required for decryption, and transmits the data to the FPGA.

[0079] The FPGA receives the public key and plaintext data required for encryption or the private key and ciphertext data required for decryption from the host computer.

[0080] Convert the received data into signed binary data;

[0081] The signed binary data is subjected to a number theory transformation to obtain the transformed data. Specifically, the polynomial coefficient representation of the binary data is converted into point value data.

[0082] According to the functional requirements, the point value data is encrypted or decrypted to obtain ciphertext data or plaintext data;

[0083] The encrypted or plaintext data is transformed by inverse number theory to obtain the transformed data, which is represented by polynomial coefficients.

[0084] The data after inverse number theory transformation is converted from small-bit-width modulus to large-bit-width modulus using the Chinese Remainder Theorem, and the converted data is then transmitted to the host computer.

[0085] The host computer compares the data to check if it is correct.

[0086] Specific methods for encrypting data after number theory transformation to obtain ciphertext data include:

[0087] The data required for encryption calculation is stored sequentially in the second data storage unit. After all the data has been stored for encryption, the stored data is read out and transmitted to the encryption calculation unit to obtain ciphertext data. The ciphertext data is then transmitted to the second data storage unit for storage. The second data storage unit includes eight sets of single-port RAM. Six sets of RAM are used to store the parameters required for homomorphic encryption, and the remaining two sets of RAM are used to store the encrypted ciphertext data. Each set of RAM contains four single-port RAMs with a bit width of 17 bits and a depth of 256.

[0088] The data read from the second data storage unit is encrypted to obtain ciphertext data.

[0089] The specific methods for decrypting data after number theory transformation to obtain plaintext data include:

[0090] The data required for decryption calculation is stored sequentially in the third data storage unit. After all the data has been stored for decryption, the stored data is read out and transmitted to the decryption calculation unit to obtain plaintext data. The plaintext data is then transmitted to the third data storage unit for storage. The third data storage unit includes four sets of single-port RAM. Three sets of RAM are used to store the parameters required for homomorphic decryption, and the remaining set of RAM is used to store the plaintext data obtained from decryption. Each set of RAM contains four single-port RAMs with a bit width of 17 bits and a depth of 256.

[0091] The data read from the third data storage unit is decrypted to obtain plaintext data.

[0092] The data processing method for a homomorphic encryption hardware accelerator based on FPGA proposed in this invention reduces the complexity of finite-field polynomial multiplication in homomorphic encryption by eliminating the polynomial multiplication order reduction process, reducing the difficulty of polynomial coefficient reduction, and allowing the circuit to be synthesized into a higher-frequency structure, thus improving the efficiency of polynomial computation. Furthermore, by using modulo conversion technology to convert large-number modulo operations into multiple sets of small-number modulo operations, and designing parallel and pipelined processing schemes, the throughput of the entire accelerator is improved.

[0093] Example 3

[0094] Another embodiment of the present invention provides an FPGA capable of implementing homomorphic encryption hardware acceleration, comprising a processor and a memory, the memory for storing a computer program, the computer program including program instructions, and the processor configured to invoke the program instructions to execute the aforementioned data processing method of the FPGA-based homomorphic encryption hardware accelerator.

[0095] It should be understood that, in the embodiments of the present invention, the processor may be a Central Processing Unit (CPU), but it may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0096] The memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store information about the device type.

[0097] In specific implementations, the processor described in the embodiments of the present invention can execute the implementation methods described in the method embodiments of the present invention, or it can execute the implementation methods described in the system embodiments of the present invention, which will not be repeated here.

[0098] Example 4

[0099] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the aforementioned data processing method of the FPGA-based homomorphic encryption hardware accelerator.

[0100] The computer-readable storage medium can be an internal storage unit of the terminal described in the foregoing embodiments, such as the terminal's hard drive or memory. The computer-readable storage medium can also be an external storage device of the device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the terminal. Further, the computer-readable storage medium may include both internal storage units and external storage devices of the terminal. The computer-readable storage medium is used to store the computer program and other programs and data required by the terminal. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0101] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the terminals and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0102] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, or may be electrical, mechanical or other forms of connection.

[0103] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An FPGA-based homomorphic encryption hardware accelerator, characterized by, The FPGA terminal includes a data transmission module, a control module, a homomorphic encryption module, a homomorphic decryption module, a number theory transformation module, and a small-to-large analog-to-digital conversion module. The data transmission module is used to realize data transmission between the FPGA and the host computer; The control module is used to control the flow of data between various modules according to encryption or decryption operations; The number theory transformation module is used to perform number theory transformation or inverse number theory transformation on the input data to obtain the transformed data or the data after inverse number theory transformation. The homomorphic encryption module is used to encrypt the transformed data to obtain ciphertext data; The homomorphic decryption module is used to decrypt the transformed data to obtain plaintext data; The small-to-large analog-to-digital converter module is used to convert multiple small-width analog-to-digital encrypted or plaintext data into one large-width analog-to-digital data. The control module controls the input data to the number theory transformation module for number theory transformation, transmits the transformed data to the homomorphic encryption module or homomorphic decryption module for encryption or decryption, transmits the encrypted ciphertext data or decrypted plaintext data to the number theory transformation module for inverse number theory transformation, transmits the transformed data to the small-to-large modulus conversion module for conversion processing, and transmits the converted data to the data transmission module.

2. The FPGA-based homomorphic encryption hardware accelerator of claim 1, wherein, The data transmission module includes a UART data transmission unit, a string-to-binary unit, a large-to-small analog-to-digital conversion unit, and a first data storage unit; The UART data transmission unit includes 1 start bit, 8 data bits and 1 stop bit in a frame of data during the transmission or reception process. It also concatenates the 32 frames of data transmitted from the host computer into 256 bits of ASCII code data and transmits the 256 bits of ASCII code data to the string to binary conversion unit. The string to binary unit is used to remove the high 4 bits of every 8 bits of the received 256-bit ASCII code data to obtain a 128-bit BCD code with a value range of 0 to 9. Then, the 128-bit BCD code is converted into a 128-bit signed binary code through iterative operation. Each iteration operation multiplies 4 bits of data by 10 and accumulates them. The large-to-small modulus conversion unit performs modulus operation based on a residue system on 128-bit signed binary data, and converts one 128-bit data into four 17-bit data of modulus q 0 1 2 3 The four 17-bit data are calculated simultaneously in parallel architecture, and the processing of each data is in the form of serial structure from low to high, and then is accumulated, and is operated for 8 times to obtain the final result.​​​ The first data storage unit includes four sets of single-port RAM, of which three sets are four single ports with a width of 17 bits and a depth of 256 bits used to store the final result, and one set is a single port with a width of 256 bits and a depth of 256 bits used to store plaintext or ciphertext data to be sent to the host computer.

3. The FPGA-based homomorphic encryption hardware accelerator of claim 2, wherein, The large-to-small modular conversion unit includes a Montgomery simple element, which performs modulo operations using shift and multiplication operations.

4. The FPGA-based homomorphic encryption hardware accelerator of claim 1, wherein, The homomorphic encryption module includes an encryption control unit, an encryption calculation unit, and a second data storage unit; The encryption control unit is used to store the data required for encryption calculation in the second data storage unit in sequence. After all the data has been stored for encryption, the stored data is read out and transmitted to the encryption calculation unit to obtain ciphertext data, and the ciphertext data is transmitted to the second data storage unit. The encryption calculation unit is used to encrypt the data read from the second data storage unit to obtain ciphertext data; The second data storage unit includes eight single-port RAMs, of which six RAMs are used to store the parameters required for homomorphic encryption, and the remaining two RAMs are used to store the encrypted ciphertext data. Each RAM contains four single-port RAMs with a bit width of 17 bits and a depth of 256.

5. The FPGA-based homomorphic encryption hardware accelerator of claim 1, wherein, The homomorphic decryption module includes a decryption control unit, a decryption calculation unit, and a third data storage unit; The decryption control unit is used to store the data required for decryption calculation in the third data storage unit in sequence. After all the data has been stored in one decryption, the stored data is read out and transmitted to the decryption calculation unit to obtain plaintext data, and the plaintext data is transmitted to the third data storage unit. The decryption calculation unit is used to decrypt the data read from the third data storage unit to obtain plaintext data; The third data storage unit includes four sets of single-port RAMs. Three sets of RAMs are used to store the parameters required for homomorphic decryption, and the remaining set of RAMs is used to store the plaintext data obtained from decryption. Each set of RAMs contains four single-port RAMs with a bit width of 17 bits and a depth of 256.

6. The FPGA-based homomorphic encryption hardware accelerator of claim 1, wherein, The number theory transformation module includes a butterfly operation unit, a control unit, a preprocessing and postprocessing unit, and a fourth data storage unit; The butterfly operation unit uses frequency decimation to perform butterfly operations, which include modular addition, modular subtraction, and modular multiplication. Specifically, the first 128 data are added to the last 128 data to obtain an even number of terms, the first 128 data are subtracted from the last 128 data and then multiplied by the rotation factor to obtain an odd number of terms. The butterfly operation is performed over a finite field, and after the calculation is completed, a modulo operation is performed. The control unit is used to read data from RAM2 to perform NTT operation to obtain a first calculation result, and store the first calculation result in RAM3. When all NTT operations in this layer are completed, it reads data from RAM3 to perform NTT operation to obtain a second calculation result, and stores the second calculation result in RAM2. The operation is repeated until the entire NTT operation is completed. The preprocessing and postprocessing unit is used to complete the preprocessing and postprocessing of polynomial parameters to obtain the preprocessing calculation results and the postprocessing calculation results; The fourth data storage unit includes four sets of dual-port RAMs, wherein RAM0 and RAM1 are used to store preprocessing calculation results and postprocessing calculation results, and RAM2 and RAM3 are used to store intermediate results in the NTT transformation process. Each set of RAMs contains four dual-port RAMs with a bit width of 17 bits and a depth of 256.

7. A data processing method of a FPGA-based homomorphic encryption hardware accelerator, characterized by, The FPGA-based homomorphic encryption hardware accelerator according to any one of claims 1 to 6 comprises: Receive the public key and plaintext data required for encryption or the private key and ciphertext data required for decryption sent by the host computer; Convert the received data into signed binary data; The signed binary data is subjected to number theory transformation to obtain the number theory transformed data; According to the functional requirements, the data after the number theory transformation is encrypted or decrypted to obtain ciphertext data or plaintext data; Perform an inverse number theory transformation on either ciphertext or plaintext data to obtain the data after the inverse number theory transformation. The data after inverse number theory transformation is converted from small-bit-width modulus to large-bit-width modulus, and the converted data is transmitted to the host computer.

8. The FPGA-based homomorphic encryption hardware accelerator-based data processing method of claim 7, wherein, Specific methods for encrypting the data after the number theory transformation to obtain ciphertext data include: The data required for encryption calculation is stored sequentially in the second data storage unit. After all the data has been stored for encryption, the stored data is read out and transmitted to the encryption calculation unit to obtain ciphertext data. The ciphertext data is then transmitted to the second data storage unit for storage. The second data storage unit includes eight sets of single-port RAM. Six sets of RAM are used to store the parameters required for homomorphic encryption, and the remaining two sets of RAM are used to store the encrypted ciphertext data. Each set of RAM contains four single-port RAMs with a bit width of 17 bits and a depth of 256. The data read from the second data storage unit is encrypted to obtain ciphertext data; Specific methods for decrypting the data after the number theory transformation to obtain plaintext data include: The data required for decryption calculation is stored sequentially in the third data storage unit. After all the data has been stored for decryption, the stored data is read out and transmitted to the decryption calculation unit to obtain plaintext data. The plaintext data is then transmitted to the third data storage unit for storage. The third data storage unit includes four sets of single-port RAM. Three sets of RAM are used to store the parameters required for homomorphic decryption, and the remaining set of RAM is used to store the plaintext data obtained from decryption. Each set of RAM contains four single-port RAMs with a bit width of 17 bits and a depth of 256. The data read from the third data storage unit is decrypted to obtain plaintext data.

9. An FPGA that enables homomorphic encryption hardware acceleration, the FPGA comprising: The system includes a processor and a memory, the memory being used to store a computer program, the computer program including program instructions, characterized in that the processor is configured to invoke the program instructions to perform the method as described in any one of claims 7 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 7 to 8.

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