A method and system for optimizing FPGA chip wiring

Abstract

A method and system for optimizing FPGA chip routing, comprising the following steps: Step S1: sorting nets according to their specifications; Step S2: selecting, based on the sorted nets, the receiving point of each net that needs to be moved and adjusted as the first moving point; Step S3: selecting a search space that needs to be adjusted based on the center points of the nets where the first moving points are located; Step S4: updating the positions of the first moving points within the search space using a position evaluation function; Step S5: setting an update multiplier and re-executing Steps S1 to S4. Based on the relationship between the last obtained number of updates and the update multiplier, the final update result is obtained as the final output for FPGA chip routing. A search is performed on the center point area of ​​the target net associated with the nets, and positions with high evaluation scores are selected for movement or exchange. After updating a certain number of nets, the nets are rearranged to ensure rapid convergence.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic integrated circuits, and in particular to a method and system for optimizing FPGA chip wiring. Background Art

[0002] FPGA (Field Programmable Gate Array), namely field programmable gate array, is a programmable logic device widely used in digital circuit design, such as Figure 1 As shown, FPGAs primarily consist of programmable logic blocks (PLBs), block RAM, DSP, and I / O in a regular array. Currently, FPGA layout and routing is divided into five phases: initial layout, detailed layout, routing resource allocation, routing optimization, and timing verification. Detailed layout primarily refines the placement of logic cells based on the initial layout. Therefore, more detailed factors, such as the internal routing resource distribution of the FPGA chip and the physical characteristics of the logic cells, are considered to ensure that the layout not only minimizes wire lengths but also adapts to the chip's physical structure, meets the timing requirements of critical networks, and minimizes interconnect congestion. Routing is the most time-consuming aspect of the overall FPGA EDA process. Empirical statistics show that routing runtime can account for 50% to 70% of complex design cases. Therefore, optimizing routing runtime is crucial for improving the efficiency of the EDA convergence process. A deeper analysis of the routing time contribution reveals that global interconnect conflicts, caused by the algorithm's processing of the complex driver relationships across the PLB (Programmable Logic Block) netlist, are the primary source of time consumption. Therefore, future wiring requirements need to be fully considered during the detailed layout stage.

[0003] As FPGAs continue to grow in size, the number of logic cells can reach millions or even more, and the layout search space grows exponentially. Complex connectivity and timing requirements exist between different logic cells. Finding the optimal layout within this vast search space is a significant challenge, a critical NP-hard problem. During the detailed layout phase, multiple performance metrics, such as latency, power consumption, and area, often need to be optimized simultaneously. These metrics often constrain each other. For example, reducing latency may require increasing routing resources, resulting in increased area and power consumption. Balancing these objectives to achieve an overall optimal solution is a major challenge. Finally, in manufacturing processes, FPGA routing resources are limited and complexly distributed, with varying amounts and types of routing resources in different areas. During layout, the impact of the logic cell distribution on routing must be considered to avoid routing congestion and ensure smooth signal routing and connection. This further increases the complexity and difficulty of layout.

[0004] To address the current large-scale integrated circuit layout and routing issues, traditional layout generally uses heuristic algorithms such as simulated annealing or genetic algorithms to perform detailed layout adjustments. However, this algorithm has slow convergence speed and high complexity when faced with large-scale FPGA layouts, resulting in unstable operation results and difficulty in effectively handling complex constraints in FPGAs. Summary of the Invention

[0005] In view of the above-mentioned defects, the purpose of the present invention is to propose a method and system for optimizing FPGA chip wiring, so as to solve the problems of slow convergence speed and unstable optimization operation results of existing optimization methods.

[0006] To achieve this purpose, the present invention adopts the following technical solution: a method for optimizing FPGA chip wiring, including the following methods:

[0007] Step S1: sorting according to the specifications of the wire mesh;

[0008] Step S2: Based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted is selected as the first moving point;

[0009] Step S3: Based on the center point of the line network where the multiple first moving points are located, select the search space that needs to be adjusted;

[0010] Step S4: in the search space, using a position evaluation function to update the position of the first moving point;

[0011] Step S5: Set the update multiple, re-execute steps S1 to S4, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained number of updates and the update multiple.

[0012] Preferably, the step S1 is specifically as follows:

[0013] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0014] The nets are sorted from smallest to largest based on the average drive length.

[0015] Preferably, the step S2 is specifically as follows:

[0016] For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement;

[0017] For a line network with a driving point smaller than the first threshold and larger than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point;

[0018] For the line network with a driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

[0019] Preferably, the step S3 is specifically as follows:

[0020] Construct a set N of line networks where the first moving point is located;

[0021] Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates;

[0022] In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point;

[0023] The search space is constructed based on the first coordinate point and the second coordinate point.

[0024] Preferably, the step S4 is specifically as follows:

[0025] Step S41: Count the PLBs in the search space and calculate the density of all PLBs;

[0026] The density is obtained as follows:

[0027] Step S42: sort the PLB densities from large to small, and select the first N densities as the adjustment threshold R, where N is 5-10%;

[0028] Step S43: Searching for a movable position in the search space, moving the first movable point to the movable position, and calculating the density r after the move, determining whether the density r after the move is greater than the adjustment threshold R. If so, the first movable point does not move. If not, obtaining a score after the move based on the position evaluation function, and determining whether the score is greater than 0. If so, the first movable point is moved to the movable position. If not, the first movable point does not move.

[0029] Step S44: Replace the next first moving point and re-execute step S43 until all first moving points are calculated.

[0030] A system for optimizing FPGA chip wiring, using the method for optimizing FPGA chip wiring, comprising a sorting module, a point selection module, a region selection module, an adjustment module, and an update module;

[0031] The sorting module is used to sort the wire mesh according to its specifications;

[0032] The point selection module is used to select, based on the sorted wire meshes, a receiving point of each wire mesh that needs to be moved and adjusted as a first moving point;

[0033] The region selection module is used to select a search space that needs to be adjusted based on the center point of the line network where the multiple first moving points are located;

[0034] The adjustment module is used to update the position of the first moving point in the search space using a position evaluation function;

[0035] The update module is used to set the update multiple, re-call the sorting module, point selection module, area selection module and adjustment module, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained number of updates and the update multiple.

[0036] Preferably, the sorting module performs the following operations:

[0037] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0038] The nets are sorted from smallest to largest based on the average drive length.

[0039] Preferably, the point selection module performs the following operations:

[0040] For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement;

[0041] For a line network with a driving point smaller than the first threshold and larger than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point;

[0042] For the line network with a driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

[0043] Preferably, the region selection module performs the following operations:

[0044] Construct a set N of line networks where the first moving point is located;

[0045] Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates;

[0046] In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point;

[0047] The search space is constructed based on the first coordinate point and the second coordinate point.

[0048] Preferably, the update module includes a statistics submodule, a threshold acquisition submodule, a position determination submodule and a loop submodule;

[0049] The statistics submodule is used to count the PLBs in the search space and calculate the density of all PLBs;

[0050] The threshold acquisition submodule is used to sort the density of PLBs from large to small, and select the first N density as the adjustment threshold R, where the value of N is 5-10%;

[0051] The position judgment submodule is used to search for a movable position in the search space, move the first movable point to the movable position, and calculate the density r after the movement, and judge whether the density r after the movement is greater than the adjustment threshold R. If it is greater, the first movable point will not be moved. If it is less, a score after the movement is obtained based on the position evaluation function, and whether the score is greater than 0. If it is greater, the first movable point is moved to the movable position. If it is not greater, the first movable point will not be moved.

[0052] The loop submodule is used to replace the next first moving point and re-call the position determination submodule until all the first moving points are calculated.

[0053] One of the above technical solutions has the following advantages or beneficial effects: by sorting the line network optimization potential, the results of the line network with large optimization potential and small scale are quickly converged, thereby ensuring the success rate of the optimized layout; searching the line network center point area associated with the target line network, selecting the position with high evaluation score to move or exchange, and rearranging the line network after updating a certain number of line networks to ensure that the results converge quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 This is the basic architecture diagram of FPGA.

[0055] Figure 2 It is a positional relationship diagram between the wire networks.

[0056] Figure 3 It is a flow chart of an embodiment of the method of the present invention.

[0057] Figure 4 It is a structural diagram of an embodiment of the system of the present invention. DETAILED DESCRIPTION

[0058] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention.

[0059] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, "plurality" means two or more, unless otherwise specifically specified.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "plurality" means two or more. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0061] like Figures 1 to 4 As shown, a method for optimizing FPGA chip routing includes the following methods:

[0062] Step S1: sorting according to the specifications of the wire mesh;

[0063] In an FPGA, the number of node units is typically around 10k-100k, organized into meshes of varying sizes based on their connectivity. A mesh consists of a driver and several sinks. Depending on the number of sinks, the mesh size can range from tens to hundreds. Large fan-out meshes, such as reset signals, can exceed 800 in size. Optimizing such large fan-out meshes is prohibitively expensive, as calculating wire lengths and searching for locations is time-consuming and significantly impacts other meshes. Therefore, meshes need to be sorted by size, prioritizing smaller meshes and iterating on meshes with high optimization efficiency to achieve rapid convergence and ensure the feasibility of the optimization results.

[0064] Step S2: Based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted is selected as the first moving point;

[0065] Step S3: Based on the center point of the line network where the multiple first moving points are located, select the search space that needs to be adjusted;

[0066] Step S4: in the search space, using a position evaluation function to update the position of the first moving point;

[0067] Step S5: Set the update multiple, re-execute steps S1 to S4, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained number of updates and the update multiple.

[0068] The present invention uses a strategy based on searching in the center area of ​​associated wire meshes. First, the wire meshes are screened by scale analysis. Due to too many layout constraints, a reasonable position evaluation function needs to be designed based on comprehensive consideration of wire length, density, and timing. A unified evaluation is performed on numerous and complex constraints to ensure the feasibility of the optimization results. Subsequently, the wire meshes with large optimization potential and small scale are ranked for rapid convergence of results, ensuring the success rate of the optimized layout. The center point area of ​​the target wire mesh is searched, and positions with high evaluation scores are selected for movement or exchange. After a certain number of wire meshes are updated, the wire meshes are rearranged to ensure rapid convergence of results.

[0069] Finally, regarding the stability of the results, since the optimization effect in the later stage of optimization is relatively discrete and the optimization effect is small, an update multiple is set in the present invention. For example, if the update multiple is 100 and the closing time arrives and the number of updates is 260, the last update result will be selected as a multiple of 100, of which 200 is closest to 260 and is a multiple of 100. In this case, the 200th update result will be selected as the final output of the FPGA chip wiring. If the update multiple is 30 and the closing time arrives and the number of updates is 260, the last update result will be selected as a multiple of 30, of which 240 is closest to 260 and is a multiple of 30. In this case, the 240th update result will be selected as the final output of the FPGA chip wiring.

[0070] This ensures stable optimization results across multiple runs, meeting the actual layout and routing requirements of enterprise production. Experimental results on wire nets of varying sizes demonstrate that this method can maintain density while meeting timing constraints, reduce critical and non-critical wire lengths on large-scale wire nets, and thereby lower subsequent wiring costs, shorten wiring time, and improve efficiency, resulting in significant cost savings for enterprises. Furthermore, the optimization results are significantly superior for complex wire net connections and numerous constraints.

[0071] Preferably, the step S1 is specifically as follows:

[0072] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0073] The nets are sorted from smallest to largest based on the average drive length.

[0074] Since the scale of the wire network is generally positively correlated with the total length, it is necessary to perform unified sorting by the average wire length. Sort the initial wire network lengths according to the average driving length. Let the number of driven points of the wire network be d, the total length of the wire network be L, and the average driving length be Evaluate wire networks of different scales in a unified manner to prevent the influence of different wire network scales.

[0075] Preferably, the specific steps of step S2 are as follows:

[0076] For wire networks with the number of driving points greater than or equal to the first threshold, do not select receiving points for movement;

[0077] For wire networks with the number of driving points less than the first threshold and greater than the second threshold, select the receiving points with the top 50% of the Manhattan wire length based on the driving points as the first moving points;

[0078] For wire networks with the number of driving points less than the second threshold, select all receiving points as the first moving points.

[0079] For wire networks with a small number of driven points, the calculation is faster, so a higher selection ratio is adopted. For wire networks with a large and scattered scale, partial selection or even no selection is performed to prevent repeated calculation of the Steiner tree at large fan-out wire networks, which consumes a lot of time. After multiple tests, for large wire network scales, the first threshold is taken as 20, and when d >= 20, movement is not considered. For medium wire network scales, the second threshold can be taken as 5, and when 5 < d < 20, select the receiving points with the top 50% of the Manhattan wire length as the first moving points. For small wire network scales d <= 5, select all receiving points as the first moving points. By analyzing the driving points of wire networks of different scales, select receiving points with great optimization potential for subsequent search, fully considering the characteristic that the calculation time of wire length is relatively long, and try to avoid repeated calculation of large wire networks.

[0080] Preferably, the specific steps of step S3 are as follows:

[0081] Construct a set N of wire networks where the first moving points are located;

[0082] Find the coordinates of all nodes of each wire network in set N, obtain the central coordinates based on the coordinates of all nodes, and construct a central coordinate set from multiple central coordinates;

[0083] In the central coordinate set, select the smallest abscissa and the smallest ordinate to construct the first coordinate point, and select the largest abscissa and the largest ordinate to construct the second coordinate point;

[0084] Construct the search space based on the first coordinate point and the second coordinate point.

[0085] The search range of the node to be moved obtained above is determined to search for feasible positions. Since a receiving point sink can be driven by multiple driving points, or can drive multiple receiving point sinks to form a new network, when considering the movement of the first moving point, it is necessary to fully consider its optimization or even deterioration of other associated networks. For large-scale intensive integrated circuits, the feasible positions are limited under the consideration of various resource limitations and timing constraints. Therefore, a strategy for searching the position in the center area of ​​the associated network is used. Figure 2 As shown in the figure, assume that there are three nets net1, net2, and net3. Get the coordinates of all nodes (nodes include driving points and receiving points) of each net net1, net2, and net3 respectively, and get the center coordinates based on the coordinates of all nodes. The calculation formula of the center coordinates is:

[0086] Where p is the total number of nodes in the network, They represent the horizontal and vertical coordinates of the j-th node of the i-th network respectively;

[0087] Then we can get the center coordinates of net1 respectively The center coordinates of net2 and the center coordinates of net1 Depend on Figure 2 It can be seen that among all the horizontal coordinates, the horizontal coordinate of net2 is the smallest and the horizontal coordinate of net3 is the largest. In the vertical coordinates, the vertical coordinate of net2 is the smallest and the vertical coordinate of net1 is the largest. At this time, the first coordinate point is The second coordinate point is A rectangular search space can be determined based on two coordinate points.

[0088] Preferably, the step S4 is specifically as follows:

[0089] Step S41: Count the PLBs in the search space and calculate the density of all PLBs;

[0090] The density is obtained as follows:

[0091] Among them I con , O con They represent the input pins and output pins of the connection network in the PLB, respectively. to , O to Respectively represent all input pins and all output pins that the PLB can accommodate.

[0092] Step S42: sort the PLB densities from large to small, and select the first N densities as the adjustment threshold R, where N is 5-10%;

[0093] During detailed layout, it's crucial to ensure minimal density degradation to reduce congestion. Therefore, all PLBs are initially ranked by density, and the density before the highest density is selected as the lower limit. For example, if N is 5%, then when there are 1000 PLBs, the density of the first 50 PLBs is selected as the adjustment threshold R.

[0094] Step S43: Searching for a movable position in the search space, moving the first movable point to the movable position, and calculating the density r after the move, determining whether the density r after the move is greater than the adjustment threshold R. If so, the first movable point does not move. If not, obtaining a score after the move based on the position evaluation function, and determining whether the score is greater than 0. If so, the first movable point is moved to the movable position. If not, the first movable point does not move.

[0095] The density r after movement is the density of the PLB affected by the first moving point after movement.

[0096] The position evaluation function is as follows:

[0097] Where k is the optimization weight, Among them L noncrit is the initial non-critical line length, L crit is the initial critical line length. The critical line length is the line length connected to the driving end of the key node in the line network. The others are non-critical line lengths. crit and Δl non-crit The change in critical line length before and after the first moving point is calculated, as well as the change in non-critical line length. The critical line length is calculated using the Manhattan distance of the corresponding PLB, while the Steiner tree distance of the non-critical line length is calculated using the open source tool FLUTE.

[0098] Step S44: Replace the next first moving point and re-execute step S43 until all first moving points are calculated.

[0099] A system for optimizing FPGA chip wiring, using the method for optimizing FPGA chip wiring, comprising a sorting module, a point selection module, a region selection module, an adjustment module, and an update module;

[0100] The sorting module is used to sort the wire mesh according to its specifications;

[0101] The point selection module is used to select, based on the sorted wire meshes, a receiving point of each wire mesh that needs to be moved and adjusted as a first moving point;

[0102] The region selection module is used to select a search space that needs to be adjusted based on the center point of the line network where the multiple first moving points are located;

[0103] The adjustment module is used to update the position of the first moving point in the search space using a position evaluation function;

[0104] The update module is used to set the update multiple, re-call the sorting module, point selection module, area selection module and adjustment module, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained number of updates and the update multiple.

[0105] Preferably, the sorting module performs the following operations:

[0106] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0107] The nets are sorted from smallest to largest based on the average drive length.

[0108] Preferably, the point selection module performs the following operations:

[0109] For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement;

[0110] For a line network with a driving point smaller than the first threshold and larger than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point;

[0111] For the line network with a driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

[0112] Preferably, the region selection module performs the following operations:

[0113] Construct a set N of line networks where the first moving point is located;

[0114] Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates;

[0115] In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point;

[0116] The search space is constructed based on the first coordinate point and the second coordinate point.

[0117] Preferably, the update module includes a statistics submodule, a threshold acquisition submodule, a position determination submodule and a loop submodule;

[0118] The statistics submodule is used to count the PLBs in the search space and calculate the density of all PLBs;

[0119] The threshold acquisition submodule is used to sort the density of PLBs from large to small, and select the first N density as the adjustment threshold R, where the value of N is 5-10%;

[0120] The position judgment submodule is used to search for a movable position in the search space, move the first movable point to the movable position, and calculate the density r after the movement, and judge whether the density r after the movement is greater than the adjustment threshold R. If it is greater, the first movable point will not be moved. If it is less, a score after the movement is obtained based on the position evaluation function, and whether the score is greater than 0. If it is greater, the first movable point is moved to the movable position. If it is not greater, the first movable point will not be moved.

[0121] The loop submodule is used to replace the next first moving point and re-call the position determination submodule until all the first moving points are calculated.

[0122] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative uses of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0123] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A method for optimizing FPGA chip wiring, characterized in that: The following methods are included: Step S1: sorting according to the specifications of the wire mesh; Step S2: Based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted is selected as the first moving point; Step S3: Based on the center point of the line network where the multiple first moving points are located, select the search space that needs to be adjusted; Step S4: in the search space, using a position evaluation function to update the position of the first moving point; Step S5: Set the update multiple and re-execute steps S1 to S4. Based on the relationship between the last obtained update times and the update multiple, obtain the final update result as the final output of the FPGA chip wiring; The step S1 is specifically as follows: Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained; sorting the nets from small to large based on the average drive length; For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement; For a line network with a driving point smaller than the first threshold and larger than the second threshold, the first 50% of the receiving points in the Manhattan line length are selected as the first moving points based on the driving point; For the line network with a driving point smaller than the second threshold, all receiving points are selected as the first moving points; Construct a set N of line networks where the first moving point is located; Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates; In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point; Constructing the search space based on the first coordinate point and the second coordinate point; The step S4 is specifically as follows: Step S41: Count the PLBs in the search space and calculate the density of all PLBs; The formula for obtaining density is as follows: ,in They represent the input pins and output pins of the connection net in the PLB respectively. Respectively represent all input pins and all output pins that can be accommodated by the PLB; Step S42: Sort the PLB densities from large to small, and select the first N densities as the adjustment threshold R, where N is 5-10%; Step S43: Searching for a movable position in the search space, moving the first movable point to the movable position, and calculating the density r after the move, determining whether the density r after the move is greater than the adjustment threshold R. If so, the first movable point does not move. If not, obtaining a score after the move based on the position evaluation function, and determining whether the score is greater than 0. If so, the first movable point is moved to the movable position. If not, the first movable point does not move. The position evaluation function is as follows: , where k is the optimization weight, ,in is the initial non-critical line length, is the initial critical line length. The critical line length is the length of the line connected to the driving end of the key node in the line network. The others are non-critical line lengths. and The change values ​​of the critical line length and the non-critical line length before and after the first moving point are calculated. The Manhattan distance of the PLB to which the critical line length belongs is used for calculation, while the Steiner tree distance of the non-critical line length is calculated using the open source tool FLUTE. Step S44: Replace the next first moving point and re-execute step S43 until all first moving points are calculated.

2. A system considering FPGA chip wiring optimization, characterized in that: Using the FPGA chip wiring optimization method described in claim 1, comprising a sorting module, a point selection module, a region selection module, an adjustment module, and an update module; The sorting module is used to sort the wire mesh according to its specifications; The point selection module is used to select, based on the sorted wire meshes, a receiving point of each wire mesh that needs to be moved and adjusted as a first moving point; The region selection module is used to select a search space that needs to be adjusted based on the center point of the line network where the multiple first moving points are located; The adjustment module is used to update the position of the first moving point in the search space using a position evaluation function; The update module is used to set the update multiple, re-call the sorting module, the point selection module, the area selection module and the adjustment module, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained update number and the update multiple; The sorting module performs the following operations: Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained; sorting the nets from small to large based on the average drive length; The point selection module performs the following operations: For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement; For a line network with a driving point smaller than the first threshold and larger than the second threshold, the first 50% of the receiving points in the Manhattan line length are selected as the first moving points based on the driving point; For the line network with a driving point smaller than the second threshold, all receiving points are selected as the first moving points; The region selection module performs the following operations: Construct a set N of line networks where the first moving point is located; Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates; In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point; Constructing the search space based on the first coordinate point and the second coordinate point; The update module includes a statistics submodule, a threshold acquisition submodule, a position judgment submodule and a circulation submodule; The statistics submodule is used to count the PLBs in the search space and calculate the density of all PLBs; The threshold acquisition submodule is used to sort the density of PLBs from large to small and select the first N density as the adjustment threshold R, where the value of N is 5-10%; The formula for obtaining density is as follows: ,in They represent the input pins and output pins of the connection net in the PLB respectively. Respectively represent all input pins and all output pins that can be accommodated by the PLB; The position judgment submodule is used to search for a movable position in the search space, move the first movable point to the movable position, and calculate the density r after the movement, and judge whether the density r after the movement is greater than the adjustment threshold R. If it is greater, the first movable point will not be moved. If it is less, a score after the movement is obtained based on the position evaluation function, and whether the score is greater than 0. If it is greater, the first movable point is moved to the movable position. If it is not greater, the first movable point will not be moved. The position evaluation function is as follows: , where k is the optimization weight, ,in is the initial non-critical line length, is the initial critical line length. The critical line length is the length of the line connected to the driving end of the key node in the line network. The others are non-critical line lengths. and The change values ​​of the critical line length and the non-critical line length before and after the first moving point are calculated. The Manhattan distance of the PLB to which the critical line length belongs is used for calculation, while the Steiner tree distance of the non-critical line length is calculated using the open source tool FLUTE. The loop submodule is used to replace the next first moving point and re-call the position determination submodule until all the first moving points are calculated.

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