Method, apparatus, device and medium for generating layout constraints of chip standard cells

Abstract

The present disclosure provides a method, apparatus, device and medium for generating layout constraints for chip standard cells. The method for generating layout constraints for chip standard cells includes: determining initial width and initial height information of a core area according to area information of all provided standard cells, an expected aspect ratio of the core area, the width of a Site, the height of the Site and an expected utilization rate; classifying the provided placement modules and determining initial width and initial height information of each placement module; adjusting the initial width and initial height information of the placement modules according to area verification rules of the placement modules; and sequentially arranging the placement modules in the core area according to placement verification rules of the placement modules. The method for generating layout constraints for chip standard cells provided in some embodiments of the present disclosure can greatly reduce the time cost and labor cost of writing layout constraint scripts and accelerate the digital back-end process.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip design, and particularly to a method, apparatus, device, and medium for generating layout constraints for chip standard cells. Background Art

[0002] The main work of digital chip backend design is to complete the design process of the chip from the gate-level netlist to the GDSII physical layout.

[0003] For the conventional chip backend design process, the placement of standard cells is mainly carried out by using EDA tool software. After the user provides the gate-level netlist as an input file to the EDA software, by using the EDA software in combination with its embedded algorithms, a large number of standard cells in the gate-level netlist can be directly placed, while meeting requirements such as timing, routing resources, and design rule checking to a certain extent. This process is called placement. However, there are also flaws in the use of the conventional placement process. Although the EDA software will determine the positions of the standard cells according to the input information such as the pin connection relationships of each standard cell in the gate-level netlist and the timing constraint file, limited by its internal algorithms, when the mainstream EDA software performs placement on some special designs such as field programmable gate arrays (FPGAs), the layout results of the standard cells are often not satisfactory. In particular, there are problems such as poor timing performance of the critical path, excessive consumption of routing resources, unexpected functional adjustments to the netlist, such as unexpected adjustments to the types and quantities of standard cells in the netlist, resulting in the inability to achieve the design's expected functions.

[0004] Therefore, the prior art still needs to be improved and enhanced.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be simply considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In order to solve at least one of the above problems and one or more of other potential problems, the present disclosure proposes a method, apparatus, device, and medium for generating layout constraints for chip standard cells, which can greatly reduce the time cost and labor cost of writing layout constraint scripts and accelerate the progress of the digital backend process.

[0007] In a first aspect of the present disclosure, a method for generating layout constraints of chip standard cells is proposed. The method includes: determining initial width and initial height information of a core area according to area information of all provided standard cells, desired utilization rate, desired aspect ratio of the core area, width of a Site, and height of the Site; classifying the provided placement modules and determining initial width and initial height information of each of the above placement modules; adjusting the initial width and initial height information of the above placement modules according to the area verification rules of the above placement modules to obtain placement initial width and placement initial height information of the above placement modules; arranging the above placement modules in the above core area in sequence according to the placement verification rules of the above placement modules; after the above placement modules are arranged in the above core area, obtaining the core area information and the placement module arrangement information at the current moment, and then the obtained placement module layout information can be converted into an available layout constraint script.

[0008] Further, in some embodiments, the determining initial width and initial height information of the core area according to area information of all provided standard cells, desired utilization rate, desired aspect ratio of the core area, width of a Site, and height of the Site includes: determining an initial area of the core area according to area information of all provided standard cells and the desired utilization rate; determining the initial width and initial height information of the core area according to the desired aspect ratio of the core area, width of a Site, height of the Site, and the initial area of the core area.

[0009] Further, in some embodiments, the determining an initial area of the core area according to area information of all provided standard cells and the desired utilization rate includes: obtaining the area of each standard cell in all the above standard cells, summing the areas of all the obtained standard cells to obtain the total area of all the standard cells; determining the initial area of the core area according to the desired utilization rate of the core area and the total area of all the standard cells.

[0010] Further, in some embodiments, the determining the initial width and initial height information of the core area according to the desired aspect ratio of the core area, width of a Site, height of the Site, and the initial area of the core area includes: determining desired width information and desired height information of the core area according to the initial area of the core area and the desired aspect ratio of the core area; determining the multiple of the desired width and the width of the Site by rounding up as the initial width of the core area; determining the multiple of the desired height and the height of the Site by rounding up as the initial height of the core area.

[0011] Further, in some embodiments, the provided placement modules are classified, and the initial width and initial height information of each of the above placement modules is determined, including: classifying the same placement modules among all the provided placement modules into the same category; when the placement modules belonging to the same category are set as loose constraint modules, determining the sum of the areas of all the standard cells within the placement modules belonging to the loose constraint modules and belonging to the same category; determining the expected width information and expected height information of each of the placement modules belonging to the loose constraint modules and belonging to the same category according to the sum of the areas of all the standard cells within the placement modules belonging to the loose constraint modules and belonging to the same category, the internal utilization rate, and the internal aspect ratio; determining, in a ceiling manner, the multiple of the expected width of each of the placement modules belonging to the loose constraint modules and belonging to the same category to the width of the Site as the initial width of each of the placement modules belonging to the loose constraint modules and belonging to the same category; determining, in a ceiling manner, the multiple of the expected height of each of the placement modules belonging to the loose constraint modules and belonging to the same category to the height of the Site as the initial height of each of the placement modules belonging to the loose constraint modules and belonging to the same category.

[0012] Further, in some embodiments, the provided placement modules are classified, and the initial width and initial height information of each of the above placement modules is determined, further including: when the placement modules belonging to the same category are set as strict constraint modules, determining the sum of the areas of all the standard cells within the placement modules belonging to the strict constraint modules and belonging to the same category; determining the expected width information and expected height information of each of the placement modules belonging to the same category according to the sum of the areas of all the standard cells within the placement modules belonging to the strict constraint modules and belonging to the same category, the internal arrangement, the internal utilization rate, and the internal aspect ratio; determining, in a ceiling manner, the multiple of the expected width of each of the placement modules belonging to the strict constraint modules and belonging to the same category to the width of the Site as the initial width of each of the placement modules belonging to the strict constraint modules and belonging to the same category; determining, in a ceiling manner, the multiple of the expected height of each of the placement modules belonging to the strict constraint modules and belonging to the same category to the height of the Site as the initial height of each of the placement modules belonging to the strict constraint modules and belonging to the same category.

[0013] Further, in some embodiments, according to the area verification rule of the above placement module, the initial width and initial height information of the above placement module are adjusted to obtain the placement initial width and placement initial height information of the above placement module, including the following steps: S1, checking whether the standard cells in the placement module that belong to the strictly constrained module and belong to the same class can be arranged in the above placement module according to the above internal arrangement; S2, when the standard cells in the placement module that belong to the strictly constrained module and belong to the same class cannot be arranged in the above placement module according to the above internal arrangement, while keeping the total area within the set capacity range, reducing the initial height of the above placement module by 1 standard height and increasing the initial width of the above placement module by 1 standard width, or reducing the initial width of the above placement module by 1 standard width and increasing the initial height of the above placement module by 1 standard height, and rearranging the standard cells in the above placement module in the above placement module according to the above internal arrangement, where one standard height is the height of 1 Site and one standard width is the width of 1 Site; re-executing step S1; S3, when the standard cells in the placement module that belong to the strictly constrained module and belong to the same class are arranged in the above placement module according to the above internal arrangement, according to the adjusted width and adjusted height of the above placement module at this time, obtaining the placement initial width and placement initial height information of the above placement module.

[0014] Further, in some embodiments, in the above step S2, when the standard cells within the placement module that belong to the strict constraint module and the same name class cannot be arranged within the placement module according to the above internal arrangement method, while keeping the total area within the set capacity range, reduce the initial height of the placement module by one standard height and increase the initial width of the placement module by one standard width, or reduce the initial width of the placement module by one standard width and increase the initial height of the placement module by one standard height, including: when the area of the placement module is greater than the set capacity range after reducing the initial height of the placement module by one standard height and increasing the initial width of the placement module by one standard width, repeatedly execute an additional reduction of the initial height of the placement module by one standard height until the area of the placement module belongs to the set capacity range; when the area of the placement module is less than the set capacity range after reducing the initial height of the placement module by one standard height and increasing the initial width of the placement module by one standard width, repeatedly execute an additional increase of the initial width of the placement module by one standard width until the area of the placement module belongs to the set capacity range; when the area of the placement module is greater than the set capacity range after reducing the initial width of the placement module by one standard width and increasing the initial height of the placement module by one standard height, repeatedly execute an additional reduction of the initial width of the placement module by one standard width until the area of the placement module belongs to the set capacity range; when the area of the placement module is less than the set capacity range after reducing the initial width of the placement module by one standard width and increasing the initial height of the placement module by one standard height, repeatedly execute an additional increase of the initial height of the placement module by one standard height until the area of the placement module belongs to the set capacity range.

[0015] Further, in some embodiments, arranging the placement modules in the core area in sequence according to the placement verification rules of the placement modules includes: when arranging the selected first placement module in the core area, the placement coordinate point of the first corner of the selected rectangular first placement module is set to coincide with the integer coordinate point with the shortest distance in the core area, and the coordinate points of the remaining corners of the first placement module are rearranged according to the adjusted coordinate point of the first corner of the first placement module, so that the selected rectangular first placement module is arranged in the core area; when arranging the selected second placement module in the core area where the first placement module is placed, the placement coordinate point of the first corner of the selected rectangular second placement module is set to coincide with the integer coordinate point with the shortest distance in the core area, and the coordinate points of the remaining corners of the second placement module are rearranged according to the adjusted coordinate point of the first corner of the second placement module; checking whether the coordinate points of each of the four corners of the rectangular second placement module fall within the first placement module, and at the same time checking whether the coordinate points of each of the four corners of the rectangular first placement module fall within the second placement module; when the coordinate points of each of the four corners of the second placement module do not fall within the first placement module, and at the same time the coordinate points of each of the four corners of the first placement module do not fall within the second placement module, the selected rectangular second placement module is arranged in the core area where the first placement module is placed.

[0016] Further, in some embodiments, arranging the placement modules in the core area in sequence according to the placement verification rules of the placement modules further includes: when any one of the coordinate points of the four corners of the second placement module falls within the first placement module, or any one of the coordinate points of the four corners of the first placement module falls within the second placement module; adjusting the coordinate points of the four corners of the rectangular second placement module so that the coordinate points of each of the four corners of the second placement module do not fall within the first placement module, and at the same time the coordinate points of each of the four corners of the first placement module do not fall within the second placement module.

[0017] Further, in some embodiments, adjusting the coordinate points of the four corners of the rectangular second placement module includes: simultaneously increasing one or more standard widths of the coordinate points of the four corners of the second placement module, or simultaneously decreasing one or more standard widths of the coordinate points of the four corners of the second placement module, or simultaneously increasing one or more standard heights of the coordinate points of the four corners of the second placement module, or simultaneously decreasing one or more standard heights of the coordinate points of the four corners of the second placement module.

[0018] Further, in some embodiments, based on the placement verification rules of the above placement module, sequentially arranging the above placement module in the above core area further includes: when arranging the selected third placement module in the above core area where the above first placement module and the above second placement module are placed, the placement coordinate point of the first corner of the selected rectangular third placement module is set to coincide with the integer coordinate point at the closest distance within the above core area, and the coordinate points of the remaining corners of the above third placement module are rearranged according to the adjusted coordinate point of the first corner of the above third placement module; checking whether the coordinate points of each of the four corners of the rectangular above third placement module fall within the above first placement module and the above second placement module, and at the same time checking whether the coordinate points of each of the four corners of the rectangular above first placement module and the above second placement module fall within the above third placement module; when the coordinate points of each of the four corners of the above third placement module do not fall within the above first placement module and the above second placement module, and at the same time the coordinate points of each of the four corners of the above first placement module and the above second placement module do not fall within the above third placement module, the selected rectangular third placement module is arranged in the above core area where the above first placement module and the above second placement module are placed.

[0019] Further, in some embodiments, based on the placement verification rules of the above placement module, sequentially arranging the above placement module in the above core area further includes: when arranging the selected Nth placement module in the above core area where the above first placement module to the (N - 1)th placement module are placed, the placement coordinate point of the first corner of the selected rectangular Nth placement module is set to coincide with the integer coordinate point at the closest distance within the above core area, and the coordinate points of the remaining corners of the above Nth placement module are rearranged according to the adjusted coordinate point of the first corner of the above Nth placement module; checking whether the coordinate points of each of the four corners of the rectangular above Nth placement module fall within the above first placement module to the (N - 1)th placement module, and at the same time checking whether the coordinate points of each of the four corners of the rectangular above first placement module to the (N - 1)th placement module fall within the above Nth placement module; when the coordinate points of each of the four corners of the above Nth placement module do not fall within the above first placement module to the (N - 1)th placement module, and at the same time the coordinate points of each of the four corners of the above first placement module to the (N - 1)th placement module do not fall within the above Nth placement module, the selected rectangular Nth placement module is arranged in the above core area where the above first placement module to the (N - 1)th placement module are placed; where N is a positive integer greater than 3.

[0020] In a second aspect of the present disclosure, there is also provided a layout constraint generation device for chip standard cells, the device comprising: a core area initialization unit for determining the initial width and initial height information of the core area according to the area information of all the provided standard cells, the desired aspect ratio of the core area, the width of the Site, the height of the Site, and the desired utilization rate; a placement module initialization unit for classifying the provided placement modules and determining the initial width and initial height information of each of the placement modules; a placement module initial adjustment unit for adjusting the initial width and initial height information of the placement modules according to the area verification rules of the placement modules to obtain the placement initial width and placement initial height information of the placement modules; a placement module layout unit for sequentially arranging the placement modules in the core area according to the placement verification rules of the placement modules; and a constraint condition acquisition unit for obtaining the core area information and the placement module layout information at the current moment after the placement modules are completed in the core area.

[0021] In a third aspect of the present disclosure, there is further provided an electronic device, the electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the layout constraint generation method for chip standard cells as described above are implemented.

[0022] In a fourth aspect of the present disclosure, there is further provided a computer-readable storage medium, on which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the layout constraint generation method for chip standard cells as described above are implemented.

[0023] The present disclosure has the following beneficial effects compared with the prior art:

[0024] By setting the basic information of the standard cells, the initial width and initial height information of the core area are determined; and the initial width and initial height information of each placement module are determined; and according to the area verification rule of the placement module, the initial width and initial height information of the placement module are adjusted to obtain the placement initial width and placement initial height information of the placement module; according to the placement verification rule of the placement module, the placement modules are arranged in the core area in sequence; then the core area information and the placement module arrangement information at the current moment are obtained as the layout constraint content of the chip standard cells, realizing the acquisition of layout constraint data, and reducing the development time of the FPGA chip; further, in some embodiments, by the area verification rule and the placement verification rule of the placement module, the initial width and initial height information of the placement module are adjusted and the placement modules are effectively arranged in the core area, improving the layout accuracy. And the above-mentioned layout constraint generation method of the chip standard cells is conducive to being implemented through a graphical user interface, facilitating operations such as adjusting the aspect ratio and placing the positions of different module constraints. Compared with EDA tools, the user debugging efficiency is greatly improved. Brief Description of the Drawings

[0025] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent, wherein:

[0026] Figure 1 A flowchart showing a method for generating layout constraints of chip standard cells according to an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram showing a device for generating layout constraints of chip standard cells according to an embodiment of the present disclosure; and

[0028] In each of the drawings, the same or corresponding reference numerals denote the same or corresponding parts. Detailed Description of the Embodiments

[0029] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description below omits the description of well-known functions and structures.

[0030] In the description of the embodiments of the present disclosure, the term "including" and its like shall be understood as an open inclusion, that is, "including but not limited to". The term "based on" shall be understood as "at least partially based on". The term "an embodiment" or "the embodiment" shall be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0032] Generally, the main work of the back-end design of digital chips is to complete the design process of the chip from the gate-level netlist to the GDSⅡ physical layout. In this process, the layout of standard cells has a significant impact on key indicators such as the final performance, area, and power consumption of the chip. The product advantages brought by reasonable standard cell placement mainly include: shortening the critical path, reducing the delay of the critical path, and improving the chip performance; avoiding additional consumption of routing resources, reducing the routing difficulty while reducing the routing resource expenditure, and helping to reduce the chip area; reducing other chip sign-off checks violations such as timing violations and design rule check violations, reducing the number of iterations, and accelerating the chip tape-out.

[0033] Furthermore, for the conventional chip backend design process, the placement of standard cells is mainly carried out by using the chip backend design EDA tool software (EDA, Electronic design automation, that is, the electronic design automation software used for very large scale integrated circuits; the EDA software mentioned in this disclosure all refers to the electronic design automation software corresponding to the chip backend design part). After the user provides the gate-level netlist as an input file to the EDA software, by using the EDA software in conjunction with its embedded algorithms, a large number of standard cells in the gate-level netlist can be directly placed within the core area (Core area, that is, the main functional area of the chip, and the standard cells are placed within this area), while meeting the requirements of timing, routing resources, design rule checking, etc. to a certain extent. This process is called placement. However, there are also defects in the use of the conventional placement process. Although the EDA software will automatically determine the positions of the standard cells according to the input information such as the pin connection relationships of each standard cell in the gate-level netlist and the timing constraint files, limited by its internal algorithms, it does not always achieve satisfactory placement results. Currently, the mainstream backend design EDA software is mainly designed for the backend design process of application specific integrated circuit (ASIC) chips, which results in less than ideal placement results when it comes to placing some special designs, such as field programmable gate array (FPGA). The specific problems include: poor timing performance of the critical path; excessive consumption of routing resources; unexpected functional adjustments to the netlist, such as unexpected adjustments to the types and quantities of standard cells in the netlist, resulting in the inability to achieve the design's expected functions. This is also a problem that users have to face when they hope to carry out the chip backend process of special designs. Furthermore, it is very necessary to use a placement constraint script to constrain the placement process to obtain a placement result that better meets the user's requirements. However, how to quickly obtain an available placement constraint script often requires spending a large amount of human and time costs to write, and it cannot be quickly debugged and iterated.

[0034] To solve the above problems, the conventional solution is to provide more refined constraints for the EDA tool, including more detailed timing constraint files; and manually written layout constraint scripts for the EDA software to deeply constrain the behavior of the EDA software during the layout process. The constraint content includes, for example: restricting the height and width of the area where the standard cells belonging to a specified module can be placed; restricting the position of the area where the standard cells belonging to a specified module can be placed; for some key modules, directly specifying the position of each standard cell belonging to it, etc. Obviously, as the refinement degree of the constraint script increases, the probability of obtaining the expected layout effect by using this constraint script is higher, but the time and labor costs required for its writing will also continue to increase. In the current chip backend design, on the one hand, the number of standard cells often reaches hundreds of thousands, tens of millions, or even hundreds of millions; on the other hand, the utilization rate of a single chip needs to be maintained at a relatively high level to reduce the area cost. Precise constraint of so many standard cells in a small area means that the layout constraint file may be very long, which means that the workload of writing such a script will be very large and the time cost of script writing is relatively high. Moreover, since the standard cells cannot be placed randomly within the core area but need to be placed on Sites, if the data such as coordinates, height, and width in the constraint script are not integer multiples of the height and width of the Site, it may lead to accuracy problems in the layout constraint script. In addition, after such a script is initially completed, it often needs to be debugged multiple times to compare the performance under different placement conditions to determine the final constraint scheme. On the EDA tool, operations such as quickly and batch moving the standard cells of a specified module are not convenient, which further increases the time cost and lengthens the design time.

[0035] To solve at least one of the above problems and one or more of other potential problems, in some embodiments of the present disclosure, an attempt is made to capture and calculate information such as the size and aspect ratio of different modules and the size and aspect ratio of the core area in advance before the layout process of the formal digital backend process, and perform free placement and aspect ratio debugging of different module instantiations in a separate graphical interface. Finally, according to the layout result of the graphical interface, a layout constraint script that can be directly used in the EDA tool software is directly generated, greatly reducing the time cost and labor cost of writing the layout constraint script and accelerating the progress of the digital backend process.

[0036] It should be understood that in some embodiments of the present disclosure, a standard cell (e.g., also referred to as Standard-Cell, the basic placement unit in the back-end process of a chip) refers to the basic placement unit in the back-end process of a chip; the core area (e.g., also referred to as the Core area, the main functional area of the chip for placing standard cells) refers to the main functional area of the chip for placing standard cells; a Site refers to the basic dimension unit in the back-end of the chip; the width of a Site refers to the basic length unit of the chip width and coordinates, which is process-related; the height of a Site refers to the basic length unit of the chip height and coordinates, which is also process-related; a module (e.g., a placement module, including a module to be placed and a placed module) refers to a set of standard cells with specific functions. It should be understood that in some embodiments of the present disclosure, obtaining the initial placement width and initial placement height information of a placement module refers to reasonable initial placement width and initial placement height information. In some embodiments, the loose constraint in a loose constraint module means that in subsequent placement, the user only hopes to specify the position of the module without requiring the placement of the standard cells inside the module. In some embodiments, the strict constraint in a strict constraint module means that in subsequent placement, the user not only hopes to specify the position of the module but also has requirements for the placement of the standard cells inside the module. Further, in some embodiments, 1 standard height refers to the height of 1 Site; 1 standard width refers to the width of 1 Site.

[0037] It should also be understood that in some embodiments of the present disclosure, the method for generating layout constraints of chip standard cells can produce a script for use as an input file for EDA software as its layout constraint file to obtain the desired layout result. Further, in some embodiments, the method for generating layout constraints of chip standard cells includes: an input file generation sub-method for reading the designed EDA software and producing the input file of the tool; a layout debugging method for manually debugging the layout of the target design, including adjusting the position and aspect ratio of different modules (e.g., in a graphical interface manner operable by the user); an output file generation method for converting the coordinate file generated by the tool into a layout constraint script file usable by the EDA tool after finally confirming the layout scheme.

[0038] In contrast, in the traditional way of generating layout constraint files, it is mostly written directly by users on-site. For example, directly manually write commands in the layout constraint script: constrain module A in the target area {(X1, Y1) (X2,Y2)} in a specific constraint manner M; or confirm in advance that the placement requirements of some modules conform to certain rules. In this case, scripts can be used to generate them in batches. For example, use a script to generate N similar commands in batches: constrain module An in the target area {(X1n, Y1n) (X2n, Y2n)} in a specific constraint manner Mn. However, both of these methods have problems: for the former, when the number of modules to be constrained is large, using this method of writing one by one will result in a high time cost; for the latter, even though it solves the problem of the speed of writing scripts to a certain extent, for the specific placement of each module constraint, considering that the parameters and placement requirements of different modules are often inconsistent and there may not always be obvious rules to follow, it is very difficult to simply use scripts for batch processing. For example, when different modules need to be placed, users need to manually define information such as the aspect ratio and position of each module. When the types of modules are numerous, just this part of the work will be very cumbersome. In addition, both of these methods lack an intuitive debugging method: users need to run on the back-end EDA after writing the commands to view the results, and then adjust the aspect ratio and change the position of the constraints in the script according to the results on the graphical interface of the EDA. This process is not intuitive, inconvenient, and time-consuming, which also greatly increases the debugging cost of generating layout constraint files.

[0039] It should also be understood that in some embodiments of the present disclosure, considering that standard cells must be placed on the Row composed of Sites in the core area (Core area), for standard cells, their optional position coordinates are not continuous but discrete. Here, the Site height and width are called the standard height (basic height) and standard width (basic width), which come from the PDK (Process Design Kit) of the currently used process node. Only when the coordinate values provided to the standard cells are integer multiples of the basic height (standard height) and basic width (standard width), can the tool accurately place and fix them. Otherwise, they will be forcibly adjusted by the EDA tool due to illegal coordinate problems. Similarly, the width and height of the core area (Core area) should also be integer multiples of the basic height and basic width to avoid waste of the core area (Core area) area, and the width and height of the module corresponding constraint area should also be integer multiples of the basic height and basic width to improve the accuracy of the constraint.

[0040] The following further explains with reference to the accompanying drawings.

[0041] Figure 1A flowchart of a method for generating layout constraints of chip standard cells according to an embodiment of the present disclosure is shown. In this illustrated exemplary embodiment, a method 100 for generating layout constraints of chip standard cells is shown. The method 100 for generating layout constraints of chip standard cells includes: Step 120, determining initial width and initial height information of a core region according to area information of all provided standard cells, a desired utilization rate, a desired aspect ratio of the core region, a width of a Site, and a height of a Site; Step 140, classifying the provided placement modules and determining initial width and initial height information of each of the above placement modules; Step 160, according to the area verification rule of the above placement module, for example, first determining whether its initial dimension information is reasonable. If not, adjusting the initial width and initial height information of the above placement module; Step 180, sequentially arranging the above placement modules in the above core region according to the placement verification rule of the above placement module; Step 190, after the above placement modules are completed being arranged in the above core region, obtaining the core region information and the placement module arrangement information at the current moment and converting them into a layout constraint script. It should be understood that in actual use, it is often difficult to encounter the situation of "being in place at once", but rather repeated debugging and placement are required. Therefore, after the modules have been placed, it is still possible to continue to cancel the placement, move, cancel the placement and adjust the aspect ratio (i.e., the width-to-height ratio), re-place, etc. of the already placed modules; for this reason, after Step 180, Step 182 may further be included, re-adjusting the aspect ratio of the placement modules arranged in the above core region, or re-adjusting the position placed in a new core region, or canceling the placement modules already arranged in the above core region and re-executing the verification of Step 160 and Step 180; furthermore, Step 192 may further be included, after obtaining the core region information and the placement module arrangement information at the current moment, storing the core region information and the placement module arrangement information to facilitate setting a baseline for work and facilitating forward tracing. Even further, Step 194 may further be included, after obtaining the core region information and the placement module arrangement information at the current moment, converting the corresponding information into a layout constraint script to allow a user to reproduce a desired placement layout on a digital backend EDA using the script.

[0042] Further, in some embodiments, for step 120, the method of determining the initial width and initial height information of the core region according to the area information of all the provided standard cells, the desired utilization rate, the desired aspect ratio of the core region, the width of the Site, and the height of the Site includes: determining the initial area of the core region according to the area information of all the provided standard cells and the desired utilization rate; and determining the initial width and initial height information of the core region according to the desired aspect ratio of the core region, the width of the Site, the height of the Site, and the initial area of the core region.

[0043] Further, in some embodiments, the method of determining the initial area of the core region according to the area information of all the provided standard cells and the desired utilization rate includes: obtaining the area of each standard cell in all the provided standard cells, summing up the areas of all the obtained standard cells to obtain the total area of all the standard cells; and determining the initial area of the core region according to the desired utilization rate of the core region and the total area of all the standard cells.

[0044] Further, in some embodiments, the method of determining the initial width and initial height information of the core region according to the desired aspect ratio of the core region, the width of the Site, the height of the Site, and the initial area of the core region includes: determining the desired width information and desired height information of the core region according to the initial area of the core region and the desired aspect ratio of the core region; determining the multiple of the desired width to the width of the Site by rounding up as the initial width of the core region; and determining the multiple of the desired height to the height of the Site by rounding up as the initial height of the core region.

[0045] It should be understood that from the user's perspective, the user adjusts the parameters of the data generated by the input file according to their own needs, including: 1) the aspect ratio of the desired core region (Core region); 2) the utilization rate of the desired core region (Core region); 3) the name of the module for which strict constraint layout is desired; 4) the name of the module for which loose constraint layout is desired and the desired utilization rate inside it. After the user provides this information, the tool is ready and can be used by the EDA software that has finished reading the input file and can perform layout operations to obtain a file containing all the input information required for subsequent steps.

[0046] Further, in some embodiments, the provided placement modules are classified, and the initial width and initial height information of each of the above placement modules are determined, including: classifying the same placement modules among all the provided placement modules into the same class; when the placement modules belonging to the same class are set as loose constraint modules, determining the sum of the areas of all the standard cells within the placement modules that belong to the loose constraint modules and the same class; determining the expected width information and expected height information of each of the placement modules that belong to the loose constraint modules and the same class according to the sum of the areas of all the standard cells within the placement modules that belong to the loose constraint modules and the same class, the internal utilization rate, and the internal aspect ratio; determining, in a ceiling manner, the multiple of the expected width of each of the placement modules that belong to the loose constraint modules and the same class to the width of the Site as the initial width of each of the placement modules that belong to the loose constraint modules and the same class; determining, in a ceiling manner, the multiple of the expected height of each of the placement modules that belong to the loose constraint modules and the same class to the height of the Site as the initial height of each of the placement modules that belong to the loose constraint modules and the same class. It should be understood that for the loose constraint modules, the loose constraint adopted only needs to determine the name of the loose constraint module and its expected utilization rate inside.

[0047] Further, in some embodiments, when classifying the provided placement modules and determining the initial width and initial height information of each of the above placement modules, it further includes: when the placement modules belonging to the same class are set as strictly constrained modules, determining the sum of the areas of all standard cells within the placement modules that belong to the strictly constrained modules and the same class; determining the expected width information and expected height information of each of the above placement modules belonging to the same class according to the sum of the areas of all standard cells within the placement modules that belong to the strictly constrained modules and the same class, the internal arrangement, the internal utilization rate, and the internal aspect ratio; determining, in a ceiling manner, the multiple of the expected width of each of the above placement modules that belong to the strictly constrained modules and the same class to the width of the Site as the initial width of each of the above placement modules that belong to the strictly constrained modules and the same class; determining, in a ceiling manner, the multiple of the expected height of each of the above placement modules that belong to the strictly constrained modules and the same class to the height of the Site as the initial height of each of the above placement modules that belong to the strictly constrained modules and the same class. It should be understood that for strictly constrained modules, a strictly constrained module file or data content needs to be provided additionally, which contains the module name information to be strictly constrained, the standard cell instance name (instance name) information to which it belongs, and the arrangement order information; further, the arrangement order information can be, for example, the sequential arrangement of various types of standard cells therein.

[0048] Thus, it can be understood that an EDA software for reading the target netlist can be used to run the input file generation method to generate an input file containing the following information for the subsequent stage, such as: 1) the height and width of the core area (Core area); 2) the names of the modules to be constrained (including strictly constrained modules and loosely constrained modules) and their heights and widths; 3) among them, for the strictly constrained module, the class names (reference names) and instance names (instance names) of all the standard cells inside it; 4) the names of all the instantiations of all the modules to be constrained and their heights and widths. Regarding the height and width of the core area (Core area), data (such as scripts) can be generated through the input file, and then the sum of the areas of all the standard cells corresponding to the target design in the Gate Level Netlists obtained from the EDA tool will be obtained first; then, dividing this area sum by the desired utilization rate preset by the user can obtain the total area of the desired core area (Core area); then, according to the desired aspect ratio of the core area (Core area) preset by the user, the height and width of the aspect ratio can be obtained; then, this height and width will be converted into integer multiples (rounded up) of the standard height (basic height) and standard width (basic width); and then, subsequently, this core area (Core area) will be used as the area for layout placement.

[0049] It should also be understood that regarding the name and height-width information of the modules to be constrained, the input file generation step will capture more information about the corresponding module and all its instantiations according to the target module name provided by the user, depending on different constraint methods defined by the user. For the two constraint methods: strict constraint or loose constraint (relaxed constraint); strict constraint means that the final output constraint file will contain the positions of each standard cell under the module, maximizing the accuracy of the constraint; while loose constraint will only provide a region within a specified rectangular coordinate range for all the standard cells under the corresponding module in the constraint file to guide the layout, and the layout of the standard cells within the region will be performed by the EDA tool. Further, for the modules that need to be strictly constrained, capture the type names of the standard cells under them and the quantity, height and width of each standard cell (in units of basic height and basic width); if it is a module that only needs loose constraint, obtain the sum of the areas of all the standard cells under it calculated in the EDA tool, and then divide this area sum by the desired module utilization rate of the user; the area size of the corresponding area of the module can be obtained, and then according to the initial aspect ratio set by the user, determine its height and width. Similarly, this height and width also need to be converted into integer multiples (rounded up) of the basic height and basic width. All this information will be output to the next level as the input data for subsequent layout.

[0050] Further, in some embodiments, according to the area verification rule of the above placement module, the initial width and height of the placement module provided by the upper level are verified. If the verification fails, the initial width and initial height information of the above placement module are adjusted to obtain the adjusted and legal placement initial width and placement initial height information of the above placement module. It should be understood that the reason for the above operation steps is as follows: for a strictly constrained module, we calculate the expected length and width of the module based on the sum of the areas of the internal standard cells. We can ensure that the area of the module is definitely greater than the sum of the areas of the internal standard cells by means of rounding up during calculation. However, considering the size of the standard cells, this cannot guarantee that the internal standard cells can definitely be placed within the corresponding module area (for example, a module corresponding area is a square, and there is an extremely long and narrow cuboid standard cell with a total area of half of it inside. Whether this standard cell can be placed within the module depends on whether the length of the standard cell is less than the side length of the module). Therefore, it is also necessary to try to place them. According to the internal placement order of the strictly constrained module provided by the user, try to place them to confirm whether the current height and width are reasonable. The steps include: S1, checking whether the standard cells within the placement module that belong to the strictly constrained module and belong to the same category can be arranged within the above placement module according to the above internal arrangement method; S2, when the standard cells within the placement module that belong to the strictly constrained module and belong to the same category cannot be arranged within the above placement module according to the above internal arrangement method, while keeping the total area within the set capacity range, reduce the initial height of the above placement module by 1 standard height and increase the initial width of the above placement module by 1 or more standard widths, or reduce the initial width of the above placement module by 1 standard width and increase the initial height of the above placement module by 1 or more standard heights, and rearrange the standard cells within the above placement module within the above placement module according to the above internal arrangement method, where one standard height is the height of 1 Site and one standard width is the width of 1 Site; re-execute step S1; S3, when the standard cells within the placement module that belong to the strictly constrained module and belong to the same category can be arranged within the above placement module according to the above internal arrangement method, obtain the placement initial width and placement initial height information of the above placement module according to the adjusted width and adjusted height of the above placement module at this time.

[0051] Further, in some embodiments, in the above step S2, when the standard cells within the placement module that belong to the strict constraint module and the same name class category cannot be arranged within the placement module according to the above internal arrangement method, while keeping the total area within the set capacity range, reduce the initial height of the placement module by 1 standard height and increase the initial width of the placement module by 1 standard width, or reduce the initial width of the placement module by 1 standard width and increase the initial height of the placement module by 1 standard height, including: when the area of the placement module is greater than the set capacity range after reducing the initial height of the placement module by 1 standard height and increasing the initial width of the placement module by 1 standard width, repeatedly execute an additional reduction of the initial height of the placement module by 1 standard height until the area of the placement module belongs to the set capacity range; when the area of the placement module is less than the set capacity range after reducing the initial height of the placement module by 1 standard height and increasing the initial width of the placement module by 1 standard width, repeatedly execute an additional increase of the initial width of the placement module by 1 standard width until the area of the placement module belongs to the set capacity range; when the area of the placement module is greater than the set capacity range after reducing the initial width of the placement module by 1 standard width and increasing the initial height of the placement module by 1 standard height, repeatedly execute an additional reduction of the initial width of the placement module by 1 standard width until the area of the placement module belongs to the set capacity range; when the area of the placement module is less than the set capacity range after reducing the initial width of the placement module by 1 standard width and increasing the initial height of the placement module by 1 standard height, repeatedly execute an additional increase of the initial height of the placement module by 1 standard height until the area of the placement module belongs to the set capacity range. It should be understood that the above additional adjustment of 1 standard height or 1 standard width is carried out step by step, that is, finally, it may happen that exactly N standard heights or N standard widths are adjusted to exactly make the area of the placement module belong to the set capacity range; this increases the stability of the adjustment.

[0052] Further, in some embodiments, arranging the above placement modules in the above core area in sequence according to the above placement verification rules of the placement modules includes: when arranging the selected first placement module in the above core area, the placement coordinate point of the first corner (generally, in some embodiments, default to the upper left corner) of the selected rectangular first placement module is set to coincide with the integer coordinate point with the shortest distance in the above core area, and the coordinate points of the remaining corners of the above first placement module are rearranged according to the adjusted coordinate point of the first corner of the above first placement module. Since the module is rectangular and both the length and width are integer multiples of the standard height and standard width, when the coordinate point of one corner is an integer, the coordinate points of the remaining corners must also be integers. Thus, the selected rectangular first placement module is arranged in the above core area; when arranging the selected second placement module in the above core area where the first placement module has been placed, the placement coordinate point of the first corner of the selected rectangular second placement module is set to coincide with the integer coordinate point with the shortest distance in the above core area, and the coordinate points of the remaining corners of the above second placement module are rearranged according to the adjusted coordinate point of the first corner of the above second placement module; then, it is judged whether there is an overlapping relationship between the second placement module to be placed and the first placement module that has been placed. For this purpose, it is checked whether the coordinate points of each of the four corners of the above rectangular second placement module fall within the above first placement module, and at the same time, it is checked whether the coordinate points of each of the four corners of the above rectangular first placement module fall within the above second placement module; when the coordinate points of each of the four corners of the above second placement module do not fall within the above first placement module, and at the same time, the coordinate points of each of the four corners of the above first placement module do not fall within the above second placement module, the selected rectangular second placement module is arranged in the above core area where the above first placement module has been placed.

[0053] Further, in some embodiments, arranging the above placement modules in the above core area in sequence according to the above placement verification rules of the placement modules further includes: when the coordinate point of any one of the four corners of the above second placement module falls within the above first placement module, or the coordinate point of any one of the four corners of the above first placement module falls within the above second placement module; adjusting the coordinate points of the four corners of the above rectangular second placement module so that the coordinate points of each of the four corners of the above second placement module do not fall within the above first placement module, and at the same time, the coordinate points of each of the four corners of the above first placement module do not fall within the above second placement module.

[0054] Further, in some embodiments, the four corner coordinate points of the second placement module for adjusting the rectangular shape include: simultaneously increasing the abscissas of the four corner coordinate points of the second placement module by one or more standard widths (for example, setting the standard width as the abscissa), or simultaneously decreasing the abscissas of the four corner coordinate points of the second placement module by one or more standard widths, or simultaneously increasing the ordinates of the four corner coordinate points of the second placement module by one or more standard heights (for example, setting the standard height as the ordinate), or simultaneously decreasing the ordinates of the four corner coordinate points of the second placement module by one or more standard heights.

[0055] Further, in some embodiments, arranging the placement module in the core area in sequence according to the placement verification rule of the placement module further includes: when the selected third placement module is arranged in the core area where the first placement module and the second placement module are placed, the placement coordinate point of the first corner of the selected rectangular third placement module is set to coincide with the integer coordinate point at the closest distance in the core area, and the coordinate points of the remaining corners of the third placement module are rearranged according to the adjusted coordinate point of the first corner of the third placement module; checking whether the coordinate points of each of the four corners of the rectangular third placement module fall within the first placement module and the second placement module, and simultaneously checking whether the coordinate points of each of the four corners of the rectangular first placement module and the second placement module fall within the third placement module; when the coordinate points of each of the four corners of the third placement module do not fall within the first placement module and the second placement module, and at the same time the coordinate points of each of the four corners of the first placement module and the second placement module do not fall within the third placement module, the selected rectangular third placement module is arranged in the core area where the first placement module and the second placement module are placed.

[0056] Further, in some embodiments, arranging the placement modules in the core area in sequence according to the placement verification rules of the placement modules further includes: when arranging the selected Nth placement module in the core area where the first placement module to the (N-1)th placement module are placed, the placement coordinate point of the first corner of the selected rectangular Nth placement module is set to coincide with the integer coordinate point with the shortest distance in the core area, and the coordinate points of the remaining corners of the Nth placement module are rearranged according to the adjusted coordinate point of the first corner of the Nth placement module; checking whether the coordinate points of each of the four corners of the rectangular Nth placement module fall within the first placement module to the (N-1)th placement module, and at the same time checking whether the coordinate points of each of the four corners of the first placement module to the (N-1)th placement module fall within the Nth placement module; when the coordinate points of each of the four corners of the Nth placement module do not fall within the first placement module to the (N-1)th placement module, and at the same time the coordinate points of each of the four corners of the first placement module to the (N-1)th placement module do not fall within the Nth placement module, the selected rectangular Nth placement module is arranged in the core area where the first placement module to the (N-1)th placement module are placed; where N is a positive integer greater than 3.

[0057] It should also be understood that as a placement module (generally, a rectangular area), it will first be adsorbed onto the nearest grid (i.e., coordinate integerization). For example, the currently selected module to be placed will be preferentially placed at the upper left corner of this rectangular area; if there is a module that has already been placed at the upper left corner, then overlap detection based on the placement verification rules will be performed; if there is an overlap situation, then an attempt will be made to find another place where it can be placed; for example, first, an attempt will be made to see if the module can be placed on the right side of the module to be placed (rectangle), that is, the height coordinate (for example, set as the Y-axis coordinate) of the four vertices remains unchanged, but the width coordinate (for example, set as the X-axis coordinate) is uniformly increased by 1 standard width at the same time, and then overlap detection is performed, and the loop continues until a place where it can be placed is found; if the right side is not possible, then the bottom will be tried, that is, first the coordinates of the module to be placed are restored to the upper left corner, and then it is continuously probed down (which can be manifested as the width coordinate remaining unchanged while the height coordinate is uniformly reduced by 1 standard height) until a place where it can be placed is found. That is, it can be understood that the entire placement module tries to translate in the overall up, down, left, and right directions in the core area in order to find an overlap detection that passes the placement verification rules. If a position is found, then the module is finally placed at that position.

[0058] It should be understood that from the user's perspective, before placement, the user adjusts the aspect ratio of the instantiation of different modules (the area shapes are all rectangles); specifically, according to different module constraint methods (strict, loose), their adjustment algorithms are also different. Among them, for the instantiation of modules that require strict constraints, the number, height, and width of each type of standard cell under it are already in the input file. Therefore, when adjusting its aspect ratio, it will calculate in real time according to the number, height, and width of the standard cells inside it to ensure that all the standard cells belonging to it can definitely be placed in the rectangular area. At this time, the user can also perform detailed editing on the instantiation of this module: the user can independently adjust the spatial order of the arrangement of the standard cells inside the current rectangular area. For the instantiation of modules with loose constraints, when adjusting the aspect ratio, since the default height and width in the input file will be used first to calculate its basic area, and then, based on the default height and default width in the input file, on the premise that the total area is greater than or equal to the basic area, the aspect ratio is adjusted with the goal of making the total area as close as possible to the basic area. In terms of position, since in the digital backend process, all standard cells need to be placed on rows (layout tracks), and at the same time, its minimum interval needs to be a specific integer multiple of the site (the minimum standard cell width unit in the PDK), therefore, the placement positions of all modules also need to be integer multiples of the height and width of the Site. In particular, when the user performs placement, the position adsorption method will be used to ensure that the final position is in a compliant position, that is, the horizontal and vertical coordinate values are both integers (that is, the actual coordinates are integer multiples of the corresponding basic height or basic width).

[0059] Furthermore, for strictly constrained modules, since the standard cell information inside them has been input, therefore, the arrangement method inside the module can also be adjusted. For example, it can be adjusted individually. Furthermore, when the user has basically determined the aspect ratio of the module and the internal arrangement order of the strictly constrained module, the user can start placement. Furthermore, during placement, generally, a placement coordinate data is generated in real time; the main content of this data is basically the same as the layout input data, but for the instantiation part, coordinate information is added (the interval unit can be converted from the standard height and standard width to a normal unit, such as μm). In particular, to exclude the interference of unplaced modules, for each instantiation, when it is not placed, its coordinates will be negative, and after placement, they will be the real coordinates after placement.

[0060] Further, the generated constraint algorithm includes: after completing the above layout (for example, in the form of a schematic diagram), that is, after the placement modules are arranged in the core area, obtaining the core area information and the placement module arrangement information at the current moment, and outputting the data information as layout constraint data available for EDA tools. For example, during the layout, a set of placement coordinate data is generated in real time to record the current placement situation; for example, it includes the following information: 1) the height and width of the core area (Core area); 2) for modules with strict constraints, the position information of each standard cell inside; 3) for modules with loose constraints, the position information and size information of their corresponding tentative placement areas; thus, converting the output data into a layout constraint method that can be used by an EDA tool, which may include: setting the height and width of the Core area of the current design, setting the position of each standard cell of the strictly constrained module, and setting the position and size of each area corresponding to each module of the loosely constrained module; the specific commands are related to the EDA tool itself. Further, if it is implemented in the form of a script program, for example, after the constraint script is generated, the generated constraint script can be run in the loaded EDA tool to obtain the expected layout result; furthermore, by checking the layout result in a timely manner, adjustments can be made in a timely manner when unexpected situations are found in the layout result.

[0061] Figure 2 The schematic diagram of a layout constraint generation device for chip standard cells according to an embodiment of the present disclosure is shown. In the illustrated embodiment, a layout constraint generation device for chip standard cells is also provided, and the device includes: a core area initialization unit for determining the initial width and initial height information of the core area according to the area information of all provided standard cells, the desired aspect ratio of the core area, the width of the Site, the height of the Site, and the desired utilization rate; a placement module initialization unit for classifying the provided placement modules and determining the initial width and initial height information of each of the above placement modules; a placement module initial adjustment unit for adjusting the initial width and initial height information of the above placement modules according to the area verification rule of the above placement modules to obtain the placement initial width and placement initial height information of the above placement modules; a placement module arrangement unit for sequentially arranging the above placement modules in the above core area according to the placement verification rule of the above placement modules; a constraint condition acquisition unit for obtaining the above core area information and the above placement module arrangement information at the current moment after the above placement modules are arranged in the above core area. Thereafter, the arrangement information is converted into a layout constraint script to allow the user to use the script to reproduce the desired placement layout on the digital backend EDA.

[0062] In addition, according to an embodiment of the present disclosure, an electronic device is further provided. The electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of the layout constraint generation method for the chip standard cells as described above are implemented.

[0063] In addition, according to an embodiment of the present disclosure, a computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the layout constraint generation method for the chip standard cells as described above are implemented.

[0064] The embodiments of the present disclosure have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skill in the art to understand the disclosed embodiments.

[0065] The above are only optional embodiments of the present disclosure and are not used to limit the present disclosure. For those skilled in the art, the present disclosure may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A method for generating layout constraints of a chip standard cell, characterized in that, Including: Determine the initial width and initial height information of the core area based on the area information of all provided standard cells, the desired utilization rate, the desired aspect ratio of the core area, the width of the Site, and the height of the Site. Classify the provided placement modules, and determine the initial width and initial height information of each placement module, where the placement module is composed of standard cells and the provided placement modules are classified into loose constraint modules and strict constraint modules; the loose constraint module is set to include the name information of the loose constraint module and the desired utilization rate inside the loose constraint module; the strict constraint module is set to include the name information of the strict constraint module, the name information of the standard cell to which the strict constraint module belongs, and the arrangement order information of the standard cell to which it belongs. Adjust the initial width and initial height information of the placement module according to the area verification rule of the placement module to obtain the placement initial width and placement initial height information of the placement module. Arrange the placement modules in the core area in sequence according to the placement verification rule of the placement module. After the placement module completes the arrangement in the core area, obtain the core area information and the placement module arrangement information at the current moment.

2. The method according to claim 1, wherein The step of determining the initial width and initial height information of the core area according to the area information of all provided standard cells, the desired utilization rate, the desired aspect ratio of the core area, the width of the Site, and the height of the Site includes: Determine the initial area of the core area according to the area information of all provided standard cells and the desired utilization rate. Determine the initial width and initial height information of the core area according to the desired aspect ratio of the core area, the width of the Site, the height of the Site, and the initial area of the core area.

3. The method according to claim 2, wherein The step of determining the initial area of the core area according to the area information of all provided standard cells and the desired utilization rate includes: Obtain the area of each standard cell in all the standard cells, and sum the areas of all the obtained standard cells to obtain the total area of all the standard cells. Determine the initial area of the core area according to the desired utilization rate of the core area and the total area of all the standard cells.

4. The method according to claim 3, wherein The step of determining the initial width and initial height information of the core area according to the desired aspect ratio of the core area, the width of the Site, the height of the Site, and the initial area of the core area includes: Determine the desired width information and desired height information of the core area according to the initial area of the core area and the desired aspect ratio of the core area. Determine the multiple of the desired width to the width of the Site by rounding up as the initial width of the core area. Determine the multiple of the desired height to the height of the Site by rounding up as the initial height of the core area.

5. The method according to claim 1, wherein: classifying the provided placement modules, and determining the initial width and initial height information of each of the placement modules, including: classifying the same placement modules among all the provided placement modules into the same category; when the placement modules belonging to the same category are set as loose constraint modules, determining the sum of the areas of all the standard cells within the placement modules belonging to the loose constraint modules and of the same category; determining the expected width information and expected height information of each of the placement modules belonging to the loose constraint modules and of the same category according to the sum of the areas of all the standard cells within the placement modules belonging to the loose constraint modules and of the same category, the internal utilization rate, and the internal width-to-height ratio; determining, in a way of rounding up, the multiple of the expected width of each of the placement modules belonging to the loose constraint modules and of the same category to the width of the Site as the initial width of each of the placement modules belonging to the loose constraint modules and of the same category; determining, in a way of rounding up, the multiple of the expected height of each of the placement modules belonging to the loose constraint modules and of the same category to the height of the Site as the initial height of each of the placement modules belonging to the loose constraint modules and of the same category.

6. The method according to claim 5, wherein: classifying the provided placement modules, and determining the initial width and initial height information of each of the placement modules, further including: when the placement modules belonging to the same category are set as strict constraint modules, determining the sum of the areas of all the standard cells within the placement modules belonging to the strict constraint modules and of the same category; determining the expected width information and expected height information of each of the placement modules belonging to the same category according to the sum of the areas of all the standard cells within the placement modules belonging to the strict constraint modules and of the same category, the internal arrangement, the internal utilization rate, and the internal width-to-height ratio; determining, in a way of rounding up, the multiple of the expected width of each of the placement modules belonging to the strict constraint modules and of the same category to the width of the Site as the initial width of each of the placement modules belonging to the strict constraint modules and of the same category; determining, in a way of rounding up, the multiple of the expected height of each of the placement modules belonging to the strict constraint modules and of the same category to the height of the Site as the initial height of each of the placement modules belonging to the strict constraint modules and of the same category.

7. The method according to claim 6, wherein: adjusting the initial width and initial height information of the placement module according to the area verification rule of the placement module to obtain the placement initial width and placement initial height information of the placement module, including the following steps: S1, checking whether the standard cells within the placement modules belonging to the strict constraint modules and of the same category can be arranged within the placement module according to the internal arrangement; S2. When the standard cells within a placement module that belong to the strictly constrained module and the same class category cannot be arranged within the placement module according to the internal arrangement method, while keeping the total area within the set capacity range, reduce the initial height of the placement module by one standard height and increase the initial width of the placement module by one standard width, or reduce the initial width of the placement module by one standard width and increase the initial height of the placement module by one standard height, and rearrange the standard cells within the placement module within the placement module according to the internal arrangement method, where one standard height is the height of one Site and one standard width is the width of one Site; re-execute step S1; S3. When the standard cells within a placement module that belong to the strictly constrained module and the same class category are arranged within the placement module according to the internal arrangement method, obtain the placement initial width and placement initial height information of the placement module based on the adjusted width and adjusted height of the placement module at this time.

8. The method according to claim 7, wherein, In step S2, when the standard cells within a placement module that belong to the strictly constrained module and the same class category cannot be arranged within the placement module according to the internal arrangement method, while keeping the total area within the set capacity range, reducing the initial height of the placement module by one standard height and increasing the initial width of the placement module by one standard width, or reducing the initial width of the placement module by one standard width and increasing the initial height of the placement module by one standard height, includes: When, after reducing the initial height of the placement module by one standard height and increasing the initial width of the placement module by one standard width, the area of the placement module is greater than the set capacity range, repeatedly execute an additional reduction of the initial height of the placement module by one standard height until the area of the placement module belongs to the set capacity range; When, after reducing the initial height of the placement module by one standard height and increasing the initial width of the placement module by one standard width, the area of the placement module is less than the set capacity range, repeatedly execute an additional increase of the initial width of the placement module by one standard width until the area of the placement module belongs to the set capacity range; When, after reducing the initial width of the placement module by one standard width and increasing the initial height of the placement module by one standard height, the area of the placement module is greater than the set capacity range, repeatedly execute an additional reduction of the initial width of the placement module by one standard width until the area of the placement module belongs to the set capacity range; When, after reducing the initial width of the placement module by one standard width and increasing the initial height of the placement module by one standard height, the area of the placement module is less than the set capacity range, repeatedly execute an additional increase of the initial height of the placement module by one standard height until the area of the placement module belongs to the set capacity range.

9. The method according to claim 1, wherein, According to the placement verification rules of the placement module, arranging the placement module in the core area in sequence includes: When arranging the selected first placement module in the core area, the placement coordinate point of the first corner of the selected first placement module in the shape of a rectangle is set to coincide with the integer coordinate point at the closest distance in the core area, and the coordinate points of the remaining corners of the first placement module are rearranged according to the adjusted coordinate point of the first corner of the first placement module, so that the selected first placement module in the shape of a rectangle is arranged in the core area; When arranging the selected second placement module in the core area where the first placement module is placed, the placement coordinate point of the first corner of the selected second placement module in the shape of a rectangle is set to coincide with the integer coordinate point at the closest distance in the core area, and the coordinate points of the remaining corners of the second placement module are rearranged according to the adjusted coordinate point of the first corner of the second placement module; check whether the coordinate points of each of the four corners of the second placement module in the shape of a rectangle fall within the first placement module, and at the same time check whether the coordinate points of each of the four corners of the first placement module in the shape of a rectangle fall within the second placement module; When the coordinate points of each of the four corners of the second placement module do not fall within the first placement module, and at the same time the coordinate points of each of the four corners of the first placement module do not fall within the second placement module, the selected second placement module in the shape of a rectangle is arranged in the core area where the first placement module is placed.

10. The method according to claim 9, wherein According to the placement verification rules of the placement module, arranging the placement module in the core area in sequence further includes: When the coordinate point of any one of the four corners of the second placement module falls within the first placement module, or the coordinate point of any one of the four corners of the first placement module falls within the second placement module; adjust the coordinate points of the four corners of the second placement module in the shape of a rectangle, so that the coordinate points of each of the four corners of the second placement module do not fall within the first placement module, and at the same time the coordinate points of each of the four corners of the first placement module do not fall within the second placement module.

11. The method according to claim 10, wherein Adjusting the coordinate points of the four corners of the second placement module in the shape of a rectangle includes: Increasing the coordinate points of the four corners of the second placement module by one or more standard widths at the same time, or decreasing the coordinate points of the four corners of the second placement module by one or more standard widths at the same time, or increasing the coordinate points of the four corners of the second placement module by one or more standard heights at the same time, or decreasing the coordinate points of the four corners of the second placement module by one or more standard heights at the same time.

12. The method according to claim 9, wherein According to the placement verification rules of the placement module, arranging the placement module in the core area in sequence further includes: When the selected third placement module is arranged within the core area where the first placement module and the second placement module are placed, the placement coordinate point of the first corner of the selected rectangular third placement module is set to coincide with the integer coordinate point at the closest distance within the core area, and the coordinate points of the remaining corners of the third placement module are rearranged according to the adjusted coordinate point of the first corner of the third placement module; check whether the coordinate points of each of the four corners of the rectangular third placement module fall within the first placement module and the second placement module, and at the same time check whether the coordinate points of each of the four corners of the rectangular first placement module and the second placement module fall within the third placement module; When the coordinate points of each of the four corners of the third placement module do not fall within the first placement module and the second placement module, and at the same time the coordinate points of each of the four corners of the first placement module and the second placement module do not fall within the third placement module, the selected rectangular third placement module is arranged within the core area where the first placement module and the second placement module are placed.

13. The method according to claim 9, wherein, The step of sequentially arranging the placement modules within the core area according to the placement verification rules of the placement module further includes: When the selected Nth placement module is arranged within the core area where the first placement module to the (N - 1)th placement module are placed, the placement coordinate point of the first corner of the selected rectangular Nth placement module is set to coincide with the integer coordinate point at the closest distance within the core area, and the coordinate points of the remaining corners of the Nth placement module are rearranged according to the adjusted coordinate point of the first corner of the Nth placement module; check whether the coordinate points of each of the four corners of the rectangular Nth placement module fall within the first placement module to the (N - 1)th placement module, and at the same time check whether the coordinate points of each of the four corners of the rectangular first placement module to the (N - 1)th placement module fall within the Nth placement module; When the coordinate points of each of the four corners of the Nth placement module do not fall within the first placement module to the (N - 1)th placement module, and at the same time the coordinate points of each of the four corners of the first placement module to the (N - 1)th placement module do not fall within the Nth placement module, the selected rectangular Nth placement module is arranged within the core area where the first placement module to the (N - 1)th placement module are placed; where N is a positive integer greater than 3.

14. A layout constraint generation device for a chip standard cell, characterized in that, Including: A core area initialization unit for determining the initial width and initial height information of the core area according to the area information of all the provided standard cells, the desired aspect ratio of the core area, the width of the Site, the height of the Site, and the desired utilization rate; A placement module initialization unit is used to classify the provided placement modules and determine the initial width and initial height information of each placement module, where the placement module is composed of standard cells and the provided placement modules are classified into a loose constraint module and a strict constraint module; the loose constraint module is set to include the name information of the loose constraint module and the expected utilization rate inside the loose constraint module; the strict constraint module is set to include the name information of the strict constraint module, the name information of the standard cell to which the strict constraint module belongs, and the arrangement order information of the belonging standard cells; A placement module initial adjustment unit is used to adjust the initial width and initial height information of the placement module according to the area verification rule of the placement module to obtain the placement initial width and placement initial height information of the placement module; A placement module arrangement unit is used to sequentially arrange the placement modules in the core area according to the placement verification rule of the placement module; A constraint condition acquisition unit is used to acquire the core area information and the placement module arrangement information at the current moment after the placement module finishes being arranged in the core area.

15. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the layout constraint generation method for the chip standard cells as described in any one of claims 1-13.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the layout constraint generation method for the chip standard cells as described in any one of claims 1-13.

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