Operational amplifier with low offset voltage and electronic equipment

Abstract

According to the operational amplifier with the low offset voltage and the electronic equipment, on one hand, the offset voltage existing in the first operational amplifier unit and the offset voltage existing in the second operational amplifier unit are stored and accurately offset through the first offset voltage elimination unit and the second offset voltage elimination unit respectively; the first output current unit and the second output current unit generate first output current and second output current errors respectively due to the offset voltage. And on the other hand, the first operational amplifier module and the second operational amplifier module are controlled to be alternately in different working stages by controlling the on-off of the switch, so that the input end of the operational amplifier module in a normal working state in each clock period is ensured to have extremely low offset voltage, and the offset voltage elimination continuity is ensured.

Description

Technical Field

[0001] The invention relates to the field of high-precision operational amplifiers, and in particular to an operational amplifier and electronic equipment with low offset voltage. Background Art

[0002] During chip production, the operational amplifier may generate an offset voltage at the input of the operational amplifier due to internal transistor mismatch, process deviation, temperature drift, mechanical or thermal stress during packaging, etc. In some measurement and control systems with high precision requirements, it is usually necessary to measure and collect some weak analog signals, such as current, voltage, etc. However, due to the offset voltage of the operational amplifier itself, the sampling accuracy will be affected.

[0003] In order to eliminate the offset voltage of the operational amplifier, the technical means adopted in the prior art are usually a chopper operational amplifier and an auto-zero operational amplifier.

[0004] For chopper op amps, refer to Figure 1 , Figure 1 The circuit structure diagram of the chopper operational amplifier is shown in FIG. 1 , which is specifically composed of a first chopper unit, an operational amplifier, a second chopper unit, and a low-pass filter connected in sequence. The first chopper unit can convert the continuous input signal V in Converted into a high frequency square wave signal V with a fixed chopping frequency a At this time, the inherent offset voltage Vos at the input of the operational amplifier and the high-frequency square wave signal Va are added to the input, and then the output signal V is obtained after amplification by the operational amplifier. b . Output signal V b After passing through the second chopper unit, it is converted into a low-frequency output signal Vout. Since the offset voltage Vos only passes through the chopper unit once, its signal will be modulated to the chopping frequency by the second chopper unit, even if the input signal V in It is separated from the high-frequency offset voltage Vos. Finally, the offset voltage Vos modulated to the chopping frequency is filtered out by a low-pass filter.

[0005] The problem with this solution is that since the chopping process occurs instantaneously, the input signal V in There may be rapid changes before truncation or chopping. When these rapidly changing signals are truncated or chopped, the output signal will experience mutations or jumps, resulting in discontinuity in time, which may introduce time domain errors. At the same time, additional harmonic components may appear in the output signal. Therefore, the chopper amplifier cannot be used in scenarios where the frequency of the input signal is higher than the chopping frequency, which limits the scope of application of the chopper amplifier.

[0006] For auto-zero op amps, see Figure 2 , Figure 2 The circuit structure diagram of the auto-zero operational amplifier is shown in Figure 1. It consists of two operational amplifiers with auxiliary input ports, where A1 is set as the main amplifier and A2 is set as the zeroing amplifier; A1 and A2 have offset voltages of certain magnitudes, Vos1 and Vos2, respectively. The auto-zero operational amplifier is divided into two working modes, the zeroing stage and the amplification stage.

[0007] In the zeroing stage, the corresponding switches S2 and S4 are closed; S1 and S3 are opened. The input port of A2 is short-circuited, and its output is connected to capacitor CM1. At the same time, capacitor CM1 is connected to the auxiliary input terminal of A2 to form a negative feedback structure. Therefore, the input offset voltage of A2 is stored in capacitor CM1. Next, the amplification stage is entered, and the corresponding switches S2 and S4 are opened; S1 and S3 are closed. Since the capacitor voltage cannot change suddenly, the voltage stored in capacitor CM1 remains as the offset voltage of A2 itself and serves as the input signal of the auxiliary port of A2. The offset voltage stored in capacitor CM1 is combined with the input signal Vin and input to A2, where it is amplified and output to capacitor CM2. This signal is input to the auxiliary input terminal of A1 to offset the offset voltage Vos1 at the input terminal of A1.

[0008] The problem with this solution is that since the self-zeroing operational amplifier needs to store the offset voltage in the zeroing stage before it can cancel the offset voltage in the amplification stage, the self-zeroing operational amplifier does not eliminate the offset voltage continuously, which greatly limits its application scenarios.

[0009] Therefore, providing an operational amplifier that can eliminate offset voltage with high precision and continuously without limiting the usage scenarios has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0010] In order to solve the above problems, the present invention provides an operational amplifier and an electronic device with low offset voltage.

[0011] According to a first aspect of the present invention, there is provided an operational amplifier with low offset voltage, comprising: a first operational amplifier module, a second operational amplifier module, and a voltage output module;

[0012] The first operational amplifier module includes a first operational amplifier unit and a first offset voltage elimination unit; the first operational amplifier unit has a non-inverting input terminal connected to a first input signal, and the first operational amplifier unit has an inverting input terminal connected to the first input signal or a second input signal through a second switch; the first terminal of the first operational amplifier unit is coupled to the output terminal of the first offset voltage elimination unit; the output terminal of the first operational amplifier unit is coupled to the input terminal of the first offset voltage elimination unit through a third switch, and serves as the output terminal of the first operational amplifier module;

[0013] The second operational amplifier module includes a second operational amplifier unit and a second offset voltage elimination unit; the in-phase input terminal of the second operational amplifier unit is connected to the first input signal, and the inverting input terminal of the second operational amplifier unit is connected to the first input signal through a fifth switch or the second input signal through a fourth switch; the first terminal of the second operational amplifier unit is coupled to the output terminal of the second offset voltage elimination unit; the output terminal of the second operational amplifier unit is coupled to the input terminal of the second offset voltage elimination unit through a sixth switch, and serves as the output terminal of the second operational amplifier module;

[0014] The voltage output module includes a first output current unit, a second output current unit, and a first resistor; the control end of the first output current unit is coupled to the output end of the first operational amplifier module through a seventh switch, the output end of the first output current unit is coupled to the ground end or the first end of the first resistor, and the first end and the second end of the first output current unit are respectively coupled to the second input signal and the power supply voltage; the first output current unit is used to generate and output a first output current according to the voltage output by the first operational amplifier module;

[0015] The control end of the second output current unit is coupled to the output end of the second operational amplifier module through the eighth switch, the output end of the second output current unit is coupled to the ground end or the first end of the first resistor, and the first end and the second end of the first output current unit are respectively coupled to the second input signal and the power supply voltage; the second output current unit is used to generate and output a second output current according to the voltage output by the second operational amplifier module; the first end of the first resistor serves as the output end of the voltage output module, the second end of the first resistor is grounded, and the first resistor is used to generate and output a first output voltage or a second output voltage according to the first output current or the second output current; wherein the first output current is the same as the second output current; wherein:

[0016] If the first operational amplifier module is in the offset voltage storage stage, the second switch and the third switch are both turned on, and the first switch and the seventh switch are both turned off; the first offset voltage elimination unit is used to store the voltage output by the first operational amplifier unit, and generate a first offset compensation current and output it to the first operational amplifier unit; if the second operational amplifier module is in the offset voltage storage stage, the fifth switch and the sixth switch are both turned on, and the fourth switch and the eighth switch are both turned off; the second offset voltage elimination unit is used to store the voltage output by the second operational amplifier unit, and generate a second offset compensation current and output it to the second operational amplifier unit;

[0017] If the first operational amplifier module is in the offset voltage elimination stage, the second switch and the third switch are both turned off, and the first switch and the seventh switch are both turned on; the first offset voltage elimination unit is used to maintain the first offset compensation current according to the stored voltage so that the first input signal is equal to the second input signal; the output end of the first output current unit is coupled to the ground; if the second operational amplifier module is in the offset voltage elimination stage, the fifth switch and the sixth switch are both turned off, and the fourth switch and the eighth switch are both turned on; the second offset voltage elimination unit is used to maintain the second offset compensation current according to the stored voltage so that the first input signal is equal to the second input signal; the output end of the second output current unit is coupled to the ground;

[0018] If the first operational amplifier module is in a normal working stage, the second switch and the third switch are still turned off, and the first switch and the seventh switch are still turned on; the output end of the first output current unit is coupled to the first end of the first resistor; if the second operational amplifier module is in a normal working stage, the fourth switch and the eighth switch are still turned on, and the fifth switch and the sixth switch are still turned off; the output end of the second output current unit is coupled to the first end of the first resistor;

[0019] If the first operational amplifier module is in the offset voltage storage stage and the offset voltage elimination stage respectively, the second operational amplifier module is in the normal working stage; if the second operational amplifier module is in the offset voltage storage stage and the offset voltage elimination stage respectively, the first operational amplifier module is in the normal working stage.

[0020] Optionally, the first offset voltage elimination unit includes a first capacitor, a first PMOS tube, a second resistor, a first NMOS tube, and a second NMOS tube; the first end of the first capacitor is coupled to the gate of the first PMOS tube and serves as the input end of the first offset voltage elimination unit, and the second end of the first capacitor and the second end of the second resistor are both coupled to the power supply voltage; the source of the first PMOS tube is coupled to the first end of the second resistor, and the drain of the first PMOS tube is coupled to the drain of the first NMOS tube; the gate of the first NMOS tube is coupled to its own drain and to the gate of the second NMOS tube, the drain of the second NMOS tube serves as the output end of the first offset voltage elimination unit, and the source of the second NMOS tube and the source of the first NMOS tube are both grounded.

[0021] Optionally, the first operational amplifier unit includes a first differential input unit, a first amplification path, a second amplification path, a first amplification output unit, and a first bias unit;

[0022] The non-inverting input terminal of the first differential input unit is connected to the first input signal, and the inverting input terminal of the first differential input unit is connected to the first input signal through the second switch or the second input signal through the first switch; the first end of the first amplifying path is coupled to the first end of the first differential input unit; the first end of the second amplifying path is coupled to the second end of the first differential input unit; the second end of the second amplifying path is respectively coupled to the first bias end of the first amplifying output unit and the output end of the first offset voltage elimination unit; the third end of the first differential input unit is coupled to the input end of the first bias unit, and the bias end of the first bias unit and the second bias end of the first amplifying output unit are both connected to the bias voltage; the output end of the first amplifying output unit serves as the output end of the first operational amplifier unit.

[0023] Optionally, the first differential input unit includes a third NMOS tube and a fourth NMOS tube; the gate of the third NMOS tube and the gate of the fourth NMOS tube serve as the in-phase input terminal and the inverting input terminal of the first differential input unit respectively, the drain of the third NMOS tube serves as the second terminal of the first differential input unit, and the drain of the fourth NMOS tube serves as the first terminal of the first differential input unit; the source of the third NMOS tube serves as the third terminal of the first differential input unit and is coupled to the source of the fourth NMOS tube.

[0024] Optionally, the first bias unit includes a fifth NMOS tube; the gate of the fifth NMOS tube is connected to the bias voltage, the drain of the fifth NMOS tube serves as the input end of the first bias unit, and the source of the fifth NMOS tube is grounded.

[0025] Optionally, the first amplification path includes a second PMOS tube, a third PMOS tube, and a sixth NMOS tube; the second amplification path includes a fourth PMOS tube, a fifth PMOS tube, and a seventh NMOS tube;

[0026] The gate of the second PMOS tube is coupled to the gate of the fourth PMOS tube, the gate of the second PMOS tube is also coupled to the drain of the third PMOS tube, the drain of the second PMOS tube serves as the first end of the first amplification path and is coupled to the source of the third PMOS tube, the source of the second PMOS tube and the source of the fourth PMOS tube are both coupled to the power supply voltage; the gate of the third PMOS tube is coupled to the gate of the fifth PMOS tube, the drain of the third PMOS tube is coupled to the drain of the sixth NMOS tube; the gate of the sixth NMOS tube is connected to the bias voltage and coupled to the gate of the seventh NMOS tube, the source of the sixth NMOS tube and the source of the seventh NMOS tube are both grounded;

[0027] The drain of the fourth PMOS tube serves as the first end of the second amplifying path and is coupled to the source of the fifth PMOS tube; the drain of the fifth PMOS tube serves as the second end of the second amplifying path and is coupled to the drain of the seventh NMOS tube.

[0028] Optionally, the first amplifying output unit includes a sixth PMOS tube and an eighth NMOS tube; the gate of the sixth PMOS tube serves as the first bias end of the first amplifying output unit, the source of the sixth PMOS tube is coupled to the power supply voltage, the drain of the sixth PMOS tube serves as the output end of the first amplifying output unit and is coupled to the drain of the eighth NMOS tube; the gate of the eighth NMOS tube serves as the second bias end of the first amplifying output unit, and the source of the eighth NMOS tube is grounded.

[0029] Optionally, the second offset voltage elimination unit includes a second capacitor, a seventh PMOS tube, a third resistor, a ninth NMOS tube, and a tenth NMOS tube; the first end of the second capacitor is coupled to the gate of the seventh PMOS tube and serves as the input end of the second offset voltage elimination unit, and the second end of the second capacitor and the second end of the third resistor are both coupled to the power supply voltage; the source of the seventh PMOS tube is coupled to the first end of the third resistor, and the drain of the seventh PMOS tube is coupled to the drain of the ninth NMOS tube; the gate of the ninth NMOS tube is coupled to its own drain and to the gate of the tenth NMOS tube, the drain of the tenth NMOS tube serves as the output end of the second offset voltage elimination unit, and the source of the tenth NMOS tube and the source of the ninth NMOS tube are both grounded.

[0030] Optionally, the second operational amplifier unit includes a second differential input unit, a third amplification path, a fourth amplification path, a second amplification output unit, and a second bias unit;

[0031] The in-phase input terminal of the second differential input unit is connected to the first input signal, and the inverting input terminal of the second differential input unit is connected to the first input signal through the fifth switch or the second input signal through the fourth switch; the first end of the third amplifying path is coupled to the second end of the second differential input unit; the first end of the fourth amplifying path is coupled to the first end of the second differential input unit; the second end of the fourth amplifying path is respectively coupled to the first bias end of the second amplifying output unit and the output end of the second offset voltage elimination unit; the third end of the second differential input unit is coupled to the input end of the second bias unit, and the bias end of the second bias unit and the second bias end of the second amplifying output unit are both connected to the bias voltage; the output end of the second amplifying output unit serves as the output end of the second operational amplifier unit.

[0032] Optionally, the second differential input unit includes an eleventh NMOS tube and a twelfth NMOS tube; the gate of the eleventh NMOS tube and the gate of the twelfth NMOS tube serve as the in-phase input terminal and the inverting input terminal of the second differential input unit respectively, the drain of the eleventh NMOS tube serves as the second terminal of the second differential input unit, and the drain of the twelfth NMOS tube serves as the first terminal of the second differential input unit; the source of the eleventh NMOS tube serves as the third terminal of the second differential input unit and is coupled to the source of the twelfth NMOS tube.

[0033] Optionally, the second bias unit includes a fifteenth NMOS tube; the gate of the fifteenth NMOS tube is connected to the bias voltage, the drain of the fifteenth NMOS tube serves as the input end of the second bias unit, and the source of the fifteenth NMOS tube is grounded.

[0034] Optionally, the third amplifying path includes an eighth PMOS tube, a ninth PMOS tube, and a thirteenth NMOS tube; the fourth amplifying path includes a tenth PMOS tube, an eleventh PMOS tube, and a fourteenth NMOS tube;

[0035] The gate of the eighth PMOS tube is coupled to the gate of the tenth PMOS tube, and the gate of the eighth PMOS tube is also coupled to the drain of the ninth PMOS tube. The drain of the eighth PMOS tube serves as the third end of the third amplification path and is coupled to the source of the ninth PMOS tube. The source of the eighth PMOS tube and the source of the tenth PMOS tube are both coupled to the power supply voltage; the gate of the ninth PMOS tube is coupled to the gate of the eleventh PMOS tube, and the drain of the ninth PMOS tube is coupled to the drain of the thirteenth NMOS tube; the gate of the thirteenth NMOS tube is connected to the bias voltage and coupled to the gate of the fourteenth NMOS tube, and the source of the thirteenth NMOS tube and the source of the fourteenth NMOS tube are both grounded;

[0036] The drain of the tenth PMOS tube serves as the first end of the fourth amplifying path and is coupled to the source of the eleventh PMOS tube; the drain of the eleventh PMOS tube serves as the second end of the fourth amplifying path and is coupled to the drain of the fourteenth NMOS tube.

[0037] Optionally, the second amplifying and outputting unit includes a twelfth PMOS tube and a sixteenth NMOS tube; the gate of the twelfth PMOS tube serves as the first bias terminal of the second amplifying and outputting unit, the source of the twelfth PMOS tube is coupled to the power supply voltage, the drain of the twelfth PMOS tube serves as the output terminal of the second amplifying and outputting unit and is coupled to the drain of the sixteenth NMOS tube; the gate of the sixteenth NMOS tube serves as the second bias terminal of the second amplifying and outputting unit, and the source of the sixteenth NMOS tube is grounded.

[0038] Optionally, the first output current unit includes a thirteenth PMOS tube and a fourth resistor; the gate of the thirteenth PMOS tube serves as the control end of the first output current unit, the source of the thirteenth PMOS tube is coupled to the first end of the fourth resistor, and the drain of the thirteenth PMOS tube serves as the output end of the first output current unit; the first end and the second end of the fourth resistor are respectively connected to the second input signal and the power supply voltage.

[0039] Optionally, the second output current unit includes a fourteenth PMOS tube and a fifth resistor; the gate of the fourteenth PMOS tube serves as the input end of the second output current unit, the source of the fourteenth PMOS tube is coupled to the first end of the fifth resistor, and the drain of the fourteenth PMOS tube serves as the output end of the second output current unit; the first end and the second end of the fifth resistor are respectively connected to the second input signal and the power supply voltage.

[0040] Optionally, it further includes a switch array; the switch array includes a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, and a twentieth PMOS tube;

[0041] The gate of the fifteenth PMOS tube is connected to the first control signal, the source of the fifteenth PMOS tube is coupled to the output end of the first output current unit, and the drain of the fifteenth PMOS tube is respectively coupled to the source of the seventeenth PMOS tube and the source of the eighteenth PMOS tube; the drain of the seventeenth PMOS tube is grounded, the drain of the eighteenth PMOS tube is coupled to the first end of the first resistor, and the gate of the seventeenth PMOS tube and the gate of the eighteenth PMOS tube are respectively connected to the second control signal and the third control signal;

[0042] The gate of the sixteenth PMOS tube is connected to the fourth control signal, the source of the sixteenth PMOS tube is coupled to the output end of the second output current unit, and the drain of the sixteenth PMOS tube is respectively coupled to the source of the nineteenth PMOS tube and the source of the twentieth PMOS tube; the drain of the nineteenth PMOS tube is grounded, the drain of the twentieth PMOS tube is coupled to the first end of the first resistor, and the gate of the nineteenth PMOS tube and the gate of the twentieth PMOS tube are respectively connected to the fifth control signal and the sixth control signal;

[0043] Wherein, if the first operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the second operational amplifier module is in the normal working stage, the first control signal is a high level or a low level, the fourth control signal is a low level, the second control signal is a low level, the third control signal is a high level, the fifth control signal is a high level, and the sixth control signal is a low level;

[0044] If the second operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the first operational amplifier module is in the normal working stage, the fourth control signal is a high level or a low level, the first control signal is a low level, the fifth control signal is a low level, the sixth control signal is a high level, the second control signal is a high level, and the third control signal is a low level.

[0045] Optionally, the second control signal and the fifth control signal are two-phase non-overlapping signals; the second control signal is an inverted signal of the third control signal; and the fifth control signal is an inverted signal of the sixth control signal.

[0046] Optionally, a sixth resistor is further included; the sixth resistor is coupled between the drain of the seventeenth PMOS transistor and the ground terminal; wherein, the resistance value of the sixth resistor is equal to the resistance value of the first resistor.

[0047] According to a second aspect of the present invention, an electronic device is provided, including the operational amplifier with low offset voltage provided by the first aspect and optional implementation manners of the present invention.

[0048] For the operational amplifier with low offset voltage provided by the present invention, on the one hand, the first offset voltage cancellation unit and the second offset voltage cancellation unit respectively store and accurately cancel the offset voltage existing in the first operational amplification unit and the offset voltage existing in the second operational amplification unit, so as to eliminate the error caused by the offset voltage on the first output current generated by the first output current unit and the second output current generated by the second output current unit. On the other hand, by controlling the on and off of the control switch, the first operational amplification module and the second operational amplification module are controlled to alternately be in different working stages. If the first operational amplification module is successively in the offset voltage storage stage and the offset voltage cancellation stage, then the second operational amplification module is in the normal working stage; if the second operational amplification module is successively in the offset voltage storage stage and the offset voltage cancellation stage, then the first operational amplification module is in the normal working stage; in this way, it can be ensured that the input end of the operational amplification module in the normal working state within each clock cycle has an extremely low offset voltage, thereby ensuring the continuity of offset voltage cancellation. At the same time, the technical solution provided by the present invention is not limited by the input signal frequency during the process of canceling the offset voltage, increasing the application range of the present invention. Description of the Drawings

[0049] The present invention will be further described in detail below in conjunction with the drawings and specific implementation manners.

[0050] Figure 1 is the circuit structure diagram of a chopper operational amplifier in the prior art;

[0051] Figure 2 is the circuit structure diagram of a self-zeroing operational amplifier in the prior art;

[0052] Figure 3 is the module structure diagram of the operational amplifier with low offset voltage provided in the first embodiment of the present invention;

[0053] Figure 4 is the circuit structure diagram of the operational amplifier with low offset voltage provided in the first embodiment of the present invention;

[0054] Figure 5 is the timing diagram of the signals for controlling the conduction and cutoff of each switch in the operational amplifier with low offset voltage provided in the first embodiment of the present invention.

[0055] Reference numerals:

[0056] 10-first operational amplifier module; 11-first operational amplifier unit; 12-first offset voltage elimination unit; 20-second operational amplifier module; 21-second operational amplifier unit; 22-second offset voltage elimination unit; 30-voltage output module; 31-first output current unit; 32-second output current unit; S1-first switch; S2-second switch; S3-third switch; S4-fourth switch; S5-fifth switch; S6-sixth switch; S7-seventh switch; S8-eighth switch; VCS-power supply voltage; VISEN_IN-first input signal; VBUFA-second input signal; VOUT -; Vos1-; Vos2-; VBIAS-; C1-first capacitor; C2-second capacitor; R1-first resistor; R2-second resistor; R3-third resistor; R4-fourth resistor; R5-fifth resistor; NM1-first NMOS tube; NM2-second NMOS tube; NM3-third NMOS tube; NM4-fourth NMOS tube; NM5-fifth NMOS tube; NM6-sixth NMOS tube; NM7-seventh NMOS tube; NM8-eighth NMOS tube; NM9-ninth NMOS tube; NM10-tenth NMOS tube; NM11-eleventh NMOS tube; NM12 -12th NMOS tube; NM13-13th NMOS tube; NM14-14th NMOS tube; NM15-15th NMOS tube; NM16-16th NMOS tube; PM1-1st PMOS tube; PM2-2nd PMOS tube; PM3-3rd PMOS tube; PM4-4th PMOS tube; PM5-5th PMOS tube; PM6-6th PMOS tube; PM7-7th PMOS tube; PM8-8th PMOS tube; PM9-9th PMOS tube; PM10-10th PMOS tube; PM11-11th PMOS tube; PM12-12th PMOS tube; P M13-the thirteenth PMOS tube; PM14-the fourteenth PMOS tube; PM15-the fifteenth PMOS tube; PM16-the sixteenth PMOS tube; PM17-the seventeenth PMOS tube; PM18-the eighteenth PMOS tube; PM19-the nineteenth PMOS tube; PM20-the twentieth PMOS tube; AH-the second control signal; AL-the third control signal; BH-the fifth control signal; BL-the sixth control signal; A1H-the seventh control signal; A2H-the eighth control signal; A2L-the first control signal; B1H-the ninth control signal; B2H-the tenth control signal; B2L-the fourth control signal. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0058] Please refer to Figure 3 , a first embodiment of the present invention provides an operational amplifier with low offset voltage, comprising: a first operational amplifier module 10, a second operational amplifier module 20, and a voltage output module 30;

[0059] The first operational amplifier module 10 includes a first operational amplifier unit 11 and a first offset voltage elimination unit 12; the non-inverting input terminal of the first operational amplifier unit 11 is connected to the first input signal VISEN_IN, and the inverting input terminal of the first operational amplifier unit 11 is connected to the first input signal VISEN_IN through a second switch S2 or connected to the second input signal VBUFA through a first switch S1; the first terminal of the first operational amplifier unit 11 is coupled to the output terminal of the first offset voltage elimination unit 12; the output terminal of the first operational amplifier unit 11 is coupled to the input terminal of the first offset voltage elimination unit 12 through a third switch S3, and serves as the output terminal of the first operational amplifier module 10;

[0060] The second operational amplifier module 20 includes a second operational amplifier unit 21 and a second offset voltage elimination unit 22; the non-inverting input terminal of the second operational amplifier unit 21 is connected to the first input signal VISEN_IN, and the inverting input terminal of the second operational amplifier unit 21 is connected to the first input signal VISEN_IN through a fifth switch S5 or connected to the second input signal VBUFA through a fourth switch S4; the first terminal of the second operational amplifier unit 21 is coupled to the output terminal of the second offset voltage elimination unit 22; the output terminal of the second operational amplifier unit 21 is coupled to the input terminal of the second offset voltage elimination unit 22 through a sixth switch S6, and serves as the output terminal of the second operational amplifier module 20;

[0061] The voltage output module 30 includes a first output current unit 31, a second output current unit 32, and a first resistor R1; the control end of the first output current unit 31 is coupled to the output end of the first operational amplifier module 10 through a seventh switch S7, the output end of the first output current unit 31 is coupled to the ground end or the first end of the first resistor R1, and the first end and the second end of the first output current unit 31 are respectively coupled to the second input signal VBUFA and the power supply voltage VCS; the first output current unit 31 is used to generate and output a first output current according to the voltage output by the first operational amplifier module 10; the control end of the second output current unit 32 is coupled to the second operational amplifier module 20 through an eighth switch S8. The output end of the second output current unit 32 is coupled to the ground or the first end of the first resistor R1, and the first end and the second end of the first output current unit 31 are respectively coupled to the second input signal VBUFA and the power supply voltage VCS; the second output current unit 32 is used to generate and output a second output current according to the voltage output by the second operational amplifier module 20; the first end of the first resistor R1 serves as the output end of the voltage output module 30, and the second end of the first resistor R1 is grounded, and the first resistor R1 is used to generate and output a first output voltage or a second output voltage according to the first output current or the second output current; wherein the first output current is the same as the second output current; wherein:

[0062] If the first operational amplifier module 10 is in the offset voltage storage stage, the second switch S2 and the third switch S3 are both turned on, and the first switch S1 and the seventh switch S7 are both turned off; the first offset voltage elimination unit 12 is used to store the voltage output by the first operational amplifier unit 11, and generate a first offset compensation current and output it to the first operational amplifier unit 11; if the second operational amplifier module 20 is in the offset voltage storage stage, the fifth switch S5 and the sixth switch S6 are both turned on, and the fourth switch S4 and the eighth switch S8 are both turned off; the second offset voltage elimination unit is used to store the voltage output by the second operational amplifier unit 21, and generate a second offset compensation current and output it to the second operational amplifier unit 21;

[0063] If the first operational amplifier module 10 is in the offset voltage elimination stage, the second switch S2 and the third switch S3 are both turned off, and the first switch S1 and the seventh switch S7 are both turned on; the first offset voltage elimination unit 12 is used to maintain the first offset compensation current according to the stored voltage so that the first input signal VISEN_IN is equal to the second input signal VBUFA; the output end of the first output current unit 31 is coupled to the ground; if the second operational amplifier module 20 is in the offset voltage elimination stage, the fifth switch S5 and the sixth switch S6 are both turned off, and the fourth switch S4 and the eighth switch S8 are both turned on; the second offset voltage elimination unit 22 is used to maintain the second offset compensation current according to the stored voltage so that the first input signal VISEN_IN is equal to the second input signal VBUFA; the output end of the second output current unit 32 is coupled to the ground;

[0064] If the first operational amplifier module 10 is in a normal working stage, the second switch S2 and the third switch S3 are still turned off, and the first switch S1 and the seventh switch S7 are still turned on; the output end of the first output current unit 31 is coupled to the first end of the first resistor R1; if the second operational amplifier module 20 is in a normal working stage, the fourth switch S4 and the eighth switch S8 are still turned on, and the fifth switch S5 and the sixth switch S6 are still turned off; the output end of the second output current unit 32 is coupled to the first end of the first resistor R1;

[0065] If the first operational amplifier module 10 is in the offset voltage storage stage and the offset voltage elimination stage respectively, the second operational amplifier module 20 is in the normal working stage; if the second operational amplifier module 20 is in the offset voltage storage stage and the offset voltage elimination stage respectively, the first operational amplifier module 10 is in the normal working stage.

[0066] The first embodiment provided by the present invention achieves high-precision and full-cycle elimination of the influence of the offset voltage on the accuracy of the first output current and the second output current through the above technical solution. The principle is:

[0067] For a single operational amplifier module in an operational amplifier, taking the first operational amplifier module 10 as an example, if the first operational amplifier module 10 needs to eliminate the offset voltage at the input end of the first operational amplifier unit 11, the first operational amplifier module 10 first enters the offset voltage storage stage, and turns on the second switch S2 and the third switch S3, and turns off the first switch S1 and the seventh switch S7. In this stage, both the in-phase input end and the inverting input end of the first operational amplifier unit 11 are connected to the first input signal VISEN_IN, so that the two input ends of the first operational amplifier unit 11 are short-circuited. Then, the first operational amplifier can only amplify the offset voltage at the input end and output the first amplified voltage to the first offset voltage elimination unit 12. The first offset voltage elimination unit 12 is used to store the first amplified voltage in this stage. Specifically, the first offset voltage elimination unit 12 stores the first amplified voltage through an internally set capacitor. At the same time, the first offset voltage elimination unit 12 generates a first offset compensation current according to the first amplified voltage and outputs it to the first operational amplifier unit 11.

[0068] Then, the first operational amplifier module 10 enters the offset voltage elimination stage, and turns on the first switch S1 and the seventh switch S7, and turns off the second switch S2 and the third switch S3. In this stage, the first operational amplifier unit 11 has the first input signal VISEN_IN and the second input signal VBUFA connected to the in-phase input terminal and the inverting input terminal, respectively, and the output terminal of the first operational amplifier unit 11 is connected to the first output current unit 31, so that the first output current unit 31 generates the first output current. Since the capacitor voltage cannot change suddenly, the first offset voltage elimination unit 12 replaces the original input first amplified voltage with the stored voltage to maintain the first offset compensation current, thereby making the first input signal VISEN_IN input to the in-phase input terminal of the first operational amplifier module 10 the same as the second input signal VBUFA input to the inverting input terminal. At the same time, because the first terminal of the first output current unit 31 is connected to the second input signal VBUFA, the first terminal of the first output current unit 31 is equivalent to being connected to the first input signal VISEN_IN, that is, the accuracy of the first output current is ensured.

[0069] Finally, the first operational amplifier module 10 enters a normal working stage. On the basis of turning on the first switch S1 and the seventh switch S7 and turning off the second switch S2 and the third switch S3, the output end of the first output current unit 31 is coupled to the first end of the first resistor R1, so that the first output current flows through the first resistor R1, generates a first output voltage and outputs it.

[0070] Since the structure of the second operational amplifier module 20 is the same as that of the first operational amplifier module 10, the working contents of the second operational amplifier module 20 in each stage of the offset voltage storage stage, the offset voltage elimination stage and the normal working stage are the same as those of the first operational amplifier module 10, which will not be repeated here.

[0071] On the basis of eliminating the influence of the offset voltage on the output current accuracy by a single operational amplifier module, the first operational amplifier module 10 and the second operational amplifier module 20 are set to work alternately. When the first operational amplifier module 10 is in the process of the offset voltage storage stage and the offset voltage elimination stage, the second operational amplifier module 20 is in a normal working state. After the first operational amplifier module 10 completes the offset voltage elimination stage and enters the normal working state, the second operational amplifier module 20 enters the offset voltage storage stage and the offset voltage elimination stage from the normal working state. Based on this, it can be ensured that the operational amplifier modules that work normally in each clock cycle have extremely low offset voltages, thereby ensuring the continuity of the offset voltage elimination and ensuring that the sampling results of the current or voltage are not affected by the offset voltage.

[0072] The following specifically describes the various structures and working principles of the low offset voltage operational amplifier provided in the first embodiment.

[0073] Please refer to Figure 4As a specific implementation, the first offset voltage elimination unit 12 includes a first capacitor C1, a first PMOS transistor PM1, a second resistor R2, a first NMOS transistor NM1, and a second NMOS transistor NM2; a first end of the first capacitor C1 is coupled to the gate of the first PMOS transistor PM1 and serves as an input end of the first offset voltage elimination unit 12, and a second end of the first capacitor C1 and a second end of the second resistor R2 are both coupled to a power supply voltage VCS; a source of the first PMOS transistor PM1 is coupled to a first end of the second resistor R2, and a drain of the first PMOS transistor PM1 is coupled to a drain of the first NMOS transistor NM1; a gate of the first NMOS transistor NM1 is coupled to its own drain and to a gate of the second NMOS transistor NM2, a drain of the second NMOS transistor NM2 serves as an output end of the first offset voltage elimination unit 12, and a source of the second NMOS transistor NM2 and a source of the first NMOS transistor NM1 are both grounded.

[0074] The voltage output by the first operational amplifier unit 11 acts on the gate of the first PMOS transistor PM1, so that the first PMOS transistor PM1 generates a source-drain current. The formula of the source-drain current is specifically:

[0075] I DPM6 =g m *V C ; (1)

[0076] Among them, I DPM6 Used to characterize the source current of the first PMOS tube PM1; g m Used to characterize the transconductance of the first PMOS tube PM1; V C It is used to represent the voltage output by the first operational amplifier unit 11 .

[0077] Since the drain of the first NMOS tube NM1 is connected to the drain of the first PMOS tube PM1 and to its own gate. Therefore, the first NMOS tube NM1 is turned on by the source-drain current output by the first PMOS tube PM1, and the drain-source current flowing through the first NMOS tube NM1 is equal to the source current flowing through the first PMOS tube PM1. At the same time, the first NMOS tube NM1 and the second NMOS tube NM2 form a current mirror structure, so the drain-source current flowing through the first NMOS tube NM1 is proportionally mirrored to the second NMOS tube NM2. Among them, the ratio of the current mirror is specifically controlled by setting the ratio of the width-to-length ratio of the first NMOS tube NM1 and the second NMOS tube NM2. For example, the width-to-length ratio of the second NMOS tube NM2 is set to be four times the width-to-length ratio of the first NMOS tube NM1, and the drain-source current flowing through the second NMOS tube NM2 is equal to four times the drain-source current flowing through the first NMOS tube NM1. Of course, the specific ratio can be set according to actual needs and is not limited here.

[0078] As a specific implementation, the first operational amplifier unit 11 includes a first differential input unit, a first amplification path, a second amplification path, a first amplification output unit, and a first bias unit;

[0079] The in-phase input terminal of the first differential input unit is connected to the first input signal VISEN_IN, and the inverting input terminal of the first differential input unit is connected to the first input signal VISEN_IN through the second switch S2 or connected to the second input signal VBUFA through the first switch S1; the first end of the first amplification path is coupled to the first end of the first differential input unit; the first end of the second amplification path is coupled to the second end of the first differential input unit; the second end of the second amplification path is respectively coupled to the first bias end of the first amplification output unit and the output end of the first offset voltage elimination unit 12; the third end of the first differential input unit is coupled to the input end of the first bias unit, and the bias end of the first bias unit and the second bias end of the first amplification output unit are both connected to the bias voltage; the output end of the first amplification output unit serves as the output end of the first operational amplifier unit 11.

[0080] like Figure 4As shown, the first differential input unit includes a third NMOS tube NM3 and a fourth NMOS tube NM4; the gate of the third NMOS tube NM3 and the gate of the fourth NMOS tube NM4 serve as the in-phase input terminal and the inverting input terminal of the first differential input unit respectively, the drain of the third NMOS tube NM3 serves as the second terminal of the first differential input unit, and the drain of the fourth NMOS tube NM4 serves as the first terminal of the first differential input unit; the source of the third NMOS tube NM3 serves as the third terminal of the first differential input unit and is coupled to the source of the fourth NMOS tube NM4. Specifically: theoretically, when the first operational amplifier unit 11 completes the feedback connection, due to the virtual short principle, the gate voltage of the third NMOS tube NM3 is equal to the gate voltage of the fourth NMOS tube NM4, so the first input signal VISEN_IN acting on the third NMOS tube NM3 is equal to the second input signal VBUFA acting on the fourth NMOS tube NM4. However, since there is an offset voltage at the gate of the fourth NMOS transistor NM4, when the gate voltage of the third NMOS transistor NM3 is equal to the gate voltage of the fourth NMOS transistor NM4, the first input signal VISEN_IN is not equal to the second input signal VBUFA but equal to the sum of the offset voltage and the second input signal VBUFA. Eliminating the offset voltage and making the first input signal VISEN_IN equal to the second input signal VBUFA is one of the purposes to be achieved in this embodiment.

[0081] like Figure 4 As shown, the first bias unit includes a fifth NMOS tube NM5; the gate of the fifth NMOS tube NM5 is connected to the bias voltage, the drain of the fifth NMOS tube NM5 serves as the input end of the first bias unit, and the source of the fifth NMOS tube NM5 is grounded.

[0082] like Figure 4 As shown, the first amplifying path includes a second PMOS transistor PM2, a third PMOS transistor PM3, and a sixth NMOS transistor NM6; the second amplifying path includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, and a seventh NMOS transistor NM7;

[0083] The gate of the second PMOS tube PM2 is coupled to the gate of the fourth PMOS tube PM4, and the gate of the second PMOS tube PM2 is also coupled to the drain of the third PMOS tube PM3. The drain of the second PMOS tube PM2 serves as the first end of the first amplification path and is coupled to the source of the third PMOS tube PM3. The source of the second PMOS tube PM2 and the source of the fourth PMOS tube PM4 are both coupled to the power supply voltage VCS; the gate of the third PMOS tube PM3 is coupled to the gate of the fifth PMOS tube PM5, and the drain of the third PMOS tube PM3 is coupled to the drain of the sixth NMOS tube NM6; the gate of the sixth NMOS tube NM6 is connected to the bias voltage and coupled to the gate of the seventh NMOS tube NM7, and the source of the sixth NMOS tube NM6 and the source of the seventh NMOS tube NM7 are both grounded;

[0084] The drain of the fourth PMOS transistor PM4 serves as the first end of the second amplifying path and is coupled to the source of the fifth PMOS transistor PM5 ; the drain of the fifth PMOS transistor PM5 serves as the second end of the second amplifying path and is coupled to the drain of the seventh NMOS transistor NM7 .

[0085] like Figure 4 As shown, the first amplifying output unit includes a sixth PMOS tube PM6 and an eighth NMOS tube NM8; the gate of the sixth PMOS tube PM6 serves as a first bias terminal of the first amplifying output unit, the source of the sixth PMOS tube PM6 is coupled to the power supply voltage VCS, the drain of the sixth PMOS tube PM6 serves as an output terminal of the first amplifying output unit and is coupled to the drain of the eighth NMOS tube NM8; the gate of the eighth NMOS tube NM8 serves as a second bias terminal of the first amplifying output unit, and the source of the eighth NMOS tube NM8 is grounded.

[0086] like Figure 4As shown, as a specific implementation, the second offset voltage elimination unit 22 includes a second capacitor C2, a seventh PMOS transistor PM7, a third resistor R3, a ninth NMOS transistor NM9, and a tenth NMOS transistor NM10; the first end of the second capacitor C2 is coupled to the gate of the seventh PMOS transistor PM7 and serves as the input end of the second offset voltage elimination unit 22, and the second end of the second capacitor C2 and the second end of the third resistor R3 are both coupled to the power supply voltage VCS; the source of the seventh PMOS transistor PM7 is coupled to the first end of the third resistor R3, and the drain of the seventh PMOS transistor PM7 is coupled to the drain of the ninth NMOS transistor NM9; the gate of the ninth NMOS transistor NM9 is coupled to its own drain and to the gate of the tenth NMOS transistor NM10, and the drain of the tenth NMOS transistor NM10 serves as the output end of the second offset voltage elimination unit 22, and the source of the tenth NMOS transistor NM10 and the source of the ninth NMOS transistor NM9 are both grounded. The working principle of the second offset voltage elimination unit 22 is the same as that of the first offset voltage elimination unit, which will not be described in detail herein.

[0087] As a specific implementation, the second operational amplifier unit 21 includes a second differential input unit, a third amplification path, a fourth amplification path, a second amplification output unit, and a second bias unit;

[0088] The in-phase input terminal of the second differential input unit is connected to the first input signal VISEN_IN, and the inverting input terminal of the second differential input unit is connected to the first input signal VISEN_IN through the fifth switch S5 or the second input signal VBUFA through the fourth switch S4; the first end of the third amplification path is coupled to the second end of the second differential input unit; the first end of the fourth amplification path is coupled to the first end of the second differential input unit; the second end of the fourth amplification path is respectively coupled to the first bias end of the second amplification output unit and the output end of the second offset voltage elimination unit 22; the third end of the second differential input unit is coupled to the input end of the second bias unit, and the bias end of the second bias unit and the second bias end of the second amplification output unit are both connected to the bias voltage; the output end of the second amplification output unit serves as the output end of the second operational amplifier unit 21.

[0089] like Figure 4As shown, the second differential input unit includes an eleventh NMOS tube NM11 and a twelfth NMOS tube NM12; the gate of the eleventh NMOS tube NM11 and the gate of the twelfth NMOS tube NM12 serve as the in-phase input terminal and the inverting input terminal of the second differential input unit respectively, the drain of the eleventh NMOS tube NM11 serves as the second terminal of the second differential input unit, and the drain of the twelfth NMOS tube NM12 serves as the first terminal of the second differential input unit; the source of the eleventh NMOS tube NM11 serves as the third terminal of the second differential input unit and is coupled to the source of the twelfth NMOS tube NM12. The problem of the offset voltage between the in-phase input terminal and the inverting input terminal of the second differential input unit is the same as that of the first differential input unit, and will not be repeated here.

[0090] like Figure 4 As shown, the second bias unit includes a fifteenth NMOS tube NM15; the gate of the fifteenth NMOS tube NM15 is connected to the bias voltage, the drain of the fifteenth NMOS tube NM15 serves as the input end of the second bias unit, and the source of the fifteenth NMOS tube NM15 is grounded.

[0091] like Figure 4 As shown, the third amplifying path includes an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, and a thirteenth NMOS transistor NM13; the fourth amplifying path includes a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, and a fourteenth NMOS transistor NM14;

[0092] The gate of the eighth PMOS tube PM8 is coupled to the gate of the tenth PMOS tube PM10, and the gate of the eighth PMOS tube PM8 is also coupled to the drain of the ninth PMOS tube PM9. The drain of the eighth PMOS tube PM8 serves as the third end of the third amplification path and is coupled to the source of the ninth PMOS tube PM9. The source of the eighth PMOS tube PM8 and the source of the tenth PMOS tube PM10 are both coupled to the power supply voltage VCS; the gate of the ninth PMOS tube PM9 is coupled to the gate of the eleventh PMOS tube PM11, and the drain of the ninth PMOS tube PM9 is coupled to the drain of the thirteenth NMOS tube NM13; the gate of the thirteenth NMOS tube NM13 is connected to the bias voltage and coupled to the gate of the fourteenth NMOS tube NM14, and the source of the thirteenth NMOS tube NM13 and the source of the fourteenth NMOS tube NM14 are both grounded;

[0093] The drain of the tenth PMOS transistor PM10 serves as the first end of the fourth amplifying path and is coupled to the source of the eleventh PMOS transistor PM11 ; the drain of the eleventh PMOS transistor PM11 serves as the second end of the fourth amplifying path and is coupled to the drain of the fourteenth NMOS transistor NM14 .

[0094] like Figure 4 As shown, the second amplifying output unit includes a twelfth PMOS tube PM12 and a sixteenth NMOS tube NM16; the gate of the twelfth PMOS tube PM12 serves as the first bias terminal of the second amplifying output unit, the source of the twelfth PMOS tube PM12 is coupled to the power supply voltage VCS, the drain of the twelfth PMOS tube PM12 serves as the output terminal of the second amplifying output unit and is coupled to the drain of the sixteenth NMOS tube NM16; the gate of the sixteenth NMOS tube NM16 serves as the second bias terminal of the second amplifying output unit, and the source of the sixteenth NMOS tube NM16 is grounded.

[0095] like Figure 4 As shown, as a specific implementation, the first output current unit 31 includes a thirteenth PMOS tube PM13 and a fourth resistor R4; the gate of the thirteenth PMOS tube PM13 serves as the control end of the first output current unit 31, the source of the thirteenth PMOS tube PM13 is coupled to the first end of the fourth resistor R4, and the drain of the thirteenth PMOS tube PM13 serves as the output end of the first output current unit 31; the first end and the second end of the fourth resistor R4 are respectively connected to the second input signal VBUFA and the power supply voltage VCS.

[0096] like Figure 4 As shown, as a specific implementation, the second output current unit 32 includes a fourteenth PMOS tube PM14 and a fifth resistor R5; the gate of the fourteenth PMOS tube PM14 serves as the input end of the second output current unit 32, the source of the fourteenth PMOS tube PM14 is coupled to the first end of the fifth resistor R5, and the drain of the fourteenth PMOS tube PM14 serves as the output end of the second output current unit 32; the first end and the second end of the fifth resistor R5 are respectively connected to the second input signal VBUFA and the power supply voltage VCS.

[0097] Please refer to Figure 4 and Figure 5As a specific implementation, the voltage output module 30 further includes a switch array; the switch array includes a fifteenth PMOS tube PM15, a sixteenth PMOS tube PM16, a seventeenth PMOS tube PM17, an eighteenth PMOS tube PM18, a nineteenth PMOS tube PM19, and a twentieth PMOS tube PM20;

[0098] The gate of the fifteenth PMOS tube PM15 is connected to the first control signal A2L, the source of the fifteenth PMOS tube PM15 is coupled to the output end of the first output current unit 31, and the drain of the fifteenth PMOS tube PM15 is respectively coupled to the source of the seventeenth PMOS tube PM17 and the source of the eighteenth PMOS tube PM18; the drain of the seventeenth PMOS tube PM17 is grounded, the drain of the eighteenth PMOS tube PM18 is coupled to the first end of the first resistor R1, and the gate of the seventeenth PMOS tube PM17 and the gate of the eighteenth PMOS tube PM18 are respectively connected to the second control signal AH and the third control signal AL;

[0099] The gate of the sixteenth PMOS tube PM16 is connected to the fourth control signal B2L, the source of the sixteenth PMOS tube PM16 is coupled to the output end of the second output current unit 32, and the drain of the sixteenth PMOS tube PM16 is respectively coupled to the source of the nineteenth PMOS tube PM19 and the source of the twentieth PMOS tube PM20; the drain of the nineteenth PMOS tube PM19 is grounded, the drain of the twentieth PMOS tube PM20 is coupled to the first end of the first resistor R1, and the gate of the nineteenth PMOS tube PM19 and the gate of the twentieth PMOS tube PM20 are respectively connected to the fifth control signal BH and the sixth control signal BL;

[0100] Wherein, if the first operational amplifier module 10 is in the offset voltage storage stage or the offset voltage elimination stage, and the second operational amplifier module 20 is in the normal working stage, the first control signal A2L is high or low, the fourth control signal B2L is low, the second control signal AH is low, the third control signal AL is high, the fifth control signal BH is high, and the sixth control signal BL is low. Specifically: if the first operational amplifier module 10 is in the offset voltage storage stage, the first control signal A2L is high to turn off the fifteenth PMOS tube PM15. If the first operational amplifier module 10 is in the offset voltage elimination stage, the first control signal A2L is low to turn on the fifteenth PMOS tube PM15.

[0101] If the second operational amplifier module 20 is in the offset voltage storage stage or the offset voltage elimination stage, and the first operational amplifier module 10 is in the normal working stage, the fourth control signal B2L is high or low, the first control signal A2L is low, the fifth control signal BH is low, the sixth control signal BL is high, the second control signal AH is high, and the third control signal AL is low. Specifically: if the second operational amplifier module 20 is in the offset voltage storage stage, the fourth control signal B2L is high to turn off the sixteenth PMOS tube PM16. If the second operational amplifier module 20 is in the offset voltage elimination stage, the fourth control signal B2L is low to turn on the sixteenth PMOS tube PM16.

[0102] It should be noted that, when the precision requirement is not high, the circuit cost can be reduced by omitting the fifteenth PMOS transistor PM15 and the sixteenth PMOS transistor PM16. Of course, the specific selection can be made according to the requirements and is not limited here.

[0103] like Figure 4 and Figure 5 As shown, as a supplementary embodiment, the second switch S2 and the third switch S3 are both controlled by the seventh control signal A1H, the first switch S1 and the seventh switch S7 are both controlled by the eighth control signal A2H; the fifth switch S5 and the sixth switch S6 are both controlled by the ninth control signal B1H, and the fourth switch S4 and the eighth switch S8 are both controlled by the tenth control signal B2H;

[0104] The second control signal AH is an inverted signal of the third control signal AL; and the fifth control signal BH is an inverted signal of the sixth control signal BL.

[0105] The second control signal AH and the fifth control signal BH are also two-phase non-overlapping signals; the seventh control signal A1H and the eighth control signal A2H are two-phase non-overlapping signals; the ninth control signal B1H and the tenth control signal B2H are also two-phase non-overlapping signals. The beneficial effect is that it can avoid errors caused by accidental loss of charge due to simultaneous conduction of switches.

[0106] Among them, the first switch S1 to the eighth switch S8 specifically include a switch structure composed of an NMOS tube and a PMOS tube in parallel; wherein the source of the NMOS tube is connected to the drain of the PMOS tube, the drain of the NMOS tube is connected to the source of the PMOS tube, and the gate of the NMOS tube and the gate of the PMOS tube are respectively connected to a pair of signals with opposite phases; for example, if the gate of the NMOS tube is connected to a high level, the gate of the parallel PMOS tube is connected to a low level; if the gate of the NMOS tube is connected to a low level, the gate of the parallel PMOS tube is connected to a high level. It has the beneficial effect of improving the accuracy of switching at different stages, thereby improving the accuracy of offset voltage elimination. Of course, in addition to the switch structure composed of an NMOS tube and a PMOS tube in parallel, it can also include a single NMOS tube or a single PMOS tube or other circuit devices with a switch function. The specific switch structure can be selected according to actual needs and is not limited here.

[0107] Please refer to Figure 4 and Figure 5 The following is a description of the working process of the low offset voltage operational amplifier provided in the first embodiment:

[0108] First, the first operational amplifier module 10 enters the offset voltage storage stage, and the second operational amplifier module 20 enters the normal working stage. The second switch S2 and the third switch S3 are both turned on, and the first switch S1 and the seventh switch S7 are both turned off; the fourth switch S4 and the eighth switch S8 are both turned on, and the fifth switch S5 and the sixth switch S6 are both turned off. It should be noted that since the second operational amplifier module 20 at this time has not gone through the offset voltage storage stage and the offset voltage elimination stage, the second operational amplifier module 20 in the normal working stage will be affected by the offset voltage. At this time, the voltage output by the first operational amplifier unit 11 acts on the gates of the first capacitor C1 and the first PMOS tube PM1. On the one hand, the first capacitor C1 is charged, and on the other hand, the first PMOS tube PM1 generates a source-drain current. The source current flows through the first NMOS tube NM1, and is proportionally mirrored to the second NMOS tube NM2 by the current mirror structure formed by the first NMOS tube NM1 and the second NMOS tube NM2 to generate the first offset compensation current. At this time, the current formula flowing through the second PMOS transistor PM2 and the current formula flowing through the fourth PMOS transistor PM4 are respectively:

[0109] I DNM6 +I DNM4 =I DPM2 ; (2)

[0110] I DNM7 +I DNM2 +IDNM3 = I DPM4 ; (3)

[0111] I DPM1 = I DPM2 ; (4)

[0112] wherein, I DPM2 is used to represent the current flowing through the second PMOS transistor PM2; I DPM4 is used to represent the current flowing through the fourth PMOS transistor PM4; I DNM6 is used to represent the current flowing through the sixth NMOS transistor NM6; I DNM7 is used to represent the current flowing through the seventh NMOS transistor NM7; I DNM3 is used to represent the current flowing through the third NMOS transistor NM3; I DNM4 is used to represent the current flowing through the fourth NMOS transistor NM4; I DNM2 is used to represent the first offset compensation current.

[0113] Meanwhile, the gate voltage formulas of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are respectively:

[0114] V G2 = V ISEV_IN ; (5)

[0115] V G3 = V os1 + V ISEN_IN ; (6)

[0116] wherein, V G2 is used to represent the gate voltage of the third NMOS transistor NM3; V G3 is used to represent the gate voltage of the fourth NMOS transistor NM4; V ISEN_IN is used to represent the first input signal VISEN_IN; V os1 is used to represent the offset voltage.

[0117] The current formulas of the current flowing through the third NMOS transistor NM3 and the current flowing through the fourth NMOS transistor NM4 are respectively:

[0118]

[0119]

[0120] wherein; V s is used to represent the source voltage of the third NMOS transistor NM3 and the fourth NMOS transistor NM4; V thIt is used to characterize the threshold voltage of the third NMOS tube NM3 and the fourth NMOS tube NM4.

[0121] Then, after the first operational amplifier module 10 enters the offset voltage elimination stage, the second operational amplifier module 20 still works in the normal working stage. The second switch S2 and the third switch S3 are both turned off, and the first switch S1 and the seventh switch S7 are both turned on; the fourth switch S4 and the eighth switch S8 are still turned on, and the fifth switch S5 and the sixth switch S6 are still turned off. Due to the turning off of the third switch S3 and the turning on of the seventh switch S7, the output voltage of the first operational amplifier unit 11 no longer acts on the gate of the first PMOS tube PM1, but acts on the gate of the thirteenth PMOS tube PM13. At this time, the voltage stored in the first capacitor C1 is equal to the output voltage of the first operational amplifier unit 11 in the offset voltage storage stage, and because the capacitor voltage will not change suddenly, the gate voltage acting on the first PMOS tube PM1 will not change, the current flowing through the first PMOS tube PM1 will not change, and thus the first offset compensation current will not change. If the first offset compensation current does not change, and the current flowing through the second PMOS tube PM2, the current flowing through the fourth PMOS tube PM4, the current flowing through the sixth NMOS tube NM6, and the current flowing through the seventh NMOS tube NM7 do not change, then according to the above formula (2) and formula (3), the current flowing through the third NMOS tube NM3 and the current flowing through the fourth NMOS tube NM4 do not change. If the current flowing through the third NMOS tube NM3 and the current flowing through the fourth NMOS tube NM4 do not change, then according to the above formula (7) and formula (8), the gate voltage of the third NMOS tube NM3 and the gate voltage of the fourth NMOS tube NM4 will not change. At this time, the gate voltage formula of the fourth NMOS tube NM4 is:

[0122] V G3 '=V os1 +V BUFA ; (9)

[0123] Among them, V BUFA Used to characterize the second input signal VBUFA.

[0124] Since formula (9) is equal to formula (8), the first input signal VISEN_IN is equal to the second input signal VBUFA. Therefore, the second input signal VBUFA connected to the first end of the fourth resistor R4 is equivalent to the first input signal VISEN_IN, so that the input signal of the first operational amplifier module 10 is equal to the output signal. That is, the first output current formula flowing through the fourth resistor R4 is:

[0125]

[0126] At the same time, in this stage, the second control signal AH and the fifth control signal BH are low level and high level respectively. Because the second control signal AH and the third control signal AL are inverted signals, and the fifth control signal BH and the sixth control signal BL are inverted signals, the seventeenth PMOS tube PM17 and the twentieth PMOS tube PM20 are both turned on, and the eighteenth PMOS tube PM18 and the nineteenth PMOS tube PM19 are both turned off. Then, the first output current flowing through the fourth resistor R4 flows to the ground, and the second output current flowing through the fifth resistor R5 flows to the first resistor R1, so as to generate the second output voltage and output it.

[0127] Then, the first operational amplifier module 10 enters the normal working stage, and the second operational amplifier module 20 enters the offset voltage storage stage. The second switch S2 and the third switch S3 are still turned off, and the first switch S1 and the seventh switch S7 are still turned on; the fourth switch S4 and the eighth switch S8 are turned off, and the fifth switch S5 and the sixth switch S6 are turned on. Since the circuit structure of the second operational amplifier module 20 is the same as that of the first operational amplifier module 10, the working principle of the second operational amplifier module 20 in the offset voltage storage stage is the same as that of the first operational amplifier module 10, which will not be repeated here.

[0128] Finally, the first operational amplifier module 10 is still in the normal working stage, and the second operational amplifier module 20 enters the offset voltage elimination stage. The second switch S2 and the third switch S3 are still turned off, the first switch S1 and the seventh switch S7 are still turned on; the fourth switch S4 and the eighth switch S8 are both turned on, and the fifth switch S5 and the sixth switch S6 are both turned off. Since the circuit structure of the second operational amplifier module 20 is the same as that of the first operational amplifier module 10, the working principle of the second operational amplifier module 20 in the offset voltage elimination stage is the same as that of the first operational amplifier module 10, which will not be repeated here.

[0129] At this point, the low offset voltage operational amplifier provided by the first embodiment has completed the first cycle of the working process, and then the above working process is continuously repeated to achieve that the input end of the operational amplifier has an extremely low offset voltage in other cycles except the first half of the first cycle.

[0130] In summary, the low offset voltage operational amplifier provided by the first embodiment of the present invention, on the one hand, stores and accurately offsets the offset voltage existing in the first operational amplifier unit and the offset voltage existing in the second operational amplifier unit through the first offset voltage elimination unit and the second offset voltage elimination unit, so as to eliminate the error caused by the offset voltage to the first output current unit and the second output current unit to generate the first output current and the second output current respectively. On the other hand, by controlling the on and off of the switch, the first operational amplifier module and the second operational amplifier module are controlled to be alternately in different working stages. If the first operational amplifier module is in the offset voltage storage stage and the offset voltage elimination stage in sequence, the second operational amplifier module is in the normal working stage; if the second operational amplifier module is in the offset voltage storage stage and the offset voltage elimination stage in sequence, the first operational amplifier module is in the normal working stage. In this way, it can be ensured that the input end of the operational amplifier module in the normal working state in each clock cycle has an extremely low offset voltage, thereby ensuring the continuity of the offset voltage elimination. At the same time, it can be seen from the above description that the technical solution provided by the present invention will not be limited by the frequency of the input signal in the process of offsetting the offset voltage, thereby increasing the application scope of the present invention.

[0131] A second embodiment of the present invention provides an electronic device, comprising the operational amplifier with low offset voltage provided by the first embodiment of the present invention.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An operational amplifier with low offset voltage, characterized in that: include: A first operational amplifier module, a second operational amplifier module, and a voltage output module; The first operational amplifier module includes a first operational amplifier unit and a first offset voltage elimination unit; the first operational amplifier unit has a non-inverting input terminal connected to a first input signal, and the first operational amplifier unit has an inverting input terminal connected to the first input signal through a second switch or connected to a second input signal through the first switch; The first terminal of the first operational amplifier unit is coupled to the output terminal of the first offset voltage elimination unit; The output end of the first operational amplifier unit is coupled to the input end of the first offset voltage elimination unit through a third switch and serves as the output end of the first operational amplifier module; The second operational amplifier module includes a second operational amplifier unit and a second offset voltage elimination unit; the in-phase input terminal of the second operational amplifier unit is connected to the first input signal, and the inverting input terminal of the second operational amplifier unit is connected to the first input signal through the fifth switch or the second input signal through the fourth switch; The first end of the second operational amplifier unit is coupled to the output end of the second offset voltage elimination unit; the output end of the second operational amplifier unit is coupled to the input end of the second offset voltage elimination unit through a sixth switch and serves as the output end of the second operational amplifier module; The voltage output module includes a first output current unit, a second output current unit, and a first resistor; the control end of the first output current unit is coupled to the output end of the first operational amplifier module through a seventh switch, the output end of the first output current unit is coupled to the ground end or the first end of the first resistor, and the first end and the second end of the first output current unit are respectively coupled to the second input signal and the power supply voltage; the first output current unit is used to generate and output a first output current according to the voltage output by the first operational amplifier module; the control end of the second output current unit is coupled to the output end of the second operational amplifier module through an eighth switch, the output end of the second output current unit is coupled to the ground end or the first end of the first resistor, and the first end and the second end of the first output current unit are respectively coupled to the second input signal and the power supply voltage; the second output current unit is used to generate and output a second output current according to the voltage output by the second operational amplifier module; the first end of the first resistor serves as the output end of the voltage output module, the second end of the first resistor is grounded, and the first resistor is used to generate and output a first output voltage or a second output voltage according to the first output current or the second output current; wherein the first output current is the same as the second output current; wherein: If the first operational amplifier module is in the offset voltage storage stage, the second switch and the third switch are both turned on, and the first switch and the seventh switch are both turned off; the first offset voltage elimination unit is used to store the voltage output by the first operational amplifier unit, and generate a first offset compensation current and output it to the first operational amplifier unit; if the second operational amplifier module is in the offset voltage storage stage, the fifth switch and the sixth switch are both turned on, and the fourth switch and the eighth switch are both turned off; the second offset voltage elimination unit is used to store the voltage output by the second operational amplifier unit, and generate a second offset compensation current and output it to the second operational amplifier unit; If the first operational amplifier module is in the offset voltage elimination stage, the second switch and the third switch are both turned off, and the first switch and the seventh switch are both turned on; the first offset voltage elimination unit is used to maintain the first offset compensation current according to the stored voltage so that the first input signal is equal to the second input signal; the output end of the first output current unit is coupled to the ground; if the second operational amplifier module is in the offset voltage elimination stage, the fifth switch and the sixth switch are both turned off, and the fourth switch and the eighth switch are both turned on; the second offset voltage elimination unit is used to maintain the second offset compensation current according to the stored voltage so that the first input signal is equal to the second input signal; the output end of the second output current unit is coupled to the ground; If the first operational amplifier module is in a normal working stage, the second switch and the third switch are still turned off, and the first switch and the seventh switch are still turned on; the output end of the first output current unit is coupled to the first end of the first resistor; if the second operational amplifier module is in a normal working stage, the fourth switch and the eighth switch are still turned on, and the fifth switch and the sixth switch are still turned off; the output end of the second output current unit is coupled to the first end of the first resistor; If the first operational amplifier module is in the offset voltage storage stage and the offset voltage elimination stage respectively, the second operational amplifier module is in the normal working stage; if the second operational amplifier module is in the offset voltage storage stage and the offset voltage elimination stage respectively, the first operational amplifier module is in the normal working stage.

2. The low offset voltage operational amplifier according to claim 1, characterized in that: The first offset voltage elimination unit includes a first capacitor, a first PMOS tube, a second resistor, a first NMOS tube, and a second NMOS tube; a first end of the first capacitor is coupled to the gate of the first PMOS tube and serves as an input end of the first offset voltage elimination unit, and a second end of the first capacitor and a second end of the second resistor are both coupled to a power supply voltage; a source of the first PMOS tube is coupled to a first end of the second resistor, and a drain of the first PMOS tube is coupled to a drain of the first NMOS tube; The gate of the first NMOS tube is coupled to its own drain and to the gate of the second NMOS tube. The drain of the second NMOS tube serves as the output end of the first offset voltage elimination unit. The source of the second NMOS tube and the source of the first NMOS tube are both grounded.

3. The low offset voltage operational amplifier according to claim 2, characterized in that: The first operational amplifier unit includes a first differential input unit, a first amplification path, a second amplification path, a first amplification output unit, and a first bias unit; The non-inverting input terminal of the first differential input unit is connected to the first input signal, and the inverting input terminal of the first differential input unit is connected to the first input signal through the second switch or the second input signal through the first switch; the first end of the first amplification path is coupled to the first end of the first differential input unit; the first end of the second amplification path is coupled to the second end of the first differential input unit; the second end of the second amplification path is respectively coupled to the first bias end of the first amplification output unit and the output end of the first offset voltage elimination unit; The third terminal of the first differential input unit is coupled to the input terminal of the first bias unit, and the bias terminal of the first bias unit and the second bias terminal of the first amplifying output unit are both connected to a bias voltage; The output end of the first amplifying output unit serves as the output end of the first operational amplifying unit.

4. The low offset voltage operational amplifier according to claim 3, characterized in that: The first differential input unit includes a third NMOS tube and a fourth NMOS tube; the gate of the third NMOS tube and the gate of the fourth NMOS tube serve as the in-phase input terminal and the inverting input terminal of the first differential input unit respectively, the drain of the third NMOS tube serves as the second terminal of the first differential input unit, and the drain of the fourth NMOS tube serves as the first terminal of the first differential input unit; the source of the third NMOS tube serves as the third terminal of the first differential input unit and is coupled to the source of the fourth NMOS tube.

5. The low offset voltage operational amplifier according to claim 3, characterized in that: The first bias unit includes a fifth NMOS tube; the gate of the fifth NMOS tube is connected to the bias voltage, the drain of the fifth NMOS tube serves as the input end of the first bias unit, and the source of the fifth NMOS tube is grounded.

6. The low offset voltage operational amplifier according to claim 3, characterized in that: The first amplification path includes a second PMOS tube, a third PMOS tube, and a sixth NMOS tube; the second amplification path includes a fourth PMOS tube, a fifth PMOS tube, and a seventh NMOS tube; The gate of the second PMOS tube is coupled to the gate of the fourth PMOS tube, the gate of the second PMOS tube is also coupled to the drain of the third PMOS tube, the drain of the second PMOS tube serves as the first end of the first amplification path and is coupled to the source of the third PMOS tube, the source of the second PMOS tube and the source of the fourth PMOS tube are both coupled to the power supply voltage; the gate of the third PMOS tube is coupled to the gate of the fifth PMOS tube, the drain of the third PMOS tube is coupled to the drain of the sixth NMOS tube; the gate of the sixth NMOS tube is connected to the bias voltage and coupled to the gate of the seventh NMOS tube, the source of the sixth NMOS tube and the source of the seventh NMOS tube are both grounded; The drain of the fourth PMOS tube serves as the first end of the second amplifying path and is coupled to the source of the fifth PMOS tube; the drain of the fifth PMOS tube serves as the second end of the second amplifying path and is coupled to the drain of the seventh NMOS tube.

7. The low offset voltage operational amplifier according to claim 3, characterized in that: The first amplifying output unit includes a sixth PMOS tube and an eighth NMOS tube; the gate of the sixth PMOS tube serves as a first bias terminal of the first amplifying output unit, the source of the sixth PMOS tube is coupled to the power supply voltage, the drain of the sixth PMOS tube serves as an output terminal of the first amplifying output unit and is coupled to the drain of the eighth NMOS tube; the gate of the eighth NMOS tube serves as a second bias terminal of the first amplifying output unit, and the source of the eighth NMOS tube is grounded.

8. The low offset voltage operational amplifier according to claim 1, wherein: The second offset voltage elimination unit includes a second capacitor, a seventh PMOS tube, a third resistor, a ninth NMOS tube, and a tenth NMOS tube; a first end of the second capacitor is coupled to the gate of the seventh PMOS tube and serves as an input end of the second offset voltage elimination unit, and a second end of the second capacitor and a second end of the third resistor are both coupled to a power supply voltage; a source of the seventh PMOS tube is coupled to a first end of the third resistor, and a drain of the seventh PMOS tube is coupled to a drain of the ninth NMOS tube; The gate of the ninth NMOS tube is coupled to its own drain and to the gate of the tenth NMOS tube. The drain of the tenth NMOS tube serves as the output end of the second offset voltage elimination unit. The source of the tenth NMOS tube and the source of the ninth NMOS tube are both grounded.

9. The low offset voltage operational amplifier according to claim 8, characterized in that: The second operational amplifier unit includes a second differential input unit, a third amplifier path, a fourth amplifier path, a second amplifier output unit, and a second bias unit; The non-inverting input terminal of the second differential input unit is connected to the first input signal, and the inverting input terminal of the second differential input unit is connected to the first input signal through the fifth switch or the second input signal through the fourth switch; the first end of the third amplification path is coupled to the second end of the second differential input unit; the first end of the fourth amplification path is coupled to the first end of the second differential input unit; the second end of the fourth amplification path is respectively coupled to the first bias end of the second amplification output unit and the output end of the second offset voltage elimination unit; The third terminal of the second differential input unit is coupled to the input terminal of the second bias unit, and the bias terminal of the second bias unit and the second bias terminal of the second amplifying output unit are both connected to a bias voltage; The output end of the second amplifying output unit serves as the output end of the second operational amplifying unit.

10. The low offset voltage operational amplifier according to claim 9, characterized in that: The second differential input unit includes an eleventh NMOS tube and a twelfth NMOS tube; the gate of the eleventh NMOS tube and the gate of the twelfth NMOS tube serve as the in-phase input terminal and the inverting input terminal of the second differential input unit respectively, the drain of the eleventh NMOS tube serves as the second terminal of the second differential input unit, and the drain of the twelfth NMOS tube serves as the first terminal of the second differential input unit; the source of the eleventh NMOS tube serves as the third terminal of the second differential input unit and is coupled to the source of the twelfth NMOS tube.

11. The low offset voltage operational amplifier according to claim 9, characterized in that: The second bias unit includes a fifteenth NMOS tube; the gate of the fifteenth NMOS tube is connected to the bias voltage, the drain of the fifteenth NMOS tube serves as the input end of the second bias unit, and the source of the fifteenth NMOS tube is grounded.

12. The low offset voltage operational amplifier according to claim 9, characterized in that: The third amplifying path includes an eighth PMOS tube, a ninth PMOS tube, and a thirteenth NMOS tube; the fourth amplifying path includes a tenth PMOS tube, an eleventh PMOS tube, and a fourteenth NMOS tube; The gate of the eighth PMOS tube is coupled to the gate of the tenth PMOS tube, and the gate of the eighth PMOS tube is also coupled to the drain of the ninth PMOS tube. The drain of the eighth PMOS tube serves as the third end of the third amplification path and is coupled to the source of the ninth PMOS tube. The source of the eighth PMOS tube and the source of the tenth PMOS tube are both coupled to the power supply voltage; the gate of the ninth PMOS tube is coupled to the gate of the eleventh PMOS tube, and the drain of the ninth PMOS tube is coupled to the drain of the thirteenth NMOS tube; the gate of the thirteenth NMOS tube is connected to the bias voltage and coupled to the gate of the fourteenth NMOS tube, and the source of the thirteenth NMOS tube and the source of the fourteenth NMOS tube are both grounded; The drain of the tenth PMOS tube serves as the first end of the fourth amplifying path and is coupled to the source of the eleventh PMOS tube; the drain of the eleventh PMOS tube serves as the second end of the fourth amplifying path and is coupled to the drain of the fourteenth NMOS tube.

13. The low offset voltage operational amplifier according to claim 9, characterized in that: The second amplifying and outputting unit comprises a twelfth PMOS tube and a sixteenth NMOS tube; the gate of the twelfth PMOS tube serves as a first bias terminal of the second amplifying and outputting unit, the source of the twelfth PMOS tube is coupled to the power supply voltage, and the drain of the twelfth PMOS tube serves as an output terminal of the second amplifying and outputting unit and is coupled to the drain of the sixteenth NMOS tube; The gate of the sixteenth NMOS tube serves as the second bias terminal of the second amplifying output unit, and the source of the sixteenth NMOS tube is grounded.

14. The low offset voltage operational amplifier according to claim 2, characterized in that: The first output current unit includes a thirteenth PMOS tube and a fourth resistor; the gate of the thirteenth PMOS tube serves as the control end of the first output current unit, the source of the thirteenth PMOS tube is coupled to the first end of the fourth resistor, and the drain of the thirteenth PMOS tube serves as the output end of the first output current unit; the first end and the second end of the fourth resistor are respectively connected to the second input signal and the power supply voltage.

15. The low offset voltage operational amplifier according to claim 14, characterized in that: The second output current unit includes a fourteenth PMOS tube and a fifth resistor; the gate of the fourteenth PMOS tube serves as the input end of the second output current unit, the source of the fourteenth PMOS tube is coupled to the first end of the fifth resistor, and the drain of the fourteenth PMOS tube serves as the output end of the second output current unit; the first end and the second end of the fifth resistor are respectively connected to the second input signal and the power supply voltage.

16. The low offset voltage operational amplifier according to claim 15, characterized in that: It also includes a switch array; the switch array includes a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, and a twentieth PMOS tube; The gate of the fifteenth PMOS tube is connected to the first control signal, the source of the fifteenth PMOS tube is coupled to the output end of the first output current unit, and the drain of the fifteenth PMOS tube is respectively coupled to the source of the seventeenth PMOS tube and the source of the eighteenth PMOS tube; The drain of the seventeenth PMOS tube is grounded, the drain of the eighteenth PMOS tube is coupled to the first end of the first resistor, and the gate of the seventeenth PMOS tube and the gate of the eighteenth PMOS tube are respectively connected to the second control signal and the third control signal; The gate of the sixteenth PMOS tube is connected to the fourth control signal, the source of the sixteenth PMOS tube is coupled to the output end of the second output current unit, and the drain of the sixteenth PMOS tube is respectively coupled to the source of the nineteenth PMOS tube and the source of the twentieth PMOS tube; the drain of the nineteenth PMOS tube is grounded, the drain of the twentieth PMOS tube is coupled to the first end of the first resistor, and the gate of the nineteenth PMOS tube and the gate of the twentieth PMOS tube are respectively connected to the fifth control signal and the sixth control signal; Wherein, if the first operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the second operational amplifier module is in the normal working stage, the first control signal is a high level or a low level, the fourth control signal is a low level, the second control signal is a low level, the third control signal is a high level, the fifth control signal is a high level, and the sixth control signal is a low level; If the second operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the first operational amplifier module is in the normal working stage, the fourth control signal is a high level or a low level, the first control signal is a low level, the fifth control signal is a low level, the sixth control signal is a high level, the second control signal is a high level, and the third control signal is a low level.

17. The low offset voltage operational amplifier according to claim 16, characterized in that: The second control signal and the fifth control signal are two-phase non-overlapping signals; the second control signal is an inverted signal of the third control signal; and the fifth control signal is an inverted signal of the sixth control signal.

18. The low offset voltage operational amplifier according to claim 17, characterized in that: It also includes a sixth resistor; the sixth resistor is coupled between the drain terminal and the ground terminal of the seventeenth PMOS tube; wherein the resistance value of the sixth resistor is equal to the resistance value of the first resistor.

19. An electronic device, characterized in that: An operational amplifier with low offset voltage comprising the operational amplifier according to any one of claims 1 to 18.

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