Digital duty cycle calibration

Abstract

The invention relates to digital duty cycle calibration. Systems and methods for calibrating a clock signal are described. An apparatus may include a processor, a circuit, and a system duty cycle control (DCC) circuit. The circuit may perform a first phase shift on a clock signal to generate a first phase shifted signal. The circuit may perform a second phase shift on the clock signal to generate a second phase shifted signal. The circuit may perform fixed DCC on the first phase shifted signal to generate a first voltage signal. The circuit may scan the second phase-shifted signal over a duty cycle range to generate a second voltage signal. The circuit may sample the output clock signal at a time when the first voltage signal and the second voltage signal overlap. The processor may generate a digital code based on the output clock signal. The system DCC circuit may use the digital code to calibrate the clock signal.

Description

Background Art

[0001] The present disclosure generally relates to systems and methods for duty cycle calibration. In particular, a digital duty cycle calibration system using one or more digital duty cycle monitors (DCMs) is used to calibrate the duty cycle of a clock.

[0002] Data processing applications may rely on a clock signal for synchronization. The clock period of the clock signal may be maintained at a target duty cycle, such as 50%. The clock period may vary and deviate from the target duty cycle due to various mismatches, such as process, voltage, and temperature (PVT) mismatches. The clock signal may be calibrated to maintain the clock period at the target duty cycle. In one aspect, a duty cycle calibration system may use feedback of the clock signal to determine a calibration factor that may calibrate the clock signal and maintain the clock signal at the target duty cycle. Summary of the invention

[0003] In one embodiment, a semiconductor device that can implement a digital duty cycle calibration system is generally described. The semiconductor device may include a processor. The semiconductor device may also include a system duty cycle control (DCC) circuit configured to generate a clock signal. The semiconductor device may also include a circuit configured to perform a first phase shift on the clock signal to generate a first phase shift signal. The circuit may also perform a second phase shift on the clock signal to generate a second phase shift signal. The circuit may also perform a fixed DCC on the first phase shift signal to generate a first voltage signal. The circuit may also scan the second phase shift signal within a duty cycle range to generate a second voltage signal. The circuit may also sample the output clock signal at a time when the first voltage signal and the second voltage signal overlap. The processor may be configured to generate a digital code based on the output clock signal. The system DCC circuit may also be configured to calibrate the clock signal using the digital code.

[0004] In one embodiment, a semiconductor device that can implement a digital duty cycle calibration system is generally described. The semiconductor device may include a first phase shifter configured to perform a first phase shift on a clock signal to generate a first phase shifted signal. The semiconductor device may also include a second phase shifter configured to perform a second phase shift on the clock signal to generate a second phase shifted signal. The semiconductor device may also include a first duty cycle control (DCC) circuit configured to perform a fixed DCC on the first phase shifted signal to generate a first voltage signal. The semiconductor device may also include a second DCC circuit configured to scan the second phase shifted signal within a duty cycle range to generate a second voltage signal. The semiconductor device may also include a phase detector configured to sample an output clock signal at a time when the first voltage signal and the second voltage signal overlap. The calibration of the clock signal may be based on the output clock signal.

[0005] In one embodiment, a method for calibrating a clock signal is generally described. The method may include performing a first phase shift on the clock signal to generate a first phase shifted signal. The method may also include performing a second phase shift on the clock signal to generate a second phase shifted signal. The method may also include performing a fixed DCC on the first phase shifted signal to generate a first voltage signal. The method may also include scanning the second phase shifted signal within a duty cycle range to generate a second voltage signal. The method may also include sampling an output clock signal at a time when the first voltage signal and the second voltage signal overlap. The calibration of the clock signal may be based on the output clock signal.

[0006] Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings.In the drawings, like reference numerals indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating an example system in which digital duty cycle calibration may be implemented in one embodiment;

[0008] Figure 2 is a diagram illustrating a plurality of signals in a first portion of an example implementation of digital duty cycle calibration in one embodiment;

[0009] Figure 3 is a diagram showing an embodiment of Figure 2 a graph of multiple signals in a second portion of an example implementation of digital duty cycle calibration as shown;

[0010] Figure 4 is a diagram illustrating another example system in which digital duty cycle calibration may be implemented in one embodiment;

[0011] Figure 5A is a diagram showing waveforms of an example implementation of digital duty cycle calibration in one embodiment;

[0012] Figure 5B is a diagram showing waveforms of an example implementation of digital duty cycle calibration in one embodiment;

[0013] Figure 5C is a diagram showing waveforms of an example implementation of digital duty cycle calibration in one embodiment;

[0014] Figure 6 is a diagram showing waveforms of another implementation of digital duty cycle calibration in one embodiment;

[0015] Fig. 7A is a diagram showing waveforms of an example implementation of digital duty cycle calibration in one embodiment;

[0016] Figure 7B is a diagram showing an embodiment of Fig. 7A a diagram of waveforms of the example implementation shown;

[0017] Fig. 8A is a diagram showing waveforms of another example implementation of digital duty cycle calibration in one embodiment;

[0018] Figure 8B is a diagram showing an embodiment of Fig. 8A A diagram of waveforms of the illustrated example implementation; and

[0019] Fig. 9 is a flow chart illustrating a process for implementing digital duty cycle calibration in one embodiment. DETAILED DESCRIPTION

[0020] In the following description, many specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, known structures or processing steps are not described in detail.

[0021] In one aspect, a duty cycle calibration system can be implemented by an analog circuit system for continuously monitoring the duty cycle of a clock signal in a circuit. The analog duty cycle calibration system can perform feedback loop control to provide a correction factor or direction to the clock signal until a target duty cycle is reached. However, the analog duty cycle calibration system may require a startup time to stabilize to a reasonably accurate state before calibration begins. Furthermore, in an analog duty cycle calibration system, the calibration accuracy may depend on the accuracy of the analog circuit system that has its own performance variations due to PVT mismatch.

[0022] On the one hand, a digital duty cycle calibration system using an open loop can use its own clock to detect one of the clock edges and perform interpolation using logic gates, but it requires additional transition edges, and not all applications can generate additional transition edges. Interpolation also causes edge hysteresis and is prone to jitter, coupling, and may affect duty cycle accuracy. On the other hand, a digital duty cycle calibration system using an incoming clock pulse generator and a half-cycle delay line can create a pulse with a half-cycle, but the need to create a pulse can be challenging, especially when the pulse width of a high-speed clock application becomes narrow (for example, it is difficult to create half the width of a narrow pulse). On the other hand, a digital duty cycle calibration system that uses feedback and a state machine to create a clock can be relatively complex and can have significant power consumption.

[0023] Figure 1is a diagram illustrating an example system that may implement adaptive zero voltage switching for near field communication in one embodiment. System 100 may be a duty cycle calibration system that includes at least a duty cycle monitor (DCM) 102, a processor 104, and a system duty cycle control (DCC) circuit 106. Processor 104 may be, for example, a processor in a microcontroller. Processor 104 may be configured to run various applications, such as a state machine. System DCC circuit 106 may be configured to generate a clock signal labeled as system clock 108. System DCC circuit 106 may receive a DCC code 130 from processor 104 and generate and calibrate system clock 108 using DCC code 130. DCC code 130 may be a digital code that indicates an amount of calibration to be performed on system clock 108. In Figure 1 In the illustrated embodiment, the system clock 108 may be a single-ended signal.

[0024] The DCM 102 may be a digital circuit implemented by one or more semiconductor devices, such as an integrated circuit (IC), and may include digital circuit components. The DCM 102 may include at least a buffer 110, an inverter 112, a multiplexer (MUX) 114, a phase shifter 116, a phase shifter 118, a DCC circuit 120, a DCC line 122, and a phase detector implemented by a D flip-flop (DFF) 124. The DCM 102 may receive a system clock 108 from the system DCC circuit 106. The system clock 108 may be distributed to the buffer 110 and the inverter 112. The buffer 110 may pass the system clock 108 to a first input pin of the MUX 114. The inverter 112 may invert the system clock 108 and provide the inverted system clock 108 to a second input pin of the MUX 114. The processor 104 may provide an enable invert (en_inv) signal. When the en_inv signal is low, the MUX 114 may select the system clock 108 provided from the buffer 110 and output the selected system clock 108 as the voltage signal Vi. When the en_inv signal is high, the MUX 114 may select the inverted system clock 108 provided from the inverter 112 and output the selected inverted system clock 108 as the voltage signal Vi.

[0025] The voltage signal Vi may be distributed to phase shifters 116 and 118. In one embodiment, the phase shifter 116 may be a 0-degree phase shifter. The phase shifter 116 may receive the voltage signal Vi and perform a 0-degree phase shift on the voltage signal Vi to generate the voltage signal V0. In one embodiment, the phase shifter 118 may be a 180-degree phase shifter. The phase shifter 118 may receive the voltage signal Vi and perform a 180-degree phase shift on the voltage signal Vi to generate the voltage signal V180. The voltage signal V0 may be provided to the DCC circuit 120, and the voltage signal V180 may be provided to the DCC circuit 122. In one embodiment, the voltage signal V0, the voltage signal Vi, and the system clock 108 input to the DCM 102 may be the same, such as aligning their rising and falling edges.

[0026] The DCC circuit 120 may perform duty cycle control on the voltage signal V0 to generate a voltage signal labeled Vc. In one embodiment, the processor 104 may send a control signal 121 to the DCC circuit 120. The control signal 121 may include a DCC code for calibrating the duty cycle of the voltage signal Vc. In one embodiment, the control signal 121 may be a fixed DCC code and may be fixed to an intermediate code (e.g., the middle of the control range of the DCC circuit 120). When the control signal 121 is fixed at the intermediate code of the DCC 120, the duty cycle of the output voltage (e.g., the voltage signal Vc) may follow the duty cycle of the input voltage (e.g., the voltage signal V0) or may be the same as it.

[0027] The DCC circuit 122 may perform duty cycle control on the voltage signal V180 to generate a voltage signal labeled Vs. In one embodiment, the processor 104 may send a control signal labeled as a scan signal 128 to the DCC circuit 122. The scan signal 128 may include a plurality of DCC codes for performing a scan of duty cycle calibration within a duty cycle range. For example, the scan of duty cycle calibration may be a plurality of duty cycle calibrations performed by the DCC circuit 122 for calibrating the voltage signal V180 at a plurality of different duty cycles within a duty cycle range. In one embodiment, the duty cycle range may be predefined and may include a fixed DCC code for the DCC circuit 120.

[0028] The voltage signal Vc may be provided to the D pin of the DFF 124, and the voltage signal Vs may be provided to the clock (clk) pin of the DFF 124. When Vs is low, the output Q of the DFF 124 may remain unchanged. When Vc is low and Vs is high, the output Q of the DFF 124 may be low. When Vc is high and Vs is high, the output Q of the DFF 124 may be high. Therefore, when the voltage signals Vc and Vs overlap, or when they are both high, the output Q may output the sampling clock 126. The sampling clock 126 may indicate the time when the voltage signals Vc and Vs overlap.

[0029] To calibrate the system clock 108, the system 100 may perform a two-step calibration process. In a first step, the MUX 114 may select the system clock 108 provided by the buffer 110 (e.g., en_inv is disabled), and the voltage signal Vi may pass through the components in the DCM 102. In the first step, the DFF 124 may output a sampling clock 126 that samples at a first time, at which the voltage signals Vc and Vs overlap under the setting of the system clock 108 selected by the MUX 114. Then in a second step, the MUX 114 may select the inverted system clock 108 provided by the inverter 112 (e.g., en_inv is enabled), and the voltage signal Vi may pass through the components in the DCM 102. In the second step, the DFF 124 may output a sampling clock 126 that samples at a second time, at which the voltage signals Vc and Vs overlap under the setting of the inversion of the system clock 108 selected by the MUX 114.

[0030] The processor 104 may receive a first time in a first step, a second time in a second step, and determine a DCC code 130 based on the first time and the second time. In one embodiment, the processor 104 may determine a difference between the first time and the second time, and determine the DCC code 130 based on the determined difference. The system DCC circuit 106 may use the DCC code 130 to adjust or calibrate the system clock 108, and the calibrated version of the system clock 108 may be provided to the DCM 102 for another calibration. The two-step calibration process performed by the system 100 may be a closed-loop control, and the system clock 108 may be continuously monitored and calibrated. The system 100 may be implemented without using analog circuitry that may require initial startup or stabilization time, and the digital circuitry in the DCM 102 may reduce overall calibration time and power consumption.

[0031] Figure 2 is a diagram illustrating multiple signals in a first portion of an example implementation of digital duty cycle calibration in one embodiment. Figure 2 For a description, refer to Figure 1 Components shown. Figure 2 The system 100 is shown in Figure 1 )The waveforms of various signals in the first part or first step of a calibration process that can be performed. Figure 2 The example waveform in corresponds to the first step of the calibration process described herein, where MUX 114 selects the system clock 108 buffered by buffer 110. Thus, Figure 2 The voltage signal Vi shown may be the same as the system clock 108 .

[0032] Vi can be input to the phase shifter 116, and the phase shifter 116 can perform a 0 degree phase shift on Vi, thereby obtaining a voltage signal V0 that is the same as Vi (and the same as the system clock 108). Figure 2 In the example shown, the duty cycle of the voltage signal Vi is less than 50% because the amount of time that Vi is ON or HIGH is less than half of the clock period of the system clock 108, or less than T / 2, where T is the clock period. Vi may also be input to the phase shifter 118, and the phase shifter 118 may perform a 180 degree phase shift on Vi, resulting in a voltage signal V180 that may be T / 2 out of phase with V0.

[0033] The DCC 120 may receive the voltage signal V0 and perform duty cycle control on the voltage signal V0 to generate the voltage signal Vc. In one embodiment, the control signal 121 of the DCC circuit 120 may be fixed to an intermediate code so that the duty cycle of the voltage signal Vc may follow or be equal to the duty cycle of the voltage signal V0. In addition, the DCC circuit 120 may delay the voltage signal V0 by a predefined amount to generate Vc, so that Vc is out of phase with V0 by X times, such as Figure 2 shown.

[0034] The DCC 122 may receive the voltage signal V180 and perform duty cycle control on the voltage signal V180 to generate a voltage signal Vs. In one embodiment, the DCC circuit 122 may delay the voltage signal V180 by a predefined amount to generate Vs, such that Vs is out of phase with V180 by Y times, as shown in FIG. Figure 2 As shown. The delay factor Y may be greater than the delay factor X. In one embodiment, the scan signal 128 provided to the DCC circuit 122 may include a plurality of control signals. Each of the plurality of control signals may be used to control the DCC circuit 122 to generate a voltage signal Vs having a particular duty cycle. The duty cycle range 202 may be indicated in the scan signal 128. The DCC circuit 122 may perform the scan by calibrating Vs at each duty cycle in the range 202. Calibrating Vs at different duty cycles may include changing the duty cycle of Vs by changing the timing of the falling edge of Vs, from the lowest duty cycle in the range 202 to the highest duty cycle in the range 202.

[0035] The voltage signal Vc and the voltage signal Vs scanned with different duty cycles may be fed into the DFF 124. Figure 2 As shown, when Vs is low, the sampling clock 126 sampled by the DFF 124 may remain unchanged regardless of how Vc changes. When Vc is low and Vs is high, the sampling clock 126 may be low. When Vc is high and Vs is high, the rising edge of the sampling clock 126 may be triggered. The processor 104 may detect the rising edge of the sampling clock 126 and record the detection or store the time when the rising edge is triggered as Figure 2 The processor 104 may record or store the code A in a memory device that may be part of the processor 104. After receiving and storing the code A, the system 100 may proceed to the second step of the calibration process, such as Figure 3 Shown and described.

[0036] Figure 3 is a diagram showing an embodiment of Figure 2 A graph of multiple signals in a second portion of an example implementation of digital duty cycle calibration is shown. Figure 3 For a description, see Figure 1 and Figure 2 Components shown. Figure 3 The system 100 is shown in Figure 1 )The waveforms of various signals in the second part or second step of the calibration process that can be performed. Figure 3 The example waveform in corresponds to the second step of the calibration process described herein, where MUX 114 selects the inversion of the system clock 108 provided by inverter 112. Thus, Figure 3 The voltage signal Vi shown may be the inverse of the system clock 108 .

[0037] Vi can be input to the phase shifter 116, and the phase shifter 116 can perform a 0 degree phase shift on Vi, thereby obtaining a voltage signal V0 that is the same as Vi (and the same as the inverse of the system clock 108). Figure 3 In the example shown, the duty cycle of the voltage signal Vi is greater than 50% because the amount of time that Vi is ON or HIGH is greater than T / 2. Note that Figure 2 The duty cycle of Vi in Figure 3 The sum of the duty cycles of Vi in may be equal to T. Vi may also be input to the phase shifter 118, and the phase shifter 118 may perform a 180-degree phase shift on Vi, thereby obtaining a voltage signal V180 that may be out of phase with V0 by T / 2.

[0038] The DCC 120 may receive the voltage signal V0 and perform duty cycle control on the voltage signal V0 to generate the voltage signal Vc. In one embodiment, the control signal 121 of the DCC circuit 120 may be fixed to an intermediate code so that the duty cycle of the voltage signal Vc may follow or be equal to the duty cycle of the voltage signal V0. In addition, the DCC circuit 120 may delay the voltage signal V0 by a predefined amount to generate Vc, so that Vc is out of phase with V0 by X times, such as Figure 3 shown. Figure 3 The factor X shown can be compared with Figure 2 The factor X shown is the same.

[0039] The DCC 122 may receive the voltage signal V180 and perform duty cycle control on the voltage signal V180 to generate a voltage signal Vs. In one embodiment, the DCC circuit 122 may delay the voltage signal V180 by a predefined amount to generate Vs, such that Vs is out of phase with V180 by Z times, as shown in FIG. Figure 3 As shown. The delay factor Z may be less than the delay factor X. In one embodiment, the scan signal 128 provided to the DCC circuit 122 may include a plurality of control signals. Each of the plurality of control signals may be used to control the DCC circuit 122 to generate a voltage signal Vs having a specific duty cycle. The duty cycle range 302 may be indicated in the scan signal 128. The DCC circuit 122 may perform the scan by calibrating Vs at each duty cycle in the range 302. Calibrating Vs at different duty cycles may include changing the duty cycle of Vs by changing the timing of the falling edge of Vs, from the lowest duty cycle in the range 302 to the highest duty cycle in the range 302.

[0040] The voltage signal Vc and the voltage signal Vs scanned with different duty cycles may be fed into the DFF 124. Figure 2 As shown, when Vs is low, the sampling clock 126 sampled by the DFF 124 may remain unchanged regardless of how Vc changes. When Vc is low and Vs is high, the sampling clock 126 may be low. When Vc is high and Vs is high, the rising edge of the sampling clock 126 may be triggered. The processor 104 may detect the rising edge of the sampling clock 126 and record the detection or store the time when the rising edge is triggered as Figure 3 The processor 104 may record or store code B in a memory device that may be part of the processor 104. After receiving and storing code B, the processor 104 may determine the DCC code 130 based on code A and code B.

[0041] In one embodiment, the DCC code 130 may be equal to half of the difference between code A and code B, or (code A-code B) / 2. The DCC code 130 may be 0, a positive value (e.g., greater than 0), or a negative value (less than 0). Whether the DCC code 130 is 0, positive, or negative may determine the amount of adjustment made to the system clock 108 by the system DCC circuit 106. For example, if the system clock 108 has a 50% duty cycle, code A and code B will be detected at the middle code (e.g., the middle) of the range 202, 302, respectively, resulting in code A-code B=0. The DCC code 130 may be 0, and the system DCC circuit 106 may maintain the system clock 108.

[0042] If the duty cycle of the system clock 108 is less than 50%, the code A in the first step may be increased from (e.g., later than) the middle code of the range 202. In addition, the voltage signal Vs may start scanning earlier than the system clock having a larger duty cycle but less than 50%. In other words, when the duty cycle less than 50% deviates from 50%, the start time of scanning may be earlier than or farther from the middle code of the range 202. In addition, if the duty cycle of the system clock 108 is less than 50%, the code B in the second step may be decreased from (earlier than) the middle code of the range 302. Therefore, when the duty cycle of the system clock 108 is less than 50%, the difference of code A-code B may be a positive number (e.g., greater than 0), and indicates that the duty cycle of the system clock 108 needs to be increased, and the DCC code 130 may include a value for increasing the duty cycle of the system clock 108.

[0043] If the duty cycle of the system clock 108 is greater than 50%, the code A in the first step may be decreased from (e.g., earlier than) the middle code of the range 202, and the code B in the second step may be increased from (later than) the middle code of the range 302. Therefore, when the duty cycle of the system clock 108 is greater than 50%, the difference of code A-code B may be a negative number (e.g., less than 0), and indicates that the duty cycle of the system clock 108 needs to be decreased, and the DCC code 130 may include a value for decreasing the duty cycle of the system clock 108.

[0044] In one aspect, the two-step calibration process described herein can accommodate duty cycle distortion from the phase shifters 116, 118. For example, during determination of the DCC code 130, duty cycle distortion from the phase shifters 116, 118 can be equally added to Code A and Code B and ultimately canceled by the processor 104.

[0045] Figure 4 is a diagram illustrating another example system that may implement digital duty cycle calibration in one embodiment. Figure 4 For a description, see Figures 1 to 3In one aspect, if random jitter exists in the system clock 108 and if metastability exists in the DFF 124, the sampling clock 126b may be unstable when the falling edge of the voltage signal Vs is nearly aligned (e.g., relatively close) with the rising edge of Vc. The instability of the sampling clock 126 may degrade the two-step calibration process described herein (e.g., by Figure 1 The accuracy of the calibration performed by the system 100 in the sampling clock 126 may be affected by the calibration performed by the system 100 in the sampling clock 126. For example, code A determined in the first step and code B determined in the second step may not be accurate due to metastability. To mitigate the metastability problem in the sampling clock 126, a multi-sampling synchronizer circuit 402 may be connected between the output of the DFF 124 and the output of the processor 104.

[0046] The multi-sampling synchronizer circuit 402 may be configured to sample the sampling clock 126 using a local clock signal used by the processor 104, wherein the local clock signal has the same frequency as the voltage signal Vs. Since the output of the DFF 124 is sampled using the local clock, the sampling clock 126 may be synchronized. The multi-sampling synchronizer circuit 402 may output a synchronized version of the sampling clock 126 (labeled as synchronized clock 404) and an indicator 406. The indicator 406 may be a signal indicating whether the sampling clock 126 has changed when the multi-sampling synchronizer circuit 402 is enabled by an enable signal 408 from the processor 104. In one embodiment, the time at which the multi-sampling synchronizer circuit 402 is enabled may be programmable to balance the robustness of the synchronized version of the sampling clock 126, the sampling indicator, and the calibration time.

[0047] Figure 5A , Figure 5B and Figure 5C is a graph showing waveforms of an example implementation of digital duty cycle calibration in one embodiment. Figure 5A , Figure 5B and Figure 5C For a description, see Figures 1 to 4 In one embodiment, the processor 104 can generate the scanning signal 128 by identifying the DCC code defining the scanning range (e.g., ranges 202, 302) in the first and second steps of the two-step calibration process described herein. In one embodiment, the scanning range can depend on the synchronization clock 404 and the indicator 406.

[0048] In one embodiment, the processor 104 may determine a lower limit DCC code and an upper limit DCC code. The lower limit DCC code may be the last or maximum duty cycle code that satisfies the conditions that the synchronization clock 404 is 0 or low and the indicator 406 is 0 or high. The upper limit DCC code may be the first or minimum duty cycle code that satisfies the conditions that the synchronization clock 404 is 1 or high and the indicator 406 is 0 or low. In one embodiment, the indicator 406 being 0 may indicate that the sampling clock 126 is stably maintaining one state, rather than changing between a low state and a high state.

[0049] In one embodiment, the processor 104 may start scanning from any starting DCC code (such as a midamble), and the processor may perform scanning in different ways under different conditions, which may be based on the synchronization clock 404 and the indicator 406 at the starting DCC code. For example, if the synchronization clock 404 is 0 and the indicator 406 is 0 at the starting DCC code of the starting duty cycle, the processor 104 may continue to perform scanning by incrementing the DCC code of the DCC circuit 122 until an upper limit DCC code that satisfies the condition that the synchronization clock 404 is 1 and the indicator 406 is 0 is identified. In response to a specific duty cycle satisfying the condition that the synchronization clock 404 is 1 and the indicator 406 is 0, the DCC code of the specific duty cycle may be set as the ending duty cycle of the scanning, and scanning starting from the starting duty cycle code and ending at the specific duty cycle may be performed.

[0050] For example, if the synchronization clock 404 is 1 and the indicator 406 is 0 at the start DCC code, the processor 104 may continue to perform scanning by decrementing the DCC code of the DCC circuit 122 until the lower limit satisfies the condition that the synchronization clock 404 is 0 and the indicator 406 is 0. In response to the specific duty cycle satisfying the condition that the synchronization clock 404 is 0 and the indicator 406 is 0, the DCC code of the specific duty cycle may be set as the end duty cycle of the scan, and scanning starting from the start duty cycle code and ending at the specific duty cycle may be performed.

[0051] For example, if the indicator 406 is 1 at the start DCC code, the processor 104 may continue to perform scanning by incrementing the DCC code of the DCC circuit 122 regardless of the state of the synchronization clock 404 until an upper limit DCC code is identified that satisfies the condition that the synchronization clock 404 is 1 and the indicator 406 is 0. Then, the processor 104 may decrement the DCC code of the DCC circuit 122 until a lower limit DCC code is identified that satisfies the condition that the synchronization clock 404 is 0 and the indicator 406 is 0. In response to a specific duty cycle satisfying the condition that the synchronization clock 404 is 1 and the indicator 406 is 0, the DCC code of the specific duty cycle may be set as the end duty cycle of the scan, and scanning starting from the start duty cycle code and ending at the specific duty cycle may be performed.

[0052] In the example starting from Figure 5A the starting DCC code for the scan of the DCC circuit 122 can be '1'. At time 502, the multi-sampling synchronizer circuit 402 can be enabled by the processor 104. In response to the multi-sampling synchronizer circuit 402 being enabled, both the synchronization clock 404 and the indicator 406 are held at 0. Thus, the processor 104 can identify the starting DCC code of '1' as the lower limit DCC code. The processor 104 can disable the multi-sampling synchronizer circuit 402 at time 504 to change the DCC code to the next DCC code '2'.

[0053] This example can continue in Figure 5B In Figure 5B the scan moves to the next DCC code '2'. At time 512, the multi-sampling synchronizer circuit 402 can be enabled by the processor 104. At time 514, the rising edge of the synchronization clock 404 can be triggered, and the indicator 406 can be held at 0 to indicate that the DCC code '2' can potentially be the upper limit DCC code. To determine whether the DCC code '2' is really the upper limit DCC code, the processor 104 can scan additional codes to check whether the synchronization clock 404 remains at 1 and whether the indicator 406 remains at 0. At time 516, both the synchronization clock 404 and the indicator 406 become 0. Since the DCC code '1' has been identified by the processor 104 as the lower limit DCC code, the processor 104 can continue the scan even though both the synchronization clock 404 and the indicator 406 are 0. At time 518, the rising edges of the synchronization clock 404 and the indicator 406 can be triggered and held at 1 until time 520, at which time the processor 104 disables the multi-sampling synchronizer 402 to change the DCC code to the next DCC code '3'.

[0054] This example can continue in Figure 5C In Figure 5C the scan moves to the next DCC code '3'. At time 522, the multi-sampling synchronizer circuit 402 can be enabled by the processor 104. At time 524, the rising edge of the synchronization clock 404 can be triggered, and the indicator 406 can be held at 0. In response to the synchronization clock 404 remaining at 1 and the indicator 406 remaining at 0, the processor 104 can identify the DCC code '3' as the upper limit DCC code.

[0055] In one embodiment, in the first step of the two-step calibration process described herein, the processor 104 may determine code A by dividing the sum of the lower limit DCC code and the upper limit DCC code determined in the scan in the first step by 2. In other words, code A in the first step = (lower limit + upper limit) / 2. In addition, in the second step of the two-step calibration process described herein, the processor 104 may determine code B by dividing the sum of the lower limit DCC code and the upper limit DCC code determined in the scan in the second step by 2. In other words, code B in the second step = (lower limit + upper limit) / 2. Using the lower limit DCC code and the upper limit DCC code from the first and second steps to determine code A and code B may solve the metastable problem of the DFF 124 and improve the accuracy of the system 100.

[0056] Figure 6 is a graph showing waveforms of another implementation of digital duty cycle calibration in one embodiment. Figure 6 For a description, see Figures 1 to 5C Components shown. In one embodiment, system 100 can be configured to perform the system clock calibration described herein on a differential clock signal. In one embodiment, system clock 108 can be a differential clock signal including a positive signal CLK+ and a negative signal CLK-.

[0057] exist Figure 6 In the illustrated embodiment, the negative signal CLK- can be distributed to the buffer 110 and the inverter 112 in the first circuit or segment 602. The MUX 114 in the segment 602 can output the negative signal CLK- or the inversion of CLK- as the voltage signal Vi_c. The voltage signal Vi_c can be fed into the phase shifter 116. The phase shifter 116 can generate a voltage signal V0 based on the voltage signal Vi_c. The voltage signal V0 can be fed into the DCC circuit 120. The DCC circuit 120 can perform duty cycle control on the voltage signal V0 using the control signal 121 to generate the voltage signal Vc.

[0058] The positive signal CLK+ may be distributed to the buffer 110 and the inverter 112 in the second circuit or segment 604. The MUX 114 in the segment 604 may output the positive signal CLK+ or the inversion of CLK+ as the voltage signal Vi_c. The voltage signal Vi_t may be fed into the phase shifter 118. The phase shifter 118 may generate a voltage signal V180 based on the voltage signal Vi_t. The voltage signal V180 may be fed into the DCC circuit 122, and the DCC circuit 122 may perform a calibration scan on the voltage signal V180 using the scan signal 128 to generate the voltage signal Vs.

[0059] The voltage signals Vc and Vs may be fed into the DFF 124. The DFF 124 may output a sampling clock 126 from the Q-not output. Figure 6 Different clock implementations in Figure 1 and Figure 4 In comparison to the single-ended clock signal embodiment shown, the polarity of the sampling clock 126 can be reversed because the detection of Code A and Code B is performed by locating the falling edge of Vc instead of the rising edge.

[0060] Fig. 7A and Figure 7B is a graph showing waveforms of an example implementation of digital duty cycle calibration in one embodiment. Fig. 7A and Figure 7B For a description, see Figures 1 to 6 Components shown. Fig. 7A and Figure 7B The multiple waveforms shown are Figure 6 The result of an implementation of the system 100 is shown, where the negative signal CLK- has a duty cycle distortion (DCD), such as having a duty cycle of [100*(T / 2-e) / T]%, and the positive signal CLK+ has an ideal 50% duty cycle (e.g., the differential duty cycle between CLK- and CLK+ is greater than 50%).

[0061] Fig. 7A For the first step of the two-step calibration process described herein, the MUX 114 in segments 602, 604 selects the output of the buffer 110. Fig. 7A In the embodiment, the voltage signal Vi_c may be the same as the negative signal CLK-, and the voltage signal Vi_t may be the same as the positive signal CLK+. The falling edges of the voltage signals Vc and Vs are aligned, so the processor 104 can record the code A=d (intermediate code).

[0062] Figure 7B For the second step of the two-step calibration process described herein, the MUX 114 in segments 602, 604 selects the output of the inverter 112. Figure 7B In the embodiment, the voltage signal Vi_c may be the same as the inverse of the negative signal CLK-, and the voltage signal Vi_t may be the same as the inverse of the positive signal CLK+. Figure 7B In the example, the starting duty cycle for the falling edge of the scanning voltage signal Vs may be e times earlier than the midpoint. The code B may be recorded by the processor 104 as d(middle code)+d(e). Fig. 7A and Figure 7B In the illustrated embodiment, processor 104 may determine DCC code 130 as (code A - code B) / 2 = -d(e) / 2, which may compensate for a differential duty cycle between CLK- and CLK+ greater than 50%.

[0063] Fig. 8A and Figure 8Bis a graph showing waveforms of another example implementation of digital duty cycle calibration in one embodiment. Fig. 8A and Figure 8B For a description, see Figures 1 to 7B Components shown. Fig. 8A and Figure 8B The multiple waveforms shown are Figure 6 The result of an implementation of system 100 is shown, where the negative signal CLK- has an ideal 50% duty cycle and the positive signal CLK+ has a DCD, such as having a duty cycle of [100*(T / 2-e) / T]% (e.g., the differential duty cycle between CLK- and CLK+ is less than 50%).

[0064] Fig. 8A For the first step of the two-step calibration process described herein, the MUX 114 in segments 602, 604 selects the output of the buffer 110. Fig. 8A In the embodiment, the voltage signal Vi_c may be the same as the negative signal CLK-, and the voltage signal Vi_t may be the same as the positive signal CLK+. The falling edges of the voltage signals Vc and Vs are aligned, so the processor 104 can record the code A=d (intermediate code).

[0065] Figure 8B For the second step of the two-step calibration process described herein, the MUX 114 in segments 602, 604 selects the output of the inverter 112. Figure 8B In the embodiment, the voltage signal Vi_c may be the same as the inverse of the negative signal CLK-, and the voltage signal Vi_t may be the same as the inverse of the positive signal CLK+. Figure 8B In the example, the starting duty cycle of the falling edge of the scanning voltage signal Vs may be e times later than the midpoint. The code B may be recorded by the processor 104 as d(middle code)-d(e). Fig. 8A and Figure 8B In the illustrated embodiment, the processor 104 may determine the DCC code 130 as (code A - code B) / 2 = +d(e) / 2, which may compensate for the differential duty cycle between CLK- and CLK+ being less than 50%.

[0066] Fig. 9 902, 904, 906, 908, and / or 910. Although shown as discrete blocks, various blocks may be divided into more blocks, combined into fewer blocks, deleted, performed in a different order, or performed in parallel, depending on the desired implementation.

[0067] Process 900 may be performed by a digital duty cycle calibration system using one or more DCMs. Process 900 may begin at block 902, where the calibration system may perform a first phase shift on a clock signal to generate a first phase shifted signal. Process 900 may continue from block 902 to block 904. At block 904, the calibration system may perform a second phase shift on the clock signal to generate a second phase shifted signal. In one embodiment, the first phase shift may be a 0 degree phase shift, and further, the second phase shift may be a 180 degree phase shift. In one embodiment, the clock signal may be one of a single-ended clock signal and a differential clock signal.

[0068] Process 900 may continue from block 904 to block 906. At block 906, the calibration system may perform fixed DCC on the first phase-shifted signal to generate a first voltage signal. Process 900 may continue from block 906 to block 908. At block 908, the calibration system may sweep the second phase-shifted signal over a duty cycle range to generate a second voltage signal.

[0069] In one embodiment, the calibration system may perform fixed DCC on the clock signal based on a control signal including a fixed DCC code. The calibration system may also scan the second phase-shifted signal based on a scanning signal including a plurality of DCC codes corresponding to a duty cycle range.

[0070] In another embodiment, the calibration system may perform a first phase shift on the inversion of the clock signal to generate a third phase shift signal. The calibration system may also perform a second phase shift on the inversion of the clock signal to generate a fourth phase shift signal. The calibration system may also perform a fixed DCC on the third phase shift signal to generate a third voltage signal. The calibration system may also scan the fourth phase shift signal within another duty cycle range to generate a fourth voltage signal. The calibration system may also sample another output clock signal at a time when the third voltage signal and the fourth voltage signal overlap. The calibration of the clock signal is based on the output clock signal and the above-mentioned another output clock signal.

[0071] Process 900 may continue from block 908 to block 910. At block 910, the calibration system may sample the output clock signal at a time when the first voltage signal and the second voltage signal overlap. Calibration of the clock signal may be based on the output clock signal. In another embodiment, the first phase shift may be a 0 degree phase shift, and further, the second phase shift may be a 180 degree phase shift.

[0072] The flow chart and block diagram in the figure show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this respect, each frame in the flow chart or block diagram can represent an instruction module, segment or part, which includes one or more executable instructions for realizing (multiple) specified logical functions.In some alternative implementations, the function shown in the frame may not appear in the order shown in the figure.For example, according to the function involved, two frames generated continuously can actually be performed substantially at the same time, or these frames can sometimes be performed in reverse order.It will also be noted that each frame of the block diagram and / or flow chart and the combination of the frames in the block diagram and / or flow chart can be realized by a system based on special hardware that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0073] The terms used herein are only used to describe specific embodiments and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" used herein also include plural forms. It should be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0074] The corresponding structures, materials, actions, and equivalents of all means or step plus function elements (if any) in the following claims are intended to include any structure, material, or action to perform a function in combination with other elements specifically claimed. The description of the present invention is presented for the purpose of illustration and description, but is not intended to be exhaustive or to limit the invention in the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present invention. The embodiments are selected and described in order to best explain the principles and practical application of the present invention, and to enable those of ordinary skill in the art to understand various embodiments of the present invention with various modifications suitable for the intended specific use.

Claims

1. A semiconductor device comprising: processor; A system duty cycle control DCC circuit is configured to generate a clock signal; as well as The circuit is configured as: performing a first phase shift on the clock signal to generate a first phase-shifted signal; performing a second phase shift on the clock signal to generate a second phase-shifted signal; performing fixed DCC on the first phase-shifted signal to generate a first voltage signal; scanning the second phase-shifted signal within a duty cycle range to generate a second voltage signal; as well as sampling an output clock signal at a time when the first voltage signal and the second voltage signal overlap; The processor is configured to generate a digital code based on the output clock signal, and The system DCC circuit is configured to calibrate the clock signal using the digital code.

2. The semiconductor device according to claim 1, wherein the processor is configured to: generating a control signal including a fixed DCC code for the circuit to perform the fixed DCC on the clock signal; and A scanning signal including a plurality of DCC codes is generated for the circuit to scan the phase-shifted signal.

3. The semiconductor device according to claim 1, wherein: The circuit is configured as: performing the first phase shift on an inversion of the clock signal to generate a third phase-shifted signal; performing the second phase shift on the inversion of the clock signal to generate a fourth phase-shifted signal; performing the fixed DCC on the third phase-shifted signal to generate a third voltage signal; scanning the fourth phase-shifted signal within another duty cycle range to generate a fourth voltage signal; as well as sampling another output clock signal at a time when the third voltage signal and the fourth voltage signal overlap; The processor is configured to generate another digital code based on the another output clock signal; and The system DCC circuit is configured to calibrate the clock signal using the digital code and the another digital code.

4. The semiconductor device according to claim 3, wherein the processor is configured to: determining a DCC code based on a difference between the digital code and the another digital code output clock signal; and sending the DCC code to the system DCC circuit, The system DCC circuit is configured to calibrate the clock signal using the DCC code.

5. The semiconductor device according to claim 4, wherein the system DCC circuit is configured as: In response to the difference being greater than zero, increasing a duty cycle of the clock signal; and In response to the difference being less than zero, the duty cycle of the clock signal is reduced. 6 . The semiconductor device according to claim 1 , further comprising a synchronizer circuit configured to synchronize the sampled output clock signal with the second voltage signal. 7 . The semiconductor device of claim 6 , wherein the duty cycle range depends on a synchronized sampled output clock signal.

8. The semiconductor device according to claim 1, wherein: The first phase shift is a 0 degree phase shift; and The second phase shift is a 180 degree phase shift.

9. The semiconductor device according to claim 1, wherein the clock signal is one of: a single-ended clock signal; and Differential clock signal.

10. A semiconductor device comprising: a first phase shifter configured to perform a first phase shift on the clock signal to generate a first phase-shifted signal; a second phase shifter configured to perform a second phase shift on the clock signal to generate a second phase-shifted signal; a first duty cycle control DCC circuit configured to perform fixed DCC on the first phase shift signal to generate a first voltage signal; a second DCC circuit configured to scan the second phase-shifted signal within a duty cycle range to generate a second voltage signal; as well as A phase detector is configured to sample an output clock signal at a time when the first voltage signal and the second voltage signal overlap, wherein calibration of the clock signal is based on the output clock signal.

11. The semiconductor device according to claim 10, wherein: The first DCC circuit is configured to perform the fixed DCC on the clock signal based on a control signal including a fixed DCC code; and The second DCC circuit is configured to scan the second phase shift signal based on a scan signal including a plurality of DCC codes corresponding to the duty cycle range.

12. The semiconductor device according to claim 10, wherein: The first phase shifter is configured to perform the first phase shift on the inversion of the clock signal to generate a third phase-shifted signal; The second phase shifter is configured to perform the second phase shift on the inversion of the clock signal to generate a fourth phase-shifted signal; The first DCC circuit is configured to perform the fixed DCC on the third phase-shifted signal to generate a third voltage signal; The second DCC circuit is configured to scan the fourth phase-shifted signal within another duty cycle range to generate a fourth voltage signal; as well as The phase detector is configured to sample another output clock signal at a time when the third voltage signal and the fourth voltage signal overlap, wherein the calibration of the clock signal is based on the output clock signal and the another output clock signal.

13. The semiconductor device of claim 10, wherein the duty cycle range depends on a synchronized version of the output clock signal.

14. The semiconductor device according to claim 10, wherein: The first phase shift is a 0 degree phase shift; and The second phase shift is a 180 degree phase shift.

15. The semiconductor device according to claim 10, wherein the clock signal is one of: a single-ended clock signal; and Differential clock signal.

16. A method for calibrating a clock signal, the method comprising: performing a first phase shift on the clock signal to generate a first phase-shifted signal; performing a second phase shift on the clock signal to generate a second phase-shifted signal; performing fixed DCC on the first phase-shifted signal to generate a first voltage signal; scanning the second phase-shifted signal within a duty cycle range to generate a second voltage signal; as well as An output clock signal is sampled at a time when the first voltage signal and the second voltage signal overlap, wherein calibration of the clock signal is based on the output clock signal.

17. The method according to claim 16, further comprising: performing the fixed DCC on the clock signal based on a control signal including a fixed DCC code; as well as The second phase shift signal is scanned based on a scan signal including a plurality of DCC codes corresponding to the duty cycle range.

18. The method according to claim 16, further comprising: performing the first phase shift on an inversion of the clock signal to generate a third phase-shifted signal; performing the second phase shift on the inversion of the clock signal to generate a fourth phase-shifted signal; performing the fixed DCC on the third phase-shifted signal to generate a third voltage signal; scanning the fourth phase-shifted signal within another duty cycle range to generate a fourth voltage signal; as well as Another output clock signal is sampled at a time when the third voltage signal and the fourth voltage signal overlap, wherein the calibration of the clock signal is based on the output clock signal and the another output clock signal.

19. The method of claim 16, wherein: The first phase shift is a 0 degree phase shift; and The second phase shift is a 180 degree phase shift.

20. The method of claim 16, wherein the clock signal is one of: a single-ended clock signal; and Differential clock signal.

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