A sample-and-hold circuit and an electronic chip

Abstract

The present application provides a sample-and-hold circuit and an electronic chip, relating to the field of integrated circuit technology. The sample-and-hold circuit includes a gate voltage bootstrap main switch module, a gate voltage bootstrap sub-switch module, a sampling switch transistor, a signal tracking switch transistor, and a pull-up switch transistor. The gate voltage bootstrap main switch module is respectively connected to the gate voltage bootstrap sub-switch module, the signal tracking switch transistor, and the pull-up switch transistor. The gate voltage bootstrap main switch module is connected to the gate of the sampling switch transistor through a first node. The drain of the pull-up switch transistor is connected to a power supply, and the source is connected to the gate of the signal tracking switch transistor and the gate voltage bootstrap main switch module through a second node. The sample-and-hold circuit and the electronic chip provided by the present application have the advantages of faster conduction speed and better circuit linearity.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly, to a sample and hold circuit and an electronic chip. Background Art

[0002] The sample and hold circuit in a signal chain circuit is generally composed of switched capacitors. Among them, the sampling switches are mainly divided into single MOS (Metal-Oxide-Semiconductor) switches, CMOS (Complementary Metal Oxide Semiconductor) switches, and bootstrapped switches. For the traditional single MOS sampling switch, since its on-resistance changes with the input signal, it will introduce a large nonlinearity to the sampling system. The CMOS switch compensates for part of the nonlinearity, but its linearity is still insufficient for circuits with high signal requirements. Therefore, in a sampling system with certain linearity requirements, a bootstrapped switch is introduced to reduce the correlation between the on-resistance of the sampling switch and the sampling signal.

[0003] Due to the emergence of cloud computing, optical computing, machine learning, and artificial intelligence, the demand for data center networks has increased exponentially. These emerging technologies have put forward extremely high requirements for the data throughput rate of data centers. To support these growing bandwidth requirements, the development of corresponding high-speed signal processing circuits is imminent. Many traditional circuit technologies or structures are difficult to be directly applied in ultra-high-speed circuits, so traditional circuits need to be optimized and improved.

[0004] The traditional bootstrapped switch can improve the linearity of the sampling switch well. However, since the bootstrapping technology introduces a feedback loop to the circuit itself, it limits the speed of the bootstrapped switch. In addition, with the increase of signal speed and sampling speed, in an ultra-high-speed signal acquisition system, the size of the sampling capacitor is restricted by speed and power consumption. In many applications, the sampling capacitor is only in the order of fF. Therefore, the nonlinear parasitic capacitance of the sampling switch at the sampling node introduced to the signal becomes non-negligible. And the existing bootstrapped switch circuit has multiple switches connected to the sampling node, so there are more parasitic capacitances at the sampling node, which not only affects the on-speed of the bootstrapped switch but also affects the linearity of the bootstrapped switch.

[0005] In summary, the existing bootstrapped switch circuit has problems that its on-speed and linearity cannot meet the requirements of ultra-high-speed signal acquisition systems. Summary of the Invention

[0006] The purpose of this application is to provide a sample-and-hold circuit and an electronic chip to solve the problem that the switching speed and linearity of the gate voltage bootstrap switch circuit in the prior art cannot meet the requirements of an ultra-high-speed signal acquisition system.

[0007] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:

[0008] On the one hand, the embodiments of this application provide a sample-and-hold circuit. The sample-and-hold circuit includes a gate voltage bootstrap main switch module, a gate voltage bootstrap sub-switch module, a sampling switch transistor, a signal tracking switch transistor, and a pull-up switch transistor. The gate voltage bootstrap main switch module is respectively connected to the gate voltage bootstrap sub-switch module, the signal tracking switch transistor, and the pull-up switch transistor. The gate voltage bootstrap main switch module is connected to the gate of the sampling switch transistor through a first node. The drain of the pull-up switch transistor is connected to the power supply, and the source is connected to the gate of the signal tracking switch transistor and the gate voltage bootstrap main switch module through a second node.

[0009] When in the hold stage, the charging circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the bootstrap capacitors inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are charged; and the sampling switch transistor, the signal tracking switch transistor, and the pull-up switch transistor are all turned off.

[0010] When in the sampling stage, the pull-up switch transistor is turned on, and drives the sampling switch transistor and the signal tracking switch transistor to be turned on. And then the bootstrap circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the gate potential of the sampling switch transistor is bootstrapped to a set potential.

[0011] Optionally, the gate voltage bootstrap main switch module includes a first bootstrap capacitor, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, and a pull-down component. One end of the first bootstrap capacitor is connected to the drain of the first switch transistor and the drain of the signal tracking switch transistor through a third node. The source of the first switch transistor is grounded. The sources of the signal tracking switch transistor and the sampling switch transistor are both used to receive an input signal. The other end of the first bootstrap capacitor is respectively connected to the source of the second switch transistor and the source of the third switch transistor. The drain of the second switch transistor is connected to a power supply, and the gate is connected to the second node. The drain of the third switch transistor is connected to the gate of the sampling switch transistor and the gate voltage bootstrap sub-switch module. The source of the fourth switch transistor is connected to the power supply. The drain of the fourth switch transistor is connected to the gate of the third switch transistor. The source of the fifth switch transistor is connected to the third node. The drain of the fifth switch transistor is connected to the gate of the third switch transistor. The gates of the fourth switch transistor, the fifth switch transistor, and the pull-up switch transistor are all used to receive a first control signal. The gate of the first switch transistor is used to receive a second control signal. The first control signal and the second control signal are opposite signals. One end of the pull-down component is connected to the second node, and the other end is grounded; wherein,

[0012] When in the holding stage, the first switch transistor, the pull-down component, the second switch transistor, and the fourth switch transistor are turned on, and the third switch transistor and the fifth switch transistor are turned off; and the first switch transistor, the first bootstrap capacitor, and the second switch transistor form a charging circuit;

[0013] When in the sampling stage, the first switch transistor, the pull-down component, the second switch transistor, and the fourth switch transistor are turned off, and the third switch transistor and the fifth switch transistor are turned on.

[0014] Optionally, the second switch transistor, the third switch transistor, and the fourth switch transistor are all P-type transistors, and the first switch transistor and the fifth switch transistor are both N-type transistors.

[0015] Optionally, the pull-down component includes a sixth switch transistor and a seventh switch transistor. The source of the sixth switch transistor is connected to the second node. The drain of the sixth switch transistor is connected to the source of the seventh switch transistor. The gate of the sixth switch transistor is connected to a power supply. The drain of the seventh switch transistor is grounded. The gate of the seventh switch transistor is used to receive a second control signal;

[0016] When in the holding stage, both the sixth switch transistor and the seventh switch transistor are turned on; when in the sampling stage, the sixth switch transistor is turned on, the seventh switch transistor is turned off, and the potential of the second node is bootstrapped to a set potential.

[0017] Optionally, the gate voltage bootstrap sub-switch module includes a second bootstrap capacitor, an eighth switching transistor, and a ninth switching transistor. One end of the second bootstrap capacitor is connected to the third node, and the other end is connected to the sources of the eighth switching transistor and the ninth switching transistor. The drain of the eighth switching transistor is connected to the power supply, the gate of the eighth switching transistor is connected to the second node, the drain of the ninth switching transistor is connected to the second node, and the gate of the ninth switching transistor is connected to the gate of the third switching transistor;

[0018] When in the holding stage, the eighth switching transistor is turned on and the ninth switching transistor is turned off; when in the sampling stage, the eighth switching transistor is turned off and the ninth switching transistor is turned on.

[0019] Optionally, both the eighth switching transistor and the ninth switching transistor are P-type transistors.

[0020] Optionally, the gate voltage bootstrap sub-switch module further includes a tenth switching transistor. The drain of the tenth switching transistor is connected to the second node, the source of the tenth switching transistor is connected to the first node, the gate of the tenth switching transistor is connected to the power supply, and the tenth switching transistor is in an on state both in the holding stage and the sampling stage.

[0021] Optionally, the sample and hold circuit further includes an eleventh switching transistor, and the source and drain of the eleventh switching transistor are short-circuited and then connected to the drain of the sampling switching transistor.

[0022] Optionally, the capacitance values of the bootstrap capacitor inside the gate voltage bootstrap main-switch module and the bootstrap capacitor inside the gate voltage bootstrap sub-switch module are the same.

[0023] On the other hand, an embodiment of the present application further provides an electronic chip, and the electronic chip includes the above-mentioned sample and hold circuit.

[0024] Compared with the prior art, the present application has the following beneficial effects:

[0025] The present application provides a sample and hold circuit and an electronic chip. The sample and hold circuit includes a gate voltage bootstrap main switch module, a gate voltage bootstrap sub-switch module, a sampling switch transistor, a signal tracking switch transistor, and a pull-up switch transistor. The gate voltage bootstrap main switch module is respectively connected to the gate voltage bootstrap sub-switch module, the signal tracking switch transistor, and the pull-up switch transistor. The gate voltage bootstrap main switch module is connected to the gate of the sampling switch transistor through a first node. The drain of the pull-up switch transistor is connected to a power supply, and the source is connected to the gate of the signal tracking switch transistor and the gate voltage bootstrap main switch module through a second node. When in the hold stage, the charging circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the bootstrap capacitors inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are charged. Moreover, the sampling switch transistor, the signal tracking switch transistor, and the pull-up switch transistor are all turned off. When in the sampling stage, the pull-up switch transistor is turned on, and drives the sampling switch transistor and the signal tracking switch transistor to be turned on. And then the bootstrap circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the gate potential of the sampling switch transistor is bootstrapped to a set potential.

[0026] On the one hand, since the sample and hold circuit provided by the present application adds a gate voltage bootstrap sub-switch module, more switch transistors are connected to the second node, and fewer switch transistors are connected to the first node, that is, the parasitic capacitance connected to the first node is smaller. Furthermore, the bootstrap potential establishment speed of the sampling switch transistor is improved, and the linearity of the sample and hold circuit is also improved. On the other hand, since a pull-up switch transistor is added to the sample and hold circuit, and in the sampling stage, the conduction of the pull-up switch transistor can directly drive the sampling switch transistor and the signal tracking switch transistor to be turned on. Therefore, it can be realized that the sampling switch transistor is turned on first and then the bootstrap potential is established, and the conduction speed of the sampling switch transistor can be faster. At the same time, the signal tracking switch transistor also does not need to wait until the bootstrap potential is established to be turned on, improving the conduction speed of the signal tracking switch transistor.

[0027] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, the detailed description is as follows. Brief Description of the Drawings

[0028] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0029] Figure 1 It is a circuit schematic diagram of an ideal gate voltage bootstrap switch circuit.

[0030] Figure 2It is a circuit schematic diagram of a gate voltage bootstrap switch circuit actually adopted in the prior art.

[0031] Figure 3 It is a circuit schematic diagram of the sample and hold circuit provided by the embodiment of the present application.

[0032] In the figure:

[0033] 110 - Gate voltage bootstrap sub - switch module; Ms - Sampling switch transistor; Mg - Signal tracking switch transistor; Mx - Pull - up switch transistor; C1 - First bootstrap capacitor; C2 - Second bootstrap capacitor; Q1 - First switch transistor; Q2 - Second switch transistor; Q3 - Third switch transistor; Q4 - Fourth switch transistor; Q5 - Fifth switch transistor; Q6 - Sixth switch transistor; Q7 - Seventh switch transistor; Q8 - Eighth switch transistor; Q9 - Ninth switch transistor; Q10 - Tenth switch transistor; Q11 - Eleventh switch transistor; VG - First node; VP - Second node; VS - Third node. Detailed implementation manners

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0036] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, terms such as "first", "second", etc. are only used for differential description and cannot be understood as indicating or implying relative importance.

[0037] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0038] The following will describe in detail some implementation manners of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0039] As described in the background art, the sampling and holding circuit in the prior art generally uses a bootstrap switch circuit to implement. An ideal bootstrap switch circuit is as shown in Figure 1 . This circuit mainly includes a sampling switch transistor Ms, a bootstrap capacitor Cb, a sampling capacitor Cs, and switch transistors M1 - M5. Among them, the sampling capacitor Cs is used to store the sampling signal.

[0040] The operation of the bootstrap switch circuit includes two stages, namely the holding stage and the sampling stage.

[0041] When in the holding stage, switch transistors M3 and M4 are turned off, and switch transistors M1, M2, and M5 are turned on. The power supply charges the bootstrap capacitor Cb, and the charge stored on it is VDD * C1 (C1 is the capacitance value of the bootstrap capacitor Cb), and the voltage rises to VDD. It can be understood that when the voltage of the bootstrap capacitor Cb rises to VDD in this stage, it means that the voltage difference between the upper plate and the lower plate of the bootstrap capacitor Cb is VDD, that is, the potential of the upper plate is VDD, and the potential of the lower plate is ground (0V). And switch transistor M5 is turned on, setting the gate potential of the sampling switch transistor Ms to the ground potential. At this time, the sampling switch Ms is turned off, and the output Vo maintains the sampled voltage unchanged.

[0042] When in the sampling stage, switch transistors M1, M2, and M5 are turned off, and switch transistors M3 and M4 are turned on, conducting the input signal VIN to the lower plate of the bootstrap capacitor Cb. At this time, due to the conservation of charge, the voltage difference between the upper plate and the lower plate of the bootstrap capacitor Cb remains unchanged. Also, since the potential of the lower plate of the bootstrap capacitor Cb becomes VIN at this time, the potential of the upper plate of the bootstrap capacitor Cb is bootstrapped to VDD + VIN. Switch transistor M3 is turned on to transfer this potential to the gate of the sampling switch transistor Ms. The source potential of the sampling switch transistor Ms is VIN, so that the gate - source voltage V of the sampling switch transistor Ms GS is V G -V S = (VDD + VIN) - VIN = VDD, that is, the gate - source voltage of the sampling switch transistor Ms is constantly VDD. This ensures that the on - resistance of the sampling switch does not change with the change of the input signal, improving the sampling linearity of the sampling system.

[0043] Figure 2 shows the bootstrap switch circuit actually used in the prior art based on Figure 1 . In the figure, CLKH and CLKS are a pair of opposite control signals, and switch transistors M2, M5, and M6 are all P - type switch transistors, and the rest of the switch transistors are all N - type switch transistors. Combining with Figure 1 the working principle, Figure 2 the working principle of the circuit in

[0044] When in the holding stage, CLKH is a high-level signal and CLKS is a low-level signal. At this time, the switching transistors M2, M3, and M8 are turned on. The switching transistor M7 is a protection transistor and is always turned on. At this time, since the switching transistor M8 is turned on, the VG node is pulled down to ground. Therefore, the switching transistors M9, M4, and Ms connected to the VG node are all turned off, and M6 is turned on. And since the switching transistor M2 is turned on, the switching transistor M5 is turned off. Therefore, in the entire circuit, the bootstrap capacitor Cb is charged through the loop of "VDD → switching transistor M6 → bootstrap capacitor Cb → switching transistor M3 → ground".

[0045] When in the sampling stage, CLKH is a low-level signal and CLKS is a high-level signal. At this time, the switching transistor M1 is turned on, and the switching transistors M2, M3, and M8 are turned off. Since the switching transistor M1 is turned on, the gate-source voltage of the switching transistor M5 is actually the opposite value of the voltage of the bootstrap capacitor Cb, that is, -VDD. At this time, the switching transistor M5 is turned on, the potential of the VG node is gradually pulled up to VDD, the switching transistor M6 is turned off, and the switching transistors M4 and M5 are gradually turned on. The input signal VIN is conducted to the lower plate of the bootstrap capacitor Cb, so that the gate-source voltage of the sampling switch Ms is kept constant at VDD.

[0046] In practical applications, it is found that Figure 2 Although the shown gate voltage bootstrap switch circuit can well improve the linearity of the sampling switch, however, since the gate voltage bootstrap switch circuit introduces a feedback loop (that is, the loop that needs to turn on the switching transistor M5 to increase the voltage of the VG node), the speed of the gate voltage bootstrap switch is limited. In addition, with the increase of the signal speed and the sampling speed, in the ultra-high-speed signal acquisition system, the size of the sampling capacitor is restricted by speed and power consumption. In many applications, the sampling capacitor is only at the fF level. Therefore, the non-linearity introduced by the fF-level non-linear parasitic capacitance of the sampling switch at the sampling node to the signal becomes non-negligible.

[0047] In addition, before the switching transistor Ms of the traditional gate voltage bootstrap switch is turned on, it is necessary to charge the parasitic capacitances of the gates of M4 and Ms, so that M4 is turned on first. After the input signal is transmitted to the lower plate of Cb, the gate potential of Ms will change with the change of the input voltage. Therefore, the turn-on time of the gate-source voltage of Ms will be too long, which limits the higher-frequency sampling of the switch. At the same time, the larger the parasitic capacitances of the gates of M4, M6, M9, and Ms, the slower the voltage rising speed of the VG node, and due to capacitive voltage division, the self-bootstrapped gate-source voltage of Ms is lower.

[0048] In view of this, to solve the above problems, the present application provides a gate voltage bootstrap switch circuit, which achieves the effect of improving the conduction speed and linearity of the sampling and holding circuit by setting a gate voltage bootstrap sub-switch module and a pull-up switching transistor.

[0049] An exemplary description of the sample-and-hold circuit provided by the application is as follows:

[0050] As an alternative implementation, please refer to Figure 3 , the sample-and-hold circuit includes a bootstrap main switch module (not shown in the figure), a bootstrap sub-switch module 110, a sampling switch transistor Ms, a signal tracking switch transistor Mg, and a pull-up switch transistor Mx. The bootstrap main switch module is respectively connected to the bootstrap sub-switch module 110, the signal tracking switch transistor Mg, and the pull-up switch transistor Mx. The bootstrap main switch module is connected to the gate of the sampling switch transistor Ms through a first node VG. The drain of the pull-up switch transistor Mx is connected to the power supply, and the source is connected to the gate of the signal tracking switch transistor Mg and the bootstrap main switch module through a second node VP; when in the hold stage, the charging circuits inside the bootstrap main switch module and the bootstrap sub-switch module 110 are turned on, and the bootstrap capacitors inside the bootstrap main switch module and the bootstrap sub-switch module 110 are charged; and the sampling switch transistor Ms, the signal tracking switch transistor Mg, and the pull-up switch transistor Mx are all turned off; when in the sampling stage, the pull-up switch transistor Mx is turned on, and drives the sampling switch transistor Ms and the signal tracking switch transistor Mg to be turned on, and then the bootstrap circuits inside the bootstrap main switch module and the bootstrap sub-switch module 110 are turned on, and the gate potential of the sampling switch transistor Ms is bootstrapped to a set potential.

[0051] On the one hand, since the sample-and-hold circuit provided by the application adds a bootstrap sub-switch module 110, more switch transistors are connected to the second node VP, and fewer switch transistors are connected to the first node VG, that is, the parasitic capacitance connected to the first node VG is smaller, thereby improving the bootstrap potential establishment speed of the sampling switch transistor Ms and also improving the linearity of the sample-and-hold circuit. On the other hand, since a pull-up switch transistor Mx is added to the sample-and-hold circuit, and in the sampling stage, the conduction of the pull-up switch transistor Mx can directly drive the sampling switch transistor Ms and the signal tracking switch transistor Mg to be turned on, so it is possible to achieve that the sampling switch transistor is turned on first and then the bootstrap potential is established, and the conduction speed of the sampling switch transistor Ms can be faster. At the same time, the signal tracking switch transistor Mg does not need to wait for the bootstrap potential to be established before turning on, improving the conduction speed of the signal tracking switch transistor Mg.

[0052] As an alternative implementation, the gate voltage bootstrap main switch module includes a first bootstrap capacitor C1, a first switch transistor Q1, a second switch transistor Q2, a third switch transistor Q3, a fourth switch transistor Q4, a fifth switch transistor Q5, and a pull-down component. One end of the first bootstrap capacitor C1 is connected to the drain of the first switch transistor Q1 and the drain of the signal tracking switch transistor Mg through the third node VS. The source of the first switch transistor Q1 is grounded. The sources of the signal tracking switch transistor Mg and the sampling switch transistor Ms are both used to receive the input signal. The other end of the first bootstrap capacitor C1 is respectively connected to the source of the second switch transistor Q2 and the source of the third switch transistor Q3. The drain of the second switch transistor Q2 is connected to the power supply, and the gate is connected to the second node VP. The drain of the third switch transistor Q3 is connected to the gate of the sampling switch transistor Ms and the gate voltage bootstrap sub-switch module 110. The source of the fourth switch transistor Q4 is connected to the power supply. The drain of the fourth switch transistor Q4 is connected to the gate of the third switch transistor Q3. The source of the fifth switch transistor Q5 is connected to the third node VS. The drain of the fifth switch transistor Q5 is connected to the gate of the third switch transistor Q3. The gates of the fourth switch transistor Q4, the fifth switch transistor Q5, and the pull-up switch transistor Mx are all used to receive the first control signal. The gate of the first switch transistor Q1 is used to receive the second control signal. The first control signal and the second control signal are opposite signals. One end of the pull-down component is connected to the second node VP, and the other end is grounded; when in the hold stage, the first switch transistor Q1, the pull-down component, the second switch transistor Q2, and the fourth switch transistor Q4 are turned on, and the third switch transistor Q3 and the fifth switch transistor Q5 are turned off; and the first switch transistor Q1, the first bootstrap capacitor C1, and the second switch transistor Q2 form a charging circuit; when in the sampling stage, the first switch transistor Q1, the pull-down component, the second switch transistor Q2, and the fourth switch transistor Q4 are turned off, and the third switch transistor Q3 and the fifth switch transistor Q5 are turned on.

[0053] Among them, the second switch transistor Q2, the third switch transistor Q3, and the fourth switch transistor Q4 are all P-type transistors, and the first switch transistor Q1 and the fifth switch transistor Q5 are all N-type transistors.

[0054] The pull-down component includes a sixth switch transistor Q6 and a seventh switch transistor Q7. The source of the sixth switch transistor Q6 is connected to the second node VP. The drain of the sixth switch transistor Q6 is connected to the source of the seventh switch transistor Q7. The gate of the sixth switch transistor Q6 is connected to the power supply. The drain of the seventh switch transistor Q7 is grounded, and the gate of the seventh switch transistor Q7 is used to receive the second control signal; when in the hold stage, both the sixth switch transistor Q6 and the seventh switch transistor Q7 are turned on, and after being turned on, the voltage of the second node VP is pulled down to the ground; when in the sampling stage, the sixth switch transistor Q6 is turned on, and the seventh switch transistor Q7 is turned off.

[0055] Understandably, in the sample-and-hold circuit provided by the present application, since only the gate of the sampling switch transistor Ms is connected to the first node VG, the parasitic capacitance of the first node VG is greatly reduced compared to the existing topological structure. According to the capacitor charging formula T = RC, where T represents the charging time, R represents the equivalent resistance, and C represents the equivalent capacitance, when the equivalent capacitance of the first node VG decreases, during the bootstrap process, the time for charging the capacitor is shortened, thereby increasing the charging speed of the first bootstrap capacitor C1 to the first node VG and reducing the voltage drop caused by capacitor voltage division.

[0056] Moreover, since the pull-up switch transistor Mx provided by the present application can directly act on the first node VG, during the sampling phase, after the pull-up switch transistor Mx is turned on, it directly pulls up the voltage of the first node VG to the power supply VDD, causing the sampling switch transistor Ms to turn on first, and then completing the establishment of the bootstrap process, thereby improving the initial stage establishment speed of the gate voltage of the sampling switch transistor Ms. That is, the sampling switch transistor Ms turns on first, the signal starts to be established, and then the first node VG enters the bootstrap state to ensure the linearity of signal establishment, overall improving the conduction speed of the sample-and-hold circuit.

[0057] In addition, since the gate of the second switch transistor Q2 is directly connected to the second node VP, the second switch transistor Q2 does not need to wait for the establishment of the first node VG to turn off, improving the speed at which the first node VG tracks the input signal. Then, the bootstrap voltage of the gate voltage bootstrap sub-switch module 110 ensures that there is no reverse injection risk in the gate voltage bootstrap sub-switch module 110.

[0058] As an implementation, the gate voltage bootstrap sub-switch module 110 includes a second bootstrap capacitor C2, an eighth switch transistor Q8, and a ninth switch transistor Q9. One end of the second bootstrap capacitor C2 is connected to the third node VS, and the other end is connected to the sources of the eighth switch transistor Q8 and the ninth switch transistor Q9. The drain of the eighth switch transistor Q8 is connected to the power supply, the gate of the eighth switch transistor Q8 is connected to the second node VP, the drain of the ninth switch transistor Q9 is connected to the second node VP, and the gate of the ninth switch transistor Q9 is connected to the gate of the third switch transistor Q3; when in the holding phase, the eighth switch transistor Q8 is turned on and the ninth switch transistor Q9 is turned off; when in the sampling phase, the eighth switch transistor Q8 is turned off and the ninth switch transistor Q9 is turned on. Among them, both the eighth switch transistor Q8 and the ninth switch transistor Q9 are P-type transistors. In the present application, the capacitance values of the first bootstrap capacitor C1 and the second bootstrap capacitor C2 are the same.

[0059] The gate voltage bootstrap sub-switch module 110 further includes a tenth switch transistor Q10. The drain of the tenth switch transistor Q10 is connected to the second node VP, the source of the tenth switch transistor Q10 is connected to the first node VG, and the gate of the tenth switch transistor Q10 is connected to the power supply, and the tenth switch transistor Q10 is in the on state during both the holding phase and the sampling phase.

[0060] By setting the gate voltage bootstrap sub-switch module 110, a second node VP can be introduced, enabling more switching transistors to be connected to the second node VP, reducing the number of switching transistors connected to the first node VG, and thereby enhancing the gate voltage bootstrap speed of the first node VG.

[0061] Meanwhile, during the bootstrap process, the potential of the second node VP is also bootstrapped to VDD + VIN. Since the gate of the signal tracking switch transistor Mg is connected to the second node VP, the signal tracking switch transistor Mg does not need to wait for the voltage of the second node VP to be established before conducting. Instead, it conducts directly after the pull-up switch transistor Mx conducts, improving the speed at which the gate voltage of the sampling switch transistor Ms tracks the input signal. Subsequently, the second bootstrap capacitor C2 bootstraps the potential of the second node VP to VDD + VIN, ensuring the linearity of the signal tracking switch transistor Mg.

[0062] Moreover, after the second node VP is bootstrapped to VDD + VIN, since the gates of the second switch transistor Q2 and the eighth switch transistor Q8 are connected to the second node VP, it is ensured that even after bootstrap, the second switch transistor Q2 and the eighth switch transistor Q8 will not conduct, avoiding the risk of reverse current flowing from the sources of the second switch transistor Q2 and the eighth switch transistor Q8 to the power supply.

[0063] Furthermore, to further improve the linearity of the sampling switch transistor Ms, the sampling and holding circuit provided in this application further includes an eleventh switch transistor Q11. The source and drain of the eleventh switch transistor Q11 are short-circuited and connected to the drain of the sampling switch transistor Ms. By setting the eleventh switch transistor Q11, a parasitic capacitance opposite to the change of the sampling switch transistor Ms can be introduced at the signal sampling node, thereby compensating for the non-linear parasitic capacitance of the sampling switch transistor Ms.

[0064] The working principle of the circuit provided in this application will be specifically described below with reference to the circuit:

[0065] When in the holding stage, the first control signal CLKS is at a low level and the second control signal CLKH is at a high level. At this time, the first switch Q1, the fourth switch Q4, and the seventh switch Q7 are turned on, the fifth switch Q5 and the pull-up switch Mx are turned off, and the sixth switch Q6 acts as a protection transistor and is always turned on. Therefore, after the seventh switch Q7 is turned on, the voltage of the second node VP is directly pulled down to ground. The tenth switch Q10 acts as a protection transistor and is always turned on. Then, after the voltage of the second node VP is pulled down to ground, the second switch Q2 and the eighth switch Q8 are turned on, and the sampling switch Ms and the signal tracking switch Mg are turned off. At the same time, after the fourth switch Q4 is turned on, the gates of the third switch Q3 and the ninth switch Q9 are pulled up to the power supply VDD, and the third switch Q3 and the ninth switch Q9 are turned off. It can be seen that in this stage, the first bootstrap capacitor C1 is charged through the charging loop of the second switch Q2, the first bootstrap capacitor C1, and the first switch Q1; at the same time, the second bootstrap capacitor C2 is charged through the charging loop of the eighth switch Q8, the second bootstrap capacitor C2, and the first switch Q1.

[0066] When in the sampling stage, the first control signal CLKS is at a high level and the second control signal CLKH is at a low level. At this time, the first switch Q1, the fourth switch Q4, and the seventh switch Q7 are turned off, and the fifth switch Q5 and the pull-up switch Mx are turned on. It should be noted that in this stage, it actually includes the second node VP voltage establishment stage and the bootstrap stage. Since the pull-up switch Mx is turned on, the second node VP is directly pulled up to VDD. Since there is no feedback loop in this stage, the establishment process is relatively fast. When the second node VP is pulled up to VDD, the sampling switch Ms and the signal tracking switch Mg are turned on accordingly, and the second switch Q2 and the eighth switch Q8 are turned off accordingly. Since the establishment speed of this process is relatively fast, the sampling switch Ms in the circuit can work at a relatively fast speed, greatly improving the sampling frequency of the sampling switch Ms. After the sampling switch Ms and the signal tracking switch Mg are turned on, it enters the bootstrap stage. Since in the prior art, the signal tracking switch Mg needs to wait until the voltage of the first node VG is established before it can be turned on, while in this application, it is turned on during the second node voltage establishment stage, so the establishment speed of the bootstrap stage is improved.

[0067] During the bootstrap stage, under the action of the fifth switch Q5 being turned on, the third switch Q3 and the ninth switch Q9 are turned on, so that the first bootstrap capacitor C1 bootstraps the voltage of the first node VG to VDD + VIN, and the second bootstrap capacitor C2 bootstraps the voltage of the second node VP to VDD + VIN, ensuring the linearity of the sampling switch Ms and the signal tracking switch Mg.

[0068] It can be seen that in the sampling and holding circuit provided by the present application, a new topology is adopted. Without introducing a large device cost, the parasitic capacitance of the first node VG is greatly reduced, and the voltage establishment speed of the first node VG is greatly accelerated; the conduction speed of the signal tracking switch tube Mg and the turn-off speeds of the second switch tube Q2 and the eighth switch tube Q8 are accelerated, the speed of the gate voltage of the sampling switch tube Ms tracking the input signal is improved, and the initial rising speed of the voltage establishment of the first node VG is accelerated by the pull-up switch tube Mx. The on-off speed of the sampling switch tube Ms is greatly improved. In addition, the eleventh switch tube Q11 with a parasitic capacitance change opposite to that of the sampling switch tube Ms is introduced to compensate for its parasitic non-linear capacitance.

[0069] Based on the above implementation manner, an embodiment of the present application further provides an electronic chip, and the electronic chip includes the above sampling and holding circuit.

[0070] In summary, the present application provides a sampling and holding circuit and an electronic chip. The sampling and holding circuit includes a gate voltage bootstrap main switch module, a gate voltage bootstrap sub-switch module, a sampling switch tube, a signal tracking switch tube, and a pull-up switch tube. The gate voltage bootstrap main switch module is respectively connected to the gate voltage bootstrap sub-switch module, the signal tracking switch tube, and the pull-up switch tube. The gate voltage bootstrap main switch module is connected to the gate of the sampling switch tube through a first node. The drain of the pull-up switch tube is connected to a power supply, and the source is connected to the gate of the signal tracking switch tube and the gate voltage bootstrap main switch module through a second node; when in the holding stage, the charging circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the bootstrap capacitors inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are charged; and the sampling switch tube, the signal tracking switch tube, and the pull-up switch tube are all turned off; when in the sampling stage, the pull-up switch tube is turned on, and drives the sampling switch tube and the signal tracking switch tube to be turned on, and then the bootstrap circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the gate potential of the sampling switch tube is bootstrapped to a set potential.

[0071] On the one hand, since the sampling and holding circuit provided by the present application adds a gate voltage bootstrap sub-switch module, more switches are connected to the second node, and fewer switch tubes are connected to the first node, that is, the parasitic capacitance connected to the first node is smaller, thereby improving the bootstrap potential establishment speed of the sampling switch tube and also improving the linearity of the sampling and holding circuit. On the other hand, since the sampling and holding circuit adds a pull-up switch tube, and in the sampling stage, the pull-up switch tube can be directly turned on to drive the sampling switch tube and the signal tracking switch tube to be turned on, so the sampling switch tube can be turned on first and then the bootstrap potential is established, and the conduction speed of the sampling switch tube can be faster. At the same time, the signal tracking switch tube does not need to wait for the bootstrap potential to be established before being turned on, improving the conduction speed of the signal tracking switch tube.

[0072] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

[0073] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of the present application, the present application can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A sample-and-hold circuit, characterized in that The sampling and holding circuit includes a gate voltage bootstrap main switch module, a gate voltage bootstrap sub-switch module, a sampling switch transistor, a signal tracking switch transistor, and a pull-up switch transistor. The gate voltage bootstrap main switch module is connected to the gate voltage bootstrap sub-switch module, the signal tracking switch transistor, and the pull-up switch transistor respectively. The gate voltage bootstrap main switch module is connected to the gate of the sampling switch transistor through a first node. The drain of the pull-up switch transistor is connected to a power supply, and the source is connected to the gate of the signal tracking switch transistor and the gate voltage bootstrap main switch module through a second node; When in the holding stage, the charging circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the bootstrap capacitors inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are charged; and the sampling switch transistor, the signal tracking switch transistor, and the pull-up switch transistor are all turned off; When in the sampling stage, the pull-up switch transistor is turned on, and drives the sampling switch transistor and the signal tracking switch transistor to be turned on. And then the bootstrap circuits inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are turned on, and the gate potential of the sampling switch transistor is bootstrapped to a set potential; The gate voltage bootstrap main switch module includes a fifth switch transistor, and the source of the fifth switch transistor is connected to a third node; The gate voltage bootstrap sub-switch module includes a second bootstrap capacitor, an eighth switch transistor, and a ninth switch transistor. One end of the second bootstrap capacitor is connected to the third node, and the other end is connected to the sources of the eighth switch transistor and the ninth switch transistor. The drain of the eighth switch transistor is connected to the power supply, the gate of the eighth switch transistor is connected to the second node, the drain of the ninth switch transistor is connected to the second node, and the gate of the ninth switch transistor is connected to the gate of the third switch transistor; When in the holding stage, the eighth switch transistor is turned on, and the ninth switch transistor is turned off; when in the sampling stage, the eighth switch transistor is turned off, and the ninth switch transistor is turned on, and the potential of the second node is bootstrapped to a set potential.

2. The sampling and holding circuit according to claim 1, wherein The gate voltage bootstrap main switch module includes a first bootstrap capacitor, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, and a pull-down component. One end of the first bootstrap capacitor is connected to the drain of the first switch transistor and the drain of the signal tracking switch transistor through a third node. The source of the first switch transistor is grounded. The sources of the signal tracking switch transistor and the sampling switch transistor are both used to receive an input signal. The other end of the first bootstrap capacitor is respectively connected to the sources of the second switch transistor and the third switch transistor. The drain of the second switch transistor is connected to the power supply, and the gate is connected to the second node. The drain of the third switch transistor is connected to the gate of the sampling switch transistor and the gate voltage bootstrap sub-switch module. The source of the fourth switch transistor is connected to the power supply, and the drain of the fourth switch transistor is connected to the gate of the third switch transistor. The drain of the fifth switch transistor is connected to the gate of the third switch transistor. The gates of the fourth switch transistor, the fifth switch transistor, and the pull-up switch transistor are all used to receive a first control signal. The gate of the first switch transistor is used to receive a second control signal. The first control signal and the second control signal are opposite signals. One end of the pull-down component is connected to the second node, and the other end is grounded; wherein, When in the holding stage, the first switch transistor, the pull-down component, the second switch transistor, and the fourth switch transistor are turned on, and the third switch transistor and the fifth switch transistor are turned off; and the first switch transistor, the first bootstrap capacitor, and the second switch transistor form a charging circuit; When in the sampling stage, the first switch transistor, the pull-down component, the second switch transistor, and the fourth switch transistor are turned off, and the third switch transistor and the fifth switch transistor are turned on.

3. The sampling and holding circuit according to claim 2, wherein The second switch transistor, the third switch transistor, and the fourth switch transistor are all P-type transistors, and the first switch transistor and the fifth switch transistor are both N-type transistors.

4. The sampling and holding circuit according to claim 2, wherein The pull-down component includes a sixth switch transistor and a seventh switch transistor. The source of the sixth switch transistor is connected to the second node. The drain of the sixth switch transistor is connected to the source of the seventh switch transistor. The gate of the sixth switch transistor is connected to the power supply. The drain of the seventh switch transistor is grounded, and the gate of the seventh switch transistor is used to receive the second control signal; When in the holding stage, both the sixth switch transistor and the seventh switch transistor are turned on; when in the sampling stage, the sixth switch transistor is turned on, and the seventh switch transistor is turned off.

5. The sampling and holding circuit according to claim 1, wherein The eighth switch transistor and the ninth switch transistor are both P-type transistors.

6. The sampling and holding circuit according to claim 1, wherein The gate voltage bootstrap sub-switch module further includes a tenth switch transistor. The drain of the tenth switch transistor is connected to the second node. The source of the tenth switch transistor is connected to the first node. The gate of the tenth switch transistor is connected to the power supply, and the tenth switch transistor is in the on state both in the holding stage and the sampling stage.

7. The sampling and holding circuit according to claim 1, wherein The sample and hold circuit further includes an eleventh switch transistor. The source and drain of the eleventh switch transistor are short-circuited and then connected to the drain of the sampling switch transistor.

8. The sampling and holding circuit according to claim 1, wherein The capacitance values of the bootstrap capacitors inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module are the same.

9. An electronic chip, characterized in that, The electronic chip includes the sample-and-hold circuit according to any one of claims 1 to 8.

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