A PCIe switch multicast processing system and method considering efficiency and resources

Abstract

The application discloses a PCIe switch multicast processing system and method considering efficiency and resources, comprising a unicast control module, a multicast control module and a target port arbitration module.The unicast control module is used for receiving target port information of a unicast TLP packet, TLP indication signals, TLP header information and TLP load data, and issuing a unicast request.The multicast control module is used for receiving a target port list of a multicast TLP packet, TLP indication signals, TLP header information and TLP load data, and issuing a multicast request.The target port arbitration module is used for receiving the unicast request and the multicast request, and sending a request packet corresponding to the unicast request or the multicast request to a sending cache module.The sending cache module is used for receiving an authorized unicast TLP packet or a multicast TLP packet, caching the unicast TLP packet or the multicast TLP packet, and sending the unicast TLP packet or the multicast TLP packet to an egress end of a target port.The application concentrates multicast packet processing on an ingress end of a PCIe port, separates unicast packets and multicast packets for processing, opens two parallel processing channels in the multicast control module, and realizes multicast packet copying through a rollback FIFO read-write pointer mode, so that the design is simplified, resources are saved, and efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of PCIe design technology, specifically a PCIe switch multicast processing system and method that balances efficiency and resources. Background Technology

[0002] PCIe is a high-speed point-to-point data transmission mechanism. Multicast technology logically enables PCIe to achieve one-to-many point transmission. When a PCIe device needs to transmit the same data to multiple PCIe devices, unicast requires copying the same data multiple times at the source and then sending it to each destination device sequentially. However, by configuring multicast transmission, a single copy of the data is sent at the source, and intermediate PCIe switches automatically copy the data and send it to all destination devices. PCIe multicast transmission breaks through the physical limitations of point-to-point transmission, logically enabling one-to-many data transmission, significantly improving bandwidth utilization and reducing the load on the source.

[0003] Regarding the implementation of multicast in PCIe switches, patent CN117749706B, titled "A PCIe Switch Multicast Processing Method and Apparatus," proposes a method for implementing multicast in PCIe switches. This method divides the PCIe switch ports into multiple groups. First, at the source port, arbitration is used to determine whether a received packet is unicast or multicast. If it is multicast, inter-group arbitration is performed among the port groups to determine all destination groups to which the multicast destination port belongs. Once all destination groups are ready, the multicast packet is sent to all destination groups. Then, within each destination group, the multicast packet is sent to its respective destination port. During the multicast packet transmission process, other requests from that destination group are paused. The multicast implementation described in this patent, which groups ports, offers advantages in area control for PCIe switches with a large number of ports by breaking down multi-port cross-routes into smaller ones. However, besides increasing the complexity of control logic and packet processing latency, this approach has a potential problem: if ports in a group contain a destination port for a particular multicast, that group becomes the destination group for that multicast. However, not all ports within the destination group are necessarily destination ports for that multicast. If other ports in the group are destination ports for another multicast, the current multicast must be processed before the other multicast can be sent. Although these two multicasts do not conflict on the destination ports, the inability to process them in parallel simply because they are grouped together negatively impacts multicast processing efficiency. Summary of the Invention

[0004] To address the shortcomings of the existing technology, this invention provides a PCIe switch multicast processing system and method that balances efficiency and resources. This invention centralizes multicast packet processing at the ingress end of the PCIe port, separates unicast and multicast packets for processing, opens two parallel processing channels within the multicast control module, and implements multicast packet replication through rollback FIFO read / write pointers, simplifying the design, saving resources, and improving efficiency.

[0005] To achieve the above technical objectives, the present invention adopts the following technical solution:

[0006] A PCIe switch multicast processing system that balances efficiency and resources includes,

[0007] The unicast control module is used to receive the target port information of the unicast TLP packet, as well as the TLP indication signal, TLP header information and TLP payload data, and assign the TLP indication signal, TLP header information and TLP payload data to the target port corresponding to the target port information, and send a unicast request; wherein, the TLP indication signal of non-target ports is set to 0, indicating that the corresponding port has not received the TLP packet;

[0008] The multicast control module is used to receive the target port list of multicast TLP packets, as well as TLP indication signals, TLP header information and TLP payload data, and to copy and send the multicast TLP packets to each target port corresponding to the target port list, and issue a multicast request.

[0009] The target port arbitration module is used to receive the unicast request and the multicast request, and after authorizing the unicast request or the multicast request, send the request packet corresponding to the unicast request or the multicast request to the sending buffer module, wherein the request packet refers to the unicast TLP packet or the multicast TLP packet;

[0010] The sending buffer module is used to receive the authorized unicast TLP packet or the multicast TLP packet, buffer it, and after obtaining authorization from the egress end of the target port, send the unicast TLP packet or the multicast TLP packet to the egress end of the target port.

[0011] Furthermore, the unicast TLP packet includes N sets of TLP indication signals and a set of TLP header information and TLP payload data; the unicast control module is provided with N outputs corresponding to N ports, where N is a natural number greater than 1; the egress terminals of the N ports each correspond to a set of TLP indication signals and share a set of TLP header information and TLP payload data.

[0012] Furthermore, the multicast TLP packet includes N sets of TLP indication signals and N sets of TLP header information and TLP payload data; the multicast control module has two built-in multicast channels, namely multicast channel 1 and multicast channel 2, and each of the two multicast channels is provided with N outputs for corresponding to N ports, where N is a natural number greater than 1; the egress terminals of the N ports correspond to one set of TLP indication signals and one set of TLP header information and TLP payload data, respectively.

[0013] Furthermore, the multicast control module has a built-in function.

[0014] Channel 1 buffer mc_fifo1 and channel 2 buffer mc_fifo2 are used to store the TLP indication signal and the TLP payload data carried by the multicast TLP packet;

[0015] The mc_fifo1 read / write control module and the mc_fifo2 read / write control module are used to implement read / write control of the channel 1 cache mc_fifo1 and the channel 2 cache mc_fifo2, respectively.

[0016] info_fifo is used to store multicast target port information and the TLP header information of the multicast TLP packet;

[0017] The info_fifo read / write control module is used to implement read / write control of the info_fifo file.

[0018] The target port management module is used to manage target ports that have not yet been sent or have not yet completed the sending process.

[0019] The Channel 1 authorization request module and the Channel 2 authorization request module are used to provide the target port indication for the multicast TLP packet to be sent to multicast Channel 1 and multicast Channel 2, respectively.

[0020] The channel 1 transmitting module is used to buffer the TLP indication signal, TLP payload data and TLP header information output by mc_fifo1 in channel 1, assign them to the TLP information corresponding to the target port of channel 1, and send them to the arbitration module of the target port.

[0021] The channel 2 transmitting module is used to buffer the TLP indication signal, TLP payload data and TLP header information output by mc_fifo2 in channel 2, assign them to the TLP information corresponding to the target port of channel 2, and send them to the arbitration module of the target port.

[0022] Furthermore, the target port arbitration module has N built-in arbitration sub-modules, each of which is associated with a port. The arbitration sub-modules receive unicast requests or multicast requests directed to the associated port from one unicast channel of the unicast control module and two multicast channels of the multicast control module, and arbitrate the requests from the three channels.

[0023] A PCIe switch multicast processing method that balances efficiency and resources includes the following steps:

[0024] Determine whether a TLP packet is unicast or multicast;

[0025] For unicast TLP packet processing, the target port information of the unicast TLP packet, as well as the TLP indication signal, TLP header information and TLP payload data are received, and the TLP indication signal, TLP header information and TLP payload data are assigned to the target port corresponding to the target port information, and a unicast request is sent; wherein, the TLP indication signal of non-target ports is set to 0, indicating that the corresponding port has not received the TLP packet;

[0026] For multicast TLP packet processing, the system receives the target port list of the multicast TLP packet, as well as the TLP indication signal, TLP header information and TLP payload data, and copies and sends the multicast TLP packet to each target port corresponding to the target port list, and issues a multicast request.

[0027] Upon receiving the unicast request and the multicast request, and after authorizing the unicast request or the multicast request, the request packet corresponding to the unicast request or the multicast request is sent to the sending cache module, wherein the request packet refers to the unicast TLP packet or the multicast TLP packet;

[0028] Receive the authorized unicast TLP packet or the multicast TLP packet, buffer it, and after obtaining authorization from the egress end of the target port, send the unicast TLP packet or the multicast TLP packet to the egress end of the target port.

[0029] Furthermore, the processing of multicast TLP packets specifically includes the following sub-steps:

[0030] Get List: Retrieves an initial list of target ports to be sent;

[0031] Authorized write: Based on the initial list of target ports to be sent, generate the sending request list for multicast channel 1 and the sending request list for multicast channel 2 respectively, and perform authorization operations on the sending request list of multicast channel 1 and the sending request list of multicast channel 2 in priority order, and write the authorized target port number into the mc_fifo1 read and write control module of channel 1 cache mc_fifo1 and the mc_fifo2 read and write control module of channel 2 cache mc_fifo2 respectively;

[0032] Sending data: Based on the authorized target port number received by each of the two multicast channels, multicast TLP packet data is read from the buffer mc_fifo1 of channel 1 and the buffer mc_fifo2 of channel 2, and sent to their respective target ports.

[0033] Furthermore, obtaining the list includes the following sub-steps:

[0034] Check if info_fifo is empty. If it is not empty, it indicates that a multicast TLP packet is being processed. At this time, the backpressure signal is set high to notify the external multicast packet to request hold and wait for reception. If info_fifo is empty, the multicast target port information and the TLP header information of the multicast TLP packet are written to info_fifo. The TLP indicator signal and TLP payload data of the multicast TLP packet are written to the channel 1 buffer mc_fifo1 and the channel 2 buffer mc_fifo2. At the same time, the multicast target port information is recorded as the initial list of target ports to be sent.

[0035] Furthermore, the authorization writing includes the following sub-steps:

[0036] In a multicast process, the sending request list of channel 1 excludes authorized target ports that multicast channel 2 is currently sending to, and the sending request list of channel 2 excludes authorized target ports that multicast channel 1 is currently sending to. Multicast channel 1 polls the sending target port request list in a round-robin order from low to high priority, and the authorized target port number is notified to the read / write control module of the mc_fifo1 cache in channel 1. Multicast channel 2 polls the sending target port request list in a round-robin order from high to low priority, and the authorized target port number is notified to the read / write control module of the mc_fifo2 cache in channel 2.

[0037] Furthermore, the data transmission includes the following sub-steps:

[0038] After all the multicast TLP packets have been written to the channel 1 buffer mc_fifo1 and the channel 2 buffer mc_fifo2, the two channels read the multicast TLP packet data from mc_fifo1 and mc_fifo2 respectively according to the authorized target port number they received, and send it to their respective target ports. When the two channels finish sending the multicast packets, they rollback their respective read pointers to address 0, which is the starting position of the multicast packet storage.

[0039] After the multicast TLP packet is sent, update the list of target ports to be sent. If there are still unsent target ports, repeat the above process to perform target port authorization and multicast packet read and send operations for both channels. If all target ports have been sent, rollback the write pointers of mc_fifo1 and mc_fifo2 to address 0 respectively.

[0040] In summary, the present invention has achieved the following technical effects:

[0041] This invention centralizes multicast packet processing at the ingress end of the PCIe port, eliminating the need for unicast and multicast packet identification at the egress end, thus simplifying the design and implementation. Within the ingress end, unicast and multicast packets are processed separately, ensuring that multicast packet processing does not block unicast packet transmission, thereby improving the overall efficiency of the system in processing TLP packets. Furthermore, the ingress ends of all ports can process multicast packet transmission requests in parallel, and if the target ports do not overlap, they will not block each other.

[0042] This invention establishes two independent channels within the ingress for multicast packet processing. Each channel serves all possible target ports, and the two channels process and send multicast packets in parallel, dynamically coordinating to complete the transmission to all target ports. Compared to a single-channel processing method, this dual-channel approach doubles the performance. Compared to a method that binds each channel to a fixed set of ports, this approach, where each channel serves all target ports and dynamically adapts to them, avoids the possibility of target ports not being in the channel's bound port sequence, preventing resource idleness and waste, and improving the overall processing efficiency of the two channels. Compared to a design that reserves a multicast channel for each port, this dual-channel approach saves significant resources and avoids the idleness of resources on non-target ports, improving resource utilization efficiency.

[0043] This invention simultaneously opens two parallel processing channels within the multicast control module and implements multicast packet replication through rollback FIFO read / write pointers. This logically enables rapid multicast packet replication, which simplifies the design, saves resources, and improves efficiency compared to physical data transport replication. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a PCIe switch multicast processing system that balances efficiency and resources.

[0045] Figure 2 This is a diagram of the internal dual-channel processing structure of the multicast control module;

[0046] Figure 3 This is the multicast packet processing flow. Detailed Implementation

[0047] The present invention will be further described in detail below with reference to the accompanying drawings.

[0048] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

[0049] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0051] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0052] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0053] Example:

[0054] Figure 1 This is a schematic diagram of a PCIe switch multicast processing system that balances efficiency and resources, including:

[0055] The unicast control module is used to receive the target port information of the unicast TLP packet, as well as the TLP indication signal, TLP header information and TLP payload data, and assign the TLP indication signal, TLP header information and TLP payload data to the target port corresponding to the target port information, and send a unicast request; wherein, the TLP indication signal of non-target ports is set to 0, indicating that the corresponding port has not received the TLP packet;

[0056] The multicast control module is used to receive the target port list of multicast TLP packets, as well as TLP indication signals, TLP header information and TLP payload data, and to copy and send the multicast TLP packets to each target port corresponding to the target port list, and issue a multicast request.

[0057] The target port arbitration module is used to receive the unicast request and the multicast request, and after authorizing the unicast request or the multicast request, send the request packet corresponding to the unicast request or the multicast request to the sending buffer module, wherein the request packet refers to the unicast TLP packet or the multicast TLP packet;

[0058] The sending buffer module is used to receive the authorized unicast TLP packet or the multicast TLP packet, buffer it, and after obtaining authorization from the egress end of the target port, send the unicast TLP packet or the multicast TLP packet to the egress end of the target port.

[0059] In this invention, at the structural level, multicast packet processing is centralized at the ingress end of the PCIe port. When a TLP packet arrives at the egress end of the PCIe port, there is no longer a need to distinguish between unicast and multicast packets; all TLP packets are processed uniformly. Within the PCIe port ingress, unicast and multicast packets are processed separately, each following an independent processing path. They are then aggregated to an arbitration module, arbitrated, and finally sent to the egress end of the target port.

[0060] The unicast TLP packet contains N sets of TLP indication signals, a set of TLP header information, and TLP payload data; the unicast control module has N outputs corresponding to N ports, where N is a natural number greater than 1; the egress terminals of the N ports each correspond to a set of TLP indication signals and share a set of TLP header information and TLP payload data.

[0061] The multicast TLP packet contains N sets of TLP indication signals, N sets of TLP header information, and N sets of TLP payload data. The multicast control module has two built-in multicast channels, namely multicast channel 1 and multicast channel 2. Each of the two multicast channels has N outputs corresponding to N ports, where N is a natural number greater than 1. The egress terminals of the N ports correspond to one set of TLP indication signals and one set of TLP header information and TLP payload data, respectively. N refers to the number of PCIe switch ports.

[0062] This invention sets up a single processing channel for the unicast control module to process only unicast packets, and sets up two processing channels for the multicast control module to process multicast packets together. Compared with the method of using only one channel to process multicast packets, this invention doubles the efficiency, speed, and accuracy.

[0063] After a TLP packet is output from the PCIe controller, both unicast and multicast routing are performed simultaneously. If the TLP packet is a memory write request or an Msg request to perform address routing, and the packet's address falls within the multicast address range, the multicast routing result is preferred for execution; otherwise, the unicast routing result is used.

[0064] For TLP packets that are determined to be unicast packets, the target port information pointed to by the unicast routing result, as well as the TLP indication signal, TLP header information, and TLP payload data, are sent to the unicast control module. The unicast control module assigns the original TLP indication signal, TLP header information, and TLP payload data to the target port according to the target port pointed to by the unicast. The TLP indication signals of other non-target ports are all set to 0, indicating that the corresponding port has not received the TLP packet.

[0065] For TLP packets identified as multicast packets, the list of destination ports indicated by the multicast routing result, along with the TLP indication signal, TLP header information, and TLP payload data, are sent to the multicast control module. The multicast control module then copies and sends the TLP packet to each destination port based on the destination port list. Once all destination ports have been reached, the module can receive and process the next multicast packet. The multicast control module has two internal processing channels, each facing all possible destination ports and having its own independent output interface.

[0066] The target port arbitration module receives output requests from the unicast control module and multicast control module, authorizes the unicast or multicast requests according to the rules, and then sends the authorized request packets to the corresponding target port. The unicast TLP packets output by the unicast control module are directed to the egress ends of all ports, and the multicast TLP packets from the two channels output by the multicast control module are also directed to the egress ends of all ports respectively. If the PCIe switch has N ports, then the unicast control module will have N outputs. These N outputs refer to TLP indication signals (including header valid signal, data valid signal, and end signal), and each port's egress end of the PCIe switch corresponds to a set of TLP indication signals. The TLP header information and TLP payload data, however, are only one set and are shared by all port egress ends. Having N outputs does not mean that all N outputs are valid; only the TLP indication signal corresponding to the target port pointed to by the unicast packet is valid. The TLP indication signals for other ports are all 0, indicating that no valid TLP packet has been sent to the egress end of that port. The outputs of the two channels corresponding to the multicast control module are similar. Each channel corresponds to N outputs, and each output corresponds to the egress end of a port. Unlike the outputs of the unicast control module, the independent N outputs of the two channels of the multicast control module are not only independent for the TLP indicator signal for each port's egress end, but also for the TLP header information and TLP payload data. This is because multicast packets may involve address translation and ECRC recalculation, which may cause the header information and ECRC of different target ports to differ.

[0067] The target port arbitration module has N built-in arbitration sub-modules, each of which is associated with a port. The arbitration sub-modules receive unicast requests or multicast requests directed to the associated port from one unicast channel of the unicast control module and two multicast channels of the multicast control module, and perform arbitration on the requests from the three channels.

[0068] The target port arbitration module contains N arbitration sub-modules (as mentioned above, N also refers to the number of PCIeswitch ports), each associated with a specific port. Each sub-module bound to a target port receives outputs directed to that target port from both the unicast control module and the multicast control module, and then performs arbitration on these three requests. Depending on the application requirements, the specific arbitration strategy can be fixed priority arbitration, round-robin arbitration (RR), or weighted round-robin arbitration (WRR). The target port arbitration module merges unicast and multicast transmission requests, authorizes these requests sequentially, and then outputs them to the transmission buffer module.

[0069] The send buffer module receives the TLP packet output by the target port arbitration module, buffers it, and sends the TLP packet out after obtaining authorization from the egress end of the target port. After the TLP packet enters the send buffer module, it no longer distinguishes between unicast and multicast packets, and all subsequent processing procedures are shared by unicast and multicast packets.

[0070] This invention centralizes multicast packet processing at the ingress end, while separating unicast and multicast processing, which helps improve the overall processing efficiency of the system.

[0071] If unicast and multicast packets share a processing channel and are processed together, multicast packets may block unicast packets, even if the destination ports of the multicast and unicast packets do not conflict. Multicast packets are destined for multiple ports, and they need to be stored for replication until all destination ports have finished sending. If a unicast packet request arrives at this time, it cannot bypass the multicast packet because it is still being processed, and must wait passively. Even if the destination ports of the unicast and multicast packets do not overlap, the transmission cannot be completed.

[0072] This situation can be avoided by separating unicast and multicast processing and using different processing channels. When the destination port of a unicast packet and the destination port of a multicast packet do not conflict, unicast and multicast packets can be processed in parallel without blocking each other. New multicast processing can also be initiated simultaneously at the ingress end of other PCIe switch ports. If the destination ports of different multicast groups do not overlap, they are sent independently at the egress end of their respective destination ports; if the destination ports of different multicast groups overlap, arbitration is performed at the egress end of the overlapping destination ports, authorizing transmission separately.

[0073] Furthermore, at the specific processing level of multicast packets, two multicast processing channels are simultaneously established within the multicast control module. Each channel has an independent buffer, and the output of each channel is not bound to the egress end of a fixed port group, but rather to the egress ends of all possible target ports. The two channels poll the multicast target port list in parallel and send multicast packets to different target ports in parallel. The two channels cooperate to complete the transmission of all multicast target ports. Compared to the single-channel processing method, this dual-channel approach doubles the performance; compared to the processing method that binds each channel to a fixed set of ports, this method, where each channel serves all target ports and dynamically adapts to target ports, avoids the possibility of target ports not being in the channel's bound port sequence, avoids resource idleness and waste, and improves the overall processing efficiency of the two channels; compared to the processing method that reserves a multicast channel for each port, this dual-channel approach saves a lot of resources and avoids the situation where resources of non-target ports are idle, thus improving resource utilization efficiency.

[0074] Furthermore, when moving multicast packet data to different target ports, the rollback internal buffer FIFO read / write pointer method is used to achieve write-once read-once replication. Compared with the physical method of repeatedly writing and reading multicast packet data to achieve replication, this simplifies the design, saves resources, and improves efficiency.

[0075] Figure 2 This is a diagram of the internal dual-channel processing structure of the multicast control module, which has built-in...

[0076] Channel 1 buffer mc_fifo1 and channel 2 buffer mc_fifo2 are used to store the TLP indication signal and the TLP payload data carried by the multicast TLP packet;

[0077] The mc_fifo1 read / write control module and the mc_fifo2 read / write control module are used to implement read / write control of the channel 1 cache mc_fifo1 and the channel 2 cache mc_fifo2, respectively.

[0078] info_fifo is used to store multicast target port information and the TLP header information of the multicast TLP packet;

[0079] The info_fifo read / write control module is used to implement read / write control of the info_fifo file.

[0080] The target port management module is used to manage target ports that have not yet been sent or have not yet completed the sending process.

[0081] The Channel 1 authorization request module and the Channel 2 authorization request module are used to provide the target port indication for the multicast TLP packet to be sent to multicast Channel 1 and multicast Channel 2, respectively.

[0082] The channel 1 transmitting module is used to buffer the TLP indication signal, TLP payload data and TLP header information output by mc_fifo1 in channel 1, assign them to the TLP information corresponding to the target port of channel 1, and send them to the arbitration module of the target port.

[0083] The channel 2 transmitting module is used to buffer the TLP indication signal, TLP payload data and TLP header information output by mc_fifo2 in channel 2, assign them to the TLP information corresponding to the target port of channel 2, and send them to the arbitration module of the target port.

[0084] Combination Figure 2 The multicast control module integrates FIFO-based buffers, specifically: channel 1 buffer mc_fifo1, channel 2 buffer mc_fifo2, and info_fifo. mc_fifo1 and mc_fifo2 store multicast TLP indication signals and the carried TLP payload data; their capacity is sufficient to store the data of a single maximum payload TLP packet. info_fifo stores multicast target port information and multicast TLP header information; all this information is stored together as a single entry, and the FIFO depth is set to 1.

[0085] The other modules integrated within the multicast control module are all used to implement control and management functions.

[0086] The info_fifo read / write control module, as its name suggests, is responsible for controlling the read and write operations of the info_fifo file.

[0087] The write enable condition for Info_fifo is: a valid multicast packet is received and Info_fifo is not full;

[0088] The read enable condition for Info_fifo is: info_fifo is not empty and multicast packets have been sent to all multicast target ports. At this time, a read operation can be performed on info_fifo. Reading it to empty means that new multicast packets can be received and processed.

[0089] The mc_fifo1 read / write control module, as its name suggests, is responsible for controlling the read and write operations of the channel 1 buffer mc_fifo1.

[0090] The conditions for enabling mc_fifo1 to write are: mc_fifo1 is not full and a valid multicast packet has been received;

[0091] The conditions for enabling mc_fifo1 to read are: the multicast packet has been completely written into mc_fifo1 and the target port assigned to channel 1 is in an idle state and can receive TLP packets;

[0092] The conditions for ending the mc_fifo1 read enable and rolling back the read pointer are as follows: When the end indicator signal of the multicast packet is received, that is, the multicast packet has been completely read and sent, the read pointer is rolled back to address 0 to prepare for the next round of read operations to be sent to another target port.

[0093] The condition for mc_fifo1 to rollback the write pointer is: multicast packets have been sent to all target ports. At this time, the write pointer will be rolled back to address 0 to prepare for receiving new multicast packets.

[0094] The mc_fifo2 read / write control module, as its name suggests, implements read / write control for the channel 2 cache mc_fifo2. While the implementation details of mc_fifo2's read / write control differ from those of mc_fifo1, the design principles remain the same, and will not be elaborated upon here.

[0095] The pending target port management module manages target ports that have not yet been sent or have not completed sending. This module is the core hub of the entire multicast control module, acting as a progress bar for multicast task processing. As long as there are still target ports that have not been sent or have not completed sending, both multicast processing channels, or at least one multicast processing channel, must remain active until the pending target port list displays 0, meaning all target ports pointed to by the multicast have been sent. Only then is the processing of the multicast packet considered complete. At the beginning of receiving multicast packets and before the sending operation is executed, the pending target port list is... Figure 1 The result of the multicast routing module matching is the multicast target port. The list of target ports to be sent is sent to the channel 1 authorization request module and the channel 2 authorization request module, respectively, indicating the target port numbers that need to be sent to channel 1 and channel 2. Based on the multicast packet transmission completion information provided by the mc_fifo1 read / write control module and the mc_fifo2 read / write control module, it indicates that the currently allocated target ports have been sent, updates the list of target ports to be sent, and removes the target ports that have been sent. The updated list of target ports to be sent is then sent to the channel 1 authorization request module and the channel 2 authorization request module to execute a new round of authorization transmission operations. When the list of target ports to be sent is 0, it means that the processing of this multicast packet is over, and the buffers in the modules (mc_fifo1 / mc_fifo2 / info_fifo) can be cleared to receive new multicast packets for processing.

[0096] The Channel 1 authorization request module provides multicast channel 1 with a target port indication for multicast packet transmission, while the Channel 2 authorization request module provides multicast channel 2 with a target port indication for message transmission. Both modules receive an initial request list from the pending port management module. For the Channel 1 authorization request module, it needs to remove the target port number currently being transmitted by Channel 2 from the initial list of pending target ports. This is because Channel 2's transmission processing for that target port is not yet complete, and the target port number still exists in the pending target port list. To avoid duplicate authorization for the same target port by two channels, the target port currently being processed by Channel 2 needs to be removed from Channel 1's pending authorization request list. Similarly, for the Channel 2 authorization request module, it also needs to remove the target port currently being processed by Channel 1 from its pending authorization request list. The pending target ports in the Channel 1 and Channel 2 authorization request lists largely overlap. To avoid two channels authorizing the same target port at the same time, the two modules are designed to poll the request lists from different directions for authorization. For example, the channel 1 authorization request module queries for authorization from the least significant digit to the most significant digit in the target port request list, while the channel 2 authorization request module queries for authorization from the most significant digit to the least significant digit in the target port request list. The two channels simultaneously advance the transmission task for the target port from different directions. If both channels have completed the transmission for the previous target port, and only one target port remains to be transmitted, a specific channel can be designated to complete the transmission for the last target port.

[0097] The channel 1 transmitting module assigns the TLP indicator signal, TLP payload data, and TLP header information output from the channel 1 buffer mc_fifo1 to the corresponding TLP information of the target port of channel 1, and then outputs it to... Figure 1 The next level module indicated is the target port arbitration module. The processing logic of the channel 2 sending module is the same as that of the channel 1 sending module.

[0098] In another embodiment, a PCIe switch multicast processing method that balances efficiency and resources is provided, including the following steps:

[0099] S100. Determine whether the TLP packet is unicast or multicast. The determination method is as follows: After the TLP packet is output from the PCIe controller, both unicast and multicast routing are executed simultaneously. If the TLP packet is a memory write request or an Msg request to execute address routing, and the address of the packet falls within the multicast address range, then the multicast routing result is executed first; otherwise, the unicast routing result is executed.

[0100] S210. For unicast TLP packet processing, receive the target port information of the unicast TLP packet, as well as the TLP indicator signal, TLP header information and TLP payload data, and assign the TLP indicator signal, TLP header information and TLP payload data to the target port corresponding to the target port information, and send a unicast request; wherein, the TLP indicator signal of non-target ports is set to 0, indicating that the corresponding port has not received the TLP packet;

[0101] S220. For multicast TLP packet processing, receive the target port list of the multicast TLP packet, as well as the TLP indication signal, TLP header information and TLP payload data, and copy and send the multicast TLP packet to each target port corresponding to the target port list, and issue a multicast request.

[0102] S300. Receive the unicast request and the multicast request, and after authorizing the unicast request or the multicast request, send the request packet corresponding to the unicast request or the multicast request to the sending cache module, wherein the request packet refers to the unicast TLP packet or the multicast TLP packet.

[0103] S400: Receive the authorized unicast TLP packet or the multicast TLP packet, buffer it, and after obtaining authorization from the egress end of the target port, send the unicast TLP packet or the multicast TLP packet to the egress end of the target port.

[0104] Specifically, the processing of multicast TLP packets includes the following sub-steps:

[0105] Get List: Retrieves an initial list of target ports to be sent;

[0106] Authorized write: Based on the initial list of target ports to be sent, generate the sending request list for multicast channel 1 and the sending request list for multicast channel 2 respectively, and perform authorization operations on the sending request list of multicast channel 1 and the sending request list of multicast channel 2 in priority order, and write the authorized target port number into the mc_fifo1 read and write control module of channel 1 cache mc_fifo1 and the mc_fifo2 read and write control module of channel 2 cache mc_fifo2 respectively;

[0107] Sending data: Based on the authorized target port number received by each of the two multicast channels, multicast TLP packet data is read from the buffer mc_fifo1 of channel 1 and the buffer mc_fifo2 of channel 2, and sent to their respective target ports.

[0108] The process of obtaining the list includes the following sub-steps:

[0109] Check if info_fifo is empty. If it is not empty, it indicates that a multicast TLP packet is being processed. At this time, the backpressure signal is set high to notify the external multicast packet to request hold and wait for reception. If info_fifo is empty, the multicast target port information and the TLP header information of the multicast TLP packet are written to info_fifo. The TLP indicator signal and TLP payload data of the multicast TLP packet are written to the channel 1 buffer mc_fifo1 and the channel 2 buffer mc_fifo2. At the same time, the multicast target port information is recorded as the initial list of target ports to be sent.

[0110] The authorization writing includes the following sub-steps:

[0111] In a multicast process, the sending request list of channel 1 excludes authorized target ports that multicast channel 2 is currently sending to, and the sending request list of channel 2 excludes authorized target ports that multicast channel 1 is currently sending to. Multicast channel 1 polls the sending target port request list in a round-robin order from low to high priority, and the authorized target port number is notified to the read / write control module of the mc_fifo1 cache in channel 1. Multicast channel 2 polls the sending target port request list in a round-robin order from high to low priority, and the authorized target port number is notified to the read / write control module of the mc_fifo2 cache in channel 2.

[0112] The data transmission includes the following sub-steps:

[0113] After all the multicast TLP packets have been written to the channel 1 buffer mc_fifo1 and the channel 2 buffer mc_fifo2, the two channels read the multicast TLP packet data from mc_fifo1 and mc_fifo2 respectively according to the authorized target port number they received, and send it to their respective target ports. When the two channels finish sending the multicast packets, they rollback their respective read pointers to address 0, which is the starting position of the multicast packet storage.

[0114] After the multicast TLP packet is sent, update the list of target ports to be sent. If there are still unsent target ports, repeat the above process to perform target port authorization and multicast packet read and send operations for both channels. If all target ports have been sent, rollback the write pointers of mc_fifo1 and mc_fifo2 to address 0 respectively.

[0115] Among them, TLP package Figure 1 The output of the PCIe controller shown is then processed by... Figure 1 Once the multicast routing module matches and determines that the packet is a multicast packet, it sends it to the multicast control module.

[0116] Figure 3This is the multicast packet processing flow. After receiving a multicast processing request, the multicast control module first checks if info_fifo is empty. If it is not empty, it means that a multicast packet is being processed. At this time, the multicast control module sets the backpressure signal high to notify the external multicast packet request to hold and wait for reception. If info_fifo is empty, the multicast target port information and multicast TLP header information are written to info_fifo. The multicast packet TLP indicator signal and TLP payload data are written to channel 1 buffer mc_fifo1 and channel 2 buffer mc_fifo2. At the same time, the multicast target port information is recorded as the initial list of target ports to be sent.

[0117] Based on the initial list of target ports to be sent, send request lists for Channel 1 and Channel 2 are generated respectively. The send request list for Channel 1 excludes authorized target ports currently being sent by Channel 2, and vice versa. Channel 1 polls the send target port request list in ascending order of priority, granting authorization and notifying the read / write control module of the cache mc_fifo1 of the authorized target port number. Channel 2 polls the send target port request list in descending order of priority, granting authorization and notifying the read / write control module of the cache mc_fifo2 of the authorized target port number.

[0118] After all multicast packets have been written to the channel 1 buffer mc_fifo1 and the channel 2 buffer mc_fifo2, the two channels read the multicast packet data from mc_fifo1 and mc_fifo2 respectively according to the authorized target port number they received, and send it to their respective target ports. When the two channels finish sending the multicast packets, they rollback their respective read pointers to address 0, which is the starting position of the multicast packet storage.

[0119] After the multicast packet is sent, the list of target ports to be sent is updated. If there are still unsent target ports, the above process is repeated, performing target port authorization and multicast packet read / send operations for both channels. If all target ports have been sent, the write pointers of mc_fifo1 and mc_fifo2 are rolled back to address 0. Before the write pointers are rolled back to address 0, the read pointers have also been rolled back to address 0, which is equivalent to clearing the buffers mc_fifo1 / mc_fifo2 of both channels, restoring them to the initial state of waiting to receive new multicast packets. At the same time, info_fifo is also read empty, so the entire system returns to the initial state of waiting to receive multicast packets, and new multicast packet processing can begin. It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A PCIe switch multicast processing system that balances efficiency and resources, comprising: The application relates to a TLP (Transaction Layer Packet) control module, which comprises the following modules: a unicast control module, which is used for receiving target port information of a unicast TLP packet, and TLP indication signals, TLP header information and TLP load data, and assigning the TLP indication signals, the TLP header information and the TLP load data to target ports corresponding to the target port information, and issuing a unicast request; wherein the TLP indication signals of non-target ports are all set to 0, indicating that the corresponding ports have not received the TLP packet; a multicast control module, which is used for receiving target port list information of a multicast TLP packet, and TLP indication signals, TLP header information and TLP load data, and copying and sending the multicast TLP packet to each target port corresponding to the target port list information, and issuing a multicast request; a target port arbitration module, which is used for receiving the unicast request and the multicast request, and sending a request packet corresponding to the unicast request or the multicast request to a sending cache module after the unicast request or the multicast request is authorized, wherein the request packet refers to the unicast TLP packet or the multicast TLP packet; a sending cache module, which is used for receiving the authorized unicast TLP packet or multicast TLP packet, and caching the unicast TLP packet or the multicast TLP packet, and sending the unicast TLP packet or the multicast TLP packet to an egress end of a target port after the egress end of the target port is authorized.

2. The PCIe switch multicast processing system with efficiency and resource consideration of claim 1, wherein: The unicast TLP packet has N groups of the TLP indication signals and one group of the TLP header information and TLP load data; the unicast control module is provided with N output paths for corresponding to N ports, and N is a natural number greater than 1; the egress ends of the N ports correspond to one group of the TLP indication signals respectively, and share one group of the TLP header information and TLP load data. 3.The PCIe switch multicast processing system with consideration of efficiency and resources of claim 1, wherein: The multicast TLP packet has N groups of the TLP indication signals and N groups of the TLP header information and TLP load data; the multicast control module is internally provided with two multicast channels, namely a multicast channel 1 and a multicast channel 2, and the two multicast channels are respectively provided with N output paths for corresponding to N ports, and N is a natural number greater than 1; the egress ends of the N ports correspond to one group of the TLP indication signals and one group of the TLP header information and TLP load data respectively.

4. The PCIe switch multicast processing system with consideration of efficiency and resources of claim 3, wherein: The multicast control module is internally provided with: a channel 1 cache mc_fifo1 and a channel 2 cache mc_fifo2, which are used for storing the TLP indication signals and the carried TLP load data of the multicast TLP packet; an mc_fifo1 read-write control module and an mc_fifo2 read-write control module, which are respectively used for realizing read-write control of the channel 1 cache mc_fifo1 and the channel 2 cache mc_fifo2; an info_fifo, which is used for storing multicast target port information and the TLP header information of the multicast TLP packet; an info_fifo read-write control module, which is used for realizing read-write control of the info_fifo; a to-be-sent target port management module, which is used for realizing management of target ports which have not been sent or have not been sent completely. The channel 1 request authorization module and the channel 2 request authorization module are respectively used for providing multicast TLP packet sending target port indication for multicast channel 1 and multicast channel 2; The channel 1 sending module is used for assigning the TLP indication signal, the TLP load data output by the channel 1 buffer mc_fifo1 and the TLP header information output by the info_fifo to the TLP information corresponding to the target port corresponding to the channel 1, and sending to the target port arbitration module; The channel 2 sending module is used for assigning the TLP indication signal, the TLP load data output by the channel 2 buffer mc_fifo2 and the TLP header information output by the info_fifo to the TLP information corresponding to the target port corresponding to the channel 2, and sending to the target port arbitration module.

5. The PCIe switch multicast processing system with efficiency and resource consideration of claim 1, wherein: The target port arbitration module is internally provided with N arbitration submodules, and the N arbitration submodules are respectively associated with one port; The arbitration submodule receives the unicast request or the multicast request directed to the associated port from one unicast channel of the unicast control module and two multicast channels of the multicast control module, and performs arbitration on the requests of the three channels.

6. A PCIe switch multicast processing method with efficiency and resource, characterized in that: The application is applied to the PCIe switch multicast processing system with efficiency and resource in any one of claims 1-5, The application comprises the following steps, Judging whether a TLP packet is unicast or multicast; For unicast TLP packet processing, receiving target port information of a unicast TLP packet, and TLP indication signal, TLP header information and TLP load data, and assigning the TLP indication signal, the TLP header information and the TLP load data to the target port corresponding to the target port information, and issuing a unicast request; wherein the TLP indication signal of a non-target port is set to 0, indicating that the corresponding port has not received a TLP packet; For multicast TLP packet processing, receiving a target port list of a multicast TLP packet, and TLP indication signal, TLP header information and TLP load data, and copying and sending the multicast TLP packet to each target port corresponding to the target port list, and issuing a multicast request; Receiving the unicast request and the multicast request, authorizing the unicast request or the multicast request, and then sending the request packet corresponding to the unicast request or the multicast request to a sending buffer module, wherein the request packet refers to the unicast TLP packet or the multicast TLP packet; Receiving the authorized unicast TLP packet or multicast TLP packet, and buffering the same, and then sending and outputting the unicast TLP packet or the multicast TLP packet to the egress end of the target port after obtaining the authorization of the egress end of the target port.

7. The PCIe switch multicast processing method with efficiency and resource consideration according to claim 6, characterized in that: The multicast TLP packet processing specifically comprises the following sub-steps: List acquisition: acquiring an initial list of target ports to be sent; Grant write: generate multicast channel 1 sending request list and multicast channel 2 sending request list according to initial list of target ports to be sent, and perform grant operation on multicast channel 1 sending request list and multicast channel 2 sending request list in priority order, and write granted target port numbers into mc_fifo1 read-write control module of channel 1 cache mc_fifo1 and mc_fifo2 read-write control module of channel 2 cache mc_fifo2 respectively; Send data: read multicast TLP packet data from channel 1 cache mc_fifo1 and channel 2 cache mc_fifo2 according to received granted target port numbers of two multicast channels respectively, and send to corresponding target ports.

8. The PCIe switch multicast processing method with efficiency and resource consideration according to claim 7, characterized in that: The obtaining list comprises the following sub-steps: judging whether the info_fifo is empty or not, if not empty, it indicates that multicast TLP packet is being processed, at this time, the back pressure signal is set high to output, informing the external multicast packet request to be kept, and waiting for receiving; if the info_fifo is empty, write multicast target port information and TLP header information of multicast TLP packet into the info_fifo, write TLP indication signal and TLP load data of multicast TLP packet into channel 1 cache mc_fifo1 and channel 2 cache mc_fifo2, and record the multicast target port information as initial list of target ports to be sent.

9. The PCIe switch multicast processing method with efficiency and resource consideration of claim 7, wherein: The grant write comprises the following sub-steps: The multicast channel 1 sending request list excludes the granted target port being sent by multicast channel 2, and the multicast channel 2 sending request list excludes the granted target port being sent by multicast channel 1; the multicast channel 1 performs polling grant on the sending target port request list in priority order from low to high, and the granted target port number informs the read-write control module of channel 1 cache mc_fifo1; the multicast channel 2 performs polling grant on the sending target port request list in priority order from high to low, and the granted target port number informs the read-write control module of channel 2 cache mc_fifo2.

10. The PCIe switch multicast processing method with efficiency and resource consideration of claim 7, wherein: The send data comprises the following sub-steps: When the multicast TLP packet has been written into channel 1 cache mc_fifo1 and channel 2 cache mc_fifo2 completely, two channels read multicast TLP packet data from mc_fifo1 and mc_fifo2 according to received granted target port numbers respectively, and send to corresponding target ports, when two channels finish sending multicast packet, respectively rollback the read pointer to 0 address position, i.e. the start position of multicast packet storage; After the multicast TLP packet is sent completely, update the list of target ports to be sent, if there is still an unsent target port, repeat the above process to perform target port grant and multicast packet read and send operation of two channels; if all target ports have been sent completely, rollback the write pointer of mc_fifo1 and mc_fifo2 to 0 address position respectively.

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