GaN-based power transistor structure with mixed gate

Abstract

Provided is a hybrid gate GaN-based power transistor structure, comprising: a laminated structure, wherein the laminated structure comprises: a substrate; a GaN buffer layer disposed on the substrate; and an Al(In, Ga) GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; a source structure disposed on a first end of the laminated structure; and a drain structure disposed on a second end of the laminated structure opposite the source structure; and a gate structure disposed on the laminated structure and between the first end and the second end, wherein the gate structure comprises: a p-(In, Al) GaN epitaxial layer disposed on the laminated structure; a doped layer disposed on a side of the p-(In, Al) GaN epitaxial layer away from the laminated structure; and a first gate metal layer disposed on a side of the doped layer away from the laminated structure, wherein the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is located between the plurality of n-type doped regions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a GaN-based power transistor structure with a hybrid gate. BACKGROUND

[0002] GaN-based power electronic devices have high breakdown field, good mobility, high carrier density and good thermal conductivity, and are rapidly commercialized for power switching applications. The current mainstream commercial enhancement (normally off) GaN-based transistor product is realized based on a p-(Al) GaN gate, but it has a compromise problem of reliability, stability and gate leakage. The transistor with an ohmic contact gate has high threshold stability, but has a large gate leakage, which increases power consumption; the Schottky contact gate can suppress the gate leakage, but has a gate reliability problem, that is, the Schottky gate interface is easy to damage at a high gate voltage, so the gate voltage working range is narrow, which is not conducive to suppressing gate ringing and mis-conduction in high-frequency power switching applications; the pn junction gate has reliable gate and wide gate voltage working range, and further reduces the gate leakage, but also aggravates the threshold instability caused by the floating of the p-(Al) GaN gate region, which worsens the dynamic performance of the power transistor and reduces the power conversion efficiency of the transistor.

[0003] Therefore, how to realize good gate reliability to obtain a larger gate drive swing required for safe operation and a more stable threshold to realize good dynamic performance under the premise of low gate leakage is currently very necessary.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information that does not constitute prior art known to those skilled in the art. SUMMARY

[0005] (I) Technical problem to be solved

[0006] In view of the problem that several existing p-(Al) GaN gate-based GaN-based enhancement power electronic devices have difficulty in simultaneously optimizing gate reliability, threshold stability and gate leakage, the present application discloses a GaN-based power transistor structure with a hybrid gate, which is based on a high-reliability pn junction gate structure, and a small p-type region is introduced to electrically connect the gate metal and the p-(In, Al) GaN inside, forming a dynamic leakage path, which can improve the threshold stability without increasing the gate leakage. The present application can simultaneously realize reliable gate, stable threshold and low gate leakage, and has important value for the development of commercial enhancement GaN-based power electronics.

[0007] (II) Technical solution

[0008] One aspect of the present application discloses a hybrid-gate GaN-based power transistor structure, comprising: a stack structure, wherein the stack structure comprises: a substrate; a GaN buffer layer disposed on the substrate; and an Al(In, Ga) GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; a source structure disposed at a first end of the stack structure; and a drain structure disposed at a second end of the stack structure opposite to the source structure; and a gate structure disposed on the stack structure and between the first end and the second end, wherein the gate structure comprises: a p-(In, Al) GaN epitaxial layer disposed on the stack structure; a doped layer disposed on a side of the p-(In, Al) GaN epitaxial layer away from the stack structure; and a first gate metal layer disposed on a side of the doped layer away from the stack structure, wherein the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is located between the plurality of n-type doped regions.

[0009] According to some embodiments of the present application, the at least one p-type doped region is surrounded by the plurality of n-type doped regions.

[0010] According to some embodiments of the present application, the p-type doped region comprises m p-type sub-doped regions, wherein m is equal to 1; or the p-type doped region comprises m p-type sub-doped regions, the m p-type sub-doped regions are spaced apart from each other along a first direction, wherein m is a positive integer greater than or equal to 2; or the p-type doped region comprises m p-type sub-doped regions, the m p-type sub-doped regions are spaced apart from each other along both the first direction and a second direction, wherein m is a positive integer greater than or equal to 4.

[0011] According to some embodiments of the present application, a projection of each of the p-type sub-doped regions on the substrate has a first width in the first direction, and the first width is 5-1000 nm.

[0012] According to some embodiments of the present application, a projection of the p-type doped region on the substrate is located within a projection of the first gate metal layer on the substrate, and an ohmic contact is formed between the p-type doped region and the first gate metal layer; and a projection of the n-type doped region on the substrate partially overlaps with a projection of the first gate metal layer on the substrate, and a Schottky contact is formed between the n-type doped region and the first gate metal layer.

[0013] According to some embodiments of the present application, a projection of each of the m p-type sub-doped regions on the substrate is strip-shaped; or a projection of each of the m p-type sub-doped regions on the substrate is rectangular; or a projection of each of the m p-type sub-doped regions on the substrate is circular.

[0014] According to some embodiments of the present application, the hybrid-gate GaN-based power transistor structure further comprises a second gate metal layer, the second gate metal layer is disposed on a side of the first gate metal layer away from the substrate, or the second gate metal layer is disposed between the doped layer and the first gate metal layer; the second gate metal layer is electrically connected with the first gate metal layer; and an ohmic contact is formed between the second gate metal layer and the n-type doped region.

[0015] According to some embodiments of the present application, the bulk material of the doped layer comprises one or more of a combination of (In, Al) GaN, polysilicon, NiO, diamond; and / or, the thickness of the doped layer is 5-500 nm; and / or, the doping concentration of the p-type doped region is 10 17 -10 21 cm -3 ; and / or, the doping concentration of the n-type doped region is 10 17 -10 21 cm -3 .

[0016] According to some embodiments of the present application, the thickness of the p-(In, Al) GaN epitaxial layer is 10-500 nm; and / or, the doping concentration of the p-(In, Al) GaN epitaxial layer is 10 17 -10 21 cm -3 .

[0017] According to some embodiments of the present application, the doping in the p-(In, Al) GaN epitaxial layer can be uniform doping; and / or, the doping in the p-(In, Al) GaN epitaxial layer can be a gradual doping from top to bottom.

[0018] According to some embodiments of the present application, the orthogonal projection of the p-type doped region on the substrate coincides with the orthogonal projection of the first gate metal layer on the substrate, an ohmic contact is formed between the first gate metal layer and the p-type doped region; and the hybrid-gate GaN-based power transistor structure further comprises: a second gate metal layer, the second gate metal layer is located on a side of the first gate metal layer away from the substrate, wherein the second gate metal layer is electrically connected with the first gate metal layer; and an ohmic contact is formed between the second gate metal layer and the n-type doped region.

[0019] According to some embodiments of the present application, the orthogonal projection of the first gate metal layer on the substrate has a second width in a first direction, the orthogonal projection of the p-(In, Al) GaN epitaxial layer on the substrate has a third width in the first direction, and the second width is less than or equal to the third width.

[0020] According to some embodiments of the present application, the work function of the first gate metal layer ranges from 5.0 to 6.5 eV; and / or, the work function of the second gate metal layer ranges from 4.0 to 5.5 eV.

[0021] Another aspect of the present application discloses a hybrid-gate GaN-based power transistor structure, comprising: a stack structure, wherein the stack structure comprises: a substrate; a GaN buffer layer disposed on the substrate; and an Al(In,Ga)GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; a source structure disposed at a first end of the stack structure; and a drain structure disposed at a second end of the stack structure opposite to the source structure; and a gate structure disposed on the stack structure and between the first end and the second end, wherein the gate structure comprises: a p-(In,Al)GaN epitaxial layer disposed on the stack structure; a doped layer disposed on a side of the p-(In,Al)GaN epitaxial layer away from the stack structure; and a first gate metal layer disposed on a side of the doped layer away from the stack structure, wherein the doped layer comprises at least one via and a plurality of n-type doped regions, the at least one via is between the plurality of n-type doped regions; and the first gate metal layer forms an ohmic contact with the p-(In,Al)GaN epitaxial layer through the at least one via.

[0022] (III) Advantages

[0023] One aspect of the present application discloses a hybrid gate GaN-based power transistor structure, comprising: a stack structure, wherein the stack structure comprises: a substrate; a GaN buffer layer disposed on the substrate; and an Al(In, Ga) GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; a source structure disposed at a first end of the stack structure; and a drain structure disposed at a second end of the stack structure opposite the source structure; and a gate structure disposed on the stack structure and between the first end and the second end, wherein the gate structure comprises: a p-(In, Al) GaN epitaxial layer disposed on the stack structure; a doped layer disposed on a side of the p-(In, Al) GaN epitaxial layer away from the stack structure; and a first gate metal layer disposed on a side of the doped layer away from the stack structure, wherein the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is between the plurality of n-type doped regions. By disposing a doped layer on the p-(In, Al) GaN gate, wherein the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is between the plurality of n-type doped regions, a p-type dynamic leakage path can be introduced on the basis of the pn junction gate with high voltage resistance and high reliability, the stability of the device is improved, the dynamic characteristics are improved, and the gate leakage is kept at a low level. The beneficial effects of the present application are as follows:

[0024] 1. High gate reliability is achieved by using a reverse-biased pn junction gate, and a large gate swing and working life are achieved.

[0025] 2. A p-type region is introduced, which connects the gate metal and the p-(In, Al) GaN epitaxial layer as a p-type dynamic leakage path. The path is in an open state at a low gate voltage, providing a charge leakage path to achieve high threshold stability; at a high gate voltage, the path is pinched off by the extension of the depletion regions on both sides, reducing the gate leakage current.

[0026] 3. The simultaneous optimization of gate reliability, stability and leakage characteristics of the hybrid gate GaN-based power transistor is achieved, which has great significance for the development of future GaN power transistors. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a structure diagram of a hybrid gate GaN-based power transistor structure according to an embodiment of the present application;

[0029] Figure 2is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0030] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D are respectively a top plan schematic diagram of a doping layer in a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0031] Figure 4 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0032] Figure 5 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0033] Figure 6 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0034] Figure 7 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0035] Figure 8 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0036] Figure 9 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application;

[0037] Figure 10 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application.

[0038] It should be noted that, for the sake of clarity, the size of a layer, structure or region can be exaggerated or reduced in the drawings used to describe embodiments of the present application, i.e. these drawings are not drawn to scale. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application.

[0040] It should be noted that in the drawings, the size and relative size of the elements can be exaggerated for clarity and / or descriptive purposes. Thus, the size and relative sizes of the elements in the drawings are not necessarily drawn to scale. In the description and drawings, identical or similar reference numerals indicate identical or similar components.

[0041] Unless otherwise defined, technical terms or scientific terms used in the present application should be understood as having the common meaning to those of ordinary skill in the art. The terms "first", "second" and similar words of comparison used in the present application do not indicate any order, number or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar words mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, and do not exclude other elements or objects.

[0042] In this document, unless otherwise specifically stated, directional terms such as "upper", "lower", "left", "right", "inner", "outer" and the like are used with reference to the orientation or position shown in the drawings, only for the convenience of describing the present application, and do not indicate or imply that the devices, elements or components referred to must have a particular orientation, be constructed or operated in a particular orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms cannot be understood as a limitation on the present application.

[0043] At least some embodiments of the present application provide a GaN-based p-(In, Al) GaN gate enhancement mode power transistor structure with a hybrid gate. On the basis of a high-reliability pn junction gate structure, by introducing a small p-type region to electrically connect the metal and the p-(In, Al) GaN, a dynamic leakage path is formed, which can improve the threshold stability without increasing the gate leakage. The present application can realize reliable gate, stable threshold and low gate leakage at the same time, which can greatly improve the stability performance of enhancement mode GaN-based power electronics and expand the application scenarios of enhancement mode GaN-based power electronics.

[0044] Figure 1 is a structure diagram of a GaN-based power transistor structure with a hybrid gate according to an embodiment of the present application.

[0045] Exemplarily, in some embodiments of the present application, referring to FIG. 1, a hybrid gate GaN-based power transistor structure includes: a stack structure 1, wherein the stack structure 1 includes: a substrate 11; a GaN buffer layer 12 disposed on the substrate 11; and an Al(In, Ga)GaN barrier layer 13 disposed on a side of the GaN buffer layer 12 away from the substrate 11; a source structure 2 disposed on a first end S1 of the stack structure 1; and a drain structure 3 disposed on a second end S2 of the stack structure 1 opposite the source structure 2; and a gate structure 4 disposed on the stack structure 1 and between the first end S1 and the second end S2, wherein the gate structure 4 includes: a p-(In, Al)GaN epitaxial layer 41 disposed on the stack structure 1; a doped layer 42 disposed on a side of the p-(In, Al)GaN epitaxial layer 41 away from the stack structure 1; and a first gate metal layer 43 disposed on a side of the doped layer 42 away from the stack structure 1, wherein the doped layer 42 includes at least one p-type doped region 421 and a plurality of n-type doped regions 422, and the at least one p-type doped region 421 is located between the plurality of n-type doped regions 422. The plurality of n-type doped regions 422 in the doped layer 42 and the p-(In, Al)GaN epitaxial layer 41 form a pn junction, which can share the gate electric field under a positive gate voltage, thereby ensuring that the transistor has high reliability and low leakage characteristics. Further, by introducing a small p-type region to electrically connect the first gate metal layer 43 and the p-(In, Al)GaN epitaxial layer 41, a dynamic leakage path is formed, which can balance the charge accumulated in the p-(In, Al)GaN epitaxial layer 41 during the switching operation of the transistor, achieve a stable threshold, and thereby improve the threshold stability of the transistor.

[0046] Figure 2 is a structural schematic diagram of a hybrid gate GaN-based power transistor structure according to some embodiments of the present application.

[0047] Exemplarily, referring to Figure 2The doping layer 42 can include a plurality of p-type doped sub-regions 4211 and a plurality of n-type doped regions 422, the plurality of p-type doped sub-regions 4211 are arranged at intervals between the plurality of n-type doped regions 422, that is, each of the plurality of p-type doped sub-regions 4211 is surrounded by the plurality of n-type doped regions 422, the plurality of p-type doped sub-regions 4211 can be in contact with the first gate metal layer 43 located on the side of the doping layer 42 away from the substrate, and the plurality of p-type doped sub-regions 4211 can be electrically connected to the p-(In, Al) GaN layer located on the side of the doping layer 42 close to the substrate, thereby forming a plurality of electrical connection paths between the first gate metal layer 43 and the p-(In, Al) GaN epitaxial layer 41, which can more efficiently leak the charges accumulated in the p-(In, Al) GaN epitaxial layer 41 during the switching operation of the transistor, and faster to reach a stable threshold, thereby improving the threshold stability of the transistor.

[0048] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D are respectively top view schematic diagrams of a doping layer in a hybrid gate GaN-based power transistor structure according to some embodiments of the present application.

[0049] Exemplarily, in some embodiments of the present application, in combination with reference to Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D , the at least one p-type doped region 421 is surrounded by the plurality of n-type doped regions 422.

[0050] Preferably, the p-type doped region 421 can include m p-type doped sub-regions 4211, where m is equal to 1. For example, referring to Figure 3A , the p-type doped region can include only one p-type doped sub-region 4211. The orthogonal projection of the only one p-type doped sub-region 4211 on the substrate 11 can be a strip.

[0051] Preferably, the p-type doped region 421 can include m p-type doped sub-regions 4211, the m p-type doped sub-regions 4211 are arranged at intervals along a first direction X, where m is a positive integer greater than or equal to 2. For example, referring to Figure 3B , the p-type doped region 421 can include a plurality of p-type doped sub-regions 4211, the orthogonal projection of each of the plurality of p-type doped sub-regions 4211 on the substrate 11 can be a strip. That is, the doping layer 42 can include a plurality of strip-distributed p-type doped sub-regions 4211.

[0052] It should be noted that the width of the projection of the plurality of p-type doped sub-regions 4211 on the substrate in the first direction X can be the same as each other or different from each other; or the length of the plurality of p-type doped sub-regions 4211 in the second direction Y can be the same as each other or different from each other.

[0053] Preferably, the p-type doped region 421 includes m p-type doped sub-regions 4211, which are arranged apart from each other in both the first direction X and the second direction Y, wherein m is a positive integer greater than or equal to 4. For example, referring to Figure 3C and Figure 3D , the m p-type doped sub-regions 4211 can be distributed in the doped layer 42 in an array.

[0054] Preferably, the projection of each of the m p-type doped sub-regions on the substrate is rectangular; or the projection of each of the m p-type doped sub-regions on the substrate is circular.

[0055] It should be noted that the projection of each of the m p-type doped sub-regions on the substrate can also be polygonal, elliptical, or various shapes, which are not particularly limited in the present application.

[0056] Exemplarily, in some embodiments of the present application, in combination with the description of Figure 1 , Figure 3A and Figure 3B , the projection of each of the p-type doped sub-regions 4211 on the substrate has a first width d1 in the first direction X, and the first width d1 is 5-1000 nm.

[0057] By setting the width of each p-type doped sub-region 4211 to be narrow, at a lower gate voltage, the depletion region 100 of the pn junction formed by the plurality of n-type doped regions 422 and the p-(In, Al) GaN epitaxial layer 41 does not pinch off the channel of the p-type doped sub-region 4211, so the p-type doped sub-region 4211 can serve as a channel for electrical connection between the first gate metal layer 43 and the p-(In, Al) GaN epitaxial layer 41, providing a charge leakage path to balance the charge accumulated inside the p-(In, Al) GaN epitaxial layer 41 when the transistor is switched, achieving a stable threshold value; at a higher gate voltage, since the width of each p-type doped sub-region 4211 is narrow and each p-type doped sub-region 4211 is surrounded by the n-type doped region 422, the depletion region 100 of the pn junction formed by the n-type doped region 422 and the p-(In, Al) GaN epitaxial layer 41 can extend laterally along the first direction X to pinch off the channel of the p-type doped sub-region 4211, thereby breaking the electrical connection between the first gate metal layer 43 and the p-(In, Al) GaN epitaxial layer 41, thereby reducing the gate-drain current of the transistor.

[0058] Preferably, refer to Figure 1 The orthographic projection of the p-type doped region 421 onto the substrate falls between the orthographic projections of the first gate metal layer 43 onto the substrate, forming an ohmic contact between the first gate metal layer 43 and the p-type doped region 421. This design ensures that when the gate voltage of the gate structure is low, the p-type doped region 421 serves as a channel directly connecting the top first gate metal layer 43 and the lower p-(In,Al)GaN epitaxial layer 41, providing a leakage path to balance the charge accumulated inside the p-(In,Al)GaN epitaxial layer 41 during transistor switching. This improves the stability of the transistor gate state, thereby increasing the stability of the transistor threshold voltage and ensuring normal transistor operation. The orthographic projection of the n-type doped region 422 on the substrate partially overlaps with the orthographic projection of the first gate metal layer 43 on the substrate. A Schottky contact is formed between the n-type doped region 422 and the first gate metal layer 43. The first gate metal layer 43 serves as the gate conductive metal. The n-type doped region 422 and the lower p-(In,Al)GaN epitaxial layer 41 form a pn junction. High gate reliability can be achieved by utilizing the reverse biased pn junction, thereby achieving a larger gate swing and a longer operating life.

[0059] By setting a doped layer 42, wherein the n-type doped region 422 and the p-(In,Al)GaN epitaxial layer 41 form a pn junction, when the gate structure 4 is under a positive gate voltage, the pn junction formed by the n-type doped region 422 and the lower p-(In,Al)GaN epitaxial layer 41 can be reverse biased to share the gate electric field, thereby ensuring that the gate of the GaN-based power transistor has high reliability characteristics. Meanwhile, since the first width d1 of the p-type doped sub-region 4211 in the first direction X is relatively narrow and each of the p-type doped sub-regions 4211 is surrounded by the n-type doped region 422, when the gate voltage of the gate structure is low, the p-type doped sub-region 4211, as a channel directly connected to the top first gate metal layer 43 and the lower p-(In,Al)GaN epitaxial layer 41, can provide a leakage path to balance the charge accumulated inside the p-(In,Al)GaN epitaxial layer 41 when the transistor is switched on and off, thereby improving the stability of the transistor gate state, and thus improving the stability of the transistor threshold voltage, ensuring the normal operation of the transistor; when the gate voltage of the gate structure is high, the depletion region 100 of the reverse biased pn junction extends along the first direction X, which can pinch off the channel of the p-type doped sub-region 4211, thereby reducing gate leakage current.

[0060] By setting the doping layer 42 on the side of the p-(In, Al) GaN epitaxial layer 41 away from the stack structure 1, a hybrid gate is formed, which can combine the high voltage and high reliability of the pn junction gate with the p-type dynamic leakage path, thereby overcoming the defect of threshold instability caused by the floating of the pn junction gate, improving the dynamic characteristics of the transistor gate, and keeping the gate leakage at a low level.

[0061] Figure 4 is a structural schematic diagram of a hybrid gate GaN-based power transistor structure according to some embodiments of the present application; Figure 5 is a structural schematic diagram of a hybrid gate GaN-based power transistor structure according to some embodiments of the present application.

[0062] For example, in some embodiments of the present application, in combination with reference to Figure 4 and Figure 5 , the hybrid gate GaN-based power transistor structure further comprises a second gate metal layer 44, which can be arranged on the side of the first gate metal layer 43 away from the substrate 11, or the second gate metal layer 44 can be arranged between the doping layer 42 and the first gate metal layer 43. The second gate metal layer 44 is electrically connected with the first gate metal layer 43; and an ohmic contact is formed between the second gate metal layer 44 and the n-type doped region 422. The ohmic contact between the second gate metal layer 44 and the n-type doped region 422 can short-circuit the parasitic Schottky diode formed between the first gate metal layer 43 and the n-type doped region 422, ensuring that all the excess gate voltage is applied to the reverse-biased pn junction, thereby facilitating the lateral depletion region of the reverse-biased pn junction to limit the gate leakage current flowing through the p-type doped region 421, and reducing the gate leakage of the transistor.

[0063] Preferably, the main body material of the doping layer comprises one or more of the following: (In, Al) GaN, polysilicon, NiO, diamond, or a combination thereof; and / or, the thickness of the doping layer is 5-500 nm; and / or, the doping concentration of the p-type doped region is 10 17 -10 21 cm -3 ; and / or, the doping concentration of the n-type doped region is 10 17 -10 21 cm -3 .

[0064] Preferably, the thickness of the p-(In, Al) GaN epitaxial layer is 10-500 nm; and / or, the doping concentration of the p-(In, Al) GaN epitaxial layer is 10 17 -10 21 cm -3 .

[0065] Preferably, the doping in the p-(In, Al)GaN epitaxial layer is uniform doping; or, the doping in the p-(In, Al)GaN epitaxial layer is a gradual doping from top to bottom.

[0066] Figure 6 is a structural schematic diagram of a hybrid-gate GaN-based power transistor structure according to some embodiments of the present application.

[0067] Exemplarily, in some embodiments of the present application, with reference to Figure 6 , the orthogonal projection of the p-type doped region 421 on the substrate 11 coincides with the orthogonal projection of the first gate metal layer 43 on the substrate, and an ohmic contact is formed between the first gate metal layer 43 and the p-type doped region 421; and the hybrid-gate GaN-based power transistor structure further comprises: a second gate metal layer 44 located on the side of the first gate metal layer 43 away from the substrate 11, wherein the second gate metal layer 44 is electrically connected with the first gate metal layer 43; and an ohmic contact is formed between the second gate metal layer 44 and the n-type doped region 422. By such design, the parasitic Schottky diode between the first gate metal layer 43 and the n-type doped region 422 can be avoided, and it is ensured that all the excess gate voltage is applied to the reverse-biased pn junction, thereby facilitating the lateral depletion region of the reverse-biased pn junction to limit the gate leakage current flowing through the p-type doped region 421, and reducing the gate leakage current of the transistor.

[0068] Preferably, with reference to Figure 1 , the orthogonal projection of the first gate metal layer 43 on the substrate 11 has a second width d2 in the first direction X, the orthogonal projection of the p-(In, Al)GaN epitaxial layer 41 on the substrate 11 has a third width d3 in the first direction X, and the second width d2 is less than or equal to the third width d3. The first width d1 is less than or equal to the second width d2

[0069] Preferably, the work function of the first gate metal layer 43 ranges from 5.0 to 6.5 eV. The first gate metal layer 43 can be a single-layer metal or a metal stack with high work function, for example, the first gate metal layer 43 can comprise one or more of Pt, Ni, Au, Pd in combination, so as to form an ohmic contact with the p-type doped region 421.

[0070] Preferably, the work function of the second gate metal layer 44 ranges from 4.0 to 5.5 eV. The second gate metal layer 44 can be a single layer metal or a metal stack with low work function, for example, the second gate metal layer 44 can include one or more of Ti, Al, Cr in combination, so as to form an ohmic contact with the n-type doped region 422.

[0071] Figure 7 is a structure diagram of a hybrid gate GaN-based power transistor structure according to some embodiments of the present application.

[0072] Exemplarily, in some embodiments of the present application, with reference to Figure 7 , the hybrid gate GaN-based power transistor structure includes: a stack structure 1, wherein the stack structure 1 includes: a substrate 11; a GaN buffer layer 12 disposed on the substrate 11; and an Al(In, Ga)GaN barrier layer 13 disposed on the GaN buffer layer 12 away from the substrate; a source structure 2 disposed at a first end S1 of the stack structure 1; and a drain structure 3 disposed at a second end S2 of the stack structure 1 opposite the source structure 2; and a gate structure 4 disposed on the stack structure 1 and located between the first end S1 and the second end S2, wherein the gate structure 4 includes: a p-(In, Al)GaN epitaxial layer 41 disposed on the stack structure 1; a doped layer 42 disposed on the p-(In, Al)GaN epitaxial layer 41 away from the stack structure 1; and a first gate metal layer 43 disposed on the doped layer 42 away from the stack structure 1, wherein the doped layer 42 includes at least one via VH located between a plurality of n-type doped regions 422; and the first gate metal layer 43 forms an ohmic contact with the p-(In, Al)GaN epitaxial layer 41 through the at least one via VH. In this way, the first gate metal layer 43 and the p-(In, Al)GaN epitaxial layer 41 are electrically connected internally, a dynamic leakage path is formed, the charge accumulated in the p-(In, Al)GaN epitaxial layer 41 during the switching operation of the transistor can be balanced, the threshold value can be stabilized, and the threshold stability of the transistor can be improved. In addition, the integration of the dynamic leakage path and the gate conductive metal can simplify the process steps and reduce the cost.

[0073] Preferably, with reference to Figure 7The vertical projection of the via VH on the substrate 11 has a fourth width d4 in the first direction X, wherein the fourth width d4 is 5-1000 nm. The first gate metal layer 43 comprises a main body portion 431 and a connecting portion 432. The connecting portion 432 is located in the via VH, and the first gate metal layer 43 is electrically connected to the inside of the p-(In, Al) GaN epitaxial layer 41 through the connecting portion 432.

[0074] Since the connecting portion 432 of the first gate metal layer is located in the via VH, the width of the vertical projection of the connecting portion 432 of the first gate metal layer on the substrate 11 in the first direction X can be defined by designing the width of the vertical projection of the via VH on the substrate 11 in the first direction X.

[0075] By setting the width of the vertical projection of the connecting portion 432 of the first gate metal layer on the substrate 11 in the first direction X to be relatively narrow, at a lower gate voltage, the depletion region 100 of the pn junction formed by the plurality of n-doped regions 422 and the p-(In, Al) GaN epitaxial layer 41 does not pinch off the connecting portion 432 of the first gate metal layer, so the connecting portion 432 of the first gate metal layer can serve as a channel for electrical connection between the first gate metal layer 43 and the p-(In, Al) GaN epitaxial layer 41, providing a charge path to balance the charge accumulated in the p-(In, Al) GaN epitaxial layer 41 during switching of the transistor, achieving a stable threshold value; at a higher gate voltage, since the width of the connecting portion 432 of the first gate metal layer is relatively narrow and each connecting portion 432 of the first gate metal layer is surrounded by the n-doped region 422, the depletion region 100 of the pn junction formed by the n-doped region 422 and the p-(In, Al) GaN epitaxial layer 41 can extend laterally along the first direction X to pinch off the connecting portion 432 of the first gate metal layer, thereby breaking the channel for electrical connection between the first gate metal layer 43 and the p-(In, Al) GaN epitaxial layer 41, reducing gate leakage.

[0076] Figure 8 is a structural schematic diagram of a hybrid gate GaN-based power transistor structure according to some embodiments of the present application; Figure 9 is a structural schematic diagram of a hybrid gate GaN-based power transistor structure according to some embodiments of the present application.

[0077] Exemplarily, in some embodiments of the present application, in combination with reference to Figure 8 and Figure 9The mixed gate GaN-based power transistor structure further comprises a second gate metal layer 44, which can be arranged on the side of the first gate metal layer 43 away from the substrate 11, or the second gate metal layer 44 can be arranged between the doped layer 42 and the first gate metal layer 43. The second gate metal layer 44 is electrically connected with the first gate metal layer 43, and an ohmic contact is formed between the second gate metal layer 44 and the n-type doped region 422. The ohmic contact between the second gate metal layer 44 and the n-type doped region 422 can short-circuit the parasitic Schottky diode formed between the first gate metal layer 43 and the n-type doped region 422, ensuring that the excess gate voltage is all applied to the reverse-biased pn junction, so as to facilitate the lateral depletion region of the reverse-biased pn junction to limit the gate leakage current flowing through the first gate metal layer connecting portion 432, and reduce the gate leakage current of the transistor.

[0078] Figure 10 FIG. 1 is a structural schematic diagram of a mixed gate GaN-based power transistor structure according to some embodiments of the present application.

[0079] For example, in some embodiments of the present application, with reference to Figure 10 , the orthogonal projection of the main body portion 431 of the first gate metal layer on the substrate 11 coincides with the orthogonal projection of the connecting portion 432 of the first gate metal layer on the substrate, and the mixed gate GaN-based power transistor structure further comprises a second gate metal layer 44 arranged on the side of the first gate metal layer 43 away from the substrate 11, wherein the second gate metal layer 44 is electrically connected with the first gate metal layer 43, and an ohmic contact is formed between the second gate metal layer 44 and the n-type doped region 422. In this way, the parasitic Schottky diode formed between the first gate metal layer 43 and the n-type doped region 422 can be avoided, and the excess gate voltage is all applied to the reverse-biased pn junction, so as to facilitate the lateral depletion region of the reverse-biased pn junction to limit the gate leakage current flowing through the first gate metal layer connecting portion 432, and reduce the gate leakage current of the transistor. In addition, the dynamic leakage path is integrated with the gate conductive metal in this way, which can simplify the process steps and reduce the cost.

[0080] Although some embodiments of the general inventive concept have been shown and described, it is to be understood that changes can be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A hybrid-gate GaN-based power transistor structure, characterized by, The application relates to a GaN-based power transistor structure with a hybrid gate. The GaN-based power transistor structure with a hybrid gate comprises: a substrate; a GaN buffer layer arranged on the substrate; an Al(In, Ga) GaN barrier layer arranged on a side of the GaN buffer layer away from the substrate; a source structure arranged at a first end of the stack structure; and a drain structure arranged at a second end of the stack structure opposite to the source structure; and a gate structure arranged on the stack structure and located between the first end and the second end, wherein the gate structure comprises: a p-(In, Al) GaN epitaxial layer arranged on the stack structure; a doped layer arranged on a side of the p-(In, Al) GaN epitaxial layer away from the stack structure; and a first gate metal layer arranged on a side of the doped layer away from the stack structure, wherein the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is located between the plurality of n-type doped regions; a projection of the p-type doped region on the substrate is located in a projection of the first gate metal layer on the substrate, and an ohmic contact is formed between the p-type doped region and the first gate metal layer; a projection of the n-type doped region on the substrate partially overlaps with a projection of the first gate metal layer on the substrate, and a Schottky contact is formed between the n-type doped region and the first gate metal layer; the GaN-based power transistor structure with a hybrid gate further comprises a second gate metal layer arranged on a side of the first gate metal layer away from the substrate, or arranged between the doped layer and the first gate metal layer; the second gate metal layer is electrically connected with the first gate metal layer; and an ohmic contact is formed between the second gate metal layer and the n-type doped region.

2. The mixed-gate GaN-based power transistor structure of claim 1, wherein, The at least one p-type doped region is surrounded by the plurality of n-type doped regions.

3. The mixed-gate GaN-based power transistor structure of claim 2, wherein, The p-type doped region comprises m p-type doped sub-regions, wherein m is equal to 1; or the p-type doped region comprises m p-type doped sub-regions, and the m p-type doped sub-regions are arranged at intervals from each other along a first direction, wherein m is a positive integer greater than or equal to 2; or the p-type doped region comprises m p-type doped sub-regions, and the m p-type doped sub-regions are arranged at intervals from each other along both a first direction and a second direction, wherein m is a positive integer greater than or equal to 4.

4. The mixed-gate GaN-based power transistor structure of claim 3, wherein, A projection of each of the p-type doped sub-regions on the substrate has a first width in the first direction, and the first width is 5-1000 nm.

5. The mixed-gate GaN-based power transistor structure of claim 3, wherein, A projection of each of the m p-type doped sub-regions on the substrate is in a strip shape; or a projection of each of the m p-type doped sub-regions on the substrate is in a rectangular shape; or a projection of each of the m p-type doped sub-regions on the substrate is in a circular shape.

6. The mixed-gate GaN-based power transistor structure of claim 2, wherein, A main body material of the doped layer comprises one or more of a combination of (In, Al) GaN, polysilicon, NiO and diamond; and / or a thickness of the doped layer is 5-500 nm; and / or The p-type doped region has a doping concentration of 10 17 -10 21 cm -3 ; and / or, The n-type doped region has a doping concentration of 10 17 -10 21 cm -3 .

7. The mixed-gate GaN-based power transistor structure of claim 2, wherein, a thickness of the p-(In, Al) GaN epitaxial layer is 10-500 nm; and / or The p-(In, Al)GaN epitaxial layer has a doping concentration of 10 17 -10 21 cm -3 .

8. The mixed-gate GaN-based power transistor structure of claim 2, wherein, The doping in the p-(In, Al) GaN epitaxial layer is uniform doping; or The doping in the p-(In, Al) GaN epitaxial layer is from top to bottom gradually changing doping.

9. The mixed gate GaN-based power transistor structure of any of claims 1-8, wherein, The first gate metal layer has a second width in the first direction, and the p-(In, Al) GaN epitaxial layer has a third width in the first direction, and the second width is less than or equal to the third width.

10. The hybrid-gate GaN-based power transistor structure of claim 9, wherein, The work function of the first gate metal layer ranges from 5.0 to 6.5 eV; and / or The work function of the second gate metal layer ranges from 4.0 to 5.5 eV.

11. A hybrid-gate GaN-based power transistor structure, characterized by, Comprising: A stack structure, wherein the stack structure comprises: A substrate; A GaN buffer layer disposed on the substrate; and An Al(In, Ga) GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; A source structure disposed at a first end of the stack structure; and A drain structure disposed at a second end of the stack structure opposite the source structure; and A gate structure disposed on the stack structure and between the first end and the second end, wherein the gate structure comprises: A p-(In, Al) GaN epitaxial layer disposed on the stack structure; A doped layer disposed on a side of the p-(In, Al) GaN epitaxial layer away from the stack structure; and a first gate metal layer disposed on a side of the doped layer away from the stack structure, The doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is located between the plurality of n-type doped regions; The p-type doped region has a projection on the substrate that coincides with a projection of the first gate metal layer on the substrate, and the first gate metal layer and the p-type doped region form an ohmic contact; and The hybrid-gate GaN-based power transistor structure further comprises: a second gate metal layer located on a side of the first gate metal layer away from the substrate, wherein the second gate metal layer is electrically connected to the first gate metal layer; and the second gate metal layer and the n-type doped region form an ohmic contact.

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