Pixel unit of CMOS image sensor and CMOS image sensor

Abstract

The invention discloses a pixel unit of a CMOS image sensor and the CMOS image sensor, and belongs to the field of semiconductors. The PN diode and the reset transistor are added, the PN diode serves as an overflow device, and the reset transistor resets the PN diode. And an electron overflow channel is formed between the second P-type doped layer at the bottom of the N region of the PN diode and the photodiode. Since the potential of the second P-type doped layer is higher than the potential of other P-type doped layers adjacent to the N region of the photodiode, the electrons overflow into the PN diode before the transmission transistor transmits the electrons to the floating diffusion region. According to the CMOS image sensor, electrons naturally overflowing when the photodiode is about to be full can be stored, dark current caused by the fact that electrons generated by insufficient negative bias of the transmission gate are diffused into the photodiode can be avoided, and therefore the dynamic range of the CMOS image sensor is widened.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a pixel unit of a CMOS image sensor and a CMOS image sensor. Background Art

[0002] When the transfer transistor in the pixel unit of a traditional CMOS (Complementary Metal Oxide Semiconductor) image sensor also serves as an overflow transistor, in order to allow the electrons of the photodiode to overflow smoothly, the potential of the silicon surface below the gate oxide layer of the transfer transistor must be high. In this way, the level of hole filling between the gate oxide layer and silicon of the transfer transistor cannot be very high, and some of the electrons emitted from the interface state will enter the photodiode, forming a dark current of the photodiode. The existence of this dark current will reduce part of the dynamic range of the CMOS image sensor. Therefore, how to improve the dynamic range of the CMOS image sensor is a technical problem that those skilled in the art currently need to solve. Summary of the invention

[0003] The purpose of the present application is to provide a pixel unit of a CMOS image sensor and a CMOS image sensor, wherein the pixel unit structure is used to improve the dynamic range of the CMOS image sensor.

[0004] To achieve the above-mentioned object, the present application provides a pixel unit of a CMOS image sensor, comprising: a substrate, on which a photodiode, an overflow device and a reset transistor are arranged;

[0005] The overflow device comprises a PN diode; the P region of the PN diode comprises a first P-type doping layer and a second P-type doping layer; the doping concentration of the second P-type doping layer is less than the doping concentration of the first P-type doping layer; the first P-type doping layer surrounds the N region of the PN diode; the second P-type doping layer is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region of the photodiode through the second P-type doping layer;

[0006] Among all the P-type doped layers adjacent to the N region of the photodiode, the second P-type doped layer has the highest potential, so that the electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doped layer;

[0007] The PN diode is connected to the reset transistor through a metal line.

[0008] Optionally, the overflow device further includes a capacitor; the capacitor is connected in parallel with the PN diode; and the capacitor is connected to the reset transistor through the metal wire.

[0009] Optionally, the capacitor is a MIM capacitor; the positive electrode of the MIM capacitor is connected to the N region of the PN diode through a contact hole and the metal wire; the capacity of the MIM capacitor is greater than 100 times the capacity of the photodiode.

[0010] Optionally, the first P-type doped layer is a first P-type medium doped layer;

[0011] The second P-type doped layer is a P-type lightly doped layer with a preset thickness, and the doping concentration of the P-type lightly doped layer is lower than 1×10 13 / cm 3 ; or, the second P-type doped layer is a second P-type medium doped layer; a side of the second P-type medium doped layer close to the N region of the PN diode overlaps with the N region of the PN diode.

[0012] Optionally, the doping concentration of the second P-type doping layer is lower than 3×10 17 / cm 3 .

[0013] Optionally, the reset transistor is an NMOS tube; the N region of the PN diode is connected to the source of the NMOS tube through the metal wire.

[0014] Optionally, the second P-type doped layer is parallel to the surface of the substrate, so that electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doped layer in a direction perpendicular to the surface of the substrate.

[0015] Optionally, the PN diode is located in the N region of the photodiode away from the end connected to the transfer transistor;

[0016] Alternatively, the PN diode is located in an upper center region of the photodiode.

[0017] Optionally, the distance between the N region of the PN diode and the shallow trench isolation is greater than 0.15 μm; the shallow trench isolation is used to isolate active regions of adjacent pixel units.

[0018] Optionally, the N region of the PN diode includes an N-type heavily doped layer and an N-type medium doped layer;

[0019] The second P-type doping layer is located at the bottom of the N-type medium doping layer, so that the N-type medium doping layer is connected to the N region of the photodiode through the second P-type doping layer.

[0020] To achieve the above object, the present application further provides a CMOS image sensor, comprising: a plurality of pixel units; the pixel units are the pixel units described in any one of the above items.

[0021] The present application provides a pixel unit of a CMOS image sensor, comprising: a substrate, on which a photodiode, an overflow device and a reset transistor are arranged;

[0022] The overflow device comprises a PN diode; the P region of the PN diode comprises a first P-type doping layer and a second P-type doping layer; the doping concentration of the second P-type doping layer is less than the doping concentration of the first P-type doping layer; the first P-type doping layer surrounds the N region of the PN diode; the second P-type doping layer is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region of the photodiode through the second P-type doping layer;

[0023] Among all the P-type doped layers adjacent to the N region of the photodiode, the second P-type doped layer has the highest potential, so that the electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doped layer;

[0024] The PN diode is connected to the reset transistor through a metal line.

[0025] Obviously, the present application adds a PN diode as an overflow device, and uses a reset transistor to reset the PN diode. An electron overflow channel is formed between the second P-type doped layer at the bottom of the N region of the PN diode and the photodiode. Since the potential of the second P-type doped layer is higher than the potential of other P-type doped layers adjacent to the N region of the photodiode, the electrons will overflow into the PN diode before the transfer transistor transfers the electrons to the floating diffusion area. It can store the electrons that naturally overflow when the photodiode is full, and avoid the dark current caused by the electrons generated by the insufficient negative bias of the transmission gate diffusing into the photodiode, thereby improving the dynamic range of the CMOS image sensor; and the PN diode as an overflow device does not require additional control, and the control is relatively simple. The present application also provides a CMOS image sensor with the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0027] Figure 1 A cross-sectional schematic diagram of a pixel unit provided in an embodiment of the present application;

[0028] Figure 2 A circuit schematic diagram of a pixel unit provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of an active area and gate layout of a pixel unit provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of a cross-sectional potential barrier of a pixel unit provided in an embodiment of the present application.

[0031] The following are the descriptions of the reference numerals:

[0032] 11-heavily doped N-type polysilicon layer; 12-oxide layer; 13-P-type isolation layer; 18-silicon-oxygen interface P-type heavily doped passivation layer; 21-silicon surface dielectric layer; 23-P-type epitaxial substrate; 31-first P-type doped layer / first P-type medium doped layer; 32-second P-type doped layer / second P-type medium doped layer; 41-N-type heavily doped silicon single crystal layer; 42-N region of the photodiode; 43-N-type medium doped layer; 44-N-type heavily doped layer;

[0033] PD-photodiode; TG-transmission transistor; RST1-first reset transistor; RST2-second reset transistor; SF-source follower; ROS-row selection transistor, DCG-dual conversion gain control unit; CPN-PN diode; C1-capacitor controlled by dual conversion gain control unit DCG; C2-MIM capacitor; STI-shallow trench isolation; FD1-first floating diffusion area; FD2-second floating diffusion area; FD3-third floating diffusion area. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] Traditional CMOS image sensors use only one floating diffusion (FD) as a capacitor, and it is difficult to achieve a dynamic range of more than 100. Therefore, a solution for pixels with high dynamic range uses several capacitors of different sizes. The smallest capacitor is used in low light, and the sum of all capacitors is used in strong light. Through appropriate timing switches, capacitors of different sizes are used in strong light and weak light, respectively, and then the function of high dynamic range is realized through circuit and algorithm processing. Due to the complexity of control, it is difficult to have a large number of the above capacitors to achieve approximately continuous adjustment. Under certain light intensities, the image may suddenly become dark.

[0036] In traditional CMOS image sensors, the electrons in the N region of the photodiode are completely depleted after reset, leaving only space charge; when collecting photogenerated electrons, the transfer transistor adds a negative bias (V1) to the silicon oxide layer of the transfer transistor. The interface state is almost completely filled with holes to prevent the electrons emitted from the interface state from entering the photodiode and becoming the dark current of the photodiode. Technically, the concentration of the P-type inversion layer is required to reach 10 18 / cm 3 At this time, the potential under the gate is slightly lower than that of the P-type substrate.

[0037] A traditional HDR (High-Dynamic Range) pixel unit, after reset, a negative bias voltage with an absolute value lower than V1 is added to the gate of the transfer transistor. After the photogenerated electrons are filled in the photodiode to the designed level, the additional photogenerated electrons in the photodiode naturally overflow to the FD, and then are stored in a large capacitor connected to the FD through a transistor for subsequent use.

[0038] To allow the electrons from the photodiode to overflow smoothly, the gate of the transfer transistor is biased more positive than V1, so that the potential of the silicon surface below the gate dielectric of the transfer transistor is higher than 0V. Since the P-type regions around the photodiode are all zero volts, in order to prevent electrical crosstalk between photodiodes before overflowing to FD, the potential of the silicon surface below the gate oxide layer of the transfer transistor is higher than 0.2V. In this way, the interface state between the gate oxide layer and silicon of the transfer transistor cannot be filled with holes at a very high level, and the transfer transistor cannot be negatively biased to a level that causes the hole concentration accumulated in the silicon below the gate to reach 1×10 18 / cm 3 As mentioned above, holes cannot fill the interface states at the interface between the gate oxide layer and the silicon, and some of the electrons emitted from the interface states will diffuse to the photodiode and cause dark current. This dark current will be sensed by the smallest FD capacitor, which reduces part of the dynamic range at the small signal end. The above problem is caused by the difficulty of the transfer transistor to simultaneously achieve a high filling level of interface state holes and assume the overflow function of the photodiode when the transfer transistor is negatively biased. Therefore, the present application provides a pixel unit of a CMOS image sensor and a CMOS image sensor, which adds a PN diode as an overflow device and uses a reset transistor to reset the PN diode. It can store the electrons that naturally overflow when the photodiode is full, and avoid the generation of dark current of the photodiode, thereby improving the dynamic range of the CMOS image sensor.

[0039] Please refer to Figure 1 , Figure 1 A cross-sectional schematic diagram of a pixel unit of a CMOS image sensor provided in an embodiment of the present application, the pixel unit of the CMOS image sensor may include: a substrate, on which a photodiode, an overflow device and a reset transistor are arranged;

[0040] The overflow device includes a PN diode; the P region of the PN diode includes a first P-type doping layer 31 and a second P-type doping layer 32; the doping concentration of the second P-type doping layer 32 is less than the doping concentration of the first P-type doping layer 31; the first P-type doping layer 31 surrounds the N region of the PN diode; the second P-type doping layer 32 is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region 42 of the photodiode through the second P-type doping layer 32;

[0041] Among all the P-type doped layers adjacent to the N region 42 of the photodiode, the second P-type doped layer 32 has the highest potential, so that the electrons overflowing from the N region 42 of the photodiode are transmitted into the PN diode through the second P-type doped layer 32;

[0042] The PN diode is connected to the reset transistor through a metal line.

[0043] It should be noted that the N region of the PN diode and the N region 42 of the photodiode are connected through the second P-type doping layer 32, and there is an electron potential barrier between the second P-type doping layer 32 and the photodiode that has reached the designed full well state after reset. Since the second P-type doping layer 32 has the highest potential among all the P-type doping layers adjacent to the N region 42 of the photodiode, the electron potential barrier between the second P-type doping layer 32 and the N region 42 of the photodiode is lower (a few tenths of a volt lower) than the electron potential barrier between the N region 42 of the photodiode and other adjacent P-type doping layers, so the second P-type doping layer 32 can be used as an electron overflow channel when the photodiode is about to be full. Since the CMOS image sensor time is in the millisecond level, during the reset and charging process, the barrier channel will restore balance during this period of time. If the N-type region is used as the barrier channel, it will bring additional noise, but the equilibrium electron concentration of the second P-type doping layer 32 is originally extremely low, so this type of side effect can be avoided.

[0044] After the photodiode is reset, the potential of the N region 42 of the photodiode is much higher than that of the second P-type doping layer 32, so the photogenerated electrons slowly accumulate in the photodiode, and the potential of the photodiode also decreases accordingly, and the barrier difference with the second P-type doping layer 32 slowly decreases. When the barrier difference is lower than a few tenths of a volt, the electrons subsequently generated in the photodiode overflow into the PN diode through the second P-type doping layer 32. The PN diode is a PN junction capacitor, so the overflowed electrons can be stored for subsequent use by circuits and algorithms.

[0045] It should be noted that the PN diode and the reset transistor are not in the same region, so the PN diode is connected to the reset transistor through a metal line.

[0046] This embodiment does not limit the specific type of the substrate, and the specific type of the substrate can be determined according to actual conditions. For example, the substrate can be a silicon wafer.

[0047] The pixel unit of the CMOS image sensor in this embodiment may include other devices in addition to the photodiode, the overflow device and the reset transistor. This embodiment does not limit the specific types and specific connection methods of the other devices, and reference may be made to the pixel unit of a traditional CMOS image sensor.

[0048] Furthermore, in order to increase the storage capacity of the overflow device, the overflow device in this embodiment may further include a capacitor; the capacitor is connected in parallel with the PN diode; the capacitor is connected to the reset transistor via a metal wire. It should be noted that both the capacitor and the PN diode are reset by the reset transistor.

[0049] This embodiment does not limit the specific type of capacitor, and can be any large-capacity capacitor, for example, the capacitor can be a MIM capacitor; the positive electrode of the MIM capacitor is connected to the N region of the PN diode through a contact hole and a metal wire. Further, in order to meet the requirements of high dynamic range, the capacity of the MIM capacitor in this embodiment can be greater than 100 times the capacity of the photodiode.

[0050] The present embodiment does not limit the specific type of the second P-type doping layer 32. For example, the first P-type doping layer 31 is a first P-type medium doping layer 31; the second P-type doping layer 32 may be a P-type lightly doped layer with a preset thickness, and the doping concentration of the P-type lightly doped layer is less than 1×10 13 / cm 3 ; Alternatively, the second P-type doped layer 32 may be a second P-type medium doped layer 32; the side of the second P-type medium doped layer 32 close to the N region of the PN diode overlaps with the N region of the PN diode. It should be noted that the potential of the second P-type medium doped layer 32 is modulated by both the N region of the PN diode and the N region 42 of the photodiode.

[0051] The present embodiment does not limit the specific doping concentration of the second P-type doping layer 32, as long as the doping concentration of the second P-type doping layer 32 is less than the doping concentration of the first P-type doping layer 31. For example, the doping concentration of the second P-type doping layer 32 can be less than 3×10 17 / cm 3 It should be noted that the second P-type doping layer 32 can be formed by implantation before gate oxidation.

[0052] This embodiment does not limit the specific type of the reset transistor, as long as it can achieve the reset of the PN diode and the capacitor. For example, the reset transistor can be an NMOS transistor; the N region of the PN diode is connected to the source of the NMOS transistor through a metal wire.

[0053] Furthermore, in this embodiment, the second P-type doping layer 32 may be parallel to the surface of the substrate, so that the electrons overflowing from the N region 42 of the photodiode are transmitted into the PN diode through the second P-type doping layer 32 in a direction perpendicular to the surface of the substrate.

[0054] This embodiment does not limit the specific position of the PN diode, and the specific position of the PN diode can be determined according to actual conditions. For example, the PN diode can be located in the N region 42 of the photodiode away from the end connected to the transfer transistor; when the design requires a high number of full-well electrons per unit area, the PN diode can also be located in the area above the center of the photodiode.

[0055] It should be noted that a shallow trench isolation is provided between active areas of adjacent pixel units, and the shallow trench isolation is used to isolate active areas of adjacent pixel units. This embodiment does not limit the specific distance between the N region of the PN diode and the shallow trench isolation, and the specific distance between the N region of the PN diode and the shallow trench isolation can be determined according to actual conditions, for example, the distance between the N region of the PN diode and the shallow trench isolation is greater than 0.15 μm.

[0056] Furthermore, in order to prevent the fluctuation of doping concentration caused by the single-layer N-type heavily doped layer 44, which leads to the fluctuation of the potential barrier between the PN diode and the photodiode, so as to improve the uniformity of the potential barrier in the chip, the N region of the PN diode in this embodiment may include an N-type heavily doped layer 44 and an N-type medium doped layer 43; the second P-type doped layer 32 is located at the bottom of the N-type medium doped layer 43, so that the N-type medium doped layer 43 is connected to the N region 42 of the photodiode through the second P-type doped layer 32. It should be noted that the N-type heavily doped layer 44 is used as an ohmic contact, and the N-type medium doped layer 43 is an extension area of ​​the N-type heavily doped layer 44, which can be prepared by sequential implantation using the same mask; the first P-type doped layer 31 is located around the N-type heavily doped layer 44, separating the direct contact between the N-type heavily doped layer 44 and the shallow trench isolation; below the N-type heavily doped layer 44, the N-type medium doped layer 43 is connected to the N region 42 of the photodiode through the second P-type doped layer 32.

[0057] Based on the above embodiments, the present application adds a PN diode as an overflow device, and uses a reset transistor to reset the PN diode. An electron overflow channel is formed between the second P-type doped layer 32 at the bottom of the N region of the PN diode and the photodiode. Since the potential of the second P-type doped layer 32 is higher than the potential of other P-type doped layers adjacent to the N region 42 of the photodiode, the electrons will overflow into the PN diode before the transfer transistor transfers the electrons to the floating diffusion area, thereby replacing the method of transmitting the overflowed electrons through the transfer transistor. It can store the electrons that naturally overflow when the photodiode is full, and avoid the dark current caused by the electrons generated by the insufficient negative bias of the transmission gate diffusing into the photodiode, thereby improving the dynamic range of the CMOS image sensor; and the PN diode as an overflow device does not require additional control, and the control is relatively simple.

[0058] Another pixel unit of a CMOS image sensor provided in an embodiment of the present application may include: a substrate, on which a photodiode, an overflow device, and a reset transistor are arranged;

[0059] The overflow device includes a PN diode and a capacitor; the capacitor is connected in parallel with the PN diode;

[0060] The N region of the PN diode includes an N-type heavily doped layer 44 and an N-type medium doped layer 43; the P region of the PN diode includes a first P-type doped layer 31 and a second P-type doped layer 32; the doping concentration of the second P-type doped layer 32 is less than the doping concentration of the first P-type doped layer 31; the first P-type doped layer 31 surrounds the N region of the PN diode; the second P-type doped layer 32 is located at the bottom of the N-type medium doped layer 43, so that the N-type medium doped layer 43 is connected to the N region 42 of the photodiode through the second P-type doped layer 32;

[0061] Among all the P-type doped layers adjacent to the N region 42 of the photodiode, the second P-type doped layer 32 has the highest potential, so that the electrons overflowing from the N region 42 of the photodiode are transmitted into the PN diode through the second P-type doped layer 32;

[0062] The PN diode and the capacitor are connected to the reset transistor through metal lines.

[0063] Based on the above embodiments, the present application adds a PN diode and a capacitor in parallel as an overflow device, and uses a reset transistor to simultaneously reset the PN diode and the capacitor. It can store the electrons that naturally overflow when the photodiode is about to be full, and avoid the dark current caused by the electrons generated by the insufficient negative bias of the transmission gate diffusing into the photodiode, thereby improving the dynamic range of the CMOS image sensor. In addition, by storing the electrons that naturally overflow when the photodiode is about to be full through the parallel PN diode and capacitor, the storage capacity of the overflow device is improved; at the same time, the PN diode adopts an N+NP type diode, and the N region adds an N-type medium doping layer 43 as an extension area of ​​the N-type heavily doped layer 44, which can prevent the doping concentration fluctuation caused by the single-layer N-type heavily doped layer 44, resulting in the potential barrier fluctuation between the PN diode and the photodiode, thereby improving the uniformity of the potential barrier in the chip.

[0064] The embodiment of the present application further provides a CMOS image sensor, comprising: a plurality of pixel units; the pixel units are the pixel units as described above.

[0065] Based on the above embodiments, compared with the traditional CMOS image sensor, the CMOS image sensor of the present application can achieve a higher dynamic range due to the use of the above-mentioned pixel unit.

[0066] The working principle of the pixel unit of the above CMOS image sensor is explained below with reference to specific examples.

[0067] Please refer to Figure 2 , Figure 2 A circuit schematic diagram of a pixel unit provided in an embodiment of the present application. The pixel unit is composed of a photodiode PD, a transfer transistor TG and five other peripheral transistors (including a first reset transistor RST1, a second reset transistor RST2, a source follower SF, a row selection transistor ROS, a dual conversion gain control unit DCG, a PN diode CPN, a capacitor C1 controlled by the dual conversion gain control unit DCG, and a large-capacity MIM capacitor C2.

[0068] Among them, the source of the transfer transistor TG is the N region of the photodiode PD; the drain of the transfer transistor TG is the first floating diffusion area FD1 connected to the gate of the source follower SF, and the drain of the transfer transistor TG and the gate of the source follower SF are both connected to the source of the first reset transistor RST1; the source of the source follower SF is connected to the drain of the row selection transistor ROS.

[0069] The second reset transistor RST2 is an NMOS transistor. The N region of the PN diode CPN and the source of the NMOS transistor are not in the same region, and are connected to the positive electrode of the MIM capacitor C2 and the source of the NMOS transistor through a metal wire, and both are reset by the NMOS transistor.

[0070] In addition, the dual conversion gain control unit DCG is an NMOS tube, the drain of which is the first floating diffusion region FD1, and the source of which is the second floating diffusion region FD2 and the capacitor C1.

[0071] The N region of the PN diode CPN and the N region of the photodiode PD are connected via a P-type doped layer. The N-type heavily doped layer 44 of the PN diode CPN serves as the third floating diffusion region FD3.

[0072] Please refer to Figure 1 and Figure 3 , Figure 1 A cross-sectional schematic diagram of a pixel unit provided in an embodiment of the present application; Figure 3 A schematic diagram of an active area and gate layout of a pixel unit provided in an embodiment of the present application.

[0073] The transfer transistor TG is arranged in the silicon surface dielectric layer 21. The drain of the transfer transistor TG is a heavily doped N-type polysilicon layer 11, the gate is an oxide layer 12, and the source is a photodiode PD. An N-type heavily doped silicon single crystal layer 41 is arranged below the transfer transistor TG, and the N-type heavily doped silicon single crystal layer 41 serves as the first floating diffusion region FD1 and is also the drain of the transfer transistor TG. The N region of the photodiode PD serves as the source end of the transfer transistor TG and is formed on a P-type epitaxial substrate 23. A silicon-oxygen interface P-type heavily doped passivation layer 18 is arranged between the photodiode PD and the silicon surface dielectric layer 21. A P-type isolation layer 13 is arranged between adjacent pixel units.

[0074] The first P-type medium doping layer 31 is arranged at the far end of the pixel unit transmission gate. Figure 1 and Figure 3As shown. In the upper part of the photodiode PD, a layer of P-type medium doping layer (including the first P-type medium doping layer 31 and the second P-type medium doping layer 32) is injected before gate oxidation, with a depth between 0.15μm and 0.4μm. . In the middle position of the P-type medium doping layer, after the sidewall process is completed, a layer of N-type medium doping layer 43 and an N-type heavily doped layer 44 are successively injected to form the N region of the PN diode CPN. The N-type medium doping layer 43 can be partially overlapped with the second P-type medium doping layer 32 to form a P-type thin layer. The effective thickness of the second P-type medium doping layer 32 under the N region of the PN diode CPN is thinner than the first P-type medium doping layer 31 outside the N region of the PN diode CPN, and the doping is also lower due to the compensation of the N-type medium doping layer 43. The electric potential of the P-type thin layer is modulated by the N-type medium-doped layer 43 and the N-type heavily-doped layer 44 of the PN diode CPN and the N region of the photodiode PD at the same time, mainly by the injection doping of the N-type medium-doped layer 43 and the bias modulation on the N-type heavily-doped layer 44, which is a few tenths of a volt higher than the surrounding first P-type medium-doped region, forming a unique and controllable electron channel from the N region of the photodiode PD to the N region of the PN diode CPN.

[0075] In addition, since the doping concentrations of the P-type isolation layer 13 and the first P-type medium doping layer 31 are similar, the P-type isolation layer 13 between adjacent pixel units can be used as a part of the first P-type medium doping layer 31. In this way, the additional first P-type medium doping layer 31 can be 0.3 μm thick. 2 Below that, the depth is less than 0.4μm, so even if it is used on a small pixel unit, it has little impact on the total quantum efficiency.

[0076] In order to save area, the PN diode CPN is a very small capacitor. The N region of the PN diode CPN is composed of an N-type heavily doped layer 44 and an N-type medium doped layer 43 at the bottom of the N-type heavily doped layer 44; the periphery of the N-type heavily doped layer 44 and the N-type medium doped layer 43 wraps the first P-type medium doped layer 31, and the bottom wraps the second P-type medium doped layer 32. The N-type heavily doped layer 44 serves as an ohmic contact and is connected to the source of the NMOS tube through a metal wire; the first P-type medium doped layer 31 separates the N-type heavily doped layer 44 and the silicon-oxygen interface P-type heavily doped passivation layer 18 at the edge of the shallow trench isolation STI, preventing the formation of a high electric field between the N-type heavily doped layer 44 and the silicon-oxygen interface P-type heavily doped passivation layer 18, which causes tunneling and introduces dark current to the PN diode CPN and the MIM capacitor C2; the N-type medium doped layer 43 can also prevent the doping fluctuation caused by the N-type heavily doped layer 44, which causes the potential barrier fluctuation between the PN diode CPN and the photodiode PD, so as to improve the uniformity of the potential barrier in the chip.

[0077] In addition, the N region of the PN diode CPN newly added on the silicon wafer and the source of the second reset transistor RST2 are not in the same area and are isolated from each other by a P-type isolation layer 13 .

[0078] The N region of the PN diode CPN is different from the floating diffusion region of the traditional CMOS image sensor. It is far away from the shallow trench isolation STI, and a silicon-oxygen interface P-type heavily doped passivation layer 18 is provided at the edge of the shallow trench isolation STI, which is very beneficial to reducing dark current.

[0079] The manufacturing steps of the pixel unit of the CMOS image sensor provided in the embodiment of the present application may be as follows:

[0080] 1. Well injection module that performs standard CMOS process;

[0081] 2. Injecting a P-type isolation layer 13;

[0082] 3. Injection into the N region 42 of the photodiode PD;

[0083] 4. Implanting the first P-type medium doped layer 31;

[0084] Two masks are added to the CMOS image sensor process flow, one for implanting the first P-type medium doping layer 31 after the shallow trench isolation STI and before the gate oxidation; the other for implanting the N-type medium doping layer 43 and the N-type heavily doped layer 44 successively after the sidewall process and before the source and drain implantation; wherein part of the implantation dose of the N-type medium doping layer 43 enters the first P-type medium doping layer 31 at the bottom of the N-type medium doping layer 43, so that it naturally forms the second P-type medium doping layer 32;

[0085] 5. Gate formation module that performs standard CMOS process;

[0086] 6. Sidewall module that implements standard CMOS process;

[0087] 7. Implant a P-type heavily doped passivation layer to form shallow trench isolation STI;

[0088] 8. Implanting a P-type heavily doped passivation layer 18 at the silicon-oxygen interface;

[0089] 9. Injecting the N-type medium doped layer 43 and the N-type heavily doped layer 44 of the PN diode CPN;

[0090] 10. Perform source and drain implantation annealing of standard CMOS process;

[0091] 11. Perform metallization of standard CMOS process.

[0092] Please refer to Figure 4 , Figure 4 A schematic diagram of a cross-sectional potential barrier of a pixel unit provided in an embodiment of the present application.

[0093] After the photodiode PD is reset, the potential of the N region of the photodiode PD is much higher than that of the above-mentioned P-type thin layer, and there is a very high potential barrier difference between the two; but the potential barrier difference between the photodiode PD and the surrounding P-type isolation layer 13 and the channel under the gate of the transfer transistor TG is even greater; as the photogenerated electrons accumulate in the photodiode PD, the potential of the photodiode PD also decreases, and the potential barrier difference with the above-mentioned P-type thin layer gradually decreases. When the potential barrier difference is lower than a few tenths of a volt, before the photogenerated electrons overflow into the floating diffusion area and the adjacent photodiode PD, the subsequently regenerated photogenerated electrons naturally overflow into the PN diode CPN and the MIM capacitor C2 connected in parallel therewith, so as to be subsequently utilized by circuits and algorithms.

[0094] Specific examples are used herein to illustrate the principles and implementation methods of the present application, and the embodiments are in a progressive relationship, each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. The description of the above embodiments is only used to help understand the method and core ideas of the present application. For ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0095] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A pixel unit of a CMOS image sensor, It is characterized in that The method comprises: a substrate on which a photodiode, an overflow device and a reset transistor are arranged; The overflow device includes a PN diode; The P region of the PN diode includes a first P-type doping layer and a second P-type doping layer; the doping concentration of the second P-type doping layer is less than the doping concentration of the first P-type doping layer; the first P-type doping layer surrounds the N region of the PN diode; the second P-type doping layer is located at the bottom of the N region of the PN diode, so that the N region of the PN diode is connected to the N region of the photodiode through the second P-type doping layer; Among all the P-type doping layers adjacent to the N region of the photodiode, the second P-type doping layer has the highest potential, so that the electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doping layer; The PN diode is connected to the reset transistor through a metal line.

2. The pixel unit of the CMOS image sensor according to claim 1, It is characterized in that The overflow device further includes a capacitor; the capacitor is connected in parallel with the PN diode; and the capacitor is connected to the reset transistor through the metal line.

3. The pixel unit of the CMOS image sensor according to claim 2, It is characterized in that The capacitor is a MIM capacitor; the positive electrode of the MIM capacitor is connected to the N region of the PN diode through a contact hole and the metal wire; the capacity of the MIM capacitor is greater than 100 times the capacity of the photodiode.

4. The pixel unit of the CMOS image sensor according to claim 1, It is characterized in that The first P-type doped layer is a first P-type medium doped layer; The second P-type doped layer is a P-type lightly doped layer with a preset thickness, and the doping concentration of the P-type lightly doped layer is lower than 1×10 13 / cm 3 ; Alternatively, the second P-type doped layer is a second P-type medium doped layer; a side of the second P-type medium doped layer close to the N region of the PN diode overlaps with the N region of the PN diode.

5. The pixel unit of the CMOS image sensor according to claim 1, It is characterized in that The doping concentration of the second P-type doping layer is lower than 3×10 17 / cm 3 .

6. The pixel unit of the CMOS image sensor according to claim 1, It is characterized in that The reset transistor is an NMOS tube; The N region of the PN diode is connected to the source of the NMOS tube through the metal wire.

7. The pixel unit of the CMOS image sensor according to claim 1, It is characterized in that The second P-type doping layer is parallel to the surface of the substrate, so that the electrons overflowing from the N region of the photodiode are transmitted into the PN diode through the second P-type doping layer in a direction perpendicular to the surface of the substrate.

8. The pixel unit of the CMOS image sensor according to claim 1, It is characterized in that The PN diode is located in the N region of the photodiode away from the end connected to the transfer transistor; Alternatively, the PN diode is located in an upper center region of the photodiode.

9. The pixel unit of the CMOS image sensor according to claim 1, It is characterized in that The distance between the N region of the PN diode and the shallow trench isolation is greater than 0.15 μm; the shallow trench isolation is used to isolate the active regions of adjacent pixel units.

10. The pixel unit of the CMOS image sensor according to any one of claims 1 to 9, It is characterized in that The N region of the PN diode includes an N-type heavily doped layer and an N-type medium doped layer; The second P-type doping layer is located at the bottom of the N-type medium doping layer, so that the N-type medium doping layer is connected to the N region of the photodiode through the second P-type doping layer.

11. A CMOS image sensor, It is characterized in that include: A plurality of pixel units; The pixel unit is the pixel unit according to any one of claims 1 to 10.

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