Display panel

Abstract

Provided is a display panel including: a driving element layer having a pixel driver; a light emitting element disposed on the driving element layer and having a first electrode, an intermediate layer disposed on the first electrode and having at least a light emitting layer, and a second electrode disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer and having an opening exposing at least a portion of the first electrode; a connection electrode disposed on the pixel defining layer and electrically connected to the pixel driver and the second electrode; and a spacer disposed on the pixel defining layer. In a contact region adjacent to the separator, a lower surface of the second electrode is in contact with an upper surface of the connection electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0163990, filed on November 23, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display panel having improved contact reliability. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, computers such as tablet computers, navigation systems, and game consoles include a display panel for displaying images. The display panel includes a light-emitting element and a circuit for driving the light-emitting element. The light-emitting element included in the display panel emits light according to a voltage applied from the circuit, and generates an image. In order to improve the reliability of the display panel, research on the connection of the light-emitting element and the circuit is underway. Summary of the invention

[0005] The embodiment provides a display panel capable of improving contact reliability.

[0006] However, the embodiments are not limited to those set forth herein.The above and other embodiments will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0007] An embodiment provides a display panel, comprising: a driving element layer including a pixel driver; a light emitting element disposed on the driving element layer and including a first electrode, an intermediate layer disposed on the first electrode and including at least a light emitting layer, and a second electrode disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer and including an opening exposing at least a portion of the first electrode; a connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driver and the second electrode; and a spacer disposed on the pixel defining layer. In a contact area adjacent to the spacer, a lower surface of the second electrode contacts an upper surface of the connecting electrode.

[0008] In an embodiment, the intermediate layer may further include a functional layer. The functional layer may include: a first intermediate functional layer disposed on the first electrode; and a second intermediate functional layer disposed on the light emitting layer, and the light emitting layer may be disposed between the first intermediate functional layer and the second intermediate functional layer.

[0009] In an embodiment, the display panel may further include: a first dummy layer disposed on the partition; and a second dummy layer disposed on the first dummy layer, wherein the first dummy layer and the functional layer may include the same material, and the second dummy layer and the second electrode may include the same material.

[0010] In an embodiment, the connection electrode may not contact the second dummy layer.

[0011] In an embodiment, the connection electrode may have a ring shape surrounding the opening of the pixel defining layer.

[0012] In an embodiment, the contact region may surround at least a portion of the opening of the pixel defining layer.

[0013] In an embodiment, the connection electrode may include a first edge portion and a second edge portion surrounding the first edge portion, and the second edge portion may overlap the spacer on a plane.

[0014] In an embodiment, the spacer may include a first side surface and a second side surface having different taper angles with respect to an upper surface of the pixel defining layer.

[0015] In an embodiment, a portion of the connection electrode may be covered by the separator.

[0016] In an embodiment, the connection electrode may include: a first connection portion disposed in the contact region; and a second connection portion disposed on a side surface of the separator.

[0017] In an embodiment, the second electrode may include: a first electrode portion disposed on the first connection portion to contact an upper surface of the first connection portion; and a second electrode portion disposed on a side surface of the second connection portion to contact a side surface of the second connection portion.

[0018] In an embodiment, the connection electrode may further include a third connection portion disposed on an upper surface of the separator.

[0019] In an embodiment, at least a portion of the second connection portion may not be in contact with the second electrode.

[0020] In an embodiment, a through hole may pass through the pixel defining layer, and the connection electrode may be connected to the pixel driver through the through hole.

[0021] In an embodiment, the intermediate layer may overlap the via.

[0022] In an embodiment, in an intermediate region provided between the contact region and the light emitting element, an intermediate layer may be provided between the connection electrode and the second electrode.

[0023] In an embodiment, a display panel may include: a driving element layer including a pixel driver; a light emitting element disposed on the driving element layer and including: a first electrode; an intermediate layer disposed on the first electrode and including at least a light emitting layer; and a second electrode disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer and including an opening exposing at least a portion of the first electrode; and a connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driver and the second electrode. In a contact region separated from a light emitting region where the light emitting element is disposed, a lower surface of the second electrode contacts an upper surface of the connecting electrode, and a connecting region where the connecting electrode and the pixel driver are connected is disposed between the contact region and the light emitting region.

[0024] In an embodiment, the opening may overlap the light emitting region, the pixel defining layer may further include a through hole spaced apart from the opening and overlapping the connection region, and the connection electrode may be connected to the pixel driver through the through hole.

[0025] In an embodiment, the display panel may further include: a spacer disposed on the pixel defining layer and adjacent to the contact area.

[0026] In an embodiment, the connection electrode may include: a first connection portion disposed in the contact region; and a second connection portion disposed on a side surface of the separator.

[0027] In an embodiment, the second electrode may include: a first electrode portion disposed on the first connection portion to contact an upper surface of the first connection portion; and a second electrode portion disposed on a side surface of the second connection portion to contact a side surface of the second connection portion.

[0028] In an embodiment, the connection electrode may further include a third connection portion disposed on an upper surface of the separator.

[0029] In an embodiment, at least a portion of the second connection portion may not be in contact with the second electrode.

[0030] In an embodiment, the intermediate layer may further include a functional layer, and the display panel may further include: a first dummy layer disposed on the partition; and a second dummy layer disposed on the first dummy layer, wherein the first dummy layer and the functional layer include the same material, and the second dummy layer and the second electrode include the same material.

[0031] In an embodiment, the connection electrode may not contact the second dummy layer.

[0032] In an embodiment, the display panel may include: a driving element layer including a plurality of pixel drivers; a plurality of light emitting elements disposed on the driving element layer and electrically connected to the plurality of pixel drivers, respectively; a plurality of connecting electrodes, respectively connected to the plurality of pixel drivers and the plurality of light emitting elements; and a partition disposed between the plurality of light emitting elements. Each of the plurality of light emitting elements may include: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. In a contact region adjacent to the partition, a lower surface of a second electrode of each of the plurality of light emitting elements contacts an upper surface of a corresponding connecting electrode among the plurality of connecting electrodes.

[0033] In an embodiment, the display panel may further include: a pixel defining layer disposed on the driving element layer and including an opening exposing at least a portion of the first electrode of each of the plurality of light emitting elements. A portion of each of the plurality of connecting electrodes may be disposed on the pixel defining layer, and a spacer may be disposed on the pixel defining layer.

[0034] In an embodiment, the plurality of light-emitting elements may include: a first light-emitting element; a second light-emitting element spaced apart from the first light-emitting element in a first direction; and a third light-emitting element spaced apart from the first light-emitting element and the second light-emitting element in a second direction intersecting the first direction. In the pixel defining layer: a first opening exposing at least a portion of a first electrode of the first light-emitting element may be defined, a second opening exposing at least a portion of a first electrode of the second light-emitting element may be defined, and a third opening exposing at least a portion of a first electrode of the third light-emitting element may be defined. The plurality of connection electrodes may include: a first connection electrode surrounding the first opening; a second connection electrode surrounding the second opening; and a third connection electrode surrounding the third opening.

[0035] In an embodiment, the plurality of pixel drivers may include: a first pixel driver electrically connected to the first light emitting element; a second pixel driver electrically connected to the second light emitting element; and a third pixel driver electrically connected to the third light emitting element. The first through hole, the second through hole, and the third through hole may pass through the pixel defining layer. The first connection electrode may be connected to the first pixel driver through the first through hole, the second connection electrode may be connected to the second pixel driver through the second through hole, and the third connection electrode may be connected to the third pixel driver through the third through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments and together with the description serve to explain the principles of the present invention. In the drawings:

[0037] Figure 1 is a schematic block diagram of a display device according to an embodiment;

[0038] Figure 2A is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0039] Figure 2B is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0040] Figure 2C is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0041] Figure 3A is a schematic plan view schematically illustrating a display panel according to an embodiment;

[0042] Figure 3B is a schematic plan view schematically illustrating a display panel according to an embodiment;

[0043] Figure 4A is an enlarged schematic plan view illustrating a partial area of ​​a display panel according to an embodiment;

[0044] Figure 4B is an enlarged schematic plan view illustrating a partial area of ​​a display panel according to an embodiment;

[0045] Figure 4C is an enlarged schematic plan view illustrating a partial area of ​​a display panel according to an embodiment;

[0046] Figure 4D is an enlarged schematic plan view illustrating a partial area of ​​a display panel according to an embodiment;

[0047] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment;

[0048] Figure 6 is an enlarged schematic cross-sectional view illustrating a partial area of ​​a display panel according to an embodiment;

[0049] 7A to 7D is an enlarged schematic cross-sectional view illustrating a partial area of ​​a display panel according to an embodiment;

[0050] Fig. 7E is capturing an image of a partial area of ​​the display panel according to the embodiment; and

[0051] Fig. 8A and Figure 8B is an enlarged schematic cross-sectional view illustrating a partial area of ​​a display panel according to an embodiment. DETAILED DESCRIPTION

[0052] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent settings. Here, various embodiments need not be exclusive, nor do they limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0053] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter referred to as "elements" respectively or collectively) may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0054] The use of cross hatching and / or shadows in the accompanying drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shadows does not convey or indicate any preference or demand for a specific material, material properties, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, for clarity and / or descriptive purposes, the size and relative size of the elements may be exaggerated. When the embodiment can be implemented in different ways, the specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals refer to the same elements.

[0055] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. In addition, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as the X-axis, the Y-axis, and the Z-axis), and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be understood to refer to only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0056] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0057] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "on," "above," "above," "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figure is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" can cover both above and below orientations. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or oriented in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0058] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "the (described)" as used herein are also intended to include plural forms. In addition, when used in this specification, the terms "include" and / or "comprise" indicate that there are stated features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It will also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as terms of degree, and are therefore used to include the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0059] Various embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as limited to the specific shapes of the areas shown, but rather include shape deviations caused by, for example, manufacturing. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and therefore, are not necessarily intended to be limiting.

[0060] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (e.g., logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It should also be expected that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuits) that perform certain functions to perform other functions. In addition, each block, unit and / or module in some embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules without departing from the scope of the present invention. Further, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0061] Hereinafter, embodiments are described with reference to the accompanying drawings.

[0062] Figure 1 is a block diagram of a display device DD according to an embodiment.

[0063] refer to Figure 1 , the display device DD may include a display panel DP, a panel driver SDC, EDC or DDC, a power supply unit PWS and a timing control unit TC. In an embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel or a quantum dot light-emitting display panel. In an embodiment to be described later, the organic light-emitting display panel is described in detail as an example. The panel driver SDC, EDC or DDC may include a scan driver SDC, an emission driver EDC and a data driver DDC.

[0064] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm (wherein m and n are integers greater than 1). The display panel DP may include pixels connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, the emission lines ESL1 to ESLn, and the data lines DL1 to DLm.

[0065] For example, a pixel PXij (where i and j are integers greater than 1) located on the i-th horizontal line (or i-th pixel row) and the j-th vertical line (or j-th pixel column) can be connected to the i-th first scan line (or write scan line GWLi), the i-th second scan line (or compensation scan line GCLi), the i-th third scan line (or first initialization scan line GILi), the i-th fourth scan line (or second initialization scan line GBLi), the i-th fifth scan line (or reset scan line GRLi), the j-th data line DLj and the i-th emission line ESLi.

[0066] The pixel PXij may include a light emitting element, a transistor, and a capacitor. The pixel PXij may receive a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (or a reference voltage VREF), a fourth power supply voltage (or a first initialization voltage VINT1), a fifth power supply voltage (or a second initialization voltage VINT2), and a sixth power supply voltage (or a compensation voltage VCOMP) through a power supply unit PWS.

[0067] The voltage values ​​of the first power supply voltage VDD and the second power supply voltage VSS can be set so that current can flow into the light emitting element to emit light. For example, the first power supply voltage VDD can be set higher than the second power supply voltage VSS.

[0068] The third power supply voltage VREF may be a voltage for initializing the gate of the driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to provide a specific grayscale by using a voltage difference with the data signal. To this end, the third power supply voltage VREF may be set to a specific voltage within the voltage range of the data signal.

[0069] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to be lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to be lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the embodiment is not limited thereto.

[0070] The fifth power supply voltage VINT2 may be a voltage for initializing a cathode of a light emitting element included in a pixel PXij. The fifth power supply voltage VINT2 may be set to be lower than the first power supply voltage VDD or the fourth power supply voltage VINT1 or to be close to or the same as the third power supply voltage VREF, but the embodiment is not limited thereto, and the fifth power supply voltage VINT2 may also be set to be close to or the same as the first power supply voltage VDD.

[0071] The sixth power supply voltage VCOMP may provide a specific current to the driving transistor while compensating for the threshold voltage of the driving transistor.

[0072] Figure 1 It is illustrated that all of the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, and VCOMP are supplied from the power supply unit PWS, but the embodiment is not limited thereto. For example, regardless of the structure of the pixel PXij, all of the first power supply voltage VDD and the second power supply voltage VSS may be supplied, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied corresponding to the structure of the pixel PXij.

[0073] According to embodiments, signal lines connected to the pixels PXij may be variously set corresponding to the circuit structure of the pixels PXij.

[0074] The scan driver SDC may receive a first control signal SCS from the timing control part TC, and the scan driver SDC may provide a scan signal to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0075] The scan signal may be set to a voltage that turns on a transistor receiving the scan signal. For example, the scan signal provided to a P-type transistor may be set to a logic low level, and the scan signal provided to an N-type transistor may be set to a logic high level. Hereinafter, the meaning of "a scan signal is provided" may be understood as a scan signal providing a logic level that turns on a transistor controlled by the scan signal.

[0076] For ease of description, Figure 1 The scan driver SDC is illustrated as a single component, but the embodiment is not limited thereto. According to the embodiment, a plurality of scan drivers may be included to provide scan signals to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn.

[0077] The emission driver EDC may provide the emission signal to the emission lines ESL1 to ESLn based on the second control signal ECS. For example, the emission signal may be sequentially provided to the emission lines ESL1 to ESLn.

[0078] According to an embodiment, the transistors connected to the emission lines ESL1 to ESLn may be N-type transistors. For example, the emission signals provided to the emission lines ESL1 to ESLn may be set to gate-on voltages. The transistors receiving the emission signals may be turned on when the emission signals are provided, and may be set to a cut-off state in other cases.

[0079] The second control signal ECS may include an emission start signal and a clock signal, and the emission driver EDC may be provided as a shift register that sequentially generates and outputs a pulse type emission signal by sequentially shifting the pulse type emission start signal using the clock signal.

[0080] The data driver DDC may receive the third control signal DCS and the image data RGB from the timing control part TC. The data driver DDC may convert the image data RGB in a digital format into an analog data signal (eg, a data signal). The data driver DDC may provide the data signal to the data lines DL1 to DLm in response to the third control signal DCS.

[0081] The third control signal DCS may include a data enable signal that guides the output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register that shifts the horizontal start signal in synchronization with the data clock signal and generates a sampling signal, a latch that latches the image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data (e.g., data in a digital format) into a data signal in an analog format, and a buffer (or amplifier) ​​that outputs the data signal to the data lines DL1 to DLm.

[0082] The power supply part PWS may supply the first power supply voltage VDD, the second power supply voltage VSS, and the third power supply voltage VREF for driving the pixel PXij to the display panel DP. In addition, the power supply part PWS may supply at least one voltage of the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP.

[0083] For example, the power supply parts PWS can respectively connect the first power supply lines VDL (see Figure 2A ), the second power line VSL (see Figure 2A ), the third power line (or reference voltage line VRL, see Figure 2A ), the fourth power line (or the first initialization voltage line VIL1, see Figure 2A ), the fifth power line (or the second initialization voltage line VIL2, see Figure 2A ) and the sixth power line (or compensation voltage line VCL, see Figure 2A ), a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VREF, a fourth power supply voltage VINT1, a fifth power supply voltage VINT2 and a sixth power supply voltage VCOMP are supplied to the display panel DP.

[0084] The power supply part PWS may be provided as a power management integrated circuit, but the embodiment is not limited thereto.

[0085] The timing control part TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, a clock signal, etc. The first control signal SCS may be provided to the scan driver SDC, the second control signal ECS may be provided to the emission driver EDC, the third control signal DCS may be provided to the data driver DDC, and the fourth control signal PCS may be provided to the power supply part PWS. The timing control part TC may generate image data RGB (or frame data) by rearranging the input image data IRGB corresponding to the arrangement of the pixels PXij in the display panel DP.

[0086] For example, the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply unit PWS and / or the timing control unit TC may be formed (e.g., directly formed) in the display panel DP, or may be provided as a separate driver chip to be connected to the display panel DP. For example, at least two of the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply unit PWS and the timing control unit TC may also be provided as a single driver chip. For example, the data driver DDC and the timing control unit TC may also be provided as a single driver chip.

[0087] In the above, reference has been made to Figure 1 The display device DD according to the embodiment is described, but the embodiment is not limited thereto. Depending on the configuration of the pixel, a signal line may be further included or omitted. In addition, the connection relationship between the pixel and the signal line may be changed. In the case where any one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0088] Figure 2A , Figure 2B and Figure 2C is a schematic diagram of an equivalent circuit of a pixel according to an embodiment. Figure 2A , Figure 2B and Figure 2C Corresponding schematic diagrams of equivalent circuits of pixels PXij, PXij-1, and PXij-2 connected to an i-th first scan line GWLi (hereinafter, a write scan line) and to a j-th data line DLj (hereinafter, a data line) are illustrated.

[0089] like Figure 2A As shown in FIG. 1 , the pixel PXij may include a light emitting element LD and a pixel driver PDC. The light emitting element LD may be connected to a first power line VDL and the pixel driver PDC.

[0090] The pixel driver PDC may be connected to the scan lines GWLi, GCLi, GILi, GBLi, and GRLi, the data lines DLj, the emission lines ESLi, and the power lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The pixel driver PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8, a first capacitor C1, and a second capacitor C2. Hereinafter, as an example, each of the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8 is described as an N-type transistor. However, the embodiment is not limited thereto, and some of the first to eighth transistors T1 to T8 may be N-type transistors and the other transistors may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be a P-type transistor, and the type is not limited to any one embodiment.

[0091] The gate of the first transistor T1 may be connected to the first node N1. The first electrode of the first transistor T1 may be connected to the second node N2, and the second electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL to the second power line VSL via the light emitting element LD in response to the voltage of the first node N1. For example, the first power supply voltage VDD may be set to have a potential higher than that of the second power supply voltage VSS.

[0092] In the specification, "a transistor is electrically connected to a signal line or a transistor is electrically connected to a transistor" means "a source, a drain or a gate of the transistor has an integral shape with the signal line or the source, the drain or the gate of the transistor or is connected to the signal line or the transistor through a connecting electrode".

[0093] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide the data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 may be turned on when the write scan signal GW is provided to the write scan line GWLi, and thus may electrically connect the data line DLj and the first node N1.

[0094] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and the second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, the gate of the third transistor T3 may receive the reset scan signal GR through the i-th fifth scan line GRLi (hereinafter, the reset scan line). The third transistor T3 may be turned on when the reset scan signal GR is supplied to the reset scan line GRLi, and thus the reference voltage VREF may be supplied to the first node N1.

[0095] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 may be connected to the third node N3, and the second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 providing the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. The gate of the fourth transistor T4 may receive the first initialization scan signal GI through the i-th third scan line GILi (hereinafter, the first initialization scan line). The fourth transistor T4 may be turned on when the first initialization scan signal GI is provided to the first initialization scan line GILi, and thus the first initialization voltage VINT1 may be provided to the third node N3.

[0096] The fifth transistor T5 may be connected between the compensation voltage line VCL and the second node N2. The first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP through the compensation voltage line VCL, and the second electrode of the fifth transistor T5 may be connected to the second node N2 to be electrically connected to the first electrode of the first transistor T1. The gate of the fifth transistor T5 may receive the compensation scan signal GC through the i-th second scan line GCLi (hereinafter, the compensation scan line). The fifth transistor T5 may be turned on when the compensation scan signal GC is supplied to the compensation scan line GCLi, and the compensation voltage VCOMP is supplied to the second node N2, so that the threshold voltage of the first transistor T1 may be compensated during the compensation period.

[0097] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. For example, the gate of the sixth transistor T6 may receive an emission signal EM through an i-th emission line ESLi (hereinafter, an emission line). The first electrode of the sixth transistor T6 may be connected to the cathode of the light emitting element LD through a fourth node N4, and the second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1 through a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. The sixth transistor T6 may be turned on when the emission signal EM is provided to the emission line ESLi, and the light emitting element LD and the first transistor T1 may be electrically connected.

[0098] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. The first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the seventh transistor T7 may receive the second power supply voltage VSS through the second power line VSL. The gate of the seventh transistor T7 may be electrically connected to the emission line ESLi. The seventh transistor T7 may be referred to as a second emission control transistor. The seventh transistor T7 may be turned on when the emission signal EM is provided to the emission line ESLi, and may electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0099] In the embodiment, the sixth transistor T6 and the seventh transistor T7 are connected to the same emission line ESLi and are turned on by the same emission signal EM, but this is an example, and the sixth transistor T6 and the seventh transistor T7 may also be turned on independently of each other in response to different signals distinguished from each other. In addition, in the pixel driver PDC according to the embodiment, any one of the sixth transistor T6 and the seventh transistor T7 may also be omitted.

[0100] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. For example, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter, the second initialization scan line), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may provide the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0101] In an embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7 and T8 can be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can operate in response to the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 can be turned on / off simultaneously by the same compensation scan signal GC. For example, the compensation scan line GCLi and the second initialization scan line GBLi can also be substantially provided as a single scan line. Accordingly, the initialization of the cathode of the light emitting element LD and the compensation of the threshold voltage of the first transistor T1 can be performed with the same timing. However, this is an example and is not limited to any one embodiment.

[0102] In addition, according to an embodiment, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 can be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be substantially provided as a single power supply line. For example, the cathode initialization operation and the threshold voltage compensation operation of the driving transistor can be performed using a power supply voltage (e.g., a single power supply voltage), so that the design of the driver can be simplified. However, this is an example and is not limited to any one embodiment.

[0103] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store charges corresponding to a voltage difference between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0104] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. For example, one electrode of the second capacitor C2 may be connected to the second power line VSL receiving the second power voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a holding capacitor. The second capacitor C2 may have a storage capacity higher than that of the first capacitor C1. Accordingly, the second capacitor C2 may minimize a voltage change of the third node N3 in response to a voltage change of the first node N1.

[0105] In an embodiment, the light emitting element LD may be connected to the pixel driver PDC via a fourth node N4. The light emitting element LD may include an anode connected to the first power line VDL and a cathode opposite to the anode. In an embodiment, the light emitting element LD may be connected to the pixel driver PDC via a cathode. For example, in a pixel PXij according to an embodiment, a connection node at which the light emitting element LD and the pixel driver PDC are connected may be a fourth node N4, and the fourth node N4 may correspond to a connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Accordingly, the potential of the fourth node N4 may substantially correspond to the potential of the cathode of the light emitting element LD.

[0106] Specifically, the anode of the light emitting element LD can be connected to the first power line VDL so that the first power supply voltage VDD, which is a constant voltage, can be applied to the anode of the light emitting element LD, and the cathode can be connected to the first transistor T1 through the sixth transistor T6. For example, in an embodiment where the first transistor T1 to the eighth transistor T8 are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if degradation occurs in the light emitting element LD, the influence on the gate-source voltage (Vgs) of the transistor constituting the pixel driver PDC (for example, the gate-source voltage (Vgs) of the driving transistor) can be reduced. For example, because the amount of change in the driving current ILD caused by the degradation of the light emitting element LD can be reduced, the afterimage defect on the display panel caused by the increase in the use time can be reduced, and the life span can be improved.

[0107] In another example, if Figure 2B As shown in FIG. 1 , the pixel PXij- 1 may also include a pixel driver PDC- 1 having two transistors T1 and T2 and a first capacitor C1 . The pixel driver PDC- 1 may be connected to the light emitting element LD, the write scan line GWLi, the data line DLj and the second power line VSL. Figure 2B The pixel driver PDC-1 shown in FIG. Figure 2A 2. The pixel driver PDC shown in FIG. 1 is a pixel driver PDC in which the third to eighth transistors T3 to T8 and the second capacitor C2 are omitted.

[0108] The first transistor T1 and the second transistor T2 may each be an N-type transistor or a P-type transistor. In an embodiment, each of the first transistor T1 and the second transistor T2 is described as an N-type transistor.

[0109] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL through a light emitting element LD, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 may be connected to the light emitting element LD through a second node N2, and to the second power line VSL through a third node N3. The first transistor T1 may be a driving transistor.

[0110] The second transistor T2 may include a gate receiving a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0111] The first capacitor C1 may include one electrode connected to the first node N1 and another electrode connected to the third node N3. The first capacitor C1 may store the data signal DATA transmitted to the first node N1.

[0112] The light emitting element LD may include an anode and a cathode. In an embodiment, the anode of the light emitting element LD may be connected to the first power line VDL, and the cathode may be connected to the pixel driver PDC-1 through the second node N2. In an embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light corresponding to the amount of current flowing through the first transistor T1 of the pixel driver PDC-1.

[0113] In an embodiment where the first transistor T1 and the second transistor T2 are N-type transistors, the cathode of the light emitting element LD and the second node N2 at which the pixel driver PDC-1 is connected may correspond to the drain of the first transistor T1. For example, a change in the gate-source voltage (Vgs) of the first transistor T1 due to the light emitting element LD may be prevented. Accordingly, since the amount of change in the drive current ILD due to the degradation of the light emitting element LD may be reduced, afterimage defects on the display panel due to an increase in the use time may be reduced, and the lifespan may be improved.

[0114] In another example, if Figure 2C As shown in , the pixel PXij- 2 may also include a pixel driver PDC- 2 having six transistors T1 , T2 , T3 , T4 a , T5 a and T6 a and two capacitors C1 and C2 .

[0115] The pixel driver PDC-2 can be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first emission line ESL1i (hereinafter, the first emission line), the i-th second emission line ESL2i (hereinafter, the second emission line), the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL and the initialization voltage line VIL.

[0116] Figure 2C The pixel driver PDC-2 shown in the figure can be used with Figure 2A The pixel driver PDC is similar to the pixel driver PDC shown in FIG. 1 , in which the fourth transistor T4 and the fifth transistor T5 are omitted. Figure 2C The area of ​​the pixel driver PDC-2 shown in the figure is smaller than Figure 2A The area of ​​the pixel driver PDC shown in the figure is reduced, so high resolution can be more easily achieved.

[0117] The first to sixth transistors T1, T2, T3, T4a, T5a and T6a may each be an N-type transistor or a P-type transistor. In an embodiment, each of the first to sixth transistors T1, T2, T3, T4a, T5a and T6a is described as an N-type transistor.

[0118] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL through a light emitting element LD, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 may be connected to the light emitting element LD through a second node N2, and to the second power line VSL through a third node N3. The first transistor T1 may be a driving transistor.

[0119] The second transistor T2 may include a gate receiving a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0120] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and the second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, the gate of the third transistor T3 may receive the reset scan signal GR through the reset scan line GRLi. The third transistor T3 may be turned on when the reset scan signal GR is supplied to the reset scan line GRLi, and supply the reference voltage VREF to the first node N1.

[0121] The fourth transistor T4a may be connected between the first transistor T1 and the light emitting element LD. For example, the gate of the fourth transistor T4a may receive the first emission signal EM1 through the first emission line ESL1i. The first electrode of the fourth transistor T4a may be connected to the cathode of the light emitting element LD through the fourth node N4, and the second electrode of the fourth transistor T4a may be connected to the first electrode of the first transistor T1 through the second node N2. The fourth transistor T4a may be referred to as a first emission control transistor. The fourth transistor T4a may be turned on when the first emission signal EM1 is provided to the first emission line ESL1i, and the light emitting element LD and the first transistor T1 may be electrically connected.

[0122] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. The first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the fifth transistor T5a may receive the second power supply voltage VSS through the second power line VSL. The gate of the fifth transistor T5a may be electrically connected to the second emission line ESL2i. The fifth transistor T5a may be referred to as a second emission control transistor. The fifth transistor T5a may be turned on when the second emission signal EM2 is provided to the second emission line ESL2i, and electrically connects the second electrode of the first transistor T1 to the second power line VSL.

[0123] In an embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to a first emission line ESL1i and a second emission line ESL2i respectively, and thus may be turned on by a first emission signal EM1 and a second emission signal EM2 respectively. For example, the fourth transistor T4a and the fifth transistor T5a may be turned on independently of each other. However, this is an example, and the embodiment is not limited thereto. For example, according to an embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to the same emission line and controlled by the same emission signal. In addition, in the pixel driver PDC-2 according to the embodiment, any one of the fourth transistor T4a and the fifth transistor T5a may also be omitted.

[0124] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. For example, the sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may provide an initialization voltage VINT to a fourth node N4 corresponding to a cathode of the light emitting element LD in response to a compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0125] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store charges corresponding to a voltage difference between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0126] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. For example, one electrode of the second capacitor C2 may be connected to the second power line VSL receiving the second power voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a holding capacitor.

[0127] The light emitting element LD may include an anode and a cathode. In an embodiment, the anode of the light emitting element LD may be connected to the first power line VDL, and the cathode may be connected to the pixel driver PDC-2 through the fourth node N4. In an embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1 through the fourth transistor T4a. The light emitting element LD may emit light corresponding to the amount of current flowing through the first transistor T1 of the pixel driver PDC-2.

[0128] In an embodiment where the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if degradation occurs in the light emitting element LD, the influence on the gate-source voltage (Vgs) of the transistor constituting the pixel driver PDC-2 (for example, the gate-source voltage (Vgs) of the driving transistor) may be reduced. For example, because the amount of change in the driving current ILD caused by the degradation of the light emitting element LD may be reduced, the afterimage defect on the display panel caused by the increase in the use time may be reduced, and the lifespan may be improved.

[0129] Figure 2A , Figure 2B and Figure 2C The circuits of the pixel drivers PDC, PDC-1 and PDC-2 according to the embodiments are illustrated, and in the display panel according to the embodiments, as long as the circuit is connected to the cathode of the light-emitting element LD, the number of transistors or their arrangement relationship and the number of capacitors or their arrangement relationship can be variously designed, and the circuit is not limited to any one embodiment.

[0130] Figure 3A and Figure 3B is a schematic plan view schematically illustrating a display panel DP according to the embodiment. Figure 3A and Figure 3B Each of the diagrams is a schematic plan view in which some components are omitted. Figure 3A and Figure 3B Embodiments are described.

[0131] refer to Figure 3A, the display panel DP according to the embodiment may be divided into a display area DA and a peripheral area (or a non-display area NDA). The display area DA may include a light emitting part EP.

[0132] The light emitting portion EP may be a pixel PXij (see Figure 1 ) respectively emit light. For example, the light emitting portions EP may each be aligned with a light emitting opening OP-PDL (see Figure 5 The light emitting opening OP-PDL may be referred to as an opening or an opening portion.

[0133] The peripheral area NDA may be disposed adjacent to the display area DA. In the embodiment, the peripheral area NDA is illustrated as a shape surrounding an edge portion of the display area DA. However, this is an example, and the peripheral area NDA may be disposed on one side of the display area DA or may also be omitted, and is not limited to any one embodiment.

[0134] In an embodiment, a scan driver SDC and a data driver DDC may be installed in the display panel DP. In an embodiment, the scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the peripheral area NDA. The scan driver SDC may overlap at least some of the light emitting portions EP disposed in the display area DA in a plane (or in a plan view). Since the scan driver SDC is disposed in the display area DA, the area of ​​the peripheral area NDA may be reduced compared to the area of ​​a typical display panel in which the scan driver is disposed in the peripheral area, and a display device having a narrow frame may be easily implemented.

[0135] In addition, Figure 3A Unlike the illustration in FIG. 1 , the scan driver SDC may also be provided as two parts distinguishable from each other. The two parts of the scan driver SDC may be separately provided on the left and right sides with the center of the display area DA located therebetween. In another example, the scan driver SDC may also be provided in approximately 2 or more numbers, and is not limited to any one embodiment.

[0136] Figure 3A An example of the display panel DP is illustrated, and the data driver DDC may also be disposed in the display area DA. For example, some of the light emitting parts EP disposed in the display area DA may overlap the data driver DDC on a plane (or in a plan view).

[0137] In an embodiment, the data driver DDC may be provided as a separate driving chip independent of the display panel DP and connected to the display panel DP. However, this is an example, and the data driver DDC and the scan driver SDC may also be formed in the same process to form the display panel DP, and the configuration is not limited to any one embodiment.

[0138] like Figure 3B As shown in , the display panel DP may also have a shape in which the length corresponding to the first direction DR1 is greater than the length corresponding to the second direction DR2. It is illustrated that in the display area DA, the pixels PX11 to PXnm are arranged in n rows and m columns. In an embodiment, the display panel DP may include scan drivers SDC1 and SDC2. It is illustrated that the scan drivers SDC1 and SDC2 include a first scan driver SDC1 and a second scan driver SDC2 spaced apart from each other in the first direction DR1.

[0139] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to the other scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0140] For ease of description, Figure 3B The pads PD of the data lines DL1 to DLm are shown. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driver DDC (see FIG. Figure 3A ).

[0141] According to an embodiment, the pads PD may be divided to be arranged at positions of the peripheral area NDA spaced apart from each other with the display area DA located therebetween. For example, some of the pads PD may be disposed on the upper side of the side adjacent to the first scan line GL1 among the scan lines GL1 to GLn, and other of the pads PD may be disposed on the lower side of the side adjacent to the last scan line GLn among the scan lines GL1 to GLn. In an embodiment, the pads PD connected to the odd-numbered data lines among the data lines DL1 to DLm may be disposed on the upper side, and the pads PD connected to the even-numbered data lines among the data lines DL1 to DLm may be disposed on the lower side.

[0142] Although not illustrated in the figure, the display panel DP may include a plurality of upper data drivers connected to the pads PD provided on the upper side and / or a plurality of lower data drivers connected to the pads PD provided on the lower side. However, this is an example, and the display panel DP may also include one upper data driver connected to the pads PD provided on the upper side and / or one lower data driver connected to the pads PD provided on the lower side. The pads PD according to the embodiment may also be provided only on one side of the display panel DP to be connected to a single data driver, and the configuration is not limited to any one embodiment.

[0143] In addition, if Figure 3A As shown in Figure 3B The display panel DP may also have a scan driver and / or a data driver arranged in the display area DA, and accordingly, some of the light-emitting parts EP arranged in the display area DA may overlap with the scan driver and / or the data driver on a plane (or in a plan view).

[0144] 4A to 4D is an enlarged schematic plan view illustrating a partial area of ​​a display panel according to an embodiment.

[0145] Figure 4A The figure shows two rows and two columns of light emitting units UT11, UT12, UT21 and UT22. Figure 4A The light-emitting part EP in the first row Rk includes the light-emitting part EP constituting the first row and first column light-emitting unit UT11 and the first row and second column light-emitting unit UT12, and the light-emitting part EP in the second row Rk+1 includes the light-emitting part EP constituting the second row and first column light-emitting unit UT21 and the second row and second column light-emitting unit UT22.

[0146] The light emitting portions EP (eg, EP1, EP2, and EP3) may each be connected to a light emitting opening OP-PDL (see Figure 5 ) corresponds to. For example, the light emitting portions EP1, EP2 and EP3 may each be a region where the aforementioned light emitting element LD emits light. The light emitting portions EP1, EP2 and EP3 may correspond to the regions generated on the display panel DP (see Figure 1 ) corresponds to a unit of an image displayed on the image display. For example, the light emitting portions EP1, EP2, and EP3 may each correspond to an area defined by a light emitting opening OP-PDL to be described later (eg, an area defined by the lower side of the light emitting opening OP-PDL).

[0147] The light-emitting parts EP1, EP2 and EP3 may include a first light-emitting part EP1, a second light-emitting part EP2 and a third light-emitting part EP3. The first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3 may emit light of different colors. For example, the first light-emitting part EP1 may emit red light, the second light-emitting part EP2 may emit green light, and the third light-emitting part EP3 may emit blue light, but the combination of colors is not limited thereto. In addition, at least two of the first to third light-emitting parts EP1, EP2 and EP3 may emit light of the same color. For example, all of the first to third light-emitting parts EP1, EP2 and EP3 may emit blue light, or may also emit white light.

[0148] The third light emitting portion EP3 displaying the light emitted by the third light emitting element LD3 among the first to third light emitting portions EP1, EP2 and EP3 may include two sub-light emitting portions EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is an example, and the third light emitting portion EP3 may also be provided as a pattern having an integral shape like the first light emitting portion EP1 and the second light emitting portion EP2, and at least one of the first light emitting portion EP1 and the second light emitting portion EP2 may also include sub-light emitting portions spaced apart from each other, and the configuration is not limited to any one embodiment.

[0149] The light-emitting part EP in the first row Rk may include the first to third light-emitting parts EP1, EP2 and EP3 constituting the first row and first column light-emitting unit UT11 and the first to third light-emitting parts EP1, EP2 and EP3a constituting the first row and second column light-emitting unit UT12, and the light-emitting part EP in the second row Rk+1 may include the first to third light-emitting parts EP1, EP2 and EP3a constituting the second row and first column light-emitting unit UT21 and the first to third light-emitting parts EP1, EP2 and EP3 constituting the second row and second column light-emitting unit UT22.

[0150] According to an embodiment, the light emitting portion EP constituting the first row and first column light emitting unit UT11 and the light emitting portion EP constituting the second row and second column light emitting unit UT22 may have substantially the same shape. In addition, the light emitting portion EP constituting the first row and second column light emitting unit UT12 and the light emitting portion EP constituting the second row and first column light emitting unit UT21 may have substantially the same shape. The shape of the light emitting portion EP constituting the first row and first column light emitting unit UT11 may be different from the shape of the light emitting portion EP constituting the first row and second column light emitting unit UT12. For example, some of the light emitting portions EP in the first row Rk and some of the light emitting portions EP in the second row Rk+1 may have symmetrical shapes.

[0151] According to the embodiment, the third light emitting portion EP3a of the second row and first column light emitting unit UT21 and the third light emitting portion EP3 of the first row and first column light emitting unit UT11 may have a shape and arrangement form symmetrical about an axis parallel to the first direction DR1, and the third light emitting portion EP3 of the second row and second column light emitting unit UT22 and the third light emitting portion EP3a of the first row and second column light emitting unit UT12 may have a shape and arrangement form symmetrical about an axis parallel to the first direction DR1. However, this is an example, and the embodiment is not limited thereto.

[0152] Figure 4B The light emitting parts EP are shown arranged in a single row. Figure 4BThe second electrodes EL2 (eg, EL2_1 , EL2_2 , and EL2_3 ), the pixel drivers PDC (eg, PDC1 , PDC2 , and PDC3 ), the connection electrodes CNE (eg, CNE1 , CNE2 , and CNE3 ), and the spacers SPR are illustrated. Figure 4C A spacer SPR, light emitting parts EP1 , EP2 , and EP3 disposed in a region partitioned by the spacer SPR, and connection electrodes CNE1 , CNE2 , and CNE3 are illustrated among components of the display panel DP.

[0153] refer to Figure 4B and Figure 4C , the second electrodes EL2_1, EL2_2 and EL2_3 may be separated by a separator SPR and thus may be electrically disconnected from each other. In an embodiment, a single light emitting unit UT11 may include three light emitting portions EP1, EP2 and EP3. Accordingly, the light emitting unit UT11 may include three second electrodes EL2_1, EL2_2 and EL2_3 (hereinafter, first cathode to third cathode), three pixel drivers PDC1, PDC2 and PDC3, and three connection electrodes CNE1, CNE2 and CNE3. However, this is an example, and the number and arrangement of the light emitting portions EP included in the light emitting unit UT11 may be variously designed and are not limited to any one embodiment.

[0154] The first to third pixel drivers PDC1, PDC2 and PDC3 may be electrically connected to the first to third light emitting elements LD1, LD2 and LD3 including the first to third light emitting parts EP1, EP2 and EP3, respectively. In the specification, the meaning of "connection" includes not only the case of physical connection through direct contact, but also the case of electrical connection.

[0155] In addition, if Figure 4B As shown in FIG. 1 , each area defined by the first to third pixel drivers PDC1, PDC2 and PDC3 on a plane (or in a plan view) may be aligned with the light emitting element LD (see FIG. 1 ) for driving the pixel. Figure 2A ) of the pixel driver PDC (see Figure 2A ) corresponds to a unit in which transistor and capacitor elements are repeatedly arranged.

[0156] The first to third pixel drivers PDC1, PDC2 and PDC3 may be sequentially arranged along the first direction DR1. In addition, the positions at which the first to third pixel drivers PDC1, PDC2 and PDC3 are arranged may be independently designed regardless of the positions or shapes of the first to third light emitting parts EP1, EP2 and EP3.

[0157] For example, the first to third pixel drivers PDC1, PDC2 and PDC3 may be disposed at a position different from the region defined by division by the partition SPR (e.g., the position at which the first to third cathodes EL2_1, EL2_2 and EL2_3 are disposed), or may be designed to have a shape and area different from the shapes and areas of the first to third cathodes EL2_1, EL2_2 and EL2_3, respectively. In another example, the first to third pixel drivers PDC1, PDC2 and PDC3 may overlap with the positions at which the first to third light emitting portions EP1, EP2 and EP3 are disposed, respectively, and may also be designed to have a shape and area similar to the area and shape of the region defined by division by the partition SPR (e.g., the first to third cathodes EL2_1, EL2_2 and EL2_3).

[0158] In the embodiment, each of the first to third pixel drivers PDC1, PDC2 and PDC3 is illustrated as a rectangular shape, and each of the first to third light emitting portions EP1, EP2 and EP3 is arranged in an area smaller than the area of ​​the shape and in a shape different therefrom. The first to third cathodes EL2_1, EL2_2 and EL2_3 are arranged at positions overlapping the first to third light emitting portions EP1, EP2 and EP3, respectively, but are illustrated as irregular shapes.

[0159] Accordingly, if Figure 4B As shown in , the first pixel driver PDC1 can be set at a position partially overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and another light-emitting unit adjacent thereto. The second pixel driver PDC2 can be set at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and the third cathode EL2_3. The third pixel driver PDC3 can be set at a position overlapping with the third light-emitting portion EP3. This is an example, and the positions of the first to third pixel drivers PDC1, PDC2, and PDC3 can be designed in various shapes and arrangements independently of the first to third light-emitting portions EP1, EP2, and EP3, and are not limited to any one embodiment.

[0160] The light emitting unit UT11 may include first to third connection electrodes CNE1, CNE2, and CNE3. The first connection electrode CNE1 may electrically connect the first pixel driver PDC1 and the first light emitting element LD1 forming the first light emitting portion EP1 (or defining the first light emitting portion EP1). The second connection electrode CNE2 may electrically connect the second pixel driver PDC2 and the second light emitting element LD2 forming the second light emitting portion EP2. The third connection electrode CNE3 may electrically connect the third pixel driver PDC3 and the third light emitting element LD3 forming the third light emitting portion EP3.

[0161] For example, the first to third connection electrodes CNE1 , CNE2 , and CNE3 may electrically connect the first to third cathodes EL2_1 , EL2_2 , and EL2_3 with the first to third pixel drivers PDC1 , PDC2 , and PDC3 in a one-to-one correspondence, respectively.

[0162] The first to third connection electrodes CNE1, CNE2, and CNE3 may be each disposed on a pixel defining layer PDL (see FIG. 1 ) to be described later. Figure 5 ). The first to third connection electrodes CNE1, CNE2, and CNE3 may have a ring shape surrounding the corresponding first to third light emitting parts EP1, EP2, and EP3. According to the embodiment, it is illustrated that each of the first to third connection electrodes CNE1, CNE2, and CNE3 has a closed line ring shape, but the embodiment is not limited thereto. For example, at least some of the first to third connection electrodes CNE1, CNE2, and CNE3 may have an open ring shape in which a portion thereof is disconnected.

[0163] Since the first to third connection electrodes CNE1, CNE2, and CNE3 have a ring shape, the degree of freedom of the positions at which the first to third connection electrodes CNE1, CNE2, and CNE3 are connected to the first to third pixel drivers PDC1, PDC2, and PDC3, respectively, can be increased. For example, the first connection electrode CNE1 can be connected to the first pixel driver PDC1 through the first contact portion CE1, the second connection electrode CNE2 can be connected to the second pixel driver PDC2 through the second contact portion CE2, and the third connection electrode CNE3 can be connected to the third pixel driver PDC3 through the connection line CN3. For example, the connection line that is additionally connected to the first connection electrode CNE1 and the second connection electrode CNE2 can be omitted.

[0164] The connection line CN3 can electrically connect the third pixel driver PDC3 and the third light emitting element LD3 constituting the third light emitting portion EP3. For example, the connection line CN3 can correspond to the light emitting element LD (see Figure 2A ) where it is connected to Figure 2A The pixel driver PDC in Figure 2B The pixel driver PDC-1 or Figure 2C The node of the pixel driver PDC-2 in Figure 2A The fourth node N4 in Figure 2B The second node N2 in Figure 2C The fourth node N4 in the.

[0165] The connection line CN3 may include a third contact portion CE3 and a driving contact portion CD3. The third contact portion CE3 may be formed (or provided) at one side of the connection line CN3, and the driving contact portion CD3 may be formed (or provided) at the other side of the connection line CN3.

[0166] The driving contact portion CD3 may be a portion of the connection line CN3 connected to the third pixel driver PDC3. In an embodiment, the driving contact portion CD3 may be connected to an electrode of a transistor constituting the third pixel driver PDC3. For example, the driving contact portion CD3 may be connected to Figure 2A The drain of the sixth transistor T6 shown in FIG. Figure 2B The drain of the first transistor T1 shown in FIG. Figure 2C The drain of the fourth transistor T4a illustrated in FIG. 1 is a drain of the fourth transistor T4a illustrated in FIG. Accordingly, the position of the driving contact portion CD3 may correspond to the position at which the transistor of the third pixel driver PDC3 is physically connected to the connection line CN3. The third contact portion CE3 may be a portion of the connection line CN3 connected to the third light emitting element LD3. In an embodiment, the third contact portion CE3 may be connected to the third connection electrode CNE3.

[0167] The first connection electrode CNE1 may include a first edge portion EG11 surrounding at least a portion of the first light emitting portion EP1 and a second edge portion EG12 surrounding the first edge portion EG11. The second connection electrode CNE2 may include a first edge portion EG21 surrounding at least a portion of the second light emitting portion EP2 and a second edge portion EG22 surrounding the first edge portion EG21. The third connection electrode CNE3 may include a first edge portion EG31 surrounding at least a portion of the third light emitting portion EP3 and a second edge portion EG32 surrounding the first edge portion EG31.

[0168] The first to third connection electrodes CNE1, CNE2, and CNE3 may be spaced apart from each other. For example, gaps GP1, GP2, and GP3 between connection electrodes adjacent to each other among the first to third connection electrodes CNE1, CNE2, and CNE3 may overlap with the separator SPR. For example, first edge portions EG11, EG21, and EG31 of the first to third connection electrodes CNE1, CNE2, and CNE3 may not be covered by the separator SPR, and second edge portions EG12, EG22, and EG32 of the first to third connection electrodes CNE1, CNE2, and CNE3 may overlap with the separator SPR. In another example, second edge portions EG12, EG22, and EG32 of the first to third connection electrodes CNE1, CNE2, and CNE3 may be covered by the separator SPR.

[0169] According to an embodiment, the first to third contact portions CE1, CE2 and CE3 may be disposed at positions that do not overlap with the first to third light emitting portions EP1, EP2 and EP3 on a plane (or in a plan view). For example, a light emitting opening OP-PDL (see FIG. 1 ) may be formed (or defined) in the pixel defining layer PDL. Figure 5) and a through hole OP-P (see Figure 5 ).

[0170] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third contact portions CE1, CE2, and CE3 may be arranged corresponding to the first to third through holes OP-P1, OP-P2, and OP-P3, respectively. The light emitting opening OP-PDL may include a first light emitting opening OP-PDL1, a second light emitting opening OP-PDL2, and a third light emitting opening OP-PDL3. The first to third light emitting portions EP1, EP2, and EP3 may be defined corresponding to the first to third light emitting openings OP-PDL1, OP-PDL2, and OP-PDL3, respectively. Therefore, the first to third contact portions CE1, CE2, and CE3 may be disposed at positions spaced apart from the first to third light emitting portions EP1, EP2, and EP3.

[0171] The first to third connection electrodes CNE1, CNE2, and CNE3 may be disposed on the pixel defining layer PDL (see Figure 5 When viewed on a plane (or in a plan view), the first connection electrode CNE1 may surround the first light emitting opening OP-PDL1, the second connection electrode CNE2 may surround the second light emitting opening OP-PDL2, and the third connection electrode CNE3 may surround the third light emitting opening OP-PDL3.

[0172] According to an embodiment, the driving contact portion CD3 (which is a transistor TR (see FIG. 1 ) at which the connection line CN3 is connected to the third pixel driver PDC3) Figure 5 ) may be limited to a position that does not overlap with the third contact portion CE3 on a plane (or in a plan view), and may be set at a position that overlaps with the third light emitting portion EP3. Since the third cathode EL2_3 and the third pixel driver PDC3 are connected to each other through the connection line CN3, the restrictions on the design of the third pixel driver PDC3 due to the position or shape of the third light emitting portion EP3 may be reduced, so that the degree of freedom of design may be improved.

[0173] The first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to the first to third connection electrodes CNE1, CNE2, and CNE3, respectively. For example, the lower surfaces of the first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to (or in contact with) the upper surfaces of the first to third connection electrodes CNE1, CNE2, and CNE3, respectively. Therefore, the contact reliability (or connection stability) between the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third connection electrodes CNE1, CNE2, and CNE3 may be further improved.

[0174] In addition, the contact areas at which the first to third cathodes EL2_1, EL2_2 and EL2_3 are respectively connected to the first to third connection electrodes CNE1, CNE2 and CNE3 may surround at least a portion of the first to third light emitting openings OP-PDL1, OP-PDL2 and OP-PDL3, respectively. The first to third cathodes EL2_1, EL2_2 and EL2_3 and the first to third connection electrodes CNE1, CNE2 and CNE3 may be respectively connected in an area adjacent to the partition SPR, and the contact areas may be each defined as being adjacent to the partition SPR. For example, the first to third cathodes EL2_1, EL2_2 and EL2_3 and the first to third connection electrodes CNE1, CNE2 and CNE3 may not be connected at a specific point, and may be connected in a relatively large area (for example, in an area similar to the shape of each of the first to third connection electrodes CNE1, CNE2 and CNE3). For example, as the contact area for connection increases, connection may be stably performed.

[0175] Figure 4D The separator SPR, the light emitting parts EP1 , EP2 , and EP3 , and the first electrode EL1 are illustrated.

[0176] refer to Figure 4D According to the embodiment, the light emitting element LD (see Figure 5 The first electrode EL1 (hereinafter, anode) of the light emitting element LD may be commonly provided to the first to third light emitting parts EP1, EP2 and EP3. For example, the anode EL1 may be formed as a single layer integrated throughout the display area DA, and accordingly, the anode EL1 may be disposed overlapping with the partition SPR. In another example, the anode EL1 of the light emitting element LD may be formed as independent conductive patterns spaced apart from each other, and may also be electrically connected to each other through another conductive layer, and accordingly, the anode EL1 may also be disposed not overlapping with the partition SPR.

[0177] As mentioned above, the first power supply voltage VDD (see Figure 2A ) may be applied to the anode EL1, and a common voltage may be provided to all the light emitting parts EP. The anode EL1 may be connected to a first power line VDL (see FIG. 1 ) that provides a first power supply voltage VDD in the peripheral area NDA. Figure 2A ) or connected to the first power line VDL in the display area DA (see Figure 2A ), and is not limited to any one embodiment.

[0178] In addition, according to an embodiment, an opening may be formed (or defined) in the anode EL1, and the opening may pass through the anode EL1. The opening in the anode EL1 may be disposed at a position not adjacent to the light emitting portion EP (see Figure 3A) and is generally defined at a position overlapping with the separator SPR. The opening can facilitate the organic layer (eg, the sixth insulating layer 60 (see FIG. 1 ) disposed below the anode EL1. Figure 5 )) The emission of gases generated. Accordingly, in the display panel manufacturing process, it may be possible to fully discharge the gas of the organic layer disposed below the light emitting element LD, and after the manufacturing process, the gas emitted from the organic layer may be reduced, so that the rate of degradation of the light emitting element LD may be reduced.

[0179] Figure 5 is a schematic cross-sectional view of a display panel DP according to an embodiment. Figure 6 is an enlarged schematic cross-sectional view illustrating a partial area of ​​the display panel DP according to the embodiment.

[0180] Figure 5 It is a graphic with Figure 4A A schematic cross-sectional view of a portion corresponding to line II'. Figure 6 yes Figure 5 An enlarged schematic cross-sectional view of region AA'.

[0181] refer to Figure 5 and Figure 6 The display panel DP according to the embodiment may include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL. However, this is an example, and according to the embodiment, the display panel DP may not include the sensing layer ISL.

[0182] The driving element layer DDL may include insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS and conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, and 60, and thus may form a pixel driver PDC. For ease of description, Figure 5 A cross section of any one portion of a region where a light emitting portion (eg, a single light emitting portion) is provided is illustrated.

[0183] The base layer BS may be a member providing a base surface on which the pixel driver PDC is disposed. The base layer BS may be a rigid substrate or a flexible substrate capable of bending, folding, and curling, etc. The base layer BS may be a glass substrate, a metal substrate, or a polymer substrate. However, the embodiment is not limited thereto, and the base layer BS may also be an inorganic layer, an organic layer, or a composite material layer.

[0184] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiOx ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0185] The polymer resin layer may include a polyimide resin. For example, the polymer resin layer may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In the specification, the term "polyimide-type" resin refers to a functional group including "polyimide".

[0186] The insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BS may each be formed by a coating process, a deposition process, etc. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by multiple cycles of a photolithography process to form holes in the insulating layer or to form semiconductor patterns, conductive patterns, signal lines, etc.

[0187] The driving element layer DDL may include first to sixth insulating layers 10 , 20 , 30 , 40 , 50 , and 60 and a pixel driver PDC sequentially stacked on the base layer BS. Figure 5 One transistor TR and two capacitors C1 and C2 of the pixel driver PDC are shown.

[0188] The transistor TR may correspond to a transistor connected to the light emitting element LD through the intermediate connection electrode CN and the connection electrode CNE. For example, the transistor TR may correspond to a node (eg, Figure 2A The fourth node N4 in Figure 2B The second node N2 in Figure 2C For example, the transistor TR may correspond to Figure 2A The sixth transistor T6 in Figure 2B The first transistor T1 or Figure 2C In addition, other transistors constituting the pixel driver PDC may have the same Figure 5 However, this is an example, and other transistors constituting the pixel driver PDC may also have a structure different from that of the connecting transistor TR, and the structure is not limited to any one embodiment.

[0189] The first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 is illustrated as a single-layer silicon oxide layer. In addition, the insulating layer to be described later may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the embodiment is not limited thereto.

[0190] In addition, the first insulating layer 10 may cover the lower conductive layer BCL. The display panel DP may further include a lower conductive layer BCL disposed overlapping the connection transistor TR. The lower conductive layer BCL may block a potential caused by a polarization phenomenon of the base layer BS, thereby protecting the connection transistor TR. In addition, the lower conductive layer BCL may block light incident from the bottom to the connection transistor TR. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layer BCL and the base layer BS.

[0191] The lower conductive layer BCL may include a reflective metal. For example, the lower conductive layer BCL may include titanium (Ti), molybdenum (Mo), an alloy including molybdenum, aluminum (Al), an alloy including aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and / or copper (Cu), etc.

[0192] In an embodiment, the lower conductive layer BCL may be connected to the source of the transistor TR (or transistor) through the source electrode pattern W1. For example, the lower conductive layer BCL may be synchronized with the source of the transistor TR to have the same potential or voltage. However, this is an example, and the lower conductive layer BCL may be connected to the gate of the transistor TR to synchronize with the gate so as to have the same potential or voltage. In another example, the lower conductive layer BCL may be connected to another electrode and may therefore receive a constant voltage or pulse signal independently. In another example, the lower conductive layer BCL may also be formed (or provided) in a form isolated from another conductive pattern. According to an embodiment, the lower conductive layer BCL may be formed (or provided) in various forms and is not limited to any one embodiment.

[0193] The connection transistor TR may be disposed on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may include an indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3However, the embodiment is not limited thereto, and the semiconductor pattern SP may also include amorphous silicon, low temperature polysilicon, or polycrystalline silicon.

[0194] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR distinguished according to the degree of conductivity. The channel region CR may be a portion overlapping the gate electrode GE on a plane (or in a plan view). The source region SR and the drain region DR may be portions spaced apart from each other, with the channel region CR therebetween. In the case where the semiconductor pattern SP is an oxide semiconductor, the source region SR and the drain region DR may each be a reduction region. Accordingly, the source region SR and the drain region DR may each have a content rate of a reduction metal that is relatively higher than the content rate of a reduction metal of the channel region CR. In another example, in the case where the semiconductor pattern SP is polycrystalline silicon, the source region SR and the drain region DR may each be a region doped with a high concentration.

[0195] The source region SR and the drain region DR may have a conductivity relatively higher than that of the channel region CR. The source region SR may correspond to a source electrode of the connection transistor TR, and the drain region DR may correspond to a drain electrode of the connection transistor TR. Figure 5 As shown in FIG. 1 , separate source electrode patterns W1 and drain electrode patterns W2 connected to the source region SR and the drain region DR, respectively, may be further provided. For example, the separate source electrode patterns W1 and drain electrode patterns W2 may each be formed in the same manner as the source electrode patterns W1 and drain electrode patterns W2. Figure 2A The pixel driver PDC in Figure 2B The pixel driver PDC-1 or Figure 2C The pixel driver PDC-2 is formed in the form of one line among the lines connected as one, and is not limited to any one embodiment.

[0196] The second insulating layer 20 may overlap with each pixel in common and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may be a single-layer silicon oxide layer.

[0197] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR. For example, the gate electrode GE may be disposed above the semiconductor pattern SP. However, this is an example, and the gate electrode GE may also be disposed below the semiconductor pattern SP, and is not limited to any one embodiment.

[0198] The gate electrode GE may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or an alloy thereof, but the embodiment is not limited thereto.

[0199] The third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0200] The first and second capacitor electrodes CPE1 and CPE2 among the conductive patterns W1, W2, CPE1, CPE2, and CPE3 may form a first capacitor C1. The first and second capacitor electrodes CPE1 and CPE2 may be spaced apart from each other with the first and second insulating layers 10 and 20 therebetween.

[0201] According to an embodiment, the first capacitor electrode CPE1 and the lower conductive layer BCL may also have an integral shape and may be formed as the same layer. In addition, the second capacitor electrode CPE2 and the gate electrode GE may also have an integral shape and may be formed as the same layer.

[0202] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2 with the third insulating layer 30 therebetween, and the third capacitor electrode CPE3 may overlap the second capacitor electrode CPE2 on a plane (or in a plan view). The third capacitor electrode CPE3 may form a second capacitor C2 with the second capacitor electrode CPE2.

[0203] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0204] The source electrode pattern W1 and the drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to the source region SR of the connection transistor TR through the first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP may serve as the source of the connection transistor TR. The drain electrode pattern W2 may be connected to the drain region DR of the connection transistor TR through the second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may serve as the drain of the connection transistor TR. The fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0205] The intermediate connection electrode CN may be disposed on the fifth insulating layer 50. The intermediate connection electrode CN may electrically connect the pixel driver PDC and the light emitting element LD. For example, the intermediate connection electrode CN may electrically connect the connection transistor TR and the light emitting element LD. The intermediate connection electrode CN may be a connection node connecting the pixel driver PDC to the light emitting element LD. For example, the intermediate connection electrode CN may correspond to Figure 2A The fourth node N4 (see Figure 2A ), corresponding to Figure 2B The second node N2 (see Figure 2B ), or corresponding to Figure 2C The fourth node N4 (see Figure 2C ).

[0206] The sixth insulating layer 60 may be disposed on the intermediate connection electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover at least a portion of the intermediate connection electrode CN. The fifth insulating layer 50 and the sixth insulating layer 60 may each be an organic layer. For example, the fifth insulating layer 50 and the sixth insulating layer 60 may each include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylate polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer and / or a mixture thereof.

[0207] A through hole OP-60 exposing at least a portion of the intermediate connection electrode CN may be formed (or provided) in the sixth insulating layer 60. The intermediate connection electrode CN may be connected to the connection electrode CNE through the portion exposed from the sixth insulating layer 60, and therefore, may be electrically connected to the light emitting element LD. For example, the intermediate connection electrode CN may electrically connect the connection transistor TR and the light emitting element LD through the connection electrode CNE. In the specification, the area at which the intermediate connection electrode CN and the connection electrode CNE are connected may be referred to as a connection area CNA. The connection area CNA may be defined by the through hole OP-60. In another example, in the display panel DP according to the embodiment, the sixth insulating layer 60 may also be omitted or provided in plurality, and is not limited to any one embodiment. In the case where the sixth insulating layer 60 is omitted, the intermediate connection electrode CN may also be omitted.

[0208] The intermediate connection electrode CN may include a first layer L1, a second layer L2, and a third layer L3 stacked in sequence along the third direction DR3. The second layer L2 may include a material different from that of the first layer L1. In addition, the second layer L2 and the third layer L3 may include different materials. The second layer L2 may have a thickness relatively greater than that of the first layer L1. In addition, the second layer L2 may have a thickness relatively greater than that of the third layer L3. The second layer L2 may include a highly conductive material. In an embodiment, the second layer L2 may include aluminum (Al).

[0209] The light emitting element layer LDL may be disposed on the driving element layer DDL. The light emitting element layer LDL may include a pixel defining layer PDL, a light emitting element LD, and a spacer SPR.

[0210] The pixel defining layer PDL may be an organic layer. For example, the pixel defining layer PDL may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylate polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer and / or a mixture thereof.

[0211] In an embodiment, the pixel defining layer PDL may have a light absorption characteristic and may have, for example, a black color. For example, the pixel defining layer PDL may include a black colorant. The black colorant may include a black pigment or a black dye. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer PDL may correspond to a light shielding pattern having a light shielding characteristic.

[0212] An opening OP-PDL (hereinafter, a light emitting opening) exposing at least a portion of the first electrode EL1 to be described later may be formed (or defined) in the pixel defining layer PDL. The light emitting opening OP-PDL may be provided in plurality and respectively arranged corresponding to the light emitting element LD. All parts of the light emitting element LD may be arranged overlapping with the light emitting opening OP-PDL, and the light emitting opening OP-PDL may be substantially an area displaying light emitted by the light emitting element LD. Accordingly, on a plane (or in a plan view), the first light emitting portion EP1 (see Figure 4A ) may substantially correspond to the shape of the light emitting opening OP-PDL. For example, a region corresponding to the first light emitting portion EP1 (eg, a region defined by the light emitting opening OP-PDL) may be referred to as a light emitting area EA.

[0213] The connection electrode CNE may be disposed on the pixel defining layer PDL. The connection electrode CNE may electrically connect the pixel driver PDC to the light emitting element LD. For example, the pixel driver PDC may be electrically connected to the light emitting element LD via the intermediate connection electrode CN and the connection electrode CNE. The connection electrode CNE may correspond to Figure 4A The first connection electrode CNE1 shown in FIG. The second connection electrode CNE2 (see Figure 4A ) and the third connection electrode CNE3 (see Figure 4A ) may also have a structure similar to that of the connecting electrode CNE.

[0214] The connection electrode CNE may include a first edge portion EG1c adjacent to the light emitting opening OP-PDL and a second edge portion EG2c surrounding the first edge portion EG1c. The second electrode EL2 of the light emitting element LD may contact the connection electrode CNE in a region adjacent to the second edge portion EG2c.

[0215] The connection electrode CNE may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) of a transparent conductive oxide (TCO). However, the material constituting the connection electrode CNE is not limited to the above examples. For example, the connection electrode CNE may also include a metal material.

[0216] A through hole OP-P spaced apart from the light emitting opening OP-PDL may be formed (or defined) in the pixel defining layer PDL (or may pass through the pixel defining layer PDL). The through hole OP-P may be provided in plurality and arranged corresponding to the light emitting element LD, respectively. The size of the through hole OP-P formed (or defined) in the pixel defining layer PDL may be larger than the size of the through hole OP-60 formed (or defined) in the sixth insulating layer 60. The connection electrode CNE may be provided in the through hole OP-P and the through hole OP-60 and connected to the intermediate connection electrode CN.

[0217] The light emitting element LD may include a first electrode EL1 , an intermediate layer IML, and a second electrode EL2 .

[0218] The first electrode EL1 may be a semi-transmissive reflective, transmissive or reflective electrode. According to an embodiment, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof, and a transparent electrode layer or a semi-transparent electrode layer formed on the reflective layer. The transparent electrode layer or the semi-transparent electrode layer may include an indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may include a stack structure of ITO / Ag / ITO.

[0219] In an embodiment, the first electrode EL1 may be an anode of the light emitting element LD. For example, the first electrode EL1 may be connected to a first power line VDL (see Figure 2A ), and a first power supply voltage VDD (see Figure 2A The first electrode EL1 may be formed in the display area DA (see Figure 3A or Figure 3B ) is connected to the first power line VDL, or in the peripheral area NDA (see Figure 3A or Figure 3B ) is connected to the first power line VDL. In the latter case, the first power line VDL may be disposed in the peripheral area NDA, and the first electrode EL1 may have a shape extending to the peripheral area NDA.

[0220] exist Figure 5 In the cross section of FIG. 1 , it is illustrated that the first electrode EL1 overlaps with the light emitting opening OP-PDL and does not overlap with the partition SPR, but as shown in FIG. Figure 4DAs described above, the first electrode EL1 of the light emitting element LD may have an integral shape, and may have a grid shape or a lattice shape defining an opening in a local area. For example, as long as the same first power supply voltage VDD is applied to the first electrode EL1 of each of the light emitting elements LD, the shape of the first electrode EL1 may be variously provided and is not limited to any one embodiment.

[0221] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include a light emitting layer EML and a functional layer FNL. The light emitting element LD may include the intermediate layer IML of various structures and is not limited to any one embodiment. For example, the functional layer FNL may be formed (or provided) as a plurality of layers, or may be formed (or provided) as at least two layers spaced apart from each other with the light emitting layer EML therebetween.

[0222] refer to Figure 5 and Figure 6 , the functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. The functional layer FNL may include a first intermediate functional layer FNLa disposed between the first electrode EL1 and the light-emitting layer EML and a second intermediate functional layer FNLb disposed between the second electrode EL2 and the light-emitting layer EML. In an embodiment, the light-emitting layer EML is illustrated as being inserted into the functional layer FNL. For example, it can be understood that the light-emitting layer EML is disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0223] The functional layer FNL may control the movement of charges between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa may include a hole injection / transport material and / or an electron blocking material. The second intermediate functional layer FNLb may include at least one of a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0224] The light emitting layer EML may include an organic light emitting material. In addition, the light emitting layer EML may include an inorganic light emitting material, or may be formed (or provided) as a mixed layer of an organic light emitting material and an inorganic light emitting material. In an embodiment, the light emitting portions EP (see FIG. 1 ) adjacent to each other are respectively included. Figure 3A ) may include luminescent materials showing different colors. For example, the luminescent layer EML included in each of the luminescent parts EP may provide light of any one color among blue, red, and green. However, the embodiment is not limited thereto, and all of the luminescent layers EML provided in each luminescent part EP may also include luminescent materials showing the same color. For example, the luminescent layer EML may provide blue light or white light.

[0225] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be connected to the connection electrode CNE to be electrically connected to the pixel driver PDC. For example, the second electrode EL2 may be electrically connected to the connection transistor TR through the connection electrode CNE.

[0226] The spacer SPR may be disposed on the pixel defining layer PDL. For example, the spacer SPR may be disposed on a gap GP between a connection electrode CNE disposed on the pixel defining layer PDL and an adjacent connection electrode CNE adjacent to the connection electrode CNE.

[0227] In an embodiment, the second electrode EL2 and the functional layer FNL may be formed by depositing in common throughout each pixel using an open mask. In addition, the second electrode EL2 and the functional layer FNL may each be separated by a separator SPR. As previously described, for each light emitting portion EP, the separator SPR may have a closed line shape, and accordingly, for each light emitting portion EP, the second electrode EL2 and the functional layer FNL may have a separated shape. For example, the second electrode EL2 and the intermediate layer IML may be electrically independent of each adjacent pixel.

[0228] In an embodiment, the spacer SPR may have an inverted tapered shape. For example, the spacer SPR may have a shape whose width increases as it moves away from the upper surface of the pixel defining layer PDL. The side surface TP of the spacer SPR may have a shape inclined from the upper surface of the pixel defining layer PDL at a blunt cone angle. However, this is an example, and as long as the spacer SPR electrically disconnects the second electrode EL2 for each pixel, the cone angle of the spacer SPR can be variously set, and for example, the spacer SPR may have a dual structure with different cone angles. For example, the spacer SPR may have a structure such as a tip portion, and is not limited to any one embodiment.

[0229] like Figure 5 and Figure 6 As shown in , the spacer SPR may be a double inverted cone shape. The side surface TP of the spacer SPR may include a first side surface TP1 (or an upper spacer portion) and a second side surface TP2 (or a lower spacer portion) with different taper angles. Relative to the upper surface of the pixel defining layer PDL, the taper angle formed by the first side surface TP1 of the spacer SPR and the taper angle formed by the second side surface TP2 may be different from each other. The taper angles may each be an obtuse angle. For example, as Figure 6As in the embodiment, the cone angle formed by the first side surface TP1 relative to the upper surface of the pixel defining layer PDL may be smaller than the cone angle formed by the second side surface TP2 relative to the upper surface of the pixel defining layer PDL. However, this is an example, and as long as the spacer SPR electrically disconnects the second electrode EL2 for each pixel, the cone angle may be variously set. For example, the spacer SPR may also have a structure such as a tip portion, and is not limited to any one embodiment.

[0230] The spacer SPR may include an insulating material such as an organic insulating material. According to an embodiment, the spacer SPR may also include an inorganic insulating material, may include a plurality of layers consisting of an organic insulating material and an inorganic insulating material, or may include a conductive material. For example, as long as the spacer SPR electrically disconnects the second electrode EL2 for each pixel, the type of material is not limited.

[0231] The dummy layer UP may be disposed above the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 and the intermediate layer IML may be formed by the same process and may include the same material. The first dummy layer UP1 may include a 1-1 dummy layer UP1a and a 1-2 dummy layer UP1b. The 1-1 dummy layer UP1a and the first intermediate functional layer FNLa may be formed by the same process and may include the same material. The 1-2 dummy layer UP1b and the second intermediate functional layer FNLb may be formed by the same process and may include the same material. The second dummy layer UP2 and the second electrode EL2 may be formed by the same process and may include the same material. For example, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously in the process of forming the functional layer FNL and the second electrode EL2, respectively. Figure 6 As shown in , the dummy layer UP may be formed not only on the upper surface of the separator SPR, but also on a portion of the side surface TP. In another embodiment, the display panel DP may not include the dummy layer UP. The dummy layer UP may not contact the connection electrode CNE or the second electrode EL2. The second dummy layer UP2 included in the dummy layer UP may not contact the connection electrode CNE or the second electrode EL2.

[0232] The second electrode EL2 may be in contact with the connection electrode CNE through the contact area CA. The contact area CA may be formed (or provided) adjacent to the spacer SPR. In the contact area CA, the upper surface CNE-us of the connection electrode CNE may be in contact with the lower surface EL2-bs of the second electrode EL2. In addition, since the spacer SPR has an inverted tapered shape and the contact area CA is provided adjacent to the spacer SPR, at least a portion of the contact area CA where the second electrode EL2 and the connection electrode CNE are in contact with each other may be disposed below the side surface TP of the spacer SPR.

[0233] In an embodiment, at least a portion of the connection electrode CNE may be disposed under the spacer SPR. The spacer SPR may be disposed on the gap GP between the connection electrode CNE and an adjacent connection electrode adjacent to the connection electrode CNE, and the second edge portion EG2c of the connection electrode CNE may be covered by the spacer SPR.

[0234] The display panel DP according to the embodiment may include an intermediate area MA disposed between the light emitting area EA where the light emitting element LD is disposed and the contact area CA. The intermediate area MA may be an area where at least a portion of the intermediate layer IML is disposed. In the intermediate area MA, the functional layer FNL included in the intermediate layer IML may be disposed between the connection electrode CNE and the second electrode EL2. For example, in the intermediate area MA, the connection electrode CNE and the second electrode EL2 may be spaced apart from each other with the functional layer FNL therebetween.

[0235] The middle area MA may be adjacent to the contact area CA. The functional layer FNL disposed in the middle area MA may include the aforementioned first middle functional layer FNLa and second middle functional layer FNLb. The first middle functional layer FNLa may be disposed between the first electrode EL1 and the light emitting layer EML in the light emitting area EA, and the second middle functional layer FNLb may be disposed between the second electrode EL2 and the light emitting layer EML in the light emitting area EA.

[0236] In the display panel DP according to the embodiment, the functional layer FNL and the second electrode EL2 may be formed by different deposition processes. The second electrode EL2 may be formed by a deposition process capable of depositing a deposition material at an incident angle lower than the incident angle of the deposition process in which the functional layer FNL is formed. The functional layer FNL may be formed by, for example, a thermal evaporation process, and the second electrode EL2 may be formed by a sputtering process to cover the functional layer FNL. Accordingly, in the process of forming the functional layer FNL, the material forming the functional layer FNL may not enter the lower portion of the side surface TP of the partition SPR (or may not be disposed below the lower portion of the side surface TP of the partition SPR), thereby exposing a portion of the connection electrode CNE, and the second electrode EL2 may be formed adjacent to the partition SPR compared to the functional layer FNL, so that the second electrode EL2 may contact the exposed upper surface CNE-us of the connection electrode CNE. For example, in the process of forming the functional layer FNL and the second electrode EL2, by the difference in the deposition process, a contact area CA at which the second electrode EL2 and the connection electrode CNE contact each other may be formed.

[0237] For example, Figure 5 As shown in , the connection area CNA at which the connection electrode CNE is connected to the intermediate connection electrode CN may be provided between the emission area EA and the contact area CA. The connection area CNA may overlap with the intermediate area MA. At least a portion of the intermediate layer IML may overlap with the connection area CNA. In the display panel DP according to the embodiment, the functional layer FNL included in the intermediate layer IML may overlap with the connection area CNA.

[0238] According to an embodiment, the connection electrode CNE may have a shape that surrounds at least a portion of the light emitting area EA at which the light emitting element LD is disposed. Therefore, the degree of freedom of the position at which the connection electrode CNE and the light emitting element LD are connected and the degree of freedom of the position at which the connection electrode CNE and the pixel driver PDC are connected can be improved. For example, through the contact area CA at which the partition SPR is adjacently defined, the upper surface CNE-us of the connection electrode CNE can be in contact with the lower surface EL2-bs of the second electrode EL2. Accordingly, the contact reliability between the connection electrode CNE and the second electrode EL2 can be improved, and since the lower surface of the connection electrode CNE and the upper surface of the intermediate connection electrode CN are in contact with each other, the contact reliability can be improved. In the display panel DP according to the embodiment, by the described structure, the size of the through holes OP-P and OP-60 for connecting the connection electrode CNE and the intermediate connection electrode CN can be reduced or minimized, and accordingly, the area or resolution of the light emitting portion EP of the display panel DP can be increased.

[0239] Reference again Figure 5, the encapsulation layer ECL may be disposed on the light emitting element layer LDL. The encapsulation layer ECL may cover the light emitting element LD and may cover the spacer SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked in sequence. However, the embodiment is not limited thereto, and the encapsulation layer ECL may further include an inorganic layer and an organic layer. In addition, the encapsulation layer ECL may be a glass substrate.

[0240] The first inorganic layer IL1 and the second inorganic layer IL2 may protect the light emitting element LD from moisture and oxygen outside the display panel DP, and the organic layer OL may protect the light emitting element LD from foreign matter such as particles remaining from the process of forming the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The organic layer OL may include an acrylic organic layer, and the type of material is not limited to any one embodiment.

[0241] The sensing layer ISL may sense external input. In an embodiment, the sensing layer ISL may be formed on the encapsulation layer ECL by a continuous process. For example, the sensing layer ISL may be described as being directly disposed on the encapsulation layer ECL. "Directly disposed" may mean that no intermediate component is disposed between the sensing layer ISL and the encapsulation layer ECL. For example, no separate adhesive member may be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is an example, and in the display panel DP according to the embodiment, the sensing layer ISL may also be formed separately and then bonded to the display panel DP by an adhesive member, and is not limited to any one embodiment.

[0242] The sensing layer ISL may include a conductive layer and an insulating layer. The conductive layer may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the insulating layer may include first to third sensing insulating layers 71, 72, and 73. However, this is an example, and the number of conductive layers and the number of insulating layers are not limited to any one embodiment.

[0243] The first to third sensing insulating layers 71, 72 and 73 may each have a single layer structure, or may each have a structure of multiple layers stacked along the third direction DR3. The first to third sensing insulating layers 71, 72 and 73 may each include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and hafnium oxide. The first to third sensing insulating layers 71, 72 and 73 may each include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin and perylene resin.

[0244] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may each have a single-layer structure, or may each have a structure of a plurality of layers stacked along the third direction DR3.

[0245] The single-layer sensing conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). For example, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, etc.

[0246] The multi-layer sensing conductive layer may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium (Ti) / aluminum (Al) / titanium (Ti). In another example, the multi-layer sensing conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0247] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may form a sensor for sensing external input in the sensing layer ISL. The sensor may operate in a capacitive manner, and may operate in a mutual capacitance manner or a self-capacitive manner. However, this is an example, and in addition to the capacitive manner, the sensor may also operate in a resistive manner, an ultrasonic manner, or an infrared manner, and the manner is not limited to any one embodiment.

[0248] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may each include a transparent conductive oxide, and may also have a metal mesh shape formed of an opaque conductive material. As long as the visibility of an image displayed by the display panel DP is not reduced, the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and shapes, and are not limited to any one embodiment.

[0249] 7A to 7D is an enlarged schematic cross-sectional view illustrating a partial area of ​​the display panel DP according to the embodiment. Fig. 7E is to capture an image of a partial area of ​​the display panel DP according to the embodiment. 7A to 7D The diagram shows Figure 5 The area AA' (such as Figure 6 ) and illustrates an enlarged schematic cross-sectional view of a region corresponding to the Figure 6 The shapes of the spacers SPR or SPR-1 and the portions corresponding to the contact areas CA of the different embodiments are shown in FIG. Figure 5 and Figure 6 The components described above are denoted by the same reference numerals or symbols, and their detailed description is omitted for convenience of description.

[0250] refer to Fig. 7A ,and Figure 6 Unlike the illustration in FIG. 1 , the separator SPR-1 may also have a single inverted cone shape instead of a double inverted cone shape. For example, the side surface TP' of the separator SPR-1 may include a surface having a consistent cone angle. The side surface TP' of the separator SPR-1 may not include an inflection point at which the cone angle changes sharply, but may include a gradually curved surface.

[0251] In the embodiment to be described later, Figure 6 The spacer SPR having a double inverted tapered shape is illustrated in FIG. 1 , but the embodiment is not limited thereto, and in a display panel according to an embodiment to be described later, a spacer SPR having a double inverted tapered shape may also be applied. Fig. 7A The separator SPR-1 having a single inverted tapered shape is shown in FIG.

[0252] refer to Figure 7B , in addition to the portion provided in the contact area CA, the connection electrode CNE may further include a portion provided on the side surface TP of the separator SPR. The connection electrode CNE may include a first connection portion CNE-1 provided in the contact area CA and a second connection portion CNE-2 provided on the side surface TP of the separator SPR. The second connection portion CNE-2 may be provided on a portion of a lower portion of the side surface TP of the separator SPR. The second connection portion CNE-2 may be in contact with the side surface TP of the separator SPR. The second connection portion CNE-2 may be in contact with the second side surface TP2 of the side surface TP of the separator SPR, and may be in contact with a portion of the first side surface TP1.

[0253] The second electrode EL2 may include a portion in contact with the connection electrode CNE in the contact area CA and a portion in contact with a portion of the connection electrode CNE disposed on the side surface TP of the separator SPR. The second electrode EL2 may include a second-first electrode portion EL2-1 (or first electrode portion) disposed above the first connection portion CNE-1, a second-second electrode portion EL2-2 (or second electrode portion) in contact with the side surface CNE-2s of the second connection portion CNE-2, and a second-third electrode portion EL2-3 disposed in the middle area MA. The lower surface EL2-bs of the second-first electrode portion EL2-1 may be in contact with the upper surface CNE-us of the first connection portion CNE-1. The side surface EL2-2s of the second-second electrode portion EL2-2 may be in contact with the side surface CNE-2s of the second connection portion CNE-2. For example, the second connection portion CNE-2 may be disposed between the separator SPR and the second-second electrode portion EL2-2 in a horizontal direction parallel to the upper surface of the pixel defining layer PDL. For example, the second-first electrode portion EL2-1, the second-second electrode portion EL2-2, and the second-third electrode portion EL2-3 may define a recessed portion EL2-Re filled with the first inorganic layer IL1. For example, the second connection portion CNE-2 and the second-second electrode portion EL2-2 may be disposed between the separator SPR and the recessed portion EL2-Re in the horizontal direction.

[0254] and Figure 6 Different from the illustration, Figure 7B A portion of the connection electrode CNE illustrated in FIG. 1 may not be disposed under the partition SPR. The connection electrode CNE may not be disposed under the partition SPR, but may have a structure in which a portion is in contact with the side surface TP of the partition SPR. According to an embodiment, in the display panel DP, as shown in FIG. Figure 5 and Figure 6 As shown in , the spacer SPR may be formed after the connection electrode CNE is formed, so that a portion of the connection electrode CNE may be disposed under the spacer SPR. Figure 7B In the embodiment illustrated in FIG. 1 , a separator SPR may be formed, and then a connection electrode CNE may be formed by the following process, so that a portion of the connection electrode CNE may not be disposed under the separator SPR, but may have a shape disposed along the side surface TP. Accordingly, in addition to the contact area CA, the connection electrode CNE and the second electrode EL2 may also contact each other on the side surface TP of the separator SPR, thereby increasing the contact area of ​​the connection electrode CNE and the second electrode EL2. For example, since the area of ​​the connection contact is increased, the connection may be stably performed.

[0255] refer to Figure 7C, the connection electrode CNE may include a first connection portion CNE-1 disposed in the contact area CA and a second connection portion CNE-2 disposed on the side surface TP of the separator SPR. The second connection portion CNE-2 may be disposed on a portion of a lower portion of the side surface TP of the separator SPR. The second connection portion CNE-2 may be in contact with the side surface TP of the separator SPR.

[0256] The second electrode EL2 may include a second-first electrode portion EL2 - 1 disposed over the first connection portion CNE- 1 and a second-second electrode portion EL2 - 2 contacting a side surface of the second connection portion CNE- 2 .

[0257] In addition, at least a portion of the second connection portion CNE-2 may not be in contact with the second electrode EL2 (or may not be covered by the second electrode EL2). Figure 7C As shown in , the height of the second connection portion CNE-2 may be greater than the height of the second-second electrode portion EL2-2, and a portion of the side surface of the second connection portion CNE-2 may not be covered by the second-second electrode portion EL2-2 and may be exposed. The second connection portion CNE-2 may include a first side surface CNE-2sa in contact with the side surface EL2-2s of the second-second electrode portion EL2-2 and a second side surface CNE-2sb that is exposed and not in contact with the second-second electrode portion EL2-2 (or may not be covered by the second-second electrode portion EL2-2).

[0258] refer to Fig.7D and Fig. 7E , a portion of the connection electrode CNE may also be disposed above the separator SPR. The connection electrode CNE may further include a third connection portion CNE-3 disposed on a portion of the upper surface SPR-U of the separator SPR. In an embodiment, the second connection portion CNE-2 of the connection electrode CNE may cover the entire side surface TP of the separator SPR and may be connected to the third connection portion CNE-3 disposed on the portion of the upper surface SPR-U of the separator SPR.

[0259] In addition, at least a portion of the second connection portion CNE-2 may not be in contact with the second electrode EL2. Fig.7D As shown in FIG, unlike the second connection portion CNE-2 corresponding to the entire side surface TP of the separator SPR, the second-second electrode portion EL2-2 may be provided to correspond to only a portion of the side surface TP of the separator SPR. A portion of the side surface of the second connection portion CNE-2 may not be covered by the second-second electrode portion EL2-2 but may be exposed.

[0260] The third connection portion CNE-3 disposed on the upper surface SPR-U of the spacer SPR may not contact the second dummy layer UP2. In the display panel DP according to the embodiment, even if a portion of the connection electrode CNE is disposed on the upper surface SPR-U of the spacer SPR, the portion may not contact the second dummy layer UP2, and therefore, it may be possible to prevent a lateral leakage current that occurs when the connection electrode CNE contacts the second dummy layer UP2.

[0261] Fig. 8A and Figure 8B are schematic cross-sectional views each illustrating an enlargement of a partial area of ​​the display panel DP according to the embodiment. For example, Fig. 8A and Figure 8B are their respective icons and Figure 5 FIG. 2 is an enlarged schematic cross-sectional view of a region corresponding to region AA′.

[0262] refer to Figure 5 and Fig. 8A , the display panel DP may further include a lower encapsulation layer IL-ad. The lower encapsulation layer IL-ad may be disposed between the pixel defining layer PDL and the spacer SPR. In an embodiment in which the lower encapsulation layer IL-ad is applied, a portion of the connection electrode CNE may be disposed on the lower encapsulation layer IL-ad. The lower encapsulation layer IL-ad may be an inorganic layer.

[0263] Even if a gap is formed in the first inorganic layer IL1 at a portion adjacent to the side surface TP of the spacer SPR, the gap can be shielded by the lower encapsulation layer IL-ad. Accordingly, even if the gap serves as a degassing path or a vapor path of the organic layer OL, gas and moisture, etc. can be shielded by the lower encapsulation layer IL-ad. Accordingly, the function of protecting the light emitting element LD can be improved, and as a result, the reliability of the display panel DP can be improved.

[0264] refer to Figure 5 and Figure 8B , the first encapsulation layer IL1a can be used instead of Figure 5 The first inorganic layer IL1 is shown in FIG. The first encapsulation layer IL1a may include sub-encapsulation layers ILs1, ILs2, and ILs3. Therefore, the first encapsulation layer IL1a may relatively gradually cover the partition SPR. Therefore, a gap formed at a portion adjacent to the side surface TP of the partition SPR may be removed from the upper surface of the first encapsulation layer IL1a. Accordingly, the function of the encapsulation layer for protecting the light emitting element LD may be improved.

[0265] According to an embodiment, the first encapsulation layer IL1a may include a first sub-encapsulation layer ILs1, a second sub-encapsulation layer ILs2, and a third sub-encapsulation layer ILs3. The first sub-encapsulation layer ILs1 may cover the partition SPR. The second sub-encapsulation layer ILs2 may be disposed on the first sub-encapsulation layer ILs1. The third sub-encapsulation layer ILs3 may be disposed on the second sub-encapsulation layer ILs2. However, this is an example, and some of the sub-encapsulation layers constituting the first encapsulation layer IL1a may be omitted, or more sub-encapsulation layers may also be included.

[0266] According to an embodiment, at least some of the first to third sub-encapsulation layers ILs1, ILs2, and ILs3 may include an organic material. In addition, the first sub-encapsulation layer ILs1 and the third sub-encapsulation layer ILs3 may include an inorganic material, and the second sub-encapsulation layer ILs2 may include an organic material. Even if a gap is formed in the first sub-encapsulation layer ILs1 at a portion adjacent to the side surface TP of the separator SPR, the gap may be filled by the second sub-encapsulation layer ILs2. In addition, the first sub-encapsulation layer ILs1 and the third sub-encapsulation layer ILs3 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The second sub-encapsulation layer ILs2 may include silicon oxycarbide (SiOC x ). However, the embodiment is not limited thereto.

[0267] According to the foregoing, the light emitting element LD and the pixel driver PDC can stably contact each other, so that the contact reliability can be improved. In the display panel DP according to the embodiment, the cathode of the light emitting element LD and the connection electrode CNE electrically connected to the pixel driver PDC can contact each other in an area adjacent to the partition SPR provided to separate the pixels, and thus can be connected to each other in a relatively large area, so that the contact reliability can be improved. In addition, since the connection area CNA where the lower surface of the connection electrode CNE contacts the upper surface of the intermediate connection electrode CN is provided between the contact area CA and the light emitting area EA, and the area where the connection electrode CNE and the cathode are connected and the area where the connection electrode CNE and the intermediate connection electrode CN are connected are provided separately, the size of the through holes OP-P and OP-60 for connecting the connection electrode CNE and the intermediate connection electrode CN can be reduced or minimized. Accordingly, it may be possible to increase the area and resolution of the light emitting portion EP of the display panel DP.

[0268] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display panel, comprising: A driving element layer, including a pixel driver; A light emitting element is disposed on the driving element layer, wherein the light emitting element includes a first electrode, an intermediate layer disposed on the first electrode and including at least a light emitting layer, and a second electrode disposed on the intermediate layer; a pixel defining layer, disposed on the driving element layer and comprising an opening exposing at least a portion of the first electrode; a connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driver and the second electrode; as well as a spacer, disposed on the pixel defining layer, Wherein, in a contact region adjacent to the separator, a lower surface of the second electrode contacts an upper surface of the connecting electrode.

2. The display panel according to claim 1, wherein: The intermediate layer further comprises a functional layer, The functional layer comprises: A first intermediate functional layer is disposed on the first electrode; and A second intermediate functional layer is disposed on the light-emitting layer, and The light emitting layer is disposed between the first intermediate functional layer and the second intermediate functional layer.

3. The display panel according to claim 2, further comprising: A first dummy layer is disposed on the separator; as well as A second dummy layer is provided on the first dummy layer, wherein: The first dummy layer and the functional layer include the same material, and The second dummy layer and the second electrode include the same material.

4. The display panel according to claim 3, wherein: The connecting electrode does not contact the second dummy layer.

5. The display panel according to claim 1, wherein: The connection electrode has a ring shape surrounding the opening of the pixel defining layer.

6. The display panel according to claim 1, wherein: The contact region surrounds at least a portion of the opening of the pixel defining layer.

7. The display panel according to claim 1, wherein: The connection electrode includes a first edge portion and a second edge portion surrounding the first edge portion, and The second edge portion overlaps the partition in a plane.

8. The display panel according to claim 1, wherein: The spacer includes a first side surface and a second side surface having different taper angles with respect to an upper surface of the pixel defining layer.

9. The display panel according to claim 1, wherein: A portion of the connection electrode is covered by the separator.

10. The display panel according to claim 1, wherein: The connecting electrode comprises: A first connecting portion, disposed in the contact region; and The second connection portion is arranged on the side surface of the partition.

11. The display panel according to claim 10, wherein: The second electrode comprises: a first electrode portion disposed on the first connection portion to contact an upper surface of the first connection portion; and The second electrode portion is provided on a side surface of the second connection portion to contact the side surface of the second connection portion.

12. The display panel according to claim 10, wherein: The connection electrode further includes a third connection portion disposed on an upper surface of the separator.

13. The display panel according to claim 10, wherein: At least a portion of the second connection portion is not in contact with the second electrode.

14. The display panel according to claim 1, wherein: The through hole passes through the pixel defining layer, and The connection electrode is connected to the pixel driver through the through hole.

15. The display panel according to claim 14, wherein: The intermediate layer overlaps the through hole.

16. The display panel according to any one of claims 1 to 15, wherein: In an intermediate region provided between the contact region and the light emitting element, the intermediate layer is provided between the connection electrode and the second electrode.

17. A display panel, comprising: A driving element layer, including a pixel driver; A light emitting element is disposed on the driving element layer, wherein the light emitting element includes a first electrode, an intermediate layer disposed on the first electrode and including at least a light emitting layer, and a second electrode disposed on the intermediate layer; a pixel defining layer, disposed on the driving element layer and comprising an opening exposing at least a portion of the first electrode; as well as A connecting electrode is disposed on the pixel defining layer and is electrically connected to the pixel driver and the second electrode, wherein: The lower surface of the second electrode contacts the upper surface of the connection electrode in a contact region separated from the light emitting region where the light emitting element is provided, and A connection region at which the connection electrode and the pixel driver are connected is provided between the contact region and the light emitting region.

18. The display panel according to claim 17, wherein: The opening overlaps with the light emitting area, The pixel defining layer further comprises: a through hole spaced apart from the opening and overlapping the connection area, and The connection electrode is connected to the pixel driver through the through hole.

19. The display panel according to claim 17 or 18, further comprising: A spacer is disposed on the pixel defining layer and adjacent to the contact area.

20. The display panel according to claim 19, wherein: The connecting electrode comprises: A first connecting portion, disposed in the contact region; and The second connection portion is arranged on the side surface of the partition.

21. The display panel according to claim 20, wherein: The second electrode comprises: a first electrode portion disposed on the first connection portion to contact an upper surface of the first connection portion; and The second electrode portion is provided on a side surface of the second connection portion to contact the side surface of the second connection portion.

22. The display panel according to claim 20, wherein: The connection electrode further includes a third connection portion disposed on an upper surface of the separator.

23. The display panel according to claim 20, wherein: At least a portion of the second connection portion is not in contact with the second electrode.

24. The display panel according to claim 19, wherein: The intermediate layer further comprises a functional layer, and The display panel further comprises: A first dummy layer is disposed on the separator; and A second dummy layer is provided on the first dummy layer, wherein: The first dummy layer and the functional layer include the same material, and The second dummy layer and the second electrode include the same material.

25. The display panel according to claim 24, wherein: The connecting electrode does not contact the second dummy layer.

26. A display panel comprising: A driving element layer, including a plurality of pixel drivers; A plurality of light emitting elements are disposed on the driving element layer and are electrically connected to the plurality of pixel drivers respectively; A plurality of connection electrodes, connected to the plurality of pixel drivers and the plurality of light emitting elements respectively; as well as a separator, disposed between the plurality of light emitting elements, Wherein, each of the plurality of light emitting elements comprises: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer, and A lower surface of the second electrode of each of the plurality of light emitting elements contacts an upper surface of a corresponding connection electrode among the plurality of connection electrodes in a contact region adjacent to the partition.

27. The display panel according to claim 26, further comprising: a pixel defining layer disposed on the driving element layer and comprising an opening exposing at least a portion of the first electrode of each of the plurality of light emitting elements, wherein: A portion of each of the plurality of connection electrodes is disposed on the pixel defining layer, and The spacer is disposed on the pixel defining layer.

28. The display panel according to claim 27, wherein: The plurality of light emitting elements include: a first light emitting element; a second light emitting element spaced apart from the first light emitting element in a first direction; and a third light emitting element spaced apart from the first light emitting element and the second light emitting element in a second direction intersecting the first direction, The opening comprises: a first opening exposing at least a portion of the first electrode of the first light emitting element; a second opening exposing at least a portion of the first electrode of the second light emitting element; and a third opening exposing at least a portion of the first electrode of the third light emitting element, and The plurality of connecting electrodes include: a first connecting electrode surrounding the first opening; a second connecting electrode surrounding the second opening; and The third connecting electrode surrounds the third opening.

29. The display panel according to claim 28, wherein: The plurality of pixel drivers include: a first pixel driver electrically connected to the first light emitting element; a second pixel driver electrically connected to the second light emitting element; and a third pixel driver, electrically connected to the third light emitting element, The first through hole, the second through hole and the third through hole pass through the pixel defining layer, The first connection electrode is connected to the first pixel driver through the first through hole, the second connection electrode is connected to the second pixel driver through the second through hole, and the third connection electrode is connected to the third pixel driver through the third through hole.

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