Probe testing device, probe testing system and probe card

Abstract

The invention relates to a probe testing device, a probe testing system and a probe card. A probe testing apparatus includes a wafer stage, a temperature sensor, a temperature adjusting mechanism, and a controller. The wafer stage includes a wafer mounting surface on which the semiconductor wafer is mounted. The temperature sensor includes a temperature observation point exposed on the wafer mounting surface, and directly measures a temperature of a rear surface of a semiconductor wafer mounted on the wafer mounting surface. The temperature adjusting mechanism adjusts the temperature of the wafer stage by heating or cooling the wafer stage. The controller controls the temperature adjusting mechanism in such a manner that the temperature measured by the temperature sensor becomes a target temperature.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure (including the specification, drawings, and abstract) of Japanese Patent Application No. 2023-199554 filed on November 27, 2023 is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a probe test device, a probe test system, and a probe card, and relates to, for example, a temperature measurement technique during probe testing. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Non-Patent Document 1] Japanese Unexamined Patent Application Publication No. 2003-142537

[0006] Patent Document 1 discloses a semiconductor test probe device that can apply equal pressure to all probes when probing electrode pads over a large area. Specifically, on the stage of the probe device, spacers having the same thickness as the wafer are installed around the wafer mounting area. As a result, the probe structure is pressed while facing both the wafer and the spacers, thereby preventing the probe structure from tilting with respect to the surface of the wafer. Summary of the Invention

[0007] In recent years, as semiconductor devices such as system-on-chips (SoCs) (in other words, semiconductor chips) have become larger and more highly integrated, the number of signals, power supplies, and other terminals of each semiconductor chip may be several thousand or more. Therefore, when performing a probe test on a semiconductor chip as a device under test, the number of probes connected to these terminals is also large. As a result, when determining the test temperature of the device under test during a probe test, it may be difficult to set the actual temperature of the device under test to the target temperature with high precision.

[0008] Specifically, to determine the test temperature of the device under test, a probe test device controls the temperature of a wafer stage on which a semiconductor wafer including the device under test is mounted, based on, for example, a temperature sensor incorporated in the wafer stage. However, if the device under test is set to a high temperature through the wafer stage, for example, when a large number of probes come into contact with the device under test, heat dissipation through the probes may occur in the device under test.

[0009] Meanwhile, due to the increased power consumption associated with larger sizes and higher integration levels, the device under test may heat up during probe testing. Here, the wafer stage typically has a higher thermal resistance than the device under test. Therefore, temperature variations in the device under test caused by the above-mentioned heat dissipation and heat generation are hardly conducted to the wafer stage. As a result, there may be a deviation between the set temperature of the wafer stage and the actual temperature of the device under test.

[0010] Other problems and novel features will become clear from the description of this specification and the drawings.

[0011] A probe testing apparatus according to an embodiment includes a wafer stage, a temperature sensor, a temperature adjusting mechanism, and a controller. The wafer stage includes a wafer mounting surface on which a semiconductor wafer is mounted. The temperature sensor includes a temperature observation point exposed on the wafer mounting surface and directly measures the temperature of the back surface of the semiconductor wafer mounted on the wafer mounting surface. The temperature adjusting mechanism adjusts the temperature of the wafer stage by heating or cooling the wafer stage. The controller controls the temperature adjusting mechanism in such a way that the temperature measured by the temperature sensor becomes a target temperature.

[0012] By using the probe testing apparatus according to the embodiment, the actual temperature of the device under test can be set with high precision. Description of the Drawings

[0013] Figure 1A is a schematic diagram illustrating a premise configuration example and a problem example in a probe testing system according to a first embodiment;

[0014] Figure 1B is a schematic diagram illustrating Figure 1A an arrangement configuration example of a temperature sensor embedded in a table surface layer in;

[0015] Figure 2A is a schematic diagram illustrating a configuration example of a main part of a probe testing system according to a first embodiment;

[0016] Figure 2B is a schematic diagram illustrating Figure 2A an arrangement configuration example of probes and a temperature sensor in;

[0017] Figure 3 is a schematic diagram illustrating Figure 2A a block diagram of a configuration example of a controller in a probe tester in;

[0018] Figure 4A is a schematic diagram illustrating a configuration example of a main part of a probe testing system according to a second embodiment;

[0019] Figure 4B is a schematic diagram illustrating Figure 4A an arrangement configuration example of a probe card and a temperature sensor in;

[0020] Figure 5 is a schematic diagram of an example of a method for predicting the actual temperature of a device under test in Figure 4A and Figure 4B the actual temperature of the device under test in

[0021] Figure 6 is a block diagram showing an example of the configuration of a controller in a prober in Figure 4A the prober in

[0022] Figure 7A is a schematic diagram showing an example of the configuration of the main part of a prober test system according to the third embodiment;

[0023] Figure 7B is a schematic diagram showing an example of the configuration of a temperature adjustment mechanism in Figure 7A the temperature adjustment mechanism in

[0024] Figure 8 is a schematic diagram showing an example of a method for flattening the temperature of an entire semiconductor wafer in Figure 7A and Figure 7B the entire semiconductor wafer in

[0025] Figure 9 is a schematic diagram showing an example of the result of flattening the temperature of an entire semiconductor wafer using the method shown in Figure 8 the method shown in

[0026] Figure 10 is a block diagram showing an example of the configuration of a controller in a prober in Figure 7A the prober in

[0027] Figure 11 is a flowchart showing an example of the processing details of the controller shown in Figure 10 the controller shown in

[0028] Figure 12 is a schematic diagram showing an example of the processing details of a temperature calculation unit in Figure 10 the temperature calculation unit in

[0029] Figure 13 is a block diagram showing an example of the modified configuration of the controller in a prober test system according to the fourth embodiment in Figure 10 the controller shown in

[0030] Figure 14A is a flowchart showing an example of the processing details of the controller shown in Figure 13 the controller shown in

[0031] Figure 14B is a flowchart showing an example of the processing details of the controller shown in Figure 13 the controller shown in

[0032] Figure 15Ais a schematic diagram showing a configuration example of a main part of a probe test system according to a fifth embodiment;

[0033] Figure 15B is a diagram showing Figure 15A a schematic diagram of an arrangement configuration example of a temperature sensor in;

[0034] Figure 16 is a diagram showing Figure 15A a block diagram of a configuration example of a controller in a probe station in;

[0035] Figure 17 is a schematic diagram showing examples of a premise problem and countermeasures against the problem in a probe test system according to a sixth embodiment;

[0036] Figure 18 is a block diagram of a configuration example of a temperature controller included in a controller in a probe station in a probe test system according to a sixth embodiment;

[0037] Figure 19 is a flowchart of an example of processing details of a controller in a probe station in a probe test system according to a sixth embodiment; and

[0038] Figure 20 is for explaining Figure 19 a supplementary diagram of a part of the processing details shown. Detailed Description of the Invention

[0039] In the following embodiments, when necessary for convenience, the embodiments will be described by dividing them into multiple parts or embodiments. However, unless otherwise specified, the embodiments are not unrelated to each other, and one embodiment is partially or wholly related to other embodiments as modifications, details, additional explanations, etc. Further, in the following embodiments, when referring to the number of elements, etc. (including the number of pieces, numerical values, quantities, ranges, etc.), unless otherwise specified or clearly limited to a specific number in principle, the number is not limited to a specific number, and the number may be equal to or greater than the specific number, or may be equal to or less than the specific number.

[0040] In addition, in the following embodiments, needless to say, constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of constituent elements, etc., those that are substantially approximate or similar to the shape, etc. are assumed to be included unless otherwise specified or unless it is clearly not the case in principle. This also applies to the above numerical values and ranges.

[0041] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted. In addition, in the following embodiments, unless otherwise particularly required, the description of the same or similar components will generally not be repeated.

[0042] (First Embodiment)

[0043] (Configuration and Problems (Premise) of Probe Test System)

[0044] Figure 1A is a schematic diagram showing an example of the premise configuration and problem example in the probe test system according to the first embodiment. Figure 1B is a schematic diagram showing Figure 1A an example of the arrangement configuration of the temperature sensor 205 embedded in the table surface layer 201. Figure 1A The probe test system shown includes a tester 1, a prober (probe test device) 2, and a probe card 3.

[0045] The tester 1 includes a tester main body 10 and a test head 11. The test head 11 includes a driver that outputs signals to the outside, a receiver that receives signals from the outside, a power supply unit that supplies a power supply voltage or power supply current to the outside and can measure the power supply current or power supply voltage, etc. The tester main body 10 controls the output signals from the driver, the power from the power supply unit, etc. based on a predetermined test program, etc., and evaluates the input signals of the receiver, the measured values in the power supply unit, etc.

[0046] The prober 2 includes a wafer stage 20 called a wafer chuck, etc., a controller 21, and a stage drive mechanism 22. The wafer stage 20 mounts and adsorbs a semiconductor wafer WF on its wafer mounting surface. On the semiconductor wafer WF, a plurality of semiconductor chips CP (which are also devices under test DUTs) are formed. The wafer stage 20 includes, for example, an insulating layer 204, a heater layer 203, a cooling layer 202, and a table surface layer 201, which are sequentially stacked toward the wafer mounting surface.

[0047] A plurality of temperature sensors 205 are embedded in the table surface layer 201. For example, as Figure 1B shown, the temperature sensors 205 are arranged in a substantially uniformly dispersed manner in the area of the table surface layer 201. The heater layer 203 heats the wafer stage 20, specifically, the table surface layer 201. On the other hand, the cooling layer 202 cools the wafer stage 20, specifically, the table surface layer 201.

[0048] As a result, the semiconductor wafer WF is heated and cooled through the table surface layer 201, and the test temperature of the device under test DUT is adjusted. In this specification, the heater layer 203 and the cooling layer 202 that adjust the temperature of the wafer stage 20 (ultimately referring to the device under test DUT) by heating or cooling the wafer stage 20 in this way are collectively referred to as the temperature adjustment mechanism (202, 203).

[0049] The controller 21 includes, for example, a processor, a memory, etc., and controls the entire prober 2 based on a control program stored in the memory. As one of the controls, the controller 21 controls the temperature adjustment mechanism (202, 203) in such a way that the temperature measured by the temperature sensor 205 becomes the target temperature. Note that the controller 21 can be implemented not only by software processing by the processor, but also by hardware processing by, for example, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc., or by a combination of software processing and hardware processing.

[0050] The probe card 3 is connected to the test head 11 via the test interface 12. The probe card 3 is configured to be detachable from each of the test head 11 and the prober 2. The probe card 3 includes a main board 30, a conversion board 31, a reinforcement board 32, and a probe head PH to which a plurality of probes PB are attached. The reinforcement board 32 connects the main board 30 and the conversion board 31 and is in a fixed connection state. The probe head PH is mounted on the conversion board 31.

[0051] The main board 30 includes a plurality of wires connected between the test interface 12 and the conversion board 31, and signals or power are transmitted through these wires. The conversion board 31 includes a plurality of wires connected between the main board 30 and the probes PB, and signals or power are transmitted through these wires.

[0052] The stage drive mechanism 22 moves the wafer stage 20 in the X-axis direction, Y-axis direction, and Z-axis direction in response to an instruction from the controller 21. In this specification, the planar direction of the semiconductor wafer WF or the planar direction of the wafer mounting surface of the wafer stage 20 is defined as the X-axis direction and the Y-axis direction perpendicular to the X-axis direction, and the direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. When the device under test DUT is tested, the stage drive mechanism 22 moves the wafer stage 20 in the X-axis direction and the Y-axis direction, and then moves the wafer stage 20 in the Z-axis direction in such a way that the probes PB contact the terminals of the device under test DUT.

[0053] In such a probe test system, when the semiconductor chip CP as the device under test (DUT), such as a system-on-chip (SoC), etc., the number of terminals of each semiconductor chip CP can be several thousand or more. Therefore, the number of probes PB in contact with the terminals also increases, and the total volume of the probes PB also increases. Here, the probes PB are made of a conductor material having a relatively small thermal resistance. Therefore, when the probes PB having a large volume come into contact with the device under test (DUT) that has been set to a high temperature, for example, heat dissipation 40b from the device under test (DUT) to the tester 1 installed in a normal temperature environment may occur.

[0054] In addition, in the device under test (DUT), heat generation 40a also occurs due to power consumption during the probe test. Therefore, during the probe test, the actual temperature of the device under test (DUT) is the temperature at which the heat generation 40a and the heat dissipation 40b are in balance, which can be a difficult-to-predict temperature. On the other hand, the table surface layer 201 generally has a higher thermal resistance than the semiconductor wafer WF. Therefore, the heat of the device under test (DUT) is easily conducted to the entire semiconductor wafer WF, but it is difficult to be conducted to the table surface layer 201.

[0055] As a result, the temperature measured by the temperature sensor 205 embedded in the table surface layer 201 does not necessarily indicate the actual temperature of the device under test (DUT), and may be a temperature that deviates from the actual temperature of the device under test (DUT) to a certain extent. In this case, even if the temperature adjustment mechanism (202, 203) is controlled based on the temperature measured by the temperature sensor 205, the actual temperature of the device under test (DUT) cannot be set to the desired test temperature. As described above, in the premise probe test system, it is difficult to set the actual temperature of the semiconductor chip CP as the device under test (DUT) with high precision. Therefore, it is advantageous to use the method of the embodiment described later.

[0056] <Configuration of the Probe Test System (Embodiment)>

[0057] Figure 2A is a schematic diagram illustrating a configuration example of the main part of the probe test system according to the first embodiment. Figure 2B is a schematic diagram illustrating Figure 2A a layout configuration example of the probes PB and the temperature sensor 45 in Figure 2A illustrates Figure 1A a configuration example of a part of the probe card 3 and a part of the probe tester (probe test device) 2 among the constituent elements described in

[0058] Different from the case of Figure 1A a non-contact temperature sensor 45 is attached to Figure 2AThe probe card 3 shown. During the probe test, the temperature sensor 45 is attached to the probe card 3 in such a way that, specifically, it is attached to the conversion board 31, the main board 30 (not shown), etc.: such that the temperature observation point is arranged at a predetermined distance D from the surface of the semiconductor wafer WF (in this case, the device under test DUT). As a result, the temperature sensor 45 measures the temperature of the device under test DUT in a non-contact manner during the probe test and outputs data regarding the measured temperature TMm.

[0059] Specifically, as Figure 2A and Figure 2B shown, the temperature observation point of the temperature sensor 45 is arranged above the internal area of the device under test DUT and at a position where the probe PB is not arranged. The term "above" refers to the direction on the Z-axis. With such an arrangement, the temperature sensor 45 can measure the actual temperature of the device under test DUT actually tested in the semiconductor wafer WF.

[0060] Specific configuration examples of the non-contact temperature sensor 45 include a fiber-optic type radiation thermometer, etc. The radiation thermometer focuses the infrared rays emitted from the measurement object (in this case, the device under test DUT) at the temperature observation point and introduces the infrared rays into the optical fiber. Then, the radiation thermometer detects the infrared rays transmitted through the optical fiber with an infrared sensor and converts the infrared rays into temperature. When using such a temperature sensor 45, the probe head PH is provided with, for example, a through-hole for the optical fiber to pass through, as Figure 2A shown.

[0061] <Details of the controller>

[0062] Figure 3 is a block diagram showing a configuration example of the controller 21a in the prober 2 in Figure 2A the figure. Figure 3 The controller 21a shown includes a communication interface (IF) 210 and a temperature controller 211. The communication interface (IF) 210 acquires the measured temperature TMm through the temperature sensor 45, more specifically, acquires data regarding the measured temperature TMm. At this time, the communication interface (IF) 210 acquires the measured temperature TMm through direct communication with the temperature sensor 45 or indirect communication via the tester 1. In the latter case, the temperature sensor 45 temporarily outputs data regarding the measured temperature TMm to the tester main body 10.

[0063] The temperature controller 211 is implemented, for example, through software processing by a processor. And Figure 1AIn a different case, the temperature controller 211 controls the temperature adjustment mechanisms (202, 203) based on the measured temperature TMm acquired via the communication interface (IF) 210. In this example, the temperature controller 211 controls the temperature adjustment mechanisms (202, 203) in such a manner that the measured temperature TMm becomes the target temperature TMt. Specifically, the temperature controller 211 performs proportional-integral control (PI control), proportional-integral-derivative control (PID control), etc. based on, for example, the error between the measured temperature TMm and the target temperature TMt to generate the manipulated variable MV (202, 203) of the temperature adjustment mechanism.

[0064] <Main effects of the first embodiment>

[0065] As described above, in the method of the first embodiment, the non-contact temperature sensor for measuring the actual temperature of the device under test is attached to the probe card, and the temperature of the wafer stage is controlled based on the temperature measured by the temperature sensor. Therefore, the actual temperature of the device under test can usually be set with high precision.

[0066] (Second embodiment)

[0067] <Configuration of the probe test system (embodiment)>

[0068] Figure 4A is a schematic diagram showing a configuration example of the main part of the probe test system according to the second embodiment. Figure 4B is a diagram showing Figure 4A a schematic diagram of the arrangement configuration example of the probe card 3 and the temperature sensor 45 in Figure 2A the same as the case of Figure 4A illustrates Figure 1A a configuration example of a part of the probe card 3 and a part of the prober (probe test device) 2 among the constituent elements described in

[0069] The same as Figure 2A the case of Figure 4A the non-contact temperature sensor 45 is attached to the probe card 3 shown in Figure 2A However, in this example, different from the case of Figure 4B as shown in, during the probe test, the temperature observation point of the temperature sensor 45 is not arranged above the internal area of the device under test DUT, but above the external area of the device under test DUT. Further, in this example, the probe card 3 includes a plurality of temperature sensors 45. For example, as shown in

[0070] Here, in the above Figure 2A and Figure 2BIn the configuration example shown, the temperature sensor 45 is arranged in the internal area of the device under test (DUT) and in an area where the probe PB is not arranged. In this case, there may be layout restrictions in the terminals of the semiconductor chip CP that are in contact with the probe PB, or there may be manufacturing restrictions in the probe card 3. In addition, if the number of the probes PB themselves is reduced, the test specifications may be affected. On the other hand, when using Figure 4A and Figure 4B the configuration example shown, such restrictions do not occur. Therefore, probe testing can be performed on various semiconductor chips CP.

[0071] However, in Figure 4A and Figure 4B the configuration example shown, different from the cases of Figure 2A and Figure 2B the temperature sensor 45 is not provided above the device under test (DUT), and thus the temperature of the device under test cannot be directly measured. Therefore, in this case, the actual temperature of the device under test (DUT) is predicted by, for example, Figure 5 the method shown. Figure 5 is a schematic diagram illustrating an example of a method for predicting the actual temperature of the device under test (DUT) in Figure 4A and Figure 4B .

[0072] Figure 5 illustrates an example of the relationship between the temperatures TMm[1] to TMm[4] measured by four temperature sensors 45[1] to 45[4] attached to the conversion board 31 and the temperature distribution RTD formed on the semiconductor wafer WF. For example, if the device under test (DUT) generates a large amount of heat during the probe test, the temperature distribution RTD of the semiconductor wafer WF is formed with the position of the device under test (DUT) as the vertex, as Figure 5 shown. The temperatures TMm[1] to TMm[4] measured by the four temperature sensors 45[1] to 45[4] are the temperatures based on the temperature distribution RTD.

[0073] On the other hand, for example, the relative positional relationship between the attachment position of the temperature sensor 45[2], the attachment position of the temperature sensor 45[1], and the position of the device under test (DUT) is always fixed. Therefore, as Figure 5 shown, based on the temperatures TMm[2] and TMm[1] measured by the temperature sensors 45[2] and 45[1] and the predetermined predicted temperature distribution PTD, the temperature of the device under test (DUT) can be predicted as the predicted temperature TMmP. The predicted temperature distribution PTD is created, for example, by performing experiments or temperature simulations in advance and is stored in a memory in the form of formulas, tables, etc.

[0074] For example, the controller 21b only needs to calculate the predicted temperature TMmP in this way so as to control the temperature adjustment mechanisms (202, 203) in such a manner that the predicted temperature TMmP becomes the target temperature TMt. Note that in this example, two temperature sensors 45[1] and 45[2] positioned in one direction with respect to the device under test DUT are used to perform temperature prediction. On the other hand, the position and number of the temperature sensors 45 to be used can be appropriately changed. However, it is desirable to perform temperature prediction based on the temperature gradient, and preferably at least two or more temperature sensors 45 are used.

[0075] <Details of the controller>

[0076] Figure 6 is a diagram Figure 4A showing a block diagram of a configuration example of the controller 21b in the probe station 2. In addition to Figure 3 the communication interface (IF) 210 and the temperature controller 211 shown, Figure 6 the controller 21b shown also includes a temperature prediction unit 212. The temperature prediction unit 212 is implemented, for example, by software processing performed by a processor. The communication interface (IF) 210 acquires the temperatures TMm[k], TMm[j],... etc. measured by a predetermined temperature sensor 45.

[0077] The controller 21b controls the temperature adjustment mechanisms (202, 203) using the temperature prediction unit 212 and the temperature controller 211 based on the measured temperatures TMm[k], TMm[j]... etc. acquired via the communication interface (IF) 210. Specifically, as Figure 5 shown, the temperature prediction unit 212 predicts the temperature of the device under test DUT as the predicted temperature TMmP based on the measured temperatures TMm[k], TMm[j]... etc. and the predicted temperature distribution PTD. For example, similar to the case of Figure 3 , the temperature controller 211 generates a manipulated variable MV and controls the temperature adjustment mechanisms (202, 203) in such a manner that the predicted temperature TMmP becomes the target temperature TMt.

[0078] <Main effects of the second embodiment>

[0079] As described above, by using the method of the second embodiment, effects substantially similar to the various effects described in the first embodiment can be obtained, and the actual temperature of the device under test can generally be set with high accuracy. In addition, different from the method of the first embodiment, there are no restrictions on the terminals or probes PB of the semiconductor chip CP, and probe tests can be performed on various semiconductor chips CP.

[0080] (Third embodiment)

[0081] <Configuration of Probe Test System (Embodiment)>

[0082] Figure 7A is a schematic diagram showing a configuration example of the main part of a probe test system according to a third embodiment. Figure 7B is a diagram showing Figure 7A a configuration example of the temperature adjustment mechanism (202, 203) in Figure 7A illustrates the same situation as Figure 4A and shows a configuration example of a part of the probe card 3 and a part of the prober (probe test device) 2 among the constituent elements described in Figure 1A . Here, the configuration of the probe card 3 is similar to that described in the second embodiment Figure 4A and Figure 4B . On the other hand, the prober 2 is different from Figure 4A in terms of the configuration of the temperature adjustment mechanism (202, 203).

[0083] That is, in Figure 4A , the temperature adjustment mechanism (202, 203) is configured to adjust the entire table surface layer 201 to a single set temperature. On the other hand, Figure 7A the temperature adjustment mechanism (202, 203) in

[0084] specifically, as shown in Figure 7B , includes a plurality of (seven in this example) adjustment regions AR[0] to AR[6], and includes split-type temperature adjustment mechanisms 50[0] to 50[6] in the seven adjustment regions AR[0] to AR[6] respectively. The split-type temperature adjustment mechanisms 50[0] to 50[6] adjust the temperatures of the adjustment regions AR[0] to AR[6] by heating or cooling respectively. In this specification, the adjustment regions AR[0] to AR[6] are collectively referred to as the adjustment region AR. In addition, the split-type temperature adjustment mechanisms 50[0] to 50[6] are collectively referred to as the split-type temperature adjustment mechanism 50.

[0085] Here, when there is one adjustment region AR, that is, in Figure 4A , mainly two problems will occur. As the first problem, as shown in Figure 5As shown by the temperature distribution RTD in [ ], the temperature gradient may be large, and thus, the prediction accuracy of the actual temperature of the device under test (DUT) may be reduced. As a second problem, for example, as a result of reducing the temperature of the entire table surface layer 201 to reduce the actual temperature of the DUT, in the region of the semiconductor wafer WF (excluding the region of the DUT), the temperature may be excessively reduced. In such a case, for example, when the DUT is moved, the stabilization time required for the DUT to reach the target temperature after the movement may increase.

[0086] Therefore, in the third embodiment, a split-type temperature adjustment mechanism 50 is used to flatten the temperature of the entire semiconductor wafer WF, as Figure 7B shown. Figure 8 FIG. is a schematic diagram showing an example of a method for flattening the temperature of the entire semiconductor wafer WF in Figure 7A and 7B . Figure 9 FIG. is a schematic diagram showing an example of the result of flattening the temperature of the entire semiconductor wafer WF using the method shown in Figure 8 .

[0087] In Figure 8 , similar to the case of Figure 5 , the four temperature sensors 45[1] to 45[4] attached to the conversion board 31 first obtain the measured temperatures TMm[1] to TMm[4] based on a temperature distribution RTD-1A similar to Figure 5 . In this state, different from the case of Figure 5 , independent manipulated variables MV[0] to MV[4] are added to the corresponding adjustment regions AR in Figure 8 .

[0088] As a result, as shown in Figure 8 and Figure 9 , when the number of adjustment regions is multiple (N), a flattened temperature distribution RTD-NA is obtained as compared with the temperature distribution RTD-1A when the number of adjustment regions AR is 1. By flattening the temperature distribution of the semiconductor wafer WF in this way, the temperature gradient becomes small, and as a result, the actual temperature of the DUT can be set to the target temperature TMt with high accuracy. In addition, when the DUT is moved, the initial temperature of the DUT after the movement can also be close to the target temperature TMt, which can shorten the stabilization time after the movement.

[0089] <Details of the controller>

[0090] Figure 10 FIG. is a block diagram showing an example of the configuration of the controller 21c in the probe station 2 in Figure 7A . Figure 11 FIG. is a diagram showing Figure 10Flowchart of an example of the processing details of the controller 21c shown. Figure 12 is a schematic diagram Figure 10 showing an example of the processing details of the temperature calculation unit 213 in the illustration.

[0091] Figure 10 The controller 21c shown includes a temperature calculation unit 213, rather than Figure 6 the temperature prediction unit 212 shown. The temperature calculation unit 213 is implemented, for example, by software processing performed by a processor. The communication interface (IF) 210 acquires the temperatures TMm[1] to TMm[m] measured by all the temperature sensors 45. The controller 21c controls the split-type temperature adjustment mechanisms 50[0] to 50[6] using the temperature calculation unit 213 and the temperature controller 211 based on the measured temperatures TMm[1] to TMm[m] acquired via the communication interface (IF) 210.

[0092] Here, Figure 12 the details of the temperature calculation unit 213 are described. Figure 12 An example of the relative positional relationship between the probe card 3 (specifically, the conversion board 31), the table surface layer 201, the semiconductor wafer WF, and the split-type temperature adjustment mechanism 50 is illustrated. As Figure 12 shown, the relative positional relationship between the semiconductor wafer WF and Figure 7B the adjustment regions AR[0] to AR[6] shown is always fixed. Therefore, if the temperature distribution of the entire semiconductor wafer WF is determined, the temperatures of the corresponding adjustment regions AR[0] to AR[6] in the semiconductor wafer WF are also determined. Based on this, the manipulated variables of the split-type temperature adjustment mechanisms 50[0] to 50[6] can be controlled individually.

[0093] On the other hand, the relative positional relationship between the probe card 3 (which ultimately represents the temperature sensor 45) and the semiconductor wafer WF changes according to the position of the device under test DUT. Therefore, depending on the position of the device under test DUT, there are temperature sensors 45a that can measure the temperature of the semiconductor wafer WF and temperature sensors 45b that cannot measure this temperature. Therefore, for each position of the device under test DUT, it is necessary to obtain the temperature distribution of the entire semiconductor wafer WF (which ultimately represents the temperature of each of the adjustment regions AR[0] to AR[6]) based on the measured temperature TMm acquired by the temperature sensors 45a that can measure the temperature.

[0094] Therefore, as Figure 10As shown, the temperature calculation unit 213 calculates the temperatures of the corresponding adjustment regions AR[0] to AR[6] in the semiconductor wafer WF as the calculated temperatures TMmC[0] to TMmC[6] based on the position information PDUT of the device under test DUT and the temperatures TMm[1] to TMm[m] measured by the temperature sensors 45. As a result, for example, in Figure 12 the case of, the unmeasured temperatures of the adjustment regions AR[3] and AR[4] are also obtained.

[0095] In addition, in order to perform such temperature calculation, the controller 21c previously stores the temperature calculation data 214 in the memory MEM. The temperature calculation data 214 is composed of, for example, mathematical data or conversion table data for obtaining the calculated temperatures TMmC[0] to TMmC[6] of the corresponding adjustment regions AR[0] to AR[7] from the temperatures TMm measured by the temperature sensors 45a capable of measuring for each position of the device under test DUT. The temperature calculation data 214 can be created, for example, by previously performing experiments or performing temperature simulations.

[0096] The temperature controller 211 individually controls the temperatures of the adjustment regions AR[0] to AR[6] such that the calculated temperatures TMmC[0] to TMmC[6] of the corresponding adjustment regions AR[0] to AR[6] from the temperature calculation unit 213 all become the target temperature TMt. Specifically, the temperature controller 211 includes, for example, seven PI controllers or the like to generate the manipulated variables MV[0] to MV[6] for the corresponding split-type temperature adjustment mechanisms 50[0] to 50[6], and individually controls the split-type temperature adjustment mechanisms 50[0] to 50[6].

[0097] Figure 11 The schematic processing details of the controller 21c are illustrated. This flowchart is implemented by, for example, a processor executing a control program stored in the memory. In Figure 11 this, the controller 21c (specifically, the communication interface (IF) 210) first obtains the temperatures TMm measured by each temperature sensor 45 on the probe card 3 (step S101).

[0098] Then, the controller 21c (specifically, the temperature calculation unit 213) calculates the temperature of each adjustment region AR as the calculated temperature TMmC based on the pre-provided temperature calculation data 214 (step S102). Next, the controller 21c (specifically, the temperature controller 211) compares the calculated temperature TMmC with the target temperature TMt (step S103). Here, when the calculated temperature TMmC matches the target temperature TMt (step S103: Yes), the controller 21c proceeds to step S105, and when the calculated temperature TMmC does not match the target temperature TMt (step S103: No), the controller 21c proceeds to steps S105 to S104.

[0099] In step S104, the temperature controller 211 uses the split-type temperature adjustment mechanism 50 of the corresponding region to adjust the temperature of the adjustment region AR that does not match the target temperature TMt so that it matches the target temperature TMt. In addition, in step S105, unless the probe test is terminated, the controller 21c returns to step S101 and performs similar processing. That is, the controller 21c repeatedly executes the processing of steps S101 to S104 at a predetermined control cycle.

[0100] <Main effects of the third embodiment>

[0101] As described above, by using the method of the third embodiment, effects substantially similar to the various effects described in the second embodiment can be obtained, and the actual temperature of the device under test can generally be set with high precision. That is, in the method of the third embodiment, by flattening the temperature distribution of the semiconductor wafer, the actual temperature of the device under test can be set with high precision. In addition, by flattening the temperature distribution of the semiconductor wafer, the temperature stabilization time required when the device under test moves can be shortened.

[0102] (Fourth embodiment)

[0103] <Details of the controller>

[0104] Figure 13 is a block diagram showing a modified configuration example of the controller in the probe test system according to the fourth embodiment Figure 10 shown. Figure 14A And Figure 14B is a flowchart showing Figure 13 an example of the processing details of the controller 21d shown. The overall configuration of the probe test system according to the fourth embodiment is similar to Figure 7A and Figure 7B the case of. Compared with the Figure 10 configuration example shown, Figure 13The illustrated controller 21d further includes a preheating control unit 215 and preheating data 216. The preheating control unit 215 is implemented, for example, by software processing performed by a processor.

[0105] Here, for example, if the method of the above-described third embodiment is used, when the movement of the device under test DUT starts, the semiconductor wafer WF is separated from the probe card 3 by the movement of the wafer stage 20 in the Z-axis direction. Therefore, the temperature sensor 45 cannot measure the temperature of the semiconductor wafer WF, and the control loop for controlling the split type temperature adjustment mechanism 50 cannot be normally formed.

[0106] Therefore, during the probe test period, the preheating control unit 215 receives the manipulated variables MV[0] to MV[6] of the corresponding adjustment regions AR[0] to AR[6] from the temperature controller 211. Then, the preheating control unit 215 stores the received manipulated variables MV[0] to MV[6] in the memory MEM as preheating data 216 for each position of the device under test DUT (i.e., each position information PDUT). During the period from the start to the completion of the movement of the device under test DUT, the preheating control unit 215 outputs the manipulated variables MV[0] to MV[6] to the split type temperature adjustment mechanisms 50[0] to 50[6] based on the preheating data 216 to control the temperatures of the adjustment regions AR[0] to AR[6].

[0107] At this time, more preferably, the preheating control unit 215 pre-controls the temperatures of the adjustment regions AR[0] to AR[6] individually based on the preheating data 216 corresponding to the position of the device under test DUT after the movement. That is, explained in chronological order, for example, when performing a probe test on a certain semiconductor wafer WF, the preheating data 216 is created or updated. Then, when performing a probe test on the next semiconductor wafer WF, the created or updated preheating data 216 is applied.

[0108] Here, for example, as Figure 8 shown, the manipulated variables MV[0] to MV[6] of the split type temperature adjustment mechanisms 50[0] to 50[6] are different values from each other and also vary according to the position of the device under test DUT. Therefore, it is desirable to pre-control the split type temperature adjustment mechanisms 50[0] to 50[6] based on the preheating data 216 corresponding to the position of the device under test DUT after the movement before the movement is actually completed. Therefore, the temperature stabilization time of the device under test DUT after the movement can be further shortened.

[0109] Figure 14A and Figure 14B illustrates the schematic processing details of the controller 21d. This flowchart is implemented by, for example, a processor executing a control program stored in a memory. In Figure 14A andFigure 14B In the flowchart shown, the processing of steps S201 to S207 is inserted between Figure 11 steps S103 or S104 and step S105 in the flowchart shown.

[0110] In step S201, unless the movement to the next device under test (DUT) starts, the controller 21d repeatedly executes the processing of steps S101 to S104, that is, the processing performed by the communication interface (IF) 210, the temperature calculation unit 213, and the temperature controller 211. On the other hand, when the movement to the next DUT starts (step S201: Yes), the controller 21d (specifically, the preheating control unit 215) associates the manipulated variable MV generated, for example, in steps S103 and S104 with the position information PDUT of the DUT, and updates the preheating data 216 (step S202).

[0111] Subsequently, the preheating control unit 215 outputs the manipulated variable MV to the split-type temperature control mechanism 50 (instead of the temperature controller 211) based on the preheating data 216 of the next DUT after the movement to perform the temperature control, that is, preheating, of each adjustment region AR. Then, the preheating control unit 215 waits for the movement to the next DUT to be completed (step S204). Then, when the movement to the next DUT is completed (step S204: Yes), the preheating control unit 215 terminates the preheating and switches in such a way that the manipulated variable MV is output from the temperature controller 211 to the split-type temperature control mechanism 50 (step S205).

[0112] Next, the controller 21d (specifically, the communication interface (IF) 210) acquires the temperature TMm measured by each temperature sensor 45 on the probe card 3 (step S206). As a result, the controller 21d can update the temperature calculation data 214 based on the acquired measured temperature TMm (step S207). That is, in step S206, by the movement of the DUT, the temperature of the unmeasured region, that is, Figure 12 the region of the semiconductor wafer WF that does not overlap with the probe card 3 in can be measured. By using this measurement result, the temperature calculation data 214 can be updated or corrected to be more accurate.

[0113] <Main effects of the fourth embodiment>

[0114] As described above, by using the method of the fourth embodiment, effects substantially similar to the various effects described in the third embodiment can be obtained, and the actual temperature of the device under test can generally be set with high accuracy. In addition, by performing preheating, compared with the method of the third embodiment, the temperature stabilization time of the device under test after the movement can be further shortened.

[0115] (Fifth Embodiment)

[0116] <Configuration of probe test system (embodiment)>

[0117] Figure 15A is a schematic diagram illustrating a configuration example of a main part of a probe test system according to a fifth embodiment. Figure 15B It is a graphic Figure 15A Schematic diagram of an arrangement configuration example of the temperature sensor 25 in FIG. Figure 15A Pictured Figure 1A A configuration example of a part of the probe card 3 and a part of the probe meter (probe test device) 2 among the constituent elements described in FIG. Figure 15A In the embodiment, unlike the case of the first to fourth embodiments, the probe card 3 does not include the temperature sensor 45 and is configured as usual.

[0118] Instead, the prober 2 includes a Figure 1A and Figure 1B The temperature sensor 205 embedded in the stage surface layer 201 is different from the temperature sensor 25. The temperature sensor 25 includes a temperature observation point exposed on the wafer mounting surface of the stage surface layer 201, and directly measures the temperature of the rear surface of the semiconductor wafer WF mounted on the wafer mounting surface without interposing a metal member or the like of the stage surface layer 201. As a result, the actual temperature of the semiconductor wafer WF can be measured with high accuracy.

[0119] The temperature sensor 25 may be a non-contact type or a contact type. Figure 15A As shown, it is desirable to use a contact type temperature sensor 25. The contact type temperature sensor 25 measures the temperature of the semiconductor wafer WF through a temperature observation point in contact with the rear surface of the semiconductor wafer WF. By using the contact type, it is easy to achieve an expansion of the temperature measurement range or a further improvement in the temperature measurement accuracy compared to the case of using a non-contact type. Examples of the contact type temperature sensor 25 include an RTD sensor using the resistance value of a resistance temperature detector such as platinum, a thermistor using the resistance temperature characteristic of a semiconductor, and a thermocouple using the Seebeck effect.

[0120] In addition, in this example, Figure 15B As shown, a plurality of temperature sensors 25 are provided. The temperature observation points of the temperature sensors 25 are arranged in a substantially uniformly dispersed manner in the region of the wafer mounting surface in the stage surface layer 201. In this example, Figure 15A The probe instrument 2 shown also includes Figure 7B The split temperature regulating mechanism 50 is shown.

[0121] When using this configuration example, different from the cases of the first to fourth embodiments, it is not necessary to attach the temperature sensor 45 to the probe card 3, which may be required for each product, and the cost can be reduced. In addition, for example, a method similar to that of the third or fourth embodiment can be implemented without performing the temperature calculation as described in Figure 12 or by performing a simple temperature calculation.

[0122] That is, different from the case of Figure 12 etc., the relative positional relationship between the temperature sensor 25 and the semiconductor wafer WF (which ultimately represents the adjustment region AR) is always fixed. Therefore, the temperature distribution of the semiconductor wafer WF is directly obtained from the temperature TMm measured by the temperature sensor 25, and the temperature of each adjustment region AR is obtained based on the temperature distribution.

[0123] Here, more preferably, the temperature observation points of the temperature sensor 25 are arranged to correspond to the respective adjustment regions AR. That is, in addition to the split-type temperature adjustment mechanisms 50[0] to 50[6], the temperature sensors 25[0] to 25[6] are preferably arranged in Figure 7B the respective adjustment regions AR[0] to AR[6]. In this case, since the temperature of each adjustment region AR can be directly obtained, temperature control becomes easy, and there are no errors associated with temperature calculation, etc.

[0124] <Details of the controller>

[0125] Figure 16 is a block diagram of a configuration example of the controller 21e in the probe instrument 2 shown in Figure 15A Here, it is assumed that a method similar to that of the fourth embodiment is implemented using the configuration example shown in Figure 15A In addition, as described above, it is assumed that the temperature sensor 25 is arranged in the respective adjustment regions AR. Different from the configuration example shown in Figure 13 the controller 21e shown in Figure 16 is not equipped with a communication interface (IF) 210, a temperature calculation unit 213, and temperature calculation data 214.

[0126] The temperature controller 211 receives the measured temperatures TMm[0] to TMm[6] from the temperature sensors 25[0] to 25[6]. Then, the temperature controller 211 individually controls the temperatures of the adjustment regions AR[0] to AR[6] in such a way that the received measured temperatures TMm[0] to TMm[6] all become the target temperature TMt. Specifically, for example, the temperature controller 211 is in a manner similar to Figure 10In a similar manner for the corresponding split-type temperature adjustment mechanisms 50[0] to 50[6], manipulation variables MV[0] to MV[6] are generated, and the split-type temperature adjustment mechanisms 50[0] to 50[6] are controlled individually. As described above, since a communication interface (IF) 210 is not required, the delay in obtaining the measured temperature TMm (which ultimately represents the delay in temperature control) can be shortened.

[0127] In addition, regarding the preheating control unit 215, in this case, different from Figure 13 the case described above, regardless of the movement of the device under test DUT, a control loop is always formed from the temperature sensors 25[0] to 25[6] to the split-type temperature adjustment mechanisms 50[0] to 50[6]. Therefore, the preheating control unit 215 is not necessarily required. However, from the perspective of performing preheating according to the position of the device under test DUT after movement, it is advantageous to provide the preheating control unit 215.

[0128] Note that in this case, an example of implementing a method similar to that of the third or fourth embodiment has been described using the Figure 15A configuration example shown. In addition to this, in some cases, a method similar to that of the second embodiment can also be implemented by using the Figure 15A configuration example shown, that is, the Figure 5 method shown. In this case, the controller 21 only needs to predict the temperature of the device under test based on the temperature TMm measured by the temperature sensor 25 and the position information PDUT of the device under test DUT.

[0129] <Main effects of the fifth embodiment>

[0130] As described above, by using the method of the fifth embodiment, effects substantially similar to various effects described in the third or fourth embodiment can be obtained, and the actual temperature of the device under test can generally be set with high accuracy. In addition, the cost of manufacturing the probe card can be reduced, and temperature control can be further promoted.

[0131] (Sixth embodiment)

[0132] <Existing problems and countermeasures>

[0133] Figure 17 is a schematic diagram showing an example of a premise problem in the probe test system according to the sixth embodiment and countermeasures for this problem. The self-heat generation in the device under test DUT varies according to the test performed. In addition, for example, when performing temperature feedback control (FB control), it is difficult to track the temperature change caused by the difference in self-heat generation at high speed within the normal control band. Therefore, as Figure 17As shown in the upper part of [[ID=]], during the test, the actual temperature RTMa of the device under test (DUT) may change significantly to some extent over time.

[0134] Therefore, in the sixth embodiment, feedforward control (FF control) is performed by pre-generating a manipulated variable MV that reflects the temporal change in the actual temperature RTMa. As a result, as Figure 17 shown in the lower part of [[ID=]], the device under test (DUT) is set to the actual temperature RTMb that suppresses temperature changes. Note that the method of the sixth embodiment can be applied in combination with any of the methods of the first to fifth embodiments described above.

[0135] <Details of the controller>

[0136] Figure 18 is a block diagram showing a configuration example of a temperature controller 211 included in a controller in a prober in a probe test system according to the sixth embodiment. In this example, Figure 18 the shown temperature controller 211 includes a PID controller. The PID controller performs PID control based on the error between the measured temperature TMm, the predicted temperature TMmP, or the calculated temperature TMmC and the target temperature TMt, using the proportional coefficient Kp, the integral coefficient Ki, and the derivative coefficient Kd, to output a manipulated variable MVx that makes the error approach zero. The PID controller can also suppress temperature changes to some extent.

[0137] Here, the temperature controller 211 also stores temperature control data 220 in the memory MEM. The temperature control data 220 is data pre-generated based on the temporal temperature change in the device under test (DUT) during the probe test period (i.e., Figure 17 the shown actual temperature RTMa) for canceling out temperature changes. The temperature controller 211 performs feedforward control on the temperature adjustment mechanism (202, 203) or the split-type temperature adjustment mechanism 50 based on the temperature control data 220 during the probe test period. Specifically, for example, the temperature controller 211 generates a final manipulated variable MV by adding the temporal correction manipulated variable dMV based on the temperature control data 220 to the manipulated variable MVx from the PID controller.

[0138] Figure 19 is a flowchart showing an example of the processing details of a controller in a prober in a probe test system according to the sixth embodiment. Figure 20 is for explaining Figure 19 a part of the processing details shown in [[ID=]]. Here, as an example, the case of applying the Figure 18 shown configuration example to the method of the third embodiment is described, that is, Figure 10 the shown temperature controller 211.

[0139] InFigure 19 In this case, the controller 21 first determines whether there is temperature control data 220 (step S301). When there is existing temperature control data 220 (step S301: Yes), the controller 21 applies the existing temperature management data 220 and proceeds to step S303. In this case, in subsequent processing, the temperature controller 211 performs FF control using the corrected manipulated variable dMV, as Figure 18 shown. On the other hand, when there is no temperature control data 220 (step S301: No), the controller 21 directly proceeds to step S303.

[0140] In step S303, the controller 21 acquires the temperature TMm measured by each temperature sensor 45. Subsequently, the controller 21 calculates the temperature of each adjustment region AR based on the acquired measured temperature TMm (step S304). Then, the controller 21 performs temperature control in such a manner that the calculated temperature TMmC becomes the target temperature TMt (step S305). Here, the controller 21 determines whether the temperature of the device under test DUT (e.g., the temperature TMm measured by any temperature sensor 45) is outside a predetermined target temperature range (step S306).

[0141] When the temperature of the device under test DUT is within the target temperature range (step S306: No), the controller 21 returns to step S303 and repeats the same process. On the other hand, when the temperature of the device under test DUT is outside the target temperature range (step S306: Yes), the controller 21 acquires time series data regarding the temperature of the device under test DUT (step S307). Subsequently, the controller 21 newly generates temperature control data 220 or updates the existing temperature control data 210 to cancel out the temperature change included in the acquired time series data (step S308).

[0142] In addition, the controller 21 can acquire the measured value of a DC test item, such as a power supply current value, from the tester 1 and update the temperature control data 220 by reflecting the measured value (step S309). That is, as Figure 20 shown, there is generally a correlation between the measured value of the DC test item and the actual temperature RTMb. Therefore, the temperature control data 220 can be updated using the measured value of the DC test item.

[0143] Thereafter, the controller 21 returns to step S301 and repeats similar processing. At this time, the temperature control data 220 created or updated in steps S308 and S309 is applied as existing temperature control data to, for example, the next device under test (DUT) or the like. In steps S308 and S309, for example, artificial intelligence (AI) can be made to learn the relationship between the temperature change in the device under test (DUT), the temperature control data 220, and the measured values of the DC test items, so as to generate temperature control data capable of suppressing the temperature change in the device under test (DUT).

[0144] <Main effects of the sixth embodiment>

[0145] As described above, by using the method of the sixth embodiment, the actual temperature of the device under test can generally be set with high precision. In particular, during the test of the device under test, the actual temperature of the device under test can be set with high precision while suppressing the change in the actual temperature according to the test items.

[0146] Although the invention of the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from the gist of the invention.

Claims

1. A probe testing device, comprising: a wafer stage including a wafer mounting surface on which a semiconductor wafer is mounted; a temperature sensor including a temperature observation point exposed on the wafer mounting surface and configured to directly measure a temperature of a rear surface of the semiconductor wafer mounted on the wafer mounting surface; a temperature adjustment mechanism configured to adjust the temperature of the wafer stage by heating or cooling the wafer stage; as well as A controller is configured to control the temperature adjustment mechanism in such a manner that the temperature measured by the temperature sensor becomes a target temperature.

2. The probe testing device according to claim 1, The temperature sensor is a contact temperature sensor configured to measure the temperature of the semiconductor wafer through the temperature observation point being in contact with the rear surface of the semiconductor wafer.

3. The probe testing device according to claim 2, further comprising: Multiple temperature sensors, The temperature observation points of the plurality of temperature sensors are arranged in a substantially uniformly dispersed manner within a region of the wafer mounting surface.

4. The probe testing device according to claim 3, wherein the temperature adjustment mechanism includes a plurality of adjustment regions that divide the region of the wafer mounting surface, and the temperature adjustment mechanism is configured to individually adjust the temperatures of the plurality of adjustment regions.

5. The probe testing device according to claim 4, The temperature observation points of the plurality of temperature sensors are arranged to correspond to the plurality of adjustment areas.

6. The probe testing device according to claim 4, wherein the controller individually controls the temperatures of the plurality of conditioning areas in such a manner that each temperature measured by the plurality of temperature sensors becomes the target temperature.

7. The probe testing device according to claim 6, The controller stores the manipulated variables for the temperature of each of the multiple adjustment areas in a memory as preheating data for each position of the device under test formed on the semiconductor wafer, and pre-individually controls the temperatures of the multiple adjustment areas based on the preheating data corresponding to the positions of the device under test after the movement during a period from the start to the completion of the movement of the device under test.

8. The probe testing device according to claim 1, wherein the controller further stores the temperature control data in a memory and performs feedforward control on the temperature adjustment mechanism based on the temperature control data during a probe test period, and The temperature control data is data generated based on a time-series temperature variation in a device under test formed on the semiconductor wafer during the probe test period to offset the temperature variation.

9. A probe test system, comprising a probe card and a probe test device, The probe card comprises: a plurality of probes attached to contact terminals of a device under test formed on a semiconductor wafer during a probe test; as well as a non-contact temperature sensor attached in such a manner that a temperature observation point is arranged at a predetermined distance from a surface of the semiconductor wafer during the probe test and configured to measure the temperature of the semiconductor wafer in a non-contact manner, and The probe testing device comprises: a wafer stage including a wafer mounting surface on which the semiconductor wafer is mounted; a temperature adjustment mechanism configured to adjust the temperature of the wafer stage by heating or cooling the wafer stage; and A controller is configured to acquire a temperature measured by the temperature sensor attached to the probe card and control the temperature adjustment mechanism based on the measured temperature.

10. The probe testing system according to claim 9, wherein the temperature observation point of the temperature sensor is arranged above the inner region of the device under test and is located at a position where the plurality of probes are not arranged, and The controller controls the temperature adjustment mechanism in such a manner that the measured temperature becomes a target temperature.

11. The probe testing system according to claim 9, further comprising: Multiple temperature sensors, wherein during the probe test, the temperature observation points of the plurality of temperature sensors are arranged above the outer area of ​​the device under test, and The controller predicts the temperature of the device under test as a predicted temperature based on the temperatures measured by the plurality of temperature sensors, and controls the temperature adjustment mechanism in such a manner that the predicted temperature becomes a target temperature.

12. The probe testing system according to claim 9, further comprising: Multiple temperature sensors, The temperature observation points of the plurality of temperature sensors are arranged in a substantially uniformly dispersed manner within the region of the probe card.

13. The probe testing system according to claim 12, wherein the temperature adjustment mechanism includes a plurality of adjustment regions that divide an area of ​​the wafer mounting surface, and the temperature adjustment mechanism is configured to individually adjust temperatures of the plurality of adjustment regions.

14. The probe testing system according to claim 13, The controller calculates the temperature of each of the multiple adjustment areas in the semiconductor wafer based on the position of the device under test and the temperature measured by the multiple temperature sensors, and individually controls the temperatures of the multiple adjustment areas in such a way that the calculated temperature of each of the multiple adjustment areas becomes a target temperature.

15. The probe testing system according to claim 14, The controller stores the manipulated variables for the temperature of each of the multiple adjustment areas in a memory as preheating data for each position of the device under test, and pre-individually controls the temperatures of the multiple adjustment areas based on the preheating data corresponding to the positions of the device under test after the movement during a period from the start to the completion of the movement of the device under test.

16. The probe testing system according to claim 9, wherein the controller further stores temperature control data in a memory, and performs feed-forward control on the temperature adjustment mechanism based on the temperature control data during a probe test period of the device under test, and The temperature control data is data generated based on a time series temperature change in the device under test during the probe test period to offset the temperature change.

17. A probe card for use in a probe test of a device under test formed on a semiconductor wafer, the probe card comprising: a plurality of probes attached to contact terminals of the device under test during the probe test; as well as A non-contact temperature sensor is attached in such a manner that a temperature observation point is arranged at a predetermined distance from a surface of the semiconductor wafer during the probe test, and is configured to measure the temperature of the semiconductor wafer in a non-contact manner.

18. The probe card according to claim 17, During the probe test, the temperature observation point of the temperature sensor is arranged above the inner region of the device under test and is located at a position where the plurality of probes are not arranged.

19. The probe card according to claim 17, further comprising: Multiple temperature sensors, During the probe test, the temperature observation points of the plurality of temperature sensors are arranged above an external area of ​​the device under test.

20. The probe card according to claim 17, further comprising: Multiple temperature sensors, The temperature observation points of the plurality of temperature sensors are arranged in a substantially uniformly dispersed manner within the region of the probe card.

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