Distribution network monitoring control chip synchronization error detection method, system and device and medium

Abstract

The invention discloses a distribution network monitoring control chip synchronization error detection method, system and device and a medium. The method comprises the following steps: executing clock synchronization processing on a first CPU core and a second CPU core based on a phase-locked loop; executing the same instruction through the first CPU core and the second CPU core, and synchronously marking an obtained calculation result and a timestamp; and performing data consistency detection on the marked calculation result and the timestamp so as to determine whether an error exists or not. According to the embodiment of the invention, through the phase-locked loop and real-time comparison, dual-core synchronous execution and real-time verification are realized, and the detection efficiency and precision can be improved. The method can be widely applied to the technical field of intelligent power grids.

Description

Technical Field

[0001] The present invention relates to the field of smart grid technology, and in particular to a method, system, device and medium for detecting synchronization errors of a distribution network monitoring control chip. Background Art

[0002] With the development of smart grid and automation technology, the demand for high reliability and fault detection capabilities of distribution network monitoring and control chips has increased significantly. In related technologies, single-core or simple dual-core architectures are difficult to effectively deal with diverse faults in complex operating environments, and the detection accuracy and real-time performance are insufficient, and the detection efficiency is low. Summary of the invention

[0003] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of the present invention is to provide an efficient distribution network monitoring control chip synchronization error detection method, system, device and medium.

[0005] In order to achieve the above technical objectives, one aspect of an embodiment of the present invention provides a method for detecting synchronization errors of a distribution network monitoring control chip, comprising the following steps: performing clock synchronization processing on a first CPU core and a second CPU core based on a phase-locked loop; performing synchronization marking on the obtained calculation results and timestamps by executing the same instructions by the first CPU core and the second CPU core; performing data consistency detection on the marked calculation results and timestamps, and then determining whether there is an error. The embodiment of the present application realizes dual-core synchronous execution and real-time verification through a phase-locked loop and real-time comparison, which is conducive to improving detection efficiency and accuracy.

[0006] In some embodiments, the method for detecting synchronization errors of a distribution network monitoring control chip according to an embodiment of the present invention further includes:

[0007] If data inconsistency is detected, the program counter is used to track the instruction stream and the error source is located by comparing with the memory log;

[0008] The status information of the main core and the backup core are synchronized in real time. If the main core fails, the backup core is switched to resume computing. The main core includes the first CPU core and the second CPU core.

[0009] In some embodiments, in one embodiment of the present invention, the real-time synchronization of the status information of the main core and the backup core, if the main core fails, switching to the backup core to resume computing, includes:

[0010] If the main core executes the task, the state information of the main core is synchronized to the memory of the standby core through the memory mapping technology;

[0011] If an error occurs in the main core, the standby core resumes calculation from the state information of the last synchronization after receiving the switching signal.

[0012] In some embodiments, in one embodiment of the present invention, the method further comprises the following steps:

[0013] If the source of the error is located as a memory or data calculation error, the standby core starts a rollback mechanism to restore to the most recent error-free state and continue execution;

[0014] Alternatively, if the source of the location error is a hardware failure, the main core and the standby core resume operation by resetting damaged modules or switching standby hardware.

[0015] In some embodiments, in one embodiment of the present invention, the method further comprises:

[0016] After the data is divided into blocks, a rough comparison is performed using a hash algorithm. If the rough comparison results are inconsistent, a detailed comparison is performed using the main core and the backup core;

[0017] Adjust CPU frequency and voltage through dynamic voltage and frequency according to real-time load to optimize power consumption;

[0018] The computing tasks are distributed to the main core and the standby core through load balancing.

[0019] In some embodiments, in one embodiment of the present invention, the method further comprises:

[0020] The task scheduler uses a priority-weighted round-robin algorithm to monitor and assign tasks in real time;

[0021] Dynamically adjust task priorities during system recovery after a failure.

[0022] In some embodiments, in one embodiment of the present invention, the method further comprises:

[0023] Constructing a dual-core lock-step architecture, the dual-core lock-step architecture includes:

[0024] The first CPU core and the second CPU core are used to synchronously execute the same instruction stream;

[0025] A lockstep controller, configured to perform clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop;

[0026] A synchronization marking module is used to synchronize the obtained calculation results and timestamps;

[0027] A synchronization comparison module, used for performing data consistency detection on the marked calculation result and the timestamp;

[0028] A fault location module is used to determine whether an error occurs.

[0029] On the other hand, an embodiment of the present invention provides a distribution network monitoring control chip synchronization error detection system, including:

[0030] The first module is used to perform clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop;

[0031] A second module is used for executing the same instruction by the first CPU core and the second CPU core to synchronously mark the obtained calculation result and timestamp;

[0032] The third module is used to perform data consistency detection on the marked calculation result and the timestamp to determine whether there is an error.

[0033] On the other hand, an embodiment of the present invention provides a distribution network monitoring control chip synchronization error detection device, comprising:

[0034] at least one processor;

[0035] at least one memory for storing at least one program;

[0036] When the at least one program is executed by the at least one processor, the at least one processor implements the above-mentioned distribution network monitoring control chip synchronization error detection method.

[0037] On the other hand, an embodiment of the present invention provides a storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to implement the above-mentioned distribution network monitoring control chip synchronization error detection method.

[0038] The embodiments of the present application include at least the following beneficial effects: The method provided by the embodiments of the present application includes: performing clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop; performing synchronization marking on the obtained calculation results and timestamps by executing the same instructions by the first CPU core and the second CPU core; performing data consistency detection on the marked calculation results and timestamps, thereby determining whether there are errors. The embodiments of the present application achieve dual-core synchronous execution and real-time verification through a phase-locked loop and real-time comparison, which is conducive to improving detection efficiency and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of a flow chart of an embodiment of a method for detecting synchronization errors of a distribution network monitoring control chip provided by the present invention;

[0041] Figure 2 A schematic diagram of the structure of an embodiment of the dual-core lockstep architecture provided by the present invention;

[0042] Figure 3 A schematic diagram of a flow chart of an embodiment of the fault tolerance and redundant backup process provided by the present invention;

[0043] Figure 4 A schematic diagram of a flow chart of an embodiment of a hardware logic optimization process provided by the present invention;

[0044] Figure 5 A schematic diagram of the structure of an embodiment of the distribution network monitoring control chip synchronization error detection system provided by the present invention;

[0045] Figure 6 A schematic structural diagram of an embodiment of a synchronization error detection device for a distribution network monitoring control chip provided by the present invention. DETAILED DESCRIPTION

[0046] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0047] First, the terms involved in this application are explained:

[0048] Dual-core lockstep: The safety-critical core processing modules are replicated, and the outputs of the two cores are compared at every clock cycle. When a failure occurs, an error identification signal is output so that the system can take timely countermeasures.

[0049] Phase-locked loop (PLL): A negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to produce a target frequency.

[0050] Direct Memory Access (DMA): In computer science, a memory access technique.

[0051] Dynamic Voltage and Frequency Scaling (DVFS): A technology that dynamically adjusts processor voltage and frequency based on system load.

[0052] With the development of smart grid and automation technology, the demand for high reliability and fault detection capabilities of distribution network monitoring and control chips has increased significantly. Traditional methods are difficult to balance detection accuracy and real-time performance in complex environments, and dual-core lockstep technology has become an important means to improve chip fault tolerance due to its advantages in parallel execution and synchronization. However, existing technologies are still insufficient in terms of synchronization error detection efficiency, and a more efficient solution is urgently needed.

[0053] In summary, the existing technology has the following defects in the error detection and fault tolerance capabilities of distribution network monitoring and control chips: First, the traditional single-core or simple dual-core architecture is difficult to effectively deal with diverse faults in complex operating environments, and the detection accuracy and real-time performance are insufficient; second, the synchronous error detection efficiency is low, and it is impossible to quickly identify and locate multi-CPU-level execution errors; third, there is a lack of efficient redundant backup mechanism, which can easily lead to system interruption when a fault occurs, affecting the stability of the distribution network. In response to the above problems, the present invention needs to solve the problems of insufficient error detection accuracy, weak fault tolerance, and low backup switching efficiency in the dual-core lock-step architecture, so as to improve the reliability and adaptability of the chip in the smart grid.

[0054] The following describes in detail the distribution network monitoring control chip synchronization error detection method and system proposed in an embodiment of the present invention with reference to the accompanying drawings. First, the distribution network monitoring control chip synchronization error detection method proposed in an embodiment of the present invention will be described with reference to the accompanying drawings.

[0055] Reference Figure 1In an embodiment of the present invention, a method for detecting synchronization errors of a distribution network monitoring and control chip is provided. The method for detecting synchronization errors of a distribution network monitoring and control chip in an embodiment of the present invention can be applied to a terminal or a server, or can be software running in a terminal or a server, etc. The terminal can be a tablet computer, a laptop computer, a desktop computer, etc., but is not limited thereto. The server can be an independent physical server, or a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The method for detecting synchronization errors of a distribution network monitoring and control chip in an embodiment of the present invention mainly includes the following steps:

[0056] S100: performing clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop;

[0057] S200: executing the same instruction by the first CPU core and the second CPU core, and synchronously marking the obtained calculation result and the timestamp;

[0058] S300: Performing data consistency check on the marked calculation results and timestamps to determine whether there are errors.

[0059] In some possible implementations, the first CPU core and the second CPU core in the present application execute the same instruction stream, and after synchronizing the two calculation results and timestamps obtained by executing the instructions, perform data consistency detection.

[0060] Optionally, in one embodiment of the present invention, the method further comprises:

[0061] If data inconsistency is detected, the program counter is used to track the instruction stream and the error source is located by comparing with the memory log;

[0062] The status information of the main core and the backup core are synchronized in real time. If the main core fails, the backup core is switched to resume computing. The main core includes a first CPU core and a second CPU core.

[0063] In some possible implementations, if a main core fails, the present application triggers recovery and performs operations through a backup core to ensure that the task is not interrupted.

[0064] Optionally, in one embodiment of the present invention, synchronizing the status information of the main core and the backup core in real time, and if the main core fails, switching to the backup core to resume computing, includes:

[0065] If the main core executes a task, the state information of the main core is synchronized to the memory of the standby core through memory mapping technology;

[0066] If an error occurs in the main core, the backup core receives the switching signal and resumes calculation from the last synchronized state information.

[0067] Optionally, in one embodiment of the present invention, the method further comprises:

[0068] If the error source is located as a memory or data calculation error, the standby core initiates the rollback mechanism, recovers to the most recent error-free state, and continues execution;

[0069] Alternatively, if the source of the error is located as a hardware failure, the main core and the backup core resume operation by resetting the damaged module or switching the backup hardware.

[0070] Optionally, in one embodiment of the present invention, the method further comprises:

[0071] After the data is divided into blocks, a rough comparison is performed using a hash algorithm. If the rough comparison results are inconsistent, a detailed comparison is performed using the main core and the backup core;

[0072] Adjust CPU frequency and voltage through dynamic voltage and frequency according to real-time load to optimize power consumption;

[0073] The computing tasks are distributed to the main core and the backup core through load balancing.

[0074] In some possible implementations, a rough comparison only requires comparing the data blocks as a whole, while a fine comparison requires comparing the data bit by bit.

[0075] Optionally, in one embodiment of the present invention, the method further comprises:

[0076] The task scheduler uses a priority-weighted round-robin algorithm to monitor and assign tasks in real time;

[0077] Dynamically adjust task priorities during system recovery after a failure.

[0078] In some possible implementations, the priorities and weights in this application can be adjusted according to actual needs.

[0079] Optionally, in one embodiment of the present invention, the method further comprises:

[0080] Build a dual-core lock-step architecture, which includes:

[0081] The first CPU core and the second CPU core are used to synchronously execute the same instruction stream;

[0082] A lockstep controller, configured to perform clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop;

[0083] A synchronization marking module is used to synchronize the obtained calculation results and timestamps;

[0084] A synchronous comparison module is used to perform data consistency detection on the marked calculation results and timestamps;

[0085] A fault location module is used to determine whether an error occurs.

[0086] The following is a detailed description of the detection method provided by the present application with a specific embodiment:

[0087] The present application provides a dual-core lock-step based distribution network monitoring control chip synchronization error detection method, comprising the following steps:

[0088] 1.1 Dual-core lock-step architecture design: With dual-core CPU architecture, two cores synchronously execute the same instruction stream, and the clock frequency is adjusted through the lock-step control module to ensure precise synchronization.

[0089] 1.2 Synchronization mark generation and transmission: After executing the instruction, each core generates a synchronization mark containing the calculation result and timestamp, which is transmitted to the comparison module through the shared bus.

[0090] 1.3 Real-time error detection and positioning: The comparison module performs periodic comparison based on the timestamp, triggers an error interrupt when the detected data is inconsistent, and locates the source of abnormal instructions or data transmission.

[0091] 1.4 Task Scheduling and Fault Tolerance Mechanism: Dynamically schedule tasks through a priority weighted polling algorithm to ensure that high-priority tasks are executed first, and initiate a fault-tolerant recovery mechanism when errors are found.

[0092] 1.5 Redundant backup and recovery: The main core and the backup core synchronize data in real time through DMA technology. When a failure occurs, the backup core takes over and restores the task to ensure system continuity.

[0093] Specifically: The present invention adopts a dual-core synchronous execution and real-time verification method, referring to Figure 2As shown in the figure, a lockstep architecture is constructed by dual-core CPU, synchronous comparison module and shared bus. The two CPU cores are respectively configured with independent cache (L1Cache) and shared memory (Shared Memory), and run the same instruction stream. To achieve high-precision synchronization, the system introduces a lockstep control module (Lockstep Controller), which adjusts the clock frequency of the two cores through the phase-locked loop (PLL) to make the instruction issuance cycle strictly consistent. After the instruction is executed, each CPU generates a synchronization mark containing the calculation result and a 64-bit timestamp, and transmits it to the comparison module through the shared bus. The comparison module uses the timestamp as the reference to verify the consistency and synchronization of the calculation results cycle by cycle. When data deviation is detected, the system immediately triggers an error interrupt, records the fault type and core number, and locates the specific instruction or data transmission abnormality source through the fault location module to provide support for subsequent fault-tolerant processing.

[0094] The present invention introduces a priority weighted round-robin algorithm (WRR) in a dual-core lock-step architecture for dynamic task scheduling. The system dynamically allocates tasks by real-time monitoring of the core load, including execution cycles and memory access frequencies. The scheduler prioritizes urgent tasks based on the urgency and computational complexity of the tasks to ensure that computing resources are optimally utilized. The error location module monitors the execution consistency between cores in real time through instruction stream comparison and timestamp tracking. When inconsistencies are detected, the system uses a program counter to track the instruction stream and locates the source of the error in combination with memory log comparison. Error analysis accurately finds the erroneous instruction or data transmission stage through a backtracking algorithm, providing a detailed basis for fault-tolerant processing and significantly improving the accuracy and efficiency of error detection.

[0095] The fault tolerance and redundant backup mechanism of the present invention ensures that the system can recover quickly when a fault occurs by synchronizing the status information of the main core and the backup core in real time. If the main core and the backup core fail at the same time, the system will quickly identify the anomaly through the fault detection module and trigger the switching mechanism. At this time, the backup core will resume calculation from the last synchronized state and continue to perform the task to ensure that the system runs without interruption. When the main core performs the task, the redundant backup module uses efficient memory mapping technology to synchronize the core's intermediate calculation state, register value and current value of the program counter to the memory of the backup core every 5ms. The synchronization process uses DMA (Direct Memory Access) transmission to reduce interrupt delay and processing overhead. If an error occurs in the core, the fault detection module uses instruction stream comparison and timestamp mechanism to quickly identify the anomaly and trigger the switching mechanism. After receiving the switching signal, the backup core resumes calculation from the last synchronized data to ensure no interruption. In order to ensure the accuracy of the recovery process, an adaptive error repair algorithm is adopted, which automatically selects a recovery strategy according to the error type. If a memory or data calculation error is detected, the algorithm will initiate a rollback mechanism to restore to the most recent error-free state and continue execution. If it is a hardware failure, it will resume operation by resetting the damaged module or switching to backup hardware.

[0096] The present invention reduces the delay and resource consumption of lock-step execution by optimizing the hardware logic design, and adopts a lightweight hash comparison algorithm to replace the traditional bit-by-bit comparison method. A simplified hash value is generated by the algorithm, and the main core and the backup core are quickly compared by hash values, reducing the computational burden during data verification. The data block is divided into fixed-size fragments, and SHA-256 is used to generate hash values ​​and compare them. Only when the hash values ​​are inconsistent, a more detailed comparison is performed, thereby reducing delays and resource consumption. In order to improve the detection efficiency, a parallel computing architecture is used to perform parallel hash calculations and comparisons on multiple data fragments to accelerate error detection. The system integrates a low-power mode module, adjusts the CPU frequency and voltage according to the real-time load, and uses dynamic voltage and frequency scaling (DVFS) technology to reduce energy consumption, ensuring efficient operation during redundant backup and fault recovery, while minimizing power consumption, and ensuring high reliability and low energy consumption of the system in a complex distribution network environment.

[0097] Reference Figure 3 As indicated, the execution of the fault tolerance and redundant backup mechanism provided by this application includes the following steps:

[0098] Step 21: Task scheduling and allocation.

[0099] The task scheduler uses a priority weighted round-robin algorithm (WRR) to monitor and assign tasks in real time. The scheduler assigns tasks to task queues based on the urgency and computing requirements of the tasks. The task queue then passes the tasks to the task preprocessing module to prepare for task execution. Based on step 22, the preprocessed tasks are assigned to the CPU cores for execution.

[0100] Step 22: Task execution and instruction flow monitoring

[0101] Based on the allocation of task scheduling in step 21, the task execution module will allocate tasks to core 1 and core 2 for execution in parallel. During the execution process, the instruction stream will be transmitted to the error location module in real time for comparison and synchronization monitoring. If there is a difference when the two cores execute the same task, based on step 23, the error location module will immediately detect the inconsistency of the instruction stream and prepare to trigger the fault detection mechanism.

[0102] Step 23: Error detection and triggering fault recovery.

[0103] Based on the result of the instruction stream comparison in step 22, the error location module will compare the core execution results through the timestamp and memory log, and pass the monitoring results to the error detection module. If an abnormality is found, the error detection module will record the error log and trigger the fault recovery module. On this basis, the fault recovery module will start the core switching mechanism and synchronize the data to the backup core through DMA to ensure that the task is not interrupted.

[0104] Step 24: Failure recovery and core switching

[0105] Based on the fault detection in step 23, the fault recovery module will use DMA to synchronize the computing state of the main core to the backup core. After the backup core takes over the task, based on step 25, the system will restore the necessary data to the main core through data redistribution to ensure that the calculation is not affected. At the same time, if the core cannot be recovered, the system will trigger the rollback mechanism to restore to the last error-free state.

[0106] Step 25: Rollback mechanism and hardware reset.

[0107] In step 24, if the backup core fails to take over the task effectively or the system cannot resume normal operation, the rollback mechanism will be activated to restore to the most recent error-free state. If the rollback fails, the fault recovery module will further trigger a hardware reset. At this time, the main core and the backup core will be restored to the initial state through hardware reset, ready to restart computing, ensuring that the system is restored to a healthy, error-free working state.

[0108] Step 26: Recovery process and task priority adjustment

[0109] Based on the hardware recovery in step 25, the scheduler will dynamically adjust the task priority during the system recovery process. The task queue will reschedule the task execution order according to the newly adjusted priority to ensure that the most urgent and critical tasks are processed first. The task execution module will perform necessary task processing during the recovery process to ensure that the system can smoothly transition after the fault is repaired and resume normal operation as soon as possible.

[0110] Reference Figure 4 As shown, the hardware logic optimization process provided by this application includes:

[0111] Step 31: Hardware optimization and data transmission optimization.

[0112] The system reduces processor latency and resource consumption through hardware logic design optimization to ensure efficient hardware resource utilization. The optimized hardware design will directly affect the data transmission efficiency, and then further optimize the bus and cache management through the data transmission optimization module to reduce data access latency and improve the overall system performance. The optimized data transmission will provide a better foundation for cache management and pipeline design.

[0113] Step 32: Cache management and pipeline design.

[0114] Based on the optimization of data transmission in step 31, the cache management module will improve the cache hit rate and reduce data access delay by optimizing the data access strategy. The optimized cache management is closely related to the pipeline design, and the instruction execution efficiency of the system is further improved by reducing the instruction execution cycle. This process provides the necessary hardware support for the parallel processing of subsequent task execution and ensures the efficient operation of the system.

[0115] Step 33: Data block division and parallel hash calculation.

[0116] Based on the optimization of the pipeline design in step 32, the system enters the data processing stage. First, data blocks are generated through the hash comparison algorithm module. These data blocks are divided into fixed sizes and are ready to enter the parallel calculation stage. Then, multiple data fragments are transmitted to the parallel hash calculation module. In this stage, multiple processing units perform hash calculations on the data fragments at the same time, thereby accelerating the calculation process. Based on step 34, multiple parallel calculation results will be centrally compared to ensure data consistency.

[0117] Step 34: Hash comparison and detailed comparison trigger

[0118] In step 33, the hash values ​​of multiple data fragments calculated in parallel will be compared. If the hash values ​​are inconsistent, the fine comparison mechanism will be triggered. This mechanism can compare the data fragments bit by bit to further ensure data consistency and determine subsequent operations based on the comparison results. At this time, the main core and the backup core will perform fine comparison tasks respectively to ensure the reliability of the calculation results.

[0119] Step 35: Redundant execution of the main core and the backup core.

[0120] Based on the results of the detailed comparison in step 34, the main core and the backup core will compare data and synchronize the calculation results as needed. If a difference is found between the calculation results of the main core and the backup core, the system will automatically select a correction path to ensure data accuracy and consistency. The redundant task execution mechanism ensures that when the main core fails, the backup core can continue to process tasks to avoid system crashes.

[0121] Step 36: Power consumption management and dynamic adjustment.

[0122] While ensuring hardware performance, the system also implements dynamic voltage and frequency scaling (DVFS) through the power management module, dynamically adjusting the CPU frequency and voltage during task execution to achieve optimal energy efficiency.

[0123] Step 37: Task execution and load balancing.

[0124] Based on the power management optimization in step 36, the system will enter the task execution phase. In this phase, the task execution module is responsible for processing tasks in parallel and executing them through the main core and the backup core. In order to ensure the system load balance, the computing tasks between the main core and the backup core will be optimized and distributed through the load balancing module. This process ensures that the load of each core is not too heavy, thereby avoiding overload and ensuring stable operation of the system.

[0125] Step 38: Task execution and redundant task processing.

[0126] After load balancing, tasks will be assigned to the primary core and backup core for parallel execution. If a core fails or its processing capacity decreases, the backup core will immediately take over the relevant tasks, thus ensuring that tasks are not interrupted and system operation is not affected. Through the redundant task execution mechanism, the system can ensure that tasks can continue to be processed efficiently in the event of a failure and avoid performance degradation.

[0127] The present invention solves the problems of high-precision synchronization and fault-tolerant processing in traditional systems through dual-core synchronous execution and real-time verification methods. The dual-core CPU and lock-step control module are used to ensure that the execution of two core instructions is completely synchronized. The timestamp comparison module is used to perform periodic verification to timely discover and correct data deviations, thereby improving system stability and reliability. The fault location module accurately tracks the abnormal source to ensure efficient and accurate fault-tolerant processing.

[0128] The priority weighted polling algorithm is introduced in task scheduling to schedule tasks in real time according to the core load, optimizing the use of computing resources. By monitoring the execution cycle and memory access frequency, the scheduler can dynamically adjust task allocation to ensure that high-priority tasks are processed in a timely manner. At the same time, the error location module accurately discovers and locates errors through instruction stream comparison and timestamp tracking, improving fault tolerance.

[0129] In terms of fault tolerance and redundant backup, efficient memory mapping and DMA technology are used to achieve real-time state synchronization between the main and standby cores, ensuring seamless takeover of the standby core in the event of a fault. Combined with an adaptive error repair algorithm, the appropriate recovery strategy is automatically selected to ensure fast recovery. The optimized hash comparison algorithm reduces the computational burden, reduces latency, and accelerates error detection through parallel computing.

[0130] In summary, the method provided by the embodiment of the present application includes: performing clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop; performing synchronization marking on the obtained calculation results and timestamps by executing the same instructions by the first CPU core and the second CPU core; performing data consistency detection on the marked calculation results and timestamps, and then determining whether there are errors. The embodiment of the present application realizes dual-core synchronous execution and real-time verification through a phase-locked loop and real-time comparison, which is conducive to improving detection efficiency and accuracy.

[0131] Secondly, refer to the attached Figure 5 A distribution network monitoring control chip synchronization error detection system proposed according to an embodiment of the present invention is described.

[0132] Figure 5 This is a schematic diagram of the structure of a distribution network monitoring control chip synchronization error detection system according to an embodiment of the present invention. The system specifically includes:

[0133] The first module 510 is used to perform clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop;

[0134] The second module 520 is used to execute the same instruction through the first CPU core and the second CPU core, and synchronously mark the obtained calculation result and the timestamp;

[0135] The third module 530 is used to perform data consistency detection on the marked calculation results and timestamps to determine whether there are errors.

[0136] It can be seen that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0137] Reference Figure 6 The embodiment of the present invention provides a distribution network monitoring control chip synchronization error detection device, comprising:

[0138] at least one processor 410;

[0139] At least one memory 420, used to store at least one program;

[0140] When the at least one program is executed by the at least one processor 410, the at least one processor 410 implements the distribution network monitoring control chip synchronization error detection method.

[0141] Similarly, the contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0142] An embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to execute the above-mentioned distribution network monitoring control chip synchronization error detection method.

[0143] Similarly, the contents of the above method embodiments are all applicable to the present storage medium embodiments. The functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0144] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0145] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0146] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several programs to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0147] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution systems, devices or apparatuses. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution systems, devices or apparatuses.

[0148] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0149] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0150] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0151] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0152] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A method for detecting synchronization errors of a distribution network monitoring control chip, characterized in that: The following steps are involved: Performing clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop; The first CPU core and the second CPU core execute the same instruction, and synchronously mark the obtained calculation result and timestamp; A data consistency check is performed on the marked calculation result and the timestamp to determine whether an error exists.

2. The method for detecting synchronization errors of a distribution network monitoring control chip according to claim 1, characterized in that: The method further comprises: If data inconsistency is detected, the program counter is used to track the instruction stream and the error source is located by comparing with the memory log; The status information of the main core and the backup core are synchronized in real time. If the main core fails, the backup core is switched to resume computing. The main core includes the first CPU core and the second CPU core.

3. The method for detecting synchronization errors of a distribution network monitoring control chip according to claim 2, characterized in that: The real-time synchronization of the status information of the main core and the backup core, and if the main core fails, switching to the backup core to resume computing, includes: If the main core executes the task, the state information of the main core is synchronized to the memory of the standby core through the memory mapping technology; If an error occurs in the main core, the standby core resumes calculation from the state information of the last synchronization after receiving the switching signal.

4. The method for detecting synchronization errors of a distribution network monitoring control chip according to claim 2, characterized in that: The method further comprises: If the source of the error is located as a memory or data calculation error, the standby core starts a rollback mechanism to restore to the most recent error-free state and continue execution; Alternatively, if the source of the location error is a hardware failure, the main core and the backup core resume operation by resetting damaged modules or switching backup hardware.

5. The method for detecting synchronization errors of a distribution network monitoring control chip according to claim 1, characterized in that: The method further comprises: After the data is divided into blocks, a rough comparison is performed using a hash algorithm. If the rough comparison results are inconsistent, a detailed comparison is performed using the main core and the backup core; Adjust CPU frequency and voltage through dynamic voltage and frequency according to real-time load to optimize power consumption; The computing tasks are distributed to the main core and the standby core through load balancing.

6. The method for detecting synchronization errors of a distribution network monitoring control chip according to claim 1, characterized in that: The method further comprises: The task scheduler uses a priority-weighted round-robin algorithm to monitor and assign tasks in real time; Dynamically adjust task priorities during system recovery after a failure.

7. The method for detecting synchronization errors of a distribution network monitoring control chip according to claim 1, characterized in that: The method further comprises: Constructing a dual-core lock-step architecture, the dual-core lock-step architecture includes: The first CPU core and the second CPU core are used to synchronously execute the same instruction stream; A lockstep controller, configured to perform clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop; A synchronization marking module is used to synchronize the obtained calculation results and timestamps; A synchronization comparison module, used for performing data consistency detection on the marked calculation result and the timestamp; A fault location module is used to determine whether an error occurs.

8. A distribution network monitoring control chip synchronization error detection system, characterized in that: include: The first module is used to perform clock synchronization processing on the first CPU core and the second CPU core based on a phase-locked loop; A second module is used for executing the same instruction by the first CPU core and the second CPU core to synchronously mark the obtained calculation result and timestamp; The third module is used to perform data consistency detection on the marked calculation result and the timestamp to determine whether there is an error.

9. A distribution network monitoring control chip synchronization error detection device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the distribution network monitoring control chip synchronization error detection method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The program executable by the processor is used to implement the distribution network monitoring control chip synchronization error detection method as described in any one of claims 1 to 7 when executed by the processor.

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