Exponential addition calculation unit of floating-point number, in-memory calculation array and method

Abstract

The invention relates to an index addition calculation unit, an in-memory calculation array and an in-memory calculation method of a floating-point number, and the index addition calculation unit comprises at least one delay unit which is provided with a high-level end and a low-level end, the delay units are configured to control the delay between the input signal and the output signal according to the level difference between the high level end and the low level end, and the delay between the input signal and the output signal of each delay unit is used for representing the addition result of the single-bit weight index signal and the input index signal; the output signal of the previous time delay unit is the input signal of the next time delay unit; the high-level gating unit is used for accessing a single-bit weight index signal; and the low-level gating unit is used for accessing a single-bit input index signal. The index addition calculation unit of the floating-point number is simple in structure, and the problem that a circuit structure of an existing index addition calculation unit is large in chip area occupation is solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and particularly to an exponent addition calculation unit for floating-point numbers, an in-memory computing array, and a circuit. Background Art

[0002] Advanced artificial intelligence edge devices are expected to support floating-point (FP) multiplication and accumulation operations while ensuring high energy efficiency and high inference accuracy. Floating-point operations mainly include processes such as exponent addition for floating-point multiplication, maximum exponent EMAX search, and shift signal generation. Among them, exponent addition for floating-point multiplication refers to adding a target exponent and a weight exponent, both of which are multi-bit data. Each single-bit data of the weight exponent is stored in each storage unit (forming a storage array, and each column of storage units corresponds to an exponent addition calculation unit). The single-bit data at the same position in the weight exponent and the target exponent are added, and the addition process of the two single-bit data is performed in the corresponding exponent addition calculation unit. Currently, the circuit structure of the exponent addition calculation unit uses a relatively large number of field-effect transistors, resulting in a high chip area occupancy. At the same time, processes such as maximum exponent EMAX search and shift signal generation are also implemented using relatively complex circuit structures, which also have a high chip area occupancy.

[0003] Regarding the problem that the current circuit structure of the exponent addition calculation unit has a high chip area occupancy, no effective solution has been proposed yet. Summary of the Invention

[0004] In the present invention, an exponent addition calculation unit for floating-point numbers, an in-memory computing array, and a circuit are provided to solve the problem that the current circuit structure of the exponent addition calculation unit has a high chip area occupancy.

[0005] In a first aspect, the present invention provides an exponent addition calculation unit for floating-point numbers, which is used to add a single-bit weight exponent signal and an input exponent signal, and includes:

[0006] At least one delay unit. The delay unit has a high-level terminal and a low-level terminal, and the delay unit is configured to: control the delay between the input signal and the output signal according to the voltage difference between the high-level terminal and the low-level terminal. The input signal and the output signal of the delay unit are both rising-edge signals, and the delay between the input signal and the output signal of the delay unit is used to represent the addition result of the single-bit weight exponent signal and the input exponent signal. When there are multiple delay units, the output signal of the previous delay unit is the input signal of the next delay unit;

[0007] A high-level gating unit for accessing a single-bit weight exponent signal, the high-level gating unit being configured to: provide a first high level to the high-level terminal of the delay unit when the single-bit weight exponent signal is 1, and provide a second high level to the high-level terminal of the delay unit when the single-bit weight exponent signal is 0;

[0008] A low-level gating unit for accessing a single-bit input exponent signal, the low-level gating unit being configured to: provide a first low level to the low-level terminal of the delay unit when the single-bit input exponent signal is 1, and provide a second low level to the low-level terminal of the delay unit when the single-bit input exponent signal is 0.

[0009] In a second aspect, a floating-point exponent addition calculation array is provided in the present invention for adding a multi-bit weight exponent signal and an input exponent signal, including:

[0010] A multi-bit weight exponent storage array, which includes multiple columns of storage units, and the multiple columns of storage units respectively store single-bit weight exponent signals of different bits in the multi-bit weight exponent signal;

[0011] Multiple exponent addition calculation units corresponding one-to-one to the multiple columns of storage units, the exponent addition calculation units being the floating-point exponent addition calculation units described in the first aspect, the output terminals of each column of storage units are connected to the high-level gating units in the corresponding exponent addition calculation units, and the low-level gating units in the multiple exponent addition calculation units are respectively used to access the single-bit input weight exponent signals of the corresponding bits in the multi-bit input exponent signal;

[0012] Wherein, in the order from the low bit to the high bit of the multi-bit weight exponent signal, the output of the previous exponent addition calculation unit is the input of the next exponent addition calculation unit.

[0013] In a third aspect, a floating-point exponent addition calculation method is provided in the present invention, including:

[0014] Respectively adding different multi-bit weight exponent signals and input exponent signals through the floating-point exponent addition calculation array described in the second aspect to obtain respective delay signals, the delay signals representing the delay between the input signal and the output signal of the exponent addition calculation array, the input signal of the exponent addition calculation array being the input signal of the first delay unit of the lowest-bit exponent addition calculation unit, and the output signal of the exponent addition calculation array being the output signal of the last delay unit of the highest-bit exponent addition calculation unit;

[0015] Taking the delay signal representing the largest value as the target delay signal, and respectively obtaining respective difference signals by subtracting each other delay signal from the target delay signal through an exclusive-OR gate;

[0016] The respective difference signals are respectively input into a ten-bit ring counter, and shift signals of respective other delay signals relative to the target delay signal are obtained through the ten-bit ring counter;

[0017] The target delay signal, the respective other delay signals and their corresponding shift signals are input into an adder.

[0018] In a fourth aspect, a static random access memory is provided in the present invention, and an adder calculation of a multi-bit weight exponent signal and an input exponent signal is implemented by using the exponent addition calculation array of the floating-point number described in the second aspect.

[0019] Compared with the related art, the present invention provides that an exponent addition calculation unit of a floating-point number can represent an addition result between a single-bit weight exponent signal and an input exponent signal through a delay, and can represent an addition result between a multi-bit weight exponent signal and an input exponent signal through an accumulated delay. More importantly, the structure of the above exponent addition calculation unit of the floating-point number is relatively simple, and solves the problem that the circuit structure of the current exponent addition calculation unit occupies a relatively large chip area.

[0020] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more concise and understandable. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a structural diagram of an exponent addition calculation unit of a floating-point number provided in some embodiments of the present invention;

[0022] Figure 2 is a structural diagram of an exponent addition calculation unit of a floating-point number provided in other embodiments of the present invention;

[0023] Figure 3 is a structural diagram of an exponent addition calculation unit of a floating-point number provided in an embodiment of the present invention;

[0024] Figure 4 is a structural diagram of an exponent addition calculation unit of a floating-point number provided in another embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of an exponent addition calculation array of a floating-point number provided in an embodiment of the present invention;

[0026] Figure 6 is a diagram of groups of delay signals output by an exponent addition calculation array in an embodiment of the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] For a clearer understanding of the purpose, technical solution, and advantages of the present application, the present application will be described and illustrated below with reference to the drawings and embodiments.

[0028] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by those of ordinary skill in the technical field to which this application belongs. In this application, words such as "a", "an", "one kind", "the", "these", etc. do not indicate a limitation in quantity and can be singular or plural. The terms "including", "comprising", "having" and any variants thereof used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The terms "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" used in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. used in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0029] In an embodiment of the present invention, an exponent addition calculation unit for floating-point numbers is provided, which is used to add a single-bit weight exponent signal and an input exponent signal.

[0030] Figure 1 is a structural diagram of the exponent addition calculation unit for floating-point numbers provided in some embodiments of the present invention. Figure 2 is a structural diagram of the exponent addition calculation unit for floating-point numbers provided in other embodiments of the present invention.

[0031] Referring to Figure 1 and Figure 2 , the exponent addition calculation unit for floating-point numbers includes: at least one delay unit, a high-level gating unit for accessing the single-bit weight exponent signal, and a low-level gating unit for accessing the single-bit input exponent signal.

[0032] The delay unit has a high-level terminal and a low-level terminal, and the delay unit is configured to: control the delay between the input signal EIN and the output signal EOUT according to the level difference between the high-level terminal and the low-level terminal. Both the input signal EIN and the output signal EOUT of the delay unit are rising-edge signals. The delay between the input signal EIN and the output signal EOUT of the delay unit is used to represent the addition result of the single-bit weight index signal and the input index signal. When there are multiple delay units, the output signal of the previous delay unit is the input signal of the next delay unit; the high-level gating unit is configured to: provide a first high level to the high-level terminal of the delay unit when the single-bit weight index signal is 1, and provide a second high level to the high-level terminal of the delay unit when the single-bit weight index signal is 0; the low-level gating unit is configured to: provide a first low level to the low-level terminal of the delay unit when the single-bit input index signal is 1, and provide a second low level to the low-level terminal of the delay unit when the single-bit input index signal is 0.

[0033] In this embodiment, the exponent addition calculation unit of the floating-point number is only composed of a delay unit, a high-level gating unit, and a low-level gating unit, and its structure is relatively simple. And the exponent addition calculation unit of the floating-point number represents the exponent addition calculation result of the floating-point number through the delay between the input signal and the output signal of the delay unit.

[0034] The principle is that when the weight exponent signal of a single bit is different from the input exponent signal, there is a different potential difference between the high-level end and the low-level end of the delay unit. As a result, the delay unit has different delay effects, and thus the delay between the input signal and the output signal of the delay unit can represent the result of exponential addition calculation. Specifically, when the weight exponent signal is 1 and the input exponent signal is 1, the levels of the high-level end and the low-level end of the delay unit are the first high level and the first low level respectively; when the weight exponent signal is 1 and the input exponent signal is 0, the levels of the high-level end and the low-level end of the delay unit are the first high level and the second low level respectively; when the weight exponent signal is 0 and the input exponent signal is 1, the levels of the high-level end and the low-level end of the delay unit are the second high level and the first low level respectively; when the weight exponent signal is 0 and the input exponent signal is 0, the levels of the high-level end and the low-level end of the delay unit are the second high level and the second low level respectively. Therefore, by setting the first high level, the first low level, the second high level and the second low level, the delay unit can generate different arithmetic delays. Exemplarily, when the levels of the high-level end and the low-level end of the delay unit are the second high level and the second low level respectively, the delay generated by the delay unit is t; when the levels of the high-level end and the low-level end of the delay unit are the second high level and the first low level or the first high level and the second low level respectively, the delay generated by the delay unit is t + a; when the levels of the high-level end and the low-level end of the delay unit are the first high level and the first low level respectively, the delay generated by the delay unit is t + 2a. At this time, it can be defined that the addition result is 0 when the delay generated by the delay unit is t. Comparing other delays with t, if the delay increases by a, the addition result increases by 1. From the above description, it can be seen that when the calculation results of single-bit data differ by 1, the delay unit generates a unit delay difference. Further, in order to enable the delay unit to generate different arithmetic delays, the specific values of the first high level, the first low level, the second high level and the second low level can be determined through simulation software.

[0035] Further, a single exponential addition calculation unit is used to add the weight exponent signal of a single bit and the input exponent signal. In actual calculations, it is often the weight exponent signal and the input exponent signal of multiple bits that are added. At this time, multiple exponential addition calculation units can be used to add the signals of different bits in the multiple-bit data respectively, and the delays generated by multiple delay units are accumulated (the output of the previous exponential addition calculation unit is used as the input of the next exponential addition calculation unit), and the total delay is used to represent the addition result of the multiple-bit data.

[0036] Among them, in the multiple-bit data, the weights of the single-bit data of different bits are different, and different multiples of delay differences can be realized by multiplexing the delay unit.

[0037] Exemplarily, in multi-bit data (from low bit to high bit): the weight of the single-bit data of the first bit is 1, that is, the single-bit data 1 represents the value 1. Then, an exponential addition calculation unit with only one delay unit can be used for calculation. At this time, when the calculation result of this single-bit data differs by 1, the exponential addition calculation unit generates a unit delay difference. The weight of the single-bit data of the second bit is 2, that is, the single-bit data 1 represents the value 2. Then, an exponential addition calculation unit with two delay units can be used for calculation. At this time, when the calculation result of this single-bit data differs by 1 (the actual value differs by 2), each delay unit generates a unit delay difference, and the exponential addition calculation unit generates two unit delay differences. And so on, the single-bit data of the third bit is calculated by an exponential addition calculation unit with four delay units. At this time, when the calculation result of this single-bit data differs by 1 (the actual value differs by 4), the exponential addition calculation unit generates four unit delay differences. To sum up, for the total delay, a difference of one unit delay indicates that the actual value differs by 1. At this time, the total delay corresponding to adding all 0s or adding all 1s can be used as a reference to judge the delay difference between other total delays and this reference delay, so as to determine the specific calculation value represented by other total delays.

[0038] Correspondingly, while keeping the same number of delay units, different multiples of delay differences can also be achieved by adjusting the first high level, the second high level, the first low level, and the second low level. Continuing with the previous example, in an exponential addition calculation unit with one delay unit, when the levels of the high-level end and the low-level end of the delay unit are the second high level and the second low level respectively, the delay generated by the delay unit is t. When the levels of the high-level end and the low-level end of the delay unit are the second high level and the first low level respectively, or are the first high level and the second low level respectively, the delay generated by the delay unit is t + a. When the levels of the high-level end and the low-level end of the delay unit are the first high level and the first low level respectively, the delay generated by the delay unit is t + 2a. By adjusting the first high level and the first low level, when the levels of the high-level end and the low-level end of the delay unit are the second high level and the first low level respectively, or are the first high level and the second low level respectively, the delay generated by the delay unit can be made t + 2a. When the levels of the high-level end and the low-level end of the delay unit are the first high level and the first low level respectively, the delay generated by the delay unit is t + 4a. Similarly, when the addition result of the single-bit data differs by 1, the delay difference generated by the exponential addition calculation unit can be doubled, so as to represent the addition result of the single-bit data of the higher bit. Correspondingly, the adjustment of each level can still be determined by simulation.

[0039] As can be seen from the above description, the present invention provides that the exponent addition calculation unit of floating-point numbers can represent the addition result between the weighted exponent signal of a single bit and the input exponent signal through delay, and can represent the addition result between the weighted exponent signal of multiple bits and the input exponent signal through cumulative delay. More importantly, the structure of the above-mentioned exponent addition calculation unit of floating-point numbers is relatively simple, and the current circuit structure of the exponent addition calculation unit has a problem of high chip area occupation.

[0040] In some of these embodiments, the delay between the input signal and the output signal of the delay unit is negatively correlated with the voltage difference between the high-level terminal and the low-level terminal; the first high level is higher than the second high level, and the first low level is lower than the second low level; the addition result of the weighted exponent of a single bit and the input exponent is negatively correlated with the delay between the input signal and the output signal of the delay unit.

[0041] Specifically, when the weighted exponent signal is 1 and the input exponent signal is 1, the voltages of the high-level terminal and the low-level terminal of the delay unit are the first high level and the first low level respectively. At this time, the voltage difference is the largest, and the delay generated by the delay unit is the smallest; when the weighted exponent signal is 1 and the input exponent signal is 0, the voltages of the high-level terminal and the low-level terminal of the delay unit are the first high level and the second low level respectively, and the delay generated by the delay unit is in the middle; when the weighted exponent signal is 0 and the input exponent signal is 1, the voltages of the high-level terminal and the low-level terminal of the delay unit are the second high level and the first low level respectively, and the delay generated by the delay unit is in the middle; when the weighted exponent signal is 0 and the input exponent signal is 0, the voltages of the high-level terminal and the low-level terminal of the delay unit are the second high level and the second low level respectively, and the delay generated by the delay unit is the largest. At this time, the minimum delay can be used as a reference. At this time, the addition calculation result of this single-bit data is 2, that is, binary 10. When the delay increases by one unit delay, the addition calculation result of this single-bit data decreases by 1. In the addition calculation of multi-bit data, the minimum total delay can also be used as a reference. The minimum total delay represents the addition calculation result of two multi-bit data with all 1s. When the total delay increases by one unit delay, the addition calculation result of this multi-bit data decreases by 1.

[0042] To implement the addition calculation of single-bit data in the above embodiments, the delay unit, the high-level gating unit, and the low-level gating unit can adopt the following specific structures.

[0043] Figure 3 is the structural diagram of the exponent addition calculation unit of floating-point numbers provided in an embodiment of the present invention. Figure 4 is the structural diagram of the exponent addition calculation unit of floating-point numbers provided in another embodiment of the present invention.

[0044] Refer to Figure 3 and Figure 4, in a specific embodiment, each delay unit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a fourth NMOS transistor N4; the gates of the first PMOS transistor P1 and the first NMOS transistor N1 are connected to form the input end of the delay unit, the source of the first PMOS transistor P1 is connected to the power supply, the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, and the gate of the second PMOS transistor P2 are connected, the source of the first NMOS transistor N1 forms the low-level end of the delay unit, the source of the second PMOS transistor P2 forms the high-level end of the delay unit, the drain of the second PMOS transistor P2 and the drain of the fourth NMOS transistor N4 are connected to form the output end of the delay unit, and the gate and source of the fourth NMOS transistor N4 are respectively connected to the reset signal Rst and ground.

[0045] The low-level gating unit includes a second NMOS transistor N2 and a third NMOS transistor N3; the drains of the second NMOS transistor N2 and the third NMOS transistor N3 are both connected to the low-level end of the delay unit, the gate of the second NMOS transistor N2 is used to receive the inverted signal of the single-bit input exponent signal IN, the gate of the third NMOS transistor N3 is used to receive the single-bit input exponent signal IN, the source of the second NMOS transistor N2 is used to receive the second low level VN, the source of the third NMOS transistor N3 is grounded, and the first low level is the ground level.

[0046] The high-level gating unit includes a third PMOS transistor P3 and a fourth PMOS transistor P4; the drains of the third PMOS transistor P3 and the fourth PMOS transistor P4 are both connected to the high-level end of the delay unit, the gate of the third PMOS transistor P3 is used to receive the single-bit weight exponent signal W, the gate of the fourth NMOS transistor N4 is used to receive the inverted signal of the single-bit weight exponent signal W, the source of the third PMOS transistor P3 is used to receive the second high level VP, the source of the fourth NMOS transistor N4 is connected to the power supply, and the first high level is the power supply level.

[0047] First, a rising-edge signal EIN is input from the gates of N1 and P1. When EIN is at a low level, N1 is turned off and P1 is turned on, and the drains of N1 and P1 are at a high level. When EIN jumps to a high level, P1 is turned off and N1 is turned on, and the drains of N1 and P1 discharge from the high level through N1 and become low level. Among them, the magnitude of the discharge current is proportional to the gate-source voltage of N1. By the value of the input exponent, the source voltage of N1 is controlled to change the delay of N1 pulling down. Similarly, for the subsequent operations of P2 and N4, the output EOUT is still a rising-edge signal, and this signal is used as the EIN for the next-bit exponent addition operation.

[0048] When performing exponential addition operations using the exponential calculation unit, the IN exponent is input through N2 and N3, the W exponent is input through P3 and P4, and the source voltages of N1 and P2 are controlled by the values of IN and W, thereby changing the charge and discharge times of N1 and P2, and further affecting the delay between EIN and OUT, so as to represent different exponential sums and magnitudes.

[0049] Exemplarily, there are four cases for controlling the source voltages of N1 and P2 by the values of IN and W: when IN = 0 and W = 0, N2 and P3 are turned on, N3 and P4 are turned off, Va = VN0, Vb = VP0, and the circuit charges and discharges through N2 and P3, with the minimum current and the slowest speed, and the delay between EIN and OUT is t0 + 2△t; when IN = 0 and W = 1, N2 and P4 are turned on, N3 and P3 are turned off, Va = VN0, Vb = VDD, and the circuit charges and discharges through N2 and P3, with the current magnitude being medium and the speed being medium, and the delay between EIN and OUT is t0 + △t; when IN = 1 and W = 0, N3 and P3 are turned on, N2 and P4 are turned off, Va = VSS, Vb = VP0, and the circuit charges and discharges through N3 and P3, with the current magnitude being medium and the speed being medium, and the delay between EIN and OUT is t0 + △t; when IN = 1 and W = 1, N3 and P4 are turned on, N2 and P3 are turned off, Va = VDD, Vb = VSS, and the circuit charges and discharges through N3 and P3, with the maximum current and the fastest speed, and the delay between EIN and OUT is t0.

[0050] The exponential addition calculation unit for floating-point numbers provided by the present invention can implement the addition operation of a single-bit weighted exponent signal and an input exponent signal. By combining multiple exponential addition calculation units and connecting them to the storage array, the addition operation of a single-bit weighted exponent signal and an input exponent signal can be implemented.

[0051] Figure 5 It is a schematic diagram of the exponential addition calculation array for floating-point numbers provided in the embodiments of the present invention. Refer to Figure 5 In the embodiments of the present invention, an exponential addition calculation array for floating-point numbers is further provided, which is used to add multi-bit weighted exponent signals and input exponent signals, and includes a multi-bit weighted exponent storage array and a plurality of exponential addition calculation units corresponding one-to-one to multiple columns of storage units.

[0052] The multi-bit weight exponent storage array includes multiple columns of storage units, and the multiple columns of storage units respectively store single-bit weight exponent signals of different bits in the multi-bit weight exponent signal; the exponent addition calculation unit is the exponent addition calculation unit for floating-point numbers provided in the present invention. The output end of each column of storage units is connected to the high-level gating unit in the corresponding exponent addition calculation unit, and the low-level gating units in multiple exponent addition calculation units are respectively used to access the single-bit input weight exponent signals of the corresponding bits in the multi-bit input exponent signal; wherein, in the order from the low bit to the high bit of the multi-bit weight exponent signal, the output signal of the previous exponent addition calculation unit is the input signal of the next exponent addition calculation unit.

[0053] Among them, in multi-bit data, the weights of single-bit data of different bits are different, and different multiples of delay differences can be realized by multiplexing delay units.

[0054] In some of the embodiments, in the order from the low bit to the high bit of the multi-bit weight exponent signal: the number of delay units in each exponent addition calculation unit is twice the number of delay units in its previous exponent addition calculation unit, and each delay unit has the same combination of a first high level, a second high level, a first low level, and a second low level.

[0055] Exemplarily, in multi-bit data (from low bit to high bit): the weight of the single-bit data in the first bit is 1, that is, the single-bit data 1 represents the value 1. Then, an exponent addition calculation unit with only one delay unit can be used for calculation. At this time, when the calculation result of this single-bit data differs by 1, this exponent addition calculation unit generates a unit delay difference; the weight of the single-bit data in the second bit is 2, that is, the single-bit data 1 represents the value 2. Then, an exponent addition calculation unit with two delay units can be used for calculation. At this time, when the calculation result of this single-bit data differs by 1 (the actual value differs by 2), each delay unit generates a unit delay difference, and this exponent addition calculation unit generates two unit delay differences; and so on. The single-bit data in the third bit is calculated by an exponent addition calculation unit with four delay units. At this time, when the calculation result of this single-bit data differs by 1 (the actual value differs by 4), this exponent addition calculation unit generates four unit delay differences. To sum up, for the total delay, a difference of one unit delay indicates that the actual value differs by 1. At this time, the total delay corresponding to adding all 0s or adding all 1s can be used as a reference to judge the delay difference between other total delays and this reference delay, so as to determine the specific calculation value represented by other total delays.

[0056] Correspondingly, while maintaining the same number of delay units, different multiples of delay differences can also be achieved by adjusting the first high level, the second high level, the first low level, and the second low level.

[0057] In some other embodiments, in the order from the low bit to the high bit of the weight exponent signal of multiple bits: the first and second exponent addition calculation units each have a delay unit, and the delay units of the two-bit exponent addition calculation unit have different combinations of a first high level, a second high level, a first low level, and a second low level; the number of delay units of each exponent addition calculation unit after the third bit is twice the number of delay units of its previous exponent addition calculation unit, and each delay unit has the same combination of a first high level, a second high level, a first low level, and a second low level as the delay unit of the second exponent addition calculation unit.

[0058] Continuing with the previous example, in the exponent addition calculation unit with one delay unit, when the levels of the high-level end and the low-level end of the delay unit are the second high level and the second low level respectively, the delay generated by the delay unit is t; when the levels of the high-level end and the low-level end of the delay unit are the second high level and the first low level respectively or are the first high level and the second low level respectively, the delay generated by the delay unit is t + a; when the levels of the high-level end and the low-level end of the delay unit are the first high level and the first low level respectively, the delay generated by the delay unit is t + 2a. By adjusting the first high level and the first low level, it can be made that when the levels of the high-level end and the low-level end of the delay unit are the second high level and the first low level respectively or are the first high level and the second low level respectively, the delay generated by the delay unit is t + 2a; when the levels of the high-level end and the low-level end of the delay unit are the first high level and the first low level respectively, the delay generated by the delay unit is t + 4a. Similarly, when the addition results of single-bit data differ by 1, the delay difference generated by the exponent addition calculation unit doubles, thereby representing the addition result of a higher-order single-bit data. Correspondingly, the adjustment of each level can still be determined through simulation.

[0059] In an embodiment of the present invention, a method for adding exponents of floating-point numbers is further provided, including step S110, step S120, step S130, and step S140.

[0060] In step S110, the floating-point number exponent addition calculation array provided by the present invention is used to add different multiple-bit weight exponent signals and input exponent signals respectively to obtain respective delay signals. The delay signals represent the delay between the input signal and the output signal of the exponent addition calculation array. The input signal of the exponent addition calculation array is the input signal of the first delay unit of the lowest-bit exponent addition calculation unit, and the output signal of the exponent addition calculation array is the output signal of the last delay unit of the highest-bit exponent addition calculation unit.

[0061] Step S120: Take the delay signal with the largest represented value as the target delay signal, and use an exclusive-OR gate to subtract each of the other delay signals from the target delay signal to obtain respective difference signals.

[0062] Step S130: Input each of the difference signals into a ten-bit ring counter, and use the ten-bit ring counter to obtain respective shift signals of each of the other delay signals relative to the target delay signal.

[0063] Step S140: Input the target delay signal, each of the other delay signals, and their corresponding shift signals into an adder.

[0064] Figure 6 It is a diagram of groups of delay signals output by the exponential addition calculation array in an embodiment of the invention. Exemplarily, as Figure 6 shown, according to the values of IN and W: IN0 = 00010, W0 = 01000; IN1 = 00110, W1 = 01100; IN2 = 00110, W2 = 01000; IN3 = 00001, W3 = 00011; calculate 4 groups of exponential sums (delay signals output by the exponential addition calculation array) E0 = 10, E1 = 18, E2 = 14, E3 = 4, where the exponential sum E1 (target delay signal) rises first and is the exponential maximum value EMAX. Then, use an exclusive-OR gate to subtract EMAX and the other exponential sums to obtain a pulse width signal (difference signal) related to the difference. The difference between EMAX (E1) and E0 is 8Δt, the difference between EMAX (E1) and E2 is 4Δt, and the difference between EMAX (E1) and E3 is 14Δt.

[0065] As Figure 6 shown, input the pulse width signal related to the difference obtained in the previous step into a ten-bit ring counter to obtain a shift signal; for the exponential sum E0, only Q7 in Q[9:0] is 1, and the rest are 0. For the exponential sum E2, only Q3 in Q[9:0] is 1, and the rest are 0. For the exponential sum E3, the signal width obtained by subtracting it from EMAX is greater than 10Δt, indicating that its exponential sum is too small and will not be sent to the adder, and Q[9:0] are all 0.

[0066] In an embodiment of the present invention, a static random access memory is further provided, which uses the exponential addition calculation array of floating-point numbers provided by the present invention to implement the addition calculation of multi-bit weight exponential signals and input exponential signals.

[0067] It should be understood that the specific embodiments described here are only used to explain this application, rather than to limit it. According to the embodiments provided in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0068] Obviously, the accompanying drawings are only some examples or embodiments of the present application. For those of ordinary skill in the art, the present application can also be applied to other similar situations based on these drawings without creative efforts. Additionally, it can be understood that although the work done during the development process here may be complex and time-consuming, for those of ordinary skill in the art, certain design, manufacturing, or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be regarded as insufficient disclosure of the present application.

Claims

1. A floating point exponential addition calculation unit, used for adding a single-bit weight exponential signal and an input exponential signal, characterized in that: include: At least one delay unit, the delay unit has a high level end and a low level end, the delay unit is configured to: control the delay between the input signal and the output signal according to the level difference between the high level end and the low level end, the input signal and the output signal of the delay unit are both rising edge signals, the delay between the input signal and the output signal of the delay unit is used to characterize the addition result of the single-bit weight index signal and the input index signal, and when there are multiple delay units, the output signal of the previous delay unit is the input signal of the next delay unit; A high-level gating unit for accessing a single-bit weight index signal, the high-level gating unit being configured to: provide a first high level to the high-level end of the delay unit when the single-bit weight index signal is 1, and provide a second high level to the high-level end of the delay unit when the single-bit weight index signal is 0; A low-level gating unit for accessing a single-bit input index signal, the low-level gating unit is configured to: provide a first low level to the low-level end of the delay unit when the single-bit input index signal is 1, and provide a second low level to the low-level end of the delay unit when the single-bit input index signal is 0.

2. The exponential addition calculation unit of floating point numbers according to claim 1, characterized in that: The delay between the input signal and the output signal of the delay unit is negatively correlated with the level difference between the high level end and the low level end; The first high level is higher than the second high level, and the first low level is lower than the second low level; The sum of the single-bit weight index and the input index is negatively correlated with the delay between the input signal and the output signal of the delay unit.

3. The exponential addition calculation unit of floating point numbers according to claim 2, characterized in that: Each delay unit includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a fourth NMOS tube; The gate of the first PMOS tube and the gate of the first NMOS tube are connected and constitute the input end of the delay unit, the source of the first PMOS tube is connected to the power supply, the drain of the first PMOS tube, the drain of the first NMOS tube and the gate of the second PMOS tube are connected, the source of the first NMOS tube constitutes the low level end of the delay unit, the source of the second PMOS tube constitutes the high level end of the delay unit, the drain of the second PMOS tube and the drain of the fourth NMOS tube are connected and constitute the output end of the delay unit, and the gate and source of the fourth NMOS tube are respectively connected to the reset signal and the ground.

4. The exponential addition calculation unit of floating point numbers according to claim 2, characterized in that: The low level gating unit includes a second NMOS tube and a third NMOS tube; The drain of the second NMOS tube and the drain of the third NMOS tube are both connected to the low level end of the delay unit, the gate of the second NMOS tube is used to access the inverse signal of the single-bit input exponential signal, the gate of the third NMOS tube is used to access the single-bit input exponential signal, the source of the second NMOS tube is used to access the second low level, the source of the third NMOS tube is grounded, and the first low level is the ground level.

5. The exponential addition calculation unit of floating point numbers according to claim 2, characterized in that: The high level gating unit includes a third PMOS tube and a fourth PMOS tube; The drain of the third PMOS tube and the drain of the fourth PMOS tube are both connected to the high level end of the delay unit, the gate of the third PMOS tube is used to access the single-bit weight index signal, the gate of the fourth NMOS tube is used to access the inverse signal of the single-bit weight index signal, the source of the third PMOS tube is used to access the second high level, the source of the fourth NMOS tube is connected to the power supply, and the first high level is the power supply level.

6. A floating point exponential addition calculation array for adding a multi-bit weight exponential signal and an input exponential signal, characterized in that: include: A multi-bit weight index storage array, comprising a plurality of columns of storage units, wherein the plurality of columns of storage units respectively store single-bit weight index signals of different digits in the multi-bit weight index signal; A plurality of exponential addition calculation units corresponding one to one with the plurality of columns of storage units, the exponential addition calculation units being exponential addition calculation units of floating-point numbers as described in any one of claims 1 to 5, the output end of each column of storage units being connected to a high-level gating unit in the corresponding exponential addition calculation unit, and the low-level gating units in the plurality of exponential addition calculation units being respectively used to access single-bit input weight exponent signals of corresponding bits in a multi-bit input exponent signal; Among them, according to the order from low to high bits of the multi-bit weight index signal, the output of the previous exponential addition calculation unit is the input of the next exponential addition calculation unit.

7. The exponential addition calculation array of floating point numbers according to claim 6, characterized in that: In order from low to high bits of the multi-bit weight index signal: The first-bit and second-bit exponential addition calculation units have a delay unit, and the delay unit of the two-bit exponential addition calculation unit has different combinations of the first high level, the second high level, the first low level, and the second low level; The number of delay units of each exponential addition calculation unit after the third digit is twice the number of delay units of the exponential addition calculation unit before it, and each delay unit has the same combination of the first high level, the second high level, the first low level and the second low level as the delay unit of the second exponential addition calculation unit.

8. The exponential addition calculation array of floating point numbers according to claim 6, characterized in that: In order from low to high bits of the multi-bit weight index signal: The number of delay units of each exponential addition calculation unit is twice the number of delay units of the previous exponential addition calculation unit, and each delay unit has the same combination of the first high level, the second high level, the first low level and the second low level.

9. A method for calculating exponential addition of floating point numbers, characterized in that: include: The exponential addition calculation array of floating-point numbers described in any one of claims 6 to 8 is used to respectively add different multi-bit weight exponent signals and input exponent signals to obtain respective delay signals, wherein the delay signal represents the delay between the input signal and the output signal of the exponential addition calculation array, the input signal of the exponential addition calculation array is the input signal of the first delay unit of the lowest-order exponential addition calculation unit, and the output signal of the exponential addition calculation array is the output signal of the last delay unit of the highest-order exponential addition calculation unit; The delay signal with the largest characteristic value is used as the target delay signal, and each other delay signal is subtracted from the target delay signal through an XOR gate to obtain each difference signal; Input each difference signal into a ten-bit ring counter respectively, and obtain a shift signal of each other delay signal relative to the target delay signal through the ten-bit ring counter respectively; The target delayed signal, each other delayed signal and its corresponding shifted signal are input into the adder.

10. A static random access memory, characterized in that: The exponential addition calculation array of floating-point numbers described in any one of requirements 6-8 is used to implement the addition calculation of multi-bit weight exponential signals and input exponential signals.

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