Visual multi-chip evaluation integration method and device

Abstract

The invention provides a visual multi-element chip evaluation integration method and device, and belongs to the field of chip evaluation.The method comprises the steps that a unified data model and an operation interface are constructed, and after chip performance evaluation, the data model and the operation interface are established; chip information, evaluation environment information, test case information, evaluation task information and a chip performance evaluation result are integrated, stored and managed; in combination with basic information input by a user front end, automatically analyzing evaluation log data generated by each test case by using a log analysis tool, and extracting related indexes according to the type of each test case; and performing visual display on a chip performance evaluation result, and performing intelligent analysis on data comparison information between evaluation tasks and operator result information generated by the evaluation tasks. According to the technical scheme, the chip evaluation efficiency and speed are improved, and the visualization processing and display capability is improved.

Description

Technical Field

[0001] The present application relates to the field of chip evaluation, and in particular to a visualized multi-element chip evaluation integrated method and device. Background Art

[0002] With the rapid development of chip technology, various types of AI chips have appeared on the market, and their performance evaluation and test data collection have gradually become important links in product development, optimization, and decision-making. However, traditional chip evaluation devices are mostly single evaluation devices, and they mainly have the following problems:

[0003] In terms of evaluation data management, many evaluation devices store data in a decentralized manner in the form of files or local storage, lacking unified data management. Evaluation data is usually scattered across different hardware platforms, operating systems, and evaluation tools, making it difficult to achieve cross-platform data integration and comparative analysis.

[0004] In terms of log analysis and processing, traditional evaluation devices usually rely on manual log analysis and result extraction. Users need to manually extract performance data and indicators from logs, which is cumbersome and error-prone, and cannot achieve efficient data persistence and subsequent analysis.

[0005] In terms of data visualization tools, although some multi-chip evaluation integration and visualization platforms have data visualization functions, in most cases they are limited to simple result display. There is a lack of in-depth analysis and refined visualization of complex evaluation results, and it is impossible to intuitively display the performance differences and optimization space of different chips and different configurations. Summary of the invention

[0006] The purpose of this application is to provide a visualized multi-chip evaluation integrated method and device, aiming to achieve integrated evaluation and real-time visualization of data supporting multi-chips.

[0007] According to a first aspect of the present application, a visual multi-element chip evaluation integration method is provided, comprising:

[0008] By building a unified data model and operation interface, after chip performance evaluation, chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results are integrated, stored and managed;

[0009] Combined with the basic information input by the user front end, the log analysis tool is used to automatically parse the evaluation log data generated by each test case, and relevant indicators are extracted according to the type of each test case;

[0010] The chip performance evaluation results are displayed visually, and the data comparison information between evaluation tasks and the operator result information of the evaluation tasks are intelligently analyzed.

[0011] In an optional implementation manner, the integration, storage and management of chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results further includes:

[0012] The chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation result data structure are defined by Django model, wherein:

[0013] The chip information is used to store basic data related to the chip, including video memory capacity, video memory bandwidth and computing power indicators, as well as chip interconnection information;

[0014] The evaluation environment information is used to store server hardware and software related information, including IP address, operating system version and chip model;

[0015] The test case information is used to describe the specific content of the test task, including the name, description, category and framework used;

[0016] The evaluation task information is used to record the detailed information of each evaluation task, including the chip to be evaluated, the evaluation executor, the evaluation status and time; each evaluation task is associated with multiple test cases and corresponding evaluation results;

[0017] The chip performance evaluation results are used to store the result data after each test case is executed.

[0018] In an optional implementation manner, the integration, storage and management of chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results further includes:

[0019] The Django REST Framework is used to implement the operation interface of the data model to complete data creation, deletion, update and read operations. In the creation operation, new records are added to the database through a POST request; in the read operation, a single or multiple records are queried through a GET request; in the update operation, existing records are updated through a PUT or PATCH request; in the delete operation, records are deleted through a DELETE request.

[0020] In an optional implementation, the method of automatically parsing the evaluation log data generated by each test case using a log analysis tool and extracting relevant indicators according to the type of each test case further includes:

[0021] The parsing engine automatically identifies the format of uploaded log files and implements log parsing in combination with the basic information provided by the user. During the parsing process, regular expressions are used to extract key fields and identify relevant data in the logs. According to different test case types, predefined parsing rules are applied to automatically extract relevant indicator data.

[0022] In an optional implementation, the extracted relevant indicators include one or more of the following:

[0023] For basic specification test cases, basic indicators are extracted from the logs, including chip memory usage, processing power, and bandwidth usage;

[0024] For operator test cases, the performance indicators of the operators are extracted from the logs, including execution time, throughput, and latency, and the execution efficiency of each operator is automatically identified and recorded.

[0025] For model training test cases, extract key data of the training process from the logs, including loss value, accuracy, and training time.

[0026] In an optional implementation manner, the intelligent analysis of the operator result information of the evaluation task further includes:

[0027] According to the evaluation task selected by the user on the front end, the performance data of each operator is automatically extracted from the evaluation results. The back end uses statistical methods to perform statistical analysis on the performance of the operator, including averaging the performance indicators of all operators, calculating the median value of the operator performance, generating a performance distribution histogram, and displaying the distribution of operator performance.

[0028] According to a second aspect of the present application, a visual multi-element chip evaluation integrated device is provided, comprising:

[0029] A data integration unit is used to integrate, store and manage chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results after chip performance evaluation by building a unified data model and operation interface;

[0030] The log parsing and extraction unit is used to combine the basic information input by the user front end, use the log analysis tool to automatically parse the evaluation log data generated by each test case, and extract relevant indicators according to the type of each test case;

[0031] The intelligent analysis unit is used to visualize the chip performance evaluation results and perform intelligent analysis on the data comparison information between evaluation tasks and the operator result information of the evaluation tasks.

[0032] A third aspect of the present application provides an electronic device, including a processor and a memory, wherein the memory stores a plurality of instructions, and the processor is used to read the instructions and execute the method of the first aspect.

[0033] A fourth aspect of the present application provides a computer-readable storage medium, which stores a plurality of instructions, and the plurality of instructions can be read by a processor to execute the method of the first aspect.

[0034] Compared with the related art, the technical solution of this application has the following advantages:

[0035] Through the abstraction of data structures, the evaluation results of different AI chips are integrated and centrally managed: the unified conversion of test results facilitates horizontal comparison of test results and simplifies the workload of front-end system data processing. The automatic parsing function of the evaluation log significantly improves the analysis efficiency of the evaluation results, reduces manual intervention, and thus improves the evaluation efficiency and speed. For the evaluation logs generated by different evaluation tools, they can also be quickly adapted and added through a rich rule engine. It provides flexible and rich data visualization processing and display capabilities. Multi-dimensional visual analysis helps users understand and compare the performance of different chips more intuitively, which helps with decision support.

[0036] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is the overall architecture diagram of the multi-chip evaluation integration and visualization platform based on this application.

[0039] Figure 2 It is a flow chart of a visualized multi-element chip evaluation integration method according to the present application.

[0040] Figure 3 It is an overall flow chart for automatically parsing the log results of this application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] The method provided in the present application can be implemented in the following terminal environment, and the terminal may include one or more of the following components: a processor, a memory, and a display screen. The memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the method described in the following embodiments.

[0043] The processor may include one or more processing cores. The processor uses various interfaces and lines to connect various parts of the entire terminal, and executes various functions of the terminal and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory.

[0044] The memory may include random access memory (RAM) or read-only memory (ROM). The memory may be used to store instructions, programs, codes, code sets or instructions.

[0045] The display screen is used to display the user interface of each application.

[0046] In addition, those skilled in the art will appreciate that the structure of the above terminal does not constitute a limitation on the terminal, and the terminal may include more or fewer components, or combine certain components, or arrange the components differently. For example, the terminal also includes components such as a radio frequency circuit, an input unit, a sensor, an audio circuit, and a power supply, which will not be described in detail here.

[0047] Based on the above analysis, the present application provides a visual integrated method and device for multi-chip evaluation, which integrates various chip performance test data by building a unified evaluation management platform, and realizes efficient processing and in-depth analysis of evaluation results through automated log analysis and data visualization functions.

[0048] The overall architecture of the platform is as follows Figure 1As shown. The platform comprehensively integrates and manages various evaluation data related to multiple chips. All data generated during the evaluation process are uniformly stored, accessed and analyzed on one platform. The evaluation data includes but is not limited to chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results. Through this centralized data management, the platform can achieve efficient data integration and comparative analysis.

[0049] During the chip performance evaluation process, each type of test case and each specific test case will generate a large amount of log data, including key performance indicators such as computing throughput, running time, memory usage, operator execution time, etc. In order to efficiently extract useful performance information from these logs, the platform of this application integrates intelligent log analysis tools, automatically processes evaluation logs, and extracts relevant indicator data according to the type of each test case.

[0050] While displaying the evaluation results, we further conduct in-depth comparative analysis of the results of different test cases. For example, we compare the model training results and analyze the distribution of operator performance, which helps users quickly understand performance bottlenecks and optimize chip or model design. We provide a variety of data visualization displays to help users deeply understand the evaluation data and make more accurate decisions.

[0051] The platform adopts a separate architecture of front-end (Vue) and back-end (Django, an open source web framework written in Python). The front-end is used for operation entry, data display and result upload, and the back-end is used for data storage, processing and calculation. Through this design, more efficient data interaction and flexible system scalability can be achieved. It supports flexible configuration of multiple chips and test cases, expands evaluation test cases, configuration and analysis according to user needs, or uses different evaluation tools, etc., to meet the needs of different application scenarios.

[0052] See also Figure 2 The flowchart of the present application shows that the visualized multi-element chip evaluation integrated method includes:

[0053] Step 101: After chip performance evaluation, chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results are integrated, stored and managed by building a unified data model and operation interface.

[0054] In order to achieve comprehensive management of chips, servers, test cases, evaluation tasks and evaluation results, a data management system based on the Django framework is built. The system uses Django's object-relational mapping (ORM) and RESTful API features to build data models and provide operation interfaces to efficiently organize, store and process data, supporting various operations in the hardware evaluation process.

[0055] The system involves the following data structures, each of which is defined by a Django model and stored persistently in the database:

[0056] Chip information: used to store basic data related to the chip, including memory capacity, memory bandwidth, computing power and other indicators, as well as information such as chip interconnection methods. These data are essential basic information in the evaluation process.

[0057] Evaluation environment information: stores server hardware and software related information, such as IP address, operating system version, and chip model. The chip used by each server is associated with the chip information table through a foreign key for easy management and query.

[0058] Test case information: describes the specific content of the test task, including name, description, category (such as basic specifications, operators, model training), and framework used, etc. Each type of test case contains multiple specific use cases.

[0059] Evaluation task information: records the detailed information of each evaluation task, including the chip to be evaluated, the evaluation executor, the evaluation status and time, etc. Each evaluation task can be associated with multiple test cases and corresponding evaluation results.

[0060] Chip performance evaluation results: Store the result data after each test case is executed. The evaluation results will contain different data content depending on the type of use case and are stored in JSON format to ensure good scalability.

[0061] In order to implement data creation, deletion, update, and read (CRUD) operations, the system provides a corresponding RESTful API interface based on Django to facilitate interaction with external systems. Through Django REST Framework (DRF, DjangoREST framework), the operation interface of the data model can be quickly implemented. In the creation operation, a new record is added to the database through a POST request. In the read operation, a single or multiple records are queried through a GET request. In the update operation, an existing record is updated through a PUT or PATCH request. In the delete operation, a record is deleted through a DELETE request.

[0062] The serializer function provided by DRF can convert Django model objects into JSON format and convert client-requested data into model objects, supporting data transmission and processing.

[0063] The front-end interface is developed using the Vue.js framework to achieve efficient interaction with the back-end system and user interface. Vue.js provides an intuitive user interface that supports input, viewing, and management of all the data structures mentioned above. Vue.js is a progressive JavaScript framework suitable for building complex single-page applications.

[0064] In front-end operation, users submit data through the front-end interface (such as creating a new chip, entering evaluation task information, etc.);

[0065] The front end uses Vue.js to send API requests to the back end through Axios and submits the data to the Django back end;

[0066] The backend receives requests through the Django REST Framework and processes data (such as storing, updating, or querying the database);

[0067] The backend processing results are returned to the frontend, and the frontend interface updates the displayed content based on the returned data, such as adding new records, updating status or evaluation results.

[0068] Step 102: Combined with the basic information input by the user front end, the log analysis tool is used to automatically parse the evaluation log data generated by each test case, and relevant indicators are extracted according to the type of each test case.

[0069] The overall process of automatic analysis of log results is as follows Figure 3 During the log upload and basic information input process, the user uploads the evaluation log file through the front-end page and enters some necessary basic information, including:

[0070] Associated evaluation tasks: By selecting the corresponding evaluation tasks, ensure that the analysis results are accurately associated with the tasks;

[0071] Test case type: According to the test type corresponding to the uploaded log (such as basic specifications, operators, or model training), the user selects the test case type;

[0072] This information helps the system determine log parsing rules and provides the necessary context for subsequent data storage and display.

[0073] During the log parsing and information extraction process, the backend automatically identifies the format of the uploaded log file through the parsing engine, and implements specific log parsing based on the basic information provided by the user. The parsing process includes:

[0074] Use regular expressions to extract key fields and identify relevant data in logs;

[0075] According to different test case types (such as basic specifications, operator testing, and model training), predefined parsing rules are applied to automatically extract relevant indicator data.

[0076] The specific indicators of the analysis are as follows:

[0077] Basic specification test cases: Extract basic indicators such as chip memory usage, processing power, and bandwidth usage from logs.

[0078] Operator test cases: extract the operator's execution time, throughput, latency and other performance indicators, and automatically identify and record the execution efficiency of each operator.

[0079] Model training test cases: extract key data such as loss value, accuracy, training time, etc. during the training process.

[0080] Parsing rules can be dynamically configured according to the test case type and specific evaluation task requirements to ensure that the parsing process is flexible and scalable.

[0081] Step 103: Visually display the chip performance evaluation results, and intelligently analyze the data comparison information between the evaluation tasks and the operator result information of the evaluation tasks.

[0082] Multi-dimensional data visualization and intelligent analysis include comparative analysis of data between different evaluation tasks and intelligent analysis of evaluation task operators.

[0083] The comparative analysis of data between different evaluation tasks is intended to help users identify performance differences between chips or between different evaluation tasks.

[0084] Specifically, the user selects the evaluation task to be compared on the front end and sends an API request to the back end through Axios; the back end extracts all result indicator data of the selected evaluation task from the database, summarizes and associates these data according to the test case type dimension, and returns them to the front end page for display.

[0085] The operators in the evaluation tasks usually involve a large number of different test cases, and the number of operators is huge. In order to facilitate analysis and optimization, the system needs to perform intelligent analysis on the performance of the evaluation task operators and extract useful statistical information and distribution characteristics.

[0086] Specifically, the user selects the evaluation task to be analyzed on the front end, and the system automatically extracts the performance data of each operator from the evaluation results, such as execution time, throughput, etc. The system back end uses statistical methods to perform statistical analysis on the performance of the operator, including one or more of the following aspects:

[0087] The performance indicators of all operators (such as CPU execution time, Kernel execution time, etc.) are averaged to help users understand the overall performance level;

[0088] Calculate the median value of operator performance to help users understand the distribution of performance, especially to avoid being affected by extreme data;

[0089] Generate a performance distribution histogram to display the distribution of operator performance, making it easier for users to identify the central trend of performance.

[0090] It can be seen that the visualized multi-element chip evaluation integration method provided by this application has the following advantages compared with the related technologies:

[0091] Through the abstraction of data structures, the evaluation results of different AI chips are integrated and centrally managed: the unified conversion of test results facilitates horizontal comparison of test results and simplifies the workload of front-end system data processing. The automatic parsing function of the evaluation log significantly improves the analysis efficiency of the evaluation results, reduces manual intervention, and thus improves the evaluation efficiency and speed. For the evaluation logs generated by different evaluation tools, they can also be quickly adapted and added through a rich rule engine. It provides flexible and rich data visualization processing and display capabilities. Multi-dimensional visual analysis helps users understand and compare the performance of different chips more intuitively, which helps with decision support.

[0092] Accordingly, the present application provides a second aspect of a visualized multi-element chip evaluation integrated device, comprising:

[0093] A data integration unit is used to integrate, store and manage chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results after chip performance evaluation by building a unified data model and operation interface;

[0094] The log parsing and extraction unit is used to combine the basic information input by the user front end, use the log analysis tool to automatically parse the evaluation log data generated by each test case, and extract relevant indicators according to the type of each test case;

[0095] The intelligent analysis unit is used to visualize the chip performance evaluation results and perform intelligent analysis on the data comparison information between evaluation tasks and the operator result information of the evaluation tasks.

[0096] The above-mentioned device can be implemented by the visualized multi-chip evaluation integration method provided by the embodiment of the first aspect above. The specific implementation method can be found in the description of the embodiment of the first aspect, which will not be repeated here.

[0097] Those skilled in the art may also make easily conceivable combinations and adjustments to the structural features of the above multiple embodiments according to usage requirements, and the concept of the present application should not be limited to the specific details of the above examples.

[0098] The present application also provides an electronic device, including a processor and a memory, wherein the memory stores a plurality of instructions, and the processor is used to read the instructions and execute any one of the methods in the aforementioned first aspect. The processor and the memory may be connected via a bus or in other ways, taking the bus connection as an example. The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various types of chips.

[0099] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the method in the embodiment of the present application. The processor executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory, that is, implementing the method in the above method embodiment.

[0100] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0101] The present application also provides a computer-readable medium storing a plurality of instructions, which can be loaded and executed by the processor so that the processor can perform any one of the methods in the first aspect described above. The computer-readable storage medium can be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0102] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A visual multi-element chip evaluation integration method, characterized in that: include: By building a unified data model and operation interface, after chip performance evaluation, chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results are integrated, stored and managed; Combined with the basic information input by the user front end, the log analysis tool is used to automatically parse the evaluation log data generated by each test case, and relevant indicators are extracted according to the type of each test case; The chip performance evaluation results are displayed visually, and the data comparison information between evaluation tasks and the operator result information of the evaluation tasks are intelligently analyzed.

2. The visualized multi-element chip evaluation integrated method according to claim 1, characterized in that: The integration, storage and management of chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results further includes: The chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation result data structure are defined by Django model, wherein: The chip information is used to store basic data related to the chip, including video memory capacity, video memory bandwidth and computing power indicators, as well as chip interconnection information; The evaluation environment information is used to store server hardware and software related information, including IP address, operating system version and chip model; The test case information is used to describe the specific content of the test task, including the name, description, category and framework used; The evaluation task information is used to record the detailed information of each evaluation task, including the chip to be evaluated, the evaluation executor, the evaluation status and time; each evaluation task is associated with multiple test cases and corresponding evaluation results; The chip performance evaluation results are used to store the result data after each test case is executed.

3. The visual multi-element chip evaluation integration method according to claim 1, characterized in that: The integration, storage and management of chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results further includes: The Django REST Framework is used to implement the operation interface of the data model to complete data creation, deletion, update and read operations. In the creation operation, new records are added to the database through a POST request; in the read operation, a single or multiple records are queried through a GET request; in the update operation, existing records are updated through a PUT or PATCH request; in the delete operation, records are deleted through a DELETE request.

4. The visualized multi-element chip evaluation integrated method according to claim 1, characterized in that: The method of automatically parsing the evaluation log data generated by each test case using a log analysis tool and extracting relevant indicators according to the type of each test case further includes: The parsing engine automatically identifies the format of uploaded log files and implements log parsing in combination with the basic information provided by the user. During the parsing process, regular expressions are used to extract key fields and identify relevant data in the logs. According to different test case types, predefined parsing rules are applied to automatically extract relevant indicator data.

5. The visualized multi-element chip evaluation integrated method according to claim 1, characterized in that: The extracted relevant indicators include one or more of the following: For basic specification test cases, basic indicators are extracted from the logs, including chip memory usage, computing power processing capability, and bandwidth usage; For operator test cases, the operator's performance indicators, including execution time, throughput, and latency, are extracted from the logs, and the execution efficiency of each operator is automatically identified and recorded. For model training test cases, extract key data of the training process from the logs, including loss value, accuracy, and training time.

6. The visualized multi-element chip evaluation integrated method according to claim 1, characterized in that: Intelligent analysis of the operator result information of the evaluation task further includes: According to the evaluation task selected by the user on the front end, the performance data of each operator is automatically extracted from the evaluation results. The back end uses statistical methods to perform statistical analysis on the performance of the operator, including averaging the performance indicators of all operators, calculating the median value of the operator performance, generating a performance distribution histogram, and displaying the distribution of operator performance.

7. A visual multi-element chip evaluation integrated device, characterized in that: include: A data integration unit is used to integrate, store and manage chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation results after chip performance evaluation by building a unified data model and operation interface; The log parsing and extraction unit is used to combine the basic information input by the user front end, use the log analysis tool to automatically parse the evaluation log data generated by each test case, and extract relevant indicators according to the type of each test case; The intelligent analysis unit is used to visualize the chip performance evaluation results and perform intelligent analysis on the data comparison information between evaluation tasks and the operator result information of the evaluation tasks.

8. The visualized multi-element chip evaluation integrated device according to claim 7, characterized in that: The data integration unit is further used for: The chip information, evaluation environment information, test case information, evaluation task information and chip performance evaluation result data structure are defined by Django model, wherein: The chip information is used to store basic data related to the chip, including video memory capacity, video memory bandwidth and computing power indicators, as well as chip interconnection information; The evaluation environment information is used to store server hardware and software related information, including IP address, operating system version and chip model; The test case information is used to describe the specific content of the test task, including the name, description, category and framework used; The evaluation task information is used to record the detailed information of each evaluation task, including the chip to be evaluated, the evaluation executor, the evaluation status and time; each evaluation task is associated with multiple test cases and corresponding evaluation results; The chip performance evaluation results are used to store the result data after each test case is executed.

9. The visualized multi-element chip evaluation integrated device according to claim 7, characterized in that: The data integration unit is further used for: The Django REST Framework is used to implement the operation interface of the data model to complete data creation, deletion, update and read operations. In the creation operation, new records are added to the database through a POST request; in the read operation, a single or multiple records are queried through a GET request; in the update operation, existing records are updated through a PUT or PATCH request; in the delete operation, records are deleted through a DELETE request.

10. The visualized multi-element chip evaluation integrated device according to claim 7, characterized in that: The log parsing and extracting unit is further used to: The parsing engine automatically identifies the format of uploaded log files and implements log parsing in combination with the basic information provided by the user. During the parsing process, regular expressions are used to extract key fields and identify relevant data in the logs. According to different test case types, predefined parsing rules are applied to automatically extract relevant indicator data.

11. The visualized multi-element chip evaluation integrated device according to claim 7, characterized in that: The extracted relevant indicators include one or more of the following: For basic specification test cases, basic indicators are extracted from the logs, including chip memory usage, processing power, and bandwidth usage; For operator test cases, the operator's performance indicators, including execution time, throughput, and latency, are extracted from the logs, and the execution efficiency of each operator is automatically identified and recorded. For model training test cases, extract key data of the training process from the logs, including loss value, accuracy, and training time.

12. The visualized multi-element chip evaluation integrated device according to claim 7, characterized in that: The intelligent analysis unit is further used for: According to the evaluation task selected by the user on the front end, the performance data of each operator is automatically extracted from the evaluation results. The back end uses statistical methods to perform statistical analysis on the performance of the operator, including averaging the performance indicators of all operators, calculating the median value of the operator performance, generating a performance distribution histogram, and displaying the distribution of operator performance.

13. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores a plurality of instructions, and the processor is used to read the instructions and execute the visualized multi-element chip evaluation integration method as described in any one of claims 1-6.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a plurality of instructions, and the plurality of instructions can be read by a processor and executed by the visualized multi-element chip evaluation integration method as described in any one of claims 1-6.

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