External driver circuit and memory

Abstract

This application discloses an external chip driver circuit and a memory. The external chip driver circuit, applied to a memory, includes a driving circuit, a pull-up slew rate control circuit, and a pull-down slew rate control circuit. The driving circuit generates a driving signal for the memory's interface. The pull-up slew rate control circuit, connected to the driving circuit, delays the falling edge of a first control signal to generate multiple first delay signals, thereby adjusting the pull-up slew rate of the driving signal. The pull-down slew rate control circuit, also connected to the driving circuit, delays the rising edge of a second control signal to generate multiple second delay signals, thereby adjusting the pull-down slew rate of the driving signal. Through this method, the external chip driver circuit of this application can separately adjust the pull-up and pull-down slew rates of the driving signal, thus avoiding the additional current consumption of the driving circuit and saving memory power consumption.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to an external chip driver circuit and a memory. Background Technology

[0002] Off-chip driver (OCD) circuits are primarily used in memory to drive the memory interface, transmitting data read from the memory to the host (and also receiving data from the host to write to the memory). In OCD circuits, the drive circuit generates a large transient current when reading data, leading to significant power supply noise within the memory chip and impacting its performance. To reduce the transient current during read operations, a slew rate control circuit is needed before the drive circuit to reduce the transient current by decreasing the slew rate of the output signal. However, existing slew rate control schemes generate additional through-current in the drive circuit, increasing power consumption. Summary of the Invention

[0003] To address the aforementioned issues, this application provides an external driver circuit and memory for chip operation, thereby avoiding the consumption of additional current in the driver circuit and saving power consumption.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing an external chip driver applied to a memory, the external chip driver circuit including a driving circuit, a pull-up slew rate control circuit, and a pull-down slew rate control circuit, the driving circuit being used to generate a driving signal for the interface terminal of the memory; the pull-up slew rate control circuit being connected to the driving circuit being used to delay the falling edge of a first control signal to generate multiple first delay signals to adjust the pull-up slew rate of the driving signal; the pull-down slew rate control circuit being connected to the driving circuit being used to delay the rising edge of a second control signal to generate multiple second delay signals to adjust the pull-down slew rate of the driving signal.

[0005] The driving circuit includes multiple parallel driving sub-circuits. Each driving sub-circuit includes a first transistor, a first resistor, a second resistor, and a second transistor. The first terminal of the first transistor receives the power supply voltage, and the control terminal of the first transistor receives a first delayed signal. The first terminal of the first resistor is connected to the second terminal of the first transistor. The first terminal of the second resistor is connected to the second terminal of the first resistor, and the connection between the first terminal of the second resistor and the second terminal of the first resistor serves as the output terminal of the driving sub-circuit. The first terminal of the second transistor is connected to the second terminal of the second resistor, the control terminal of the second transistor receives a second delayed signal, and the second terminal of the second transistor is grounded. The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0006] The driving circuit includes multiple parallel driving sub-circuits. Each driving sub-circuit includes a first transistor coupled to the power supply voltage and a second transistor coupled to ground. When the pull-up slew rate control circuit adjusts the pull-up slew rate of the driving signal, multiple second delay signals control all second transistors in all driving sub-circuits to turn off simultaneously, and multiple first delay signals control the first transistors in each stage of the driving sub-circuit to turn on sequentially. And / or when the pull-down slew rate control circuit adjusts the pull-down slew rate of the driving signal, multiple first delay signals control all first transistors in all driving sub-circuits to turn off simultaneously, and multiple second delay signals control the second transistors in each stage of the driving sub-circuit to turn on sequentially.

[0007] The pull-up slew rate control circuit includes multiple series-connected first delay signal output modules. Each first delay signal output module is used to output a first delay signal, and the falling edge of the first delay signal output by the later first delay signal output module is time-shifted by a corresponding delay compared to the falling edge of the first delay signal output by the previous first delay signal output module.

[0008] The pull-up slew rate control circuit further includes a first control signal generation module. Each stage of the first delay signal output module is connected to the first control signal generation module. The first stage of the first delay signal output module includes a first inverter. The input terminal of the first inverter is connected to the first control signal generation module. The connection between the input terminal of the first inverter and the first control signal generation module serves as a first node. The output terminal of the first inverter serves as the output terminal of the first stage of the first delay signal output module, outputting the first stage's first delay signal. Other first delay signal output modules besides the first stage include a first delay unit and a NAND gate unit. The input terminal of the first delay unit of the second stage of the first delay signal output module is connected to the first node. The input terminal of the first delay unit of other first delay signal output modules is connected to the output terminal of the first delay unit of the previous stage's first delay signal output module. In other first delay signal output modules besides the first stage, the first input terminal of the NAND gate unit is connected to the first control signal generation module, the second input terminal of the NAND gate unit is connected to the output terminal of the first delay unit, and the output terminal of the NAND gate serves as the output terminal of the corresponding first delay signal output module, outputting a first delay signal.

[0009] The pull-up slew rate control circuit further includes a first control signal generation module; the first-stage first delay signal output module includes a second inverter, the input of which is connected to the first control signal generation module, the connection point between the input of the second inverter and the first control signal generation module is a second node, and the output of the second inverter serves as the output of the first-stage first delay signal output module, outputting the first-stage first delay signal; all other first delay signal output modules besides the first stage include a rising edge delay unit and a second inverter, the input of the rising edge delay unit of the second-stage first delay signal output module is connected to the second node, and the input of the rising edge delay unit of the other first delay signal output modules is connected to the output of the rising edge delay unit of the previous stage first delay signal output module; in the other first delay signal output modules besides the first stage, the input of the second inverter is connected to the output of the rising edge delay unit, and the output of the second inverter serves as the output of the corresponding first delay signal output module, outputting a first delay signal.

[0010] The pull-up slew rate control circuit further includes a first control signal generation module; the first-stage first delay signal output module includes a third inverter, the input of which is connected to the first control signal generation module, and the output of which is a third node, which serves as the output of the first-stage first delay signal output module to output the first-stage first delay signal; all other first delay signal output modules except the first stage include a falling edge delay unit, the input of the falling edge delay unit of the second-stage first delay signal output module is connected to the third node, and the input of the falling edge delay unit of the other first delay signal output modules is connected to the output of the falling edge delay unit of the previous stage first delay signal output module; in the other first delay signal output modules except the first stage, the output of the falling edge delay unit serves as the output of the corresponding first delay signal output module to output a first delay signal.

[0011] The pull-down slew rate control circuit includes multiple series-connected second delay signal output modules. Each second delay signal output module is used to output a second delay signal, and the rising edge of the second delay signal output by the subsequent second delay signal output module is time-shifted by a corresponding delay compared to the rising edge of the second delay signal output by the previous second delay signal output module.

[0012] The pull-down slew rate control circuit also includes a second control signal generation module. Each stage of the second delay signal output module is connected to the second control signal generation module. The first stage of the second delay signal output module includes a fourth inverter. The input terminal of the fourth inverter is connected to the second control signal generation module. The connection between the input terminal of the fourth inverter and the second control signal generation module serves as the fourth node. The output terminal of the fourth inverter serves as the output terminal of the first stage of the second delay signal output module, outputting the second delay signal of the first stage. Other second delay signal output modules besides the first stage include a second delay unit and a NOR gate unit. The input terminal of the second delay unit of the second stage of the second delay signal output module is connected to the fourth node. The input terminal of the second delay unit of other second delay signal output modules is connected to the output terminal of the second delay unit of the previous stage of the second delay signal output module. In other second delay signal output modules besides the first stage, the first input terminal of the NOR gate unit is connected to the second control signal generation module, the second input terminal of the NOR gate unit is connected to the output terminal of the second delay unit, and the output terminal of the NOR gate serves as the output terminal of the corresponding second delay signal output module, outputting a second delay signal.

[0013] The pull-down slew rate control circuit also includes a second control signal generation module; the first-stage second delay signal output module includes a fifth inverter, the input of which is connected to the second control signal generation module, and the connection point between the input of the fifth inverter and the second control signal generation module is the fifth node; the output of the fifth inverter serves as the output of the first-stage second delay signal output module, outputting the second delay signal of the first stage; all other second delay signal output modules except the first stage include a falling edge delay unit and a fifth inverter, the input of the falling edge delay unit of the second-stage second delay signal output module is connected to the fifth node, and the input of the falling edge delay unit of the other second delay signal output modules is connected to the output of the falling edge delay unit of the previous stage second delay signal output module; in the other second delay signal output modules except the first stage, the input of the fifth inverter is connected to the output of the falling edge delay unit, and the output of the fifth inverter serves as the output of the corresponding second delay signal output module, outputting a second delay signal.

[0014] The pull-down slew rate control circuit also includes a second control signal generation module; the first-stage second delay signal output module includes a sixth inverter, the input of which is connected to the second control signal generation module, and the output of which is a sixth node. The sixth node serves as the output of the first-stage second delay signal output module, outputting the second delay signal of the first stage; all other second delay signal output modules except the first stage include rising edge delay units. The input of the rising edge delay unit of the second-stage second delay signal output module is connected to the sixth node, and the input of the rising edge delay unit of the other second delay signal output modules is connected to the output of the rising edge delay unit of the previous stage second delay signal output module; in the other second delay signal output modules except the first stage, the output of the rising edge delay unit serves as the output of the corresponding second delay signal output module, outputting a second delay signal.

[0015] The rising edge delay unit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third resistor, and a fourth resistor. The first terminal of the third transistor receives a preset voltage. The second terminal of the third transistor is connected to the first terminal of the third resistor. The connection point between the second terminal of the third transistor and the first terminal of the third resistor serves as a seventh node. The second terminal of the third resistor is connected to the first terminal of the fourth transistor. The second terminal of the fourth transistor is grounded. The control terminals of the third and fourth transistors serve as the input terminals of the rising edge delay unit. The seventh node is connected to the control terminals of the fifth and sixth transistors. The first terminal of the fifth transistor receives a preset voltage. The second terminal of the fifth transistor is connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the first terminal of the sixth transistor. The second terminal of the sixth transistor is grounded. The connection point between the second terminal of the fourth resistor and the first terminal of the sixth transistor serves as an eighth node. The eighth node serves as the output terminal of the rising edge delay unit. The third and fifth transistors are PMOS transistors, and the fourth and sixth transistors are NMOS transistors.

[0016] The falling edge delay unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a fifth resistor, and a sixth resistor. The first terminal of the seventh transistor receives a preset voltage. The second terminal of the seventh transistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to the first terminal of the eighth transistor. The connection between the second terminal of the fifth resistor and the first terminal of the eighth transistor serves as the ninth node. The second terminal of the eighth transistor is grounded. The control terminals of the seventh and eighth transistors serve as the input terminals of the falling edge delay unit. The ninth node is connected to the control terminals of the ninth and tenth transistors. The first terminal of the ninth transistor receives a preset voltage. The second terminal of the ninth transistor is connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor is connected to the first terminal of the tenth transistor. The second terminal of the tenth transistor is grounded. The connection between the second terminal of the ninth transistor and the first terminal of the sixth resistor serves as the tenth node. The tenth node serves as the output terminal of the falling edge delay unit. The seventh and ninth transistors are PMOS transistors, and the eighth and tenth transistors are NMOS transistors.

[0017] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a memory that includes the chip external driver circuit of any of the above-mentioned components.

[0018] Unlike existing technologies, the external driver circuit of this application includes a driving circuit, a pull-up slew rate control circuit, and a pull-down slew rate control circuit. The driving circuit generates a driving signal for the memory interface. The pull-up slew rate control circuit is connected to the driving circuit and is used to delay the falling edge of the first control signal to generate multiple first delay signals to adjust the pull-up slew rate of the driving signal. The pull-down slew rate control circuit is connected to the driving circuit and is used to delay the rising edge of the second control signal to generate multiple second delay signals to adjust the pull-down slew rate of the driving signal. Through this method, the external driver circuit of this application can adjust the pull-up and pull-down slew rates of the driving signal separately, thereby avoiding the additional current consumption of the driving circuit and saving memory power consumption. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0020] Figure 1 This is a schematic diagram of the structure of an embodiment of a prior art chip external driver circuit;

[0021] Figure 2 This is a timing diagram of an embodiment of a prior art chip external driver circuit;

[0022] Figure 3 This is a current schematic diagram of an embodiment of an external driver circuit for a chip in the prior art;

[0023] Figure 4 This is a schematic diagram of the structure of the first embodiment of the chip external driver circuit provided in this application;

[0024] Figure 5 This is a schematic diagram of the structure of the second embodiment of the chip external driver circuit provided in this application;

[0025] Figure 6 This is a schematic diagram of the structure of the third embodiment of the chip external driver circuit provided in this application;

[0026] Figure 7 This is a circuit timing diagram of an embodiment of the chip external driver circuit provided in this application;

[0027] Figure 8 This is a current schematic diagram of an embodiment of the chip external driver circuit provided in this application;

[0028] Figure 9 This is a schematic diagram of the structure of the fourth embodiment of the chip external driver circuit provided in this application;

[0029] Figure 10 This is a schematic diagram of the fifth embodiment of the chip external driver circuit provided in this application;

[0030] Figure 11 This is a schematic diagram of the structure of an embodiment of the rising edge delay unit provided in this application;

[0031] Figure 12 This is a schematic diagram of the structure of an embodiment of the falling edge delay unit provided in this application;

[0032] Figure 13 This is a schematic diagram of the structure of an embodiment of the memory provided in this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] Off-chip driver (OCD) circuits are primarily used in memory to drive the memory interface to transmit data read from memory to the host (and also to receive data from the host for writing to memory). In OCD circuits, the drive circuit generates a large transient current when reading data, which can lead to significant power supply noise within the memory chip and affect its performance. To reduce the transient current during read operations, a slew rate control circuit is needed before the drive circuit to reduce the transient current by decreasing the slew rate of the output signal. However, existing slew rate control schemes generate additional through-current in the drive circuit, increasing power consumption.

[0036] In the prior art, please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of an embodiment of a prior art chip external driver circuit; Figure 2 This is a timing diagram of an embodiment of a prior art chip external driver circuit. For example... Figure 1 and Figure 2 As shown, the prior art chip external driver circuit 10 includes a slew rate control circuit 11 and a drive circuit 12. The slew rate control circuit controls the slew rate of the drive signal by controlling the slew rate of the gate terminal signal of the transistor in the drive circuit. In this application, the drive signal can be the data terminal DQ (Data) signal of the memory interface, the clock terminal DQS (Data Strobe) signal, or the data mask terminal DM (Data Mask) signal.

[0037] Please see Figure 3 , Figure 3 This is a current schematic diagram of an embodiment of a prior art chip external driver circuit. For example... Figure 1 and Figure 3As shown, taking the pull-up of the drive signal as an example, when preparing to pull up the drive signal, the slew rate control circuit generates control signals IN_P and IN_N from the original control signals IN_PB and IN_NB, respectively, to slowly pull down the gate voltages of the PMOS and NMOS transistors in the drive circuit. When the gate voltage of the PMOS transistor is lower than the difference between the power supply voltage VDDQ and the threshold voltage VTHP of the PMOS transistor, the PMOS transistor turns on, thereby generating a transient current Ipu. At this time, the gate voltage of the NMOS transistor is higher than the threshold voltage VTHN of the NMOS transistor, so the NMOS transistor also turns on, generating a current Ipd. Therefore, by using the above method, the existing chip external driver circuit can reduce the generation of transient current Ipu by slowing down the turn-on speed of the PMOS transistor in the drive circuit, thereby controlling the slew rate of the drive signal.

[0038] Meanwhile, the current Ipd generated by the NMOS transistor will also shunt the transient current Ipu, which will superficially reduce the slew rate of the drive signal. However, the existing technology does not reduce the generation of transient current Ipu. Therefore, a lower slew rate of the drive signal will not improve power supply noise, but will only cause additional power consumption waste.

[0039] Therefore, to solve the above problems, this application first proposes an external chip driver circuit, which is applied to a memory. Please refer to... Figure 4 , Figure 4 This is a schematic diagram of the structure of the first embodiment of the chip external driver circuit provided in this application. Figure 4 As shown, the chip external driver circuit 100 of this embodiment includes a driving circuit 110, a pull-up slew rate control circuit 120, and a pull-down slew rate control circuit 130.

[0040] In this embodiment, the driving circuit 110 is used to generate the driving signal at the interface of the memory; the pull-up slew rate control circuit 120 is connected to the driving circuit 110 and is used to delay the falling edge of the first control signal to generate multiple first delay signals to adjust the pull-up slew rate of the driving signal; the pull-down slew rate control circuit 130 is connected to the driving circuit 110 and is used to delay the rising edge of the second control signal to generate multiple second delay signals to adjust the pull-down slew rate of the driving signal.

[0041] As mentioned above, in this embodiment, the drive signal generated by the drive circuit 110 can also be a DQ (Data) signal, a DQS (Data Strobe) signal, or a DM (Data Mask) signal. That is, the drive signal can be a data terminal signal, a clock terminal signal, or a data mask terminal signal at the external interface of the memory, used to transmit data between the host and the memory. Furthermore, in this embodiment, the pull-up slew rate of the drive signal is only controlled by the delay of the first delay signal generated by the pull-up slew rate control circuit 120, and the pull-down slew rate of the drive signal is only controlled by the delay of the second delay signal generated by the pull-down slew rate control circuit 130.

[0042] Unlike existing technologies, the external driver circuit 100 of this application includes a driving circuit 110, a pull-up slew rate control circuit 120, and a pull-down slew rate control circuit 130. The driving circuit 110 generates a driving signal for the memory interface. The pull-up slew rate control circuit 120 is connected to the driving circuit 110 and is used to delay the falling edge of the first control signal to generate multiple first delay signals to adjust the pull-up slew rate of the driving signal. The pull-down slew rate control circuit 130 is connected to the driving circuit 110 and is used to delay the rising edge of the second control signal to generate multiple second delay signals to adjust the pull-down slew rate of the driving signal. Through this method, the external driver circuit 100 of this application can adjust the pull-up and pull-down slew rates of the driving signal separately, thereby avoiding the additional current consumption of the driving circuit 110 and saving memory power consumption.

[0043] Furthermore, in this embodiment, the pull-up slew rate of the drive signal is controlled only by the delay of the first delay signal generated by the pull-up slew rate control circuit 120, and the pull-down slew rate of the drive signal is also controlled only by the delay of the second delay signal generated by the pull-down slew rate control circuit 130. Therefore, in this embodiment, the delay for controlling the pull-up or pull-down of the drive signal can be adjusted separately, and the delay levels can also be made different, thereby making the adjustment of the drive signal slew rate more flexible.

[0044] Compared with the prior art, the slew rate adjustment of the drive signal in this embodiment has a larger variation, and the chip external driver circuit 100 in this embodiment has no strict requirements for the delay module, which can reduce the power consumption and area of ​​the circuit.

[0045] Optionally, please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of the second embodiment of the chip external driver circuit provided in this application. Figure 5 As shown, the driving circuit 110 in this embodiment includes multiple parallel driving sub-circuits 111.

[0046] In this embodiment, each driving sub-circuit 111 includes a first transistor MP.i (i = 1, 2, 3, ..., n), first resistor R 1i (i = 1, 2, 3, ..., n), second resistor R 2i (i = 1, 2, 3, ..., n) and the second transistor MN i (i = 1, 2, 3, ..., n), the first transistor MP i The first terminal receives the power supply voltage VDDQ, and the first transistor MP i The control terminal receives a first delayed signal; the first resistor R 1i The first terminal and the first transistor MP i The second path terminal is connected; the second resistor R 2i The first terminal and the first resistor R 1i The second end is connected, and the second resistor R 2i The first terminal and the first resistor R 1i The connection point of the second end serves as the output terminal of the driver sub-circuit 111; the second transistor MN i The first terminal and the second resistor R 2i The second terminal is connected to the second transistor MN. i The control terminal receives a second delayed signal, and the second transistor MN i The second path terminal is grounded; wherein, the first transistor MP i The second transistor is a PMOS transistor, MN. i It is an NMOS transistor.

[0047] In this embodiment, each driving sub-circuit 111 outputs a driving sub-signal to ultimately form a driving signal. The pull-up slew rate control circuit 120 in this embodiment generates multiple first delay signals and the first transistor MP of the multi-stage driving sub-circuit 111. i One-to-one correspondence, by sequentially turning on the first transistor MP i To adjust the pull-up slew rate of the drive signal; the pull-down slew rate control circuit 130 generates multiple second delay signals and the second transistor MN of the multi-stage drive sub-circuit 111. i One-to-one correspondence, by sequentially turning on the second transistor MN. i To adjust the slew rate of the drive signal pull-down.

[0048] Optionally, based on Figure 4 and Figure 5 In this embodiment, the driving circuit 110 includes multiple parallel driving sub-circuits 111, each driving sub-circuit 111 including a first transistor MP coupled to the power supply voltage VDDQ. i The second transistor MN is coupled to ground. iWhen adjusting the pull-up slew rate of the drive signal, the pull-up slew rate control circuit 120 uses multiple second delay signals to control all second transistors MN in all drive sub-circuits 111. i Simultaneously shut down, and multiple first delay signals control the first transistor MP in each stage of the drive sub-circuit 111. i The circuit 130 enables sequential activation; and / or, when adjusting the pull-down slew rate of the drive signal, multiple first delay signals control all first transistors MP in all drive sub-circuits 111. i Simultaneously shut down, and multiple second delay signals control the second transistor MN in each stage of the drive sub-circuit 111. i Start step by step.

[0049] In this embodiment, the pull-up slew rate of the drive signal is controlled only by the delay of the first delay signal generated by the pull-up slew rate control circuit 120, and is independent of the pull-down slew rate control circuit 130; similarly, the pull-down slew rate of the drive signal is controlled only by the delay of the second delay signal generated by the pull-down slew rate control circuit 130, and is independent of the pull-up slew rate control circuit 120. Therefore, in this embodiment, the pull-up or pull-down delay of the drive signal can be adjusted separately using the above method, and different delay levels can be achieved, thus making the slew rate adjustment of the drive signal more flexible. Furthermore, in this embodiment, through the above-mentioned separate adjustment method, the first transistor MP of the drive sub-circuit 111 in the drive circuit 110 of this embodiment... i Second transistor MN i Since they will not be turned on simultaneously, the external driver circuit 100 of this embodiment can avoid additional current consumption.

[0050] Optionally, please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of the third embodiment of the chip external driver circuit provided in this application. Based on the embodiments described above, in this embodiment, the pull-up slew rate control circuit 120 includes multiple series-connected first delay signal output modules 122, each of which is used to output a first delay signal IN_P. i (i = 1, 2, ..., n), and the first delayed signal IN_P output by the first delayed signal output module 122 of the next stage. i+1 The falling edge compared to the first delayed signal IN_P output by the first delayed signal output module 122 of the previous stage i The falling edge is time-shifted with a corresponding delay.

[0051] As mentioned earlier, the delay levels can also be made different. That is, in this embodiment, the first delay signal IN_P of each stage of the first delay signal output module 122 is different. iThe delay between the falling edges can be set to the same delay or different delays; there is no limitation here, and the specific setting can be based on the actual situation.

[0052] Optionally, such as Figure 6 As shown, based on the embodiments described above, in this embodiment, the pull-down slew rate control circuit 130 includes multiple stages of second delay signal output modules 132 connected in series. Each stage of the second delay signal output module 132 is used to output a second delay signal IN_N. i (i = 1, 2, ..., n), and the second delayed signal IN_N output by the second delayed signal output module 132 of the next stage. i+1 The rising edge of the signal is compared to the second delayed signal IN_N output by the previous stage second delayed signal output module 132. i The rising edge is time-shifted and delayed accordingly.

[0053] In this embodiment, the second delay signal IN_N of each stage of the second delay signal output module 132 i The delay between rising edges can be set to the same delay or different delays; there is no limitation here, and the specific setting can be based on the actual situation.

[0054] Optionally, based on the embodiments described above, such as Figure 6 As shown, the pull-up slew rate control circuit 120 in this embodiment further includes a first control signal generation module 121, wherein the first control signal generation module 121 is used to generate a first control signal IN_PB.

[0055] In this embodiment, each stage of the first delay signal output module 122 is connected to the first control signal generation module 121. The first stage of the first delay signal output module 122 includes a first inverter 1221, the input terminal of the first inverter 1221 is connected to the first control signal generation module 121, the connection between the input terminal of the first inverter 1221 and the first control signal generation module 121 serves as the first node Q1, and the output terminal of the first inverter 1221 serves as the output terminal of the first stage of the first delay signal output module 122, outputting the first stage's first delay signal IN_P1. Other first delay signal output modules 122 besides the first stage include a first delay unit 1222 and a NAND gate unit 1223. The input terminal of the first delay unit 1222 of the first-stage delay signal output module 122 is connected to the first node Q1. The input terminals of the first delay units 1222 of other first-stage delay signal output modules 122 are connected to the output terminals of the first delay units 1222 of the previous-stage first-stage delay signal output module 122. In the other first-stage delay signal output modules 122 besides the first-stage module, the first input terminal of the NAND gate unit 1223 is connected to the first control signal generation module 121, the second input terminal of the NAND gate unit 1223 is connected to the output terminal of the first delay unit 1222, and the output terminal of the NAND gate 1223 serves as the output terminal of the corresponding first-stage delay signal output module 122, outputting a first delay signal IN_P. i (i = 2, 3, ..., n).

[0056] Optionally, such as Figure 6 As shown, in this embodiment, the pull-down slew rate control circuit 130 further includes a second control signal generation module 131, wherein the second control signal generation module 131 is used to generate a second control signal IN_NB.

[0057] In this embodiment, each stage of the second delay signal output module 132 is connected to the second control signal generation module 131; the first stage of the second delay signal output module 132 includes a fourth inverter 1321, the input terminal of the fourth inverter 1321 is connected to the second control signal generation module 131, the connection between the input terminal of the fourth inverter 1321 and the second control signal generation module 131 is the fourth node Q4, and the output terminal of the fourth inverter 1321 is the output terminal of the first stage of the second delay signal output module 132, outputting the second delay signal IN_N1 of the first stage; all other second delay signal output modules 132 except the first stage include a second delay unit 1322 and a NOR gate unit 1323, the second The input terminal of the second delay unit 1322 of the second delay signal output module 132 is connected to the fourth node Q4. The input terminals of the second delay units 1322 of other second delay signal output modules 132 are connected to the output terminals of the second delay units 1322 of the previous stage second delay signal output module 132. In the other second delay signal output modules 132 besides the first stage, the first input terminal of the NOR gate unit 1323 is connected to the second control signal generation module 131, the second input terminal of the NOR gate unit 1323 is connected to the output terminal of the second delay unit 1322, and the output terminal of the NOR gate 1323 serves as the output terminal of the corresponding second delay signal output module 132, outputting a second delay signal IN_N. i (i = 2, 3, ..., n).

[0058] Optionally, based on Figure 6 For an example, please refer to the following: Figure 7 and Figure 8 , Figure 7 This is a circuit timing diagram of an embodiment of the chip external driver circuit provided in this application. Figure 8 This is a current schematic diagram of an embodiment of the chip external driver circuit provided in this application.

[0059] like Figure 7 and Figure 8 As shown, in this embodiment, the driving circuit 110 is a 3-stage driving sub-circuit 111, and the pull-up slew rate control circuit 120 includes a 3-stage first delay signal output module, and the pull-down slew rate control circuit 130 includes a 3-stage second delay signal output module.

[0060] like Figures 6 to 8 As shown, taking the pull-up of the drive signal in the drive circuit 110 as an example, when the drive signal is ready to be pulled up, the first control signal IN_PB and the second control signal IN_NB are pulled up. The first control signal passes through the pull-up slew rate control circuit 120 to form the following... Figure 8The three first delay signals shown are IN_P1, IN_P2, and IN_P3. The gate voltage of the first transistor MP1 in the drive sub-circuit 111, controlled by the first delay signal IN_P1, is pulled low first. At this time, the first transistor MP1 is turned on, generating a current Ipu1 between the power supply voltage VDDQ and the output terminal of the drive sub-circuit 111. Meanwhile, the second control signal IN_NB is processed by the pull-down slew rate control circuit 130 to form... Figure 8 The three second delay signals shown are IN_N1, IN_N2, and IN_N3. These signals are simultaneously pulled low when the gate voltage of the first transistor MP1 in the drive sub-circuit 111, controlled by the first delay signal IN_P1, is pulled low. This simultaneously turns off the second transistors MN1, MN2, and MN3 in the first and third stage drive sub-circuits 111, preventing the generation of current Ipd between all drive sub-circuits 111 and ground VSSQ. After a corresponding time delay, the first transistor MP2 in the second stage drive sub-circuit 111 turns on, generating current Ipu2; after another corresponding time delay, the first transistor MP3 in the third stage drive sub-circuit 111 turns on, generating current Ipu3. Therefore, the pull-up slew rate control circuit 120 of this embodiment can reduce the number of simultaneously turned-on first transistors MP1 and MP2 by the above method. i The intensity of the signal is increased to reduce the generation of transient current Ipu, thereby controlling the pull-up slew rate of the drive signal.

[0061] Meanwhile, in this embodiment, when adjusting the pull-up slew rate of the drive signal, the second transistors MN in all drive sub-circuits 111 are... i Turning off, thereby avoiding the second transistor MN in the driver sub-circuit 111 i The generation of current Ipd between the ground terminal VSSQ and the ground terminal avoids additional power consumption waste.

[0062] Similarly, when adjusting the pull-down slew rate of the drive signal using the pull-down slew rate control circuit 130, it is the first transistor MP in all drive sub-circuits 111 that is in control. i Turning off, thereby preventing the first transistor MP in the driver sub-circuit 111 from being turned off. i The generation of current Ipu between the power supply voltage VDDQ also avoids additional power consumption waste.

[0063] In this embodiment, as described above, the first transistor MP of the driving sub-circuit 111 in the driving circuit 110... i Second transistor MN iSince they will not be turned on simultaneously, the chip external driver circuit 100 in this embodiment can avoid additional current consumption. The slower the slew rate of the drive signal, the smaller the transient current and the smaller the power supply noise.

[0064] Optionally, in other embodiments, the pull-up slew rate control circuit 120 and the pull-down slew rate control circuit 130 may also have other circuit structures. Please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of the fourth embodiment of the chip external driver circuit provided in this application. Figure 9 As shown, the pull-up slew rate control circuit 120 in this embodiment also includes a first control signal generation module 121.

[0065] In this embodiment, the first-stage first-delay signal output module 122 includes a second inverter 1221. The input terminal of the second inverter 1221 is connected to the first control signal generation module 121. The connection point between the input terminal of the second inverter 1221 and the first control signal generation module 121 is the second node Q2. The output terminal of the second inverter 1221 serves as the output terminal of the first-stage first-delay signal output module 122, outputting the first-stage first-delay signal IN_P1. Other first-delay signal output modules 122 besides the first stage all include a rising edge delay unit 1222 and a second inverter 1221. The input terminal of the rising edge delay unit 1222 of the delayed signal output module 122 is connected to the second node Q2. The input terminals of the rising edge delay units 1222 of other first delayed signal output modules 122 are connected to the output terminals of the rising edge delay units 1222 of the previous stage first delayed signal output module 122. In the other first delayed signal output modules 122 besides the first stage, the input terminal of the second inverter 1221 is connected to the output terminal of the rising edge delay unit 1222, and the output terminal of the second inverter 1221 serves as the output terminal of the corresponding first delayed signal output module 122, outputting a first delayed signal IN_P. i (i = 2, 3, ..., n).

[0066] Optionally, such as Figure 9 As shown, in this embodiment, the pull-down slew rate control circuit 130 further includes a second control signal generation module 131.

[0067] In this embodiment, the first-stage second delay signal output module 132 includes a fifth inverter 1321. The input terminal of the fifth inverter 1321 is connected to the second control signal generation module 131. The connection point between the input terminal of the fifth inverter 1321 and the second control signal generation module 131 is the fifth node Q5. The output terminal of the fifth inverter 1321 serves as the output terminal of the first-stage second delay signal output module 132, outputting the first-stage second delay signal IN_N1. Other second delay signal output modules 132 besides the first stage all include a falling edge delay unit 1322 and a fifth inverter 1321. The input terminal of the falling edge delay unit 1322 of the delayed signal output module 132 is connected to the fifth node Q5. The input terminals of the falling edge delay units 1322 of the other second delayed signal output modules 132 are connected to the output terminals of the falling edge delay units 1322 of the previous stage second delayed signal output module 132. In the other second delayed signal output modules 132 besides the first stage, the input terminal of the fifth inverter 1321 is connected to the output terminal of the falling edge delay unit 1322, and the output terminal of the fifth inverter 1321 serves as the output terminal of the corresponding second delayed signal output module 132, outputting a second delayed signal IN_N. i (i = 2, 3, ..., n).

[0068] In this embodiment, with Figure 6 Unlike the previous embodiment, in this embodiment, the pull-up slew rate control circuit 120 does not require NAND gates; only inverters are needed. However, in this embodiment, because the pull-up slew rate control circuit 120 adjusts the delay of the falling edge of the first control signal IN_PB, and multiple first delayed signals IN_PB... i The signal first passes through a delay unit and then through a second inverter 1221 before being output. Therefore, in order to achieve delay adjustment of the falling edge of the first control signal IN_PB, the delay unit in the pull-up slew rate control circuit 120 in this embodiment needs to be set as a rising edge delay unit 1222.

[0069] Similarly, in this embodiment, the pull-down slew rate control circuit 130 does not need to use NOR gate units; only an inverter is required. However, in this embodiment, because the pull-down slew rate control circuit 130 adjusts the rising edge of the second control signal IN_NB, and multiple second delayed signals IN_NB... i The signal first passes through a delay unit and then through the fifth inverter 1321 for output. Therefore, in order to achieve delay adjustment of the rising edge of the second control signal IN_NB, the delay unit in the pull-down slew rate control circuit 130 in this embodiment needs to be set as a falling edge delay unit 1322.

[0070] Furthermore, the timing diagram of the external chip driver circuit 100 in this embodiment is as described above. Figure 7As shown, the control principle for adjusting the drive signal is the same as described above, and will not be repeated here.

[0071] Optionally, in other embodiments, the pull-up slew rate control circuit 120 and the pull-down slew rate control circuit 130 may also have other circuit structures. Please refer to [link to relevant documentation]. Figure 10 , Figure 10 This is a schematic diagram of the fifth embodiment of the chip external driver circuit provided in this application. Figure 10 As shown, the pull-up slew rate control circuit 120 in this embodiment also includes a first control signal generation module 121.

[0072] In this embodiment, the first-stage first delay signal output module 122 includes a third inverter 1221. The input terminal of the third inverter 1221 is connected to the first control signal generation module 121, and the output terminal of the third inverter 1221 is the third node Q3. The third node Q3 serves as the output terminal of the first-stage first delay signal output module 122, outputting the first-stage first delay signal IN_P1. All other first delay signal output modules 122, except for the first stage, include a falling edge delay unit 1222. The input terminal of the falling edge delay unit 1222 of the second-stage first delay signal output module 122 is connected to the third node Q3, and the input terminal of the falling edge delay unit 1222 of the other first delay signal output modules 122 is connected to the output terminal of the falling edge delay unit 1222 of the previous stage first delay signal output module 122. In the other first delay signal output modules 122, except for the first stage, the output terminal of the falling edge delay unit 1222 serves as the output terminal of the corresponding first delay signal output module 122, outputting a first delay signal IN_P. i (i = 2, 3, ..., n).

[0073] Optionally, such as Figure 10As shown, in this embodiment, the pull-down slew rate control circuit 130 further includes a second control signal generation module 131; the first-stage second delay signal output module 132 includes a sixth inverter 1321, the input terminal of the sixth inverter 1321 is connected to the second control signal generation module 131, and the output terminal of the sixth inverter 1321 is the sixth node Q6. The sixth node Q6 serves as the output terminal of the first-stage second delay signal output module 132, outputting the first-stage second delay signal IN_N1; all other second delay signal output modules 132 besides the first stage include rising edge delay... The input terminal of the rising edge delay unit 1322 of the second-stage second delay signal output module 132 is connected to the sixth node Q6. The input terminals of the rising edge delay units 1322 of other second delay signal output modules 132 are connected to the output terminals of the rising edge delay units 1322 of the previous stage second delay signal output module 132. In the other second delay signal output modules 132 besides the first stage, the output terminal of the rising edge delay unit 1322 serves as the output terminal of the corresponding second delay signal output module 132, outputting a second delay signal IN_N. i (i = 2, 3, ..., n).

[0074] In this embodiment, with Figure 9 Unlike the previous embodiment, in this embodiment, the pull-up slew rate control circuit 120 does not need to provide an inverter in each first delay signal output module 122; only one inverter is required. In this embodiment, because the pull-up slew rate control circuit 120 adjusts the delay of the falling edge of the first control signal IN_PB, and multiple first delay signals IN_PB... i The signal first passes through the third inverter 1221 and then through the delay unit before being output. Therefore, in order to achieve delay adjustment of the falling edge of the first control signal IN_PB, the delay unit in the pull-up slew rate control circuit 120 of this embodiment and... Figure 9 The implementation is different and needs to be set as a falling edge delay unit 1222.

[0075] Similarly, in this embodiment, the pull-up slew rate control circuit 130 does not need to set an inverter in each second delay signal output module 132; only one inverter is required. In this embodiment, since the pull-down slew rate control circuit 130 adjusts the delay of the rising edge of the second control signal IN_NB, and multiple second delay signals IN_NB... i The signal first passes through the sixth inverter 1321 and then through the delay unit for output. Therefore, in order to achieve delay adjustment of the rising edge of the second control signal IN_NB, the delay unit in the pull-down slew rate control circuit 130 in this embodiment needs to be set as the rising edge delay unit 1322.

[0076] Furthermore, the timing diagram of the external chip driver circuit 100 in this embodiment is as described above. Figure 7 As shown, the control principle for adjusting the drive signal is the same as described above, and will not be repeated here.

[0077] Optionally, based on Figure 9 and Figure 10 For an example, please refer to the following: Figure 11 , Figure 11 This is a schematic diagram of an embodiment of the rising edge delay unit provided in this application. In this embodiment, the rising edge delay unit includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a third resistor R3, and a fourth resistor R4.

[0078] In this circuit, the first terminal of the third transistor M3 receives a preset voltage, the second terminal of the third transistor M3 is connected to the first terminal of the third resistor R3, and the connection between the second terminal of the third transistor M3 and the first terminal of the third resistor R3 serves as the seventh node Q7. The second terminal of the third resistor R3 is connected to the first terminal of the fourth transistor M4, and the second terminal of the fourth transistor M4 is grounded. The control terminals of the third transistor M3 and the fourth transistor M4 serve as the input terminals of the rising edge delay unit. The seventh node Q7 is connected to the control terminals of the fifth transistor M5 and the sixth transistor M6. The first terminal of the fifth transistor M5 receives a preset voltage, the second terminal of the fifth transistor M5 is connected to the first terminal of the fourth resistor R4, the second terminal of the fourth resistor R4 is connected to the first terminal of the sixth transistor M6, and the second terminal of the sixth transistor M6 is grounded. The connection between the second terminal of the fourth resistor R4 and the first terminal of the sixth transistor M6 serves as the eighth node Q8, and the eighth node Q8 serves as the output terminal of the rising edge delay unit. The third transistor M3 and the fifth transistor M5 are PMOS transistors, and the fourth transistor M4 and the sixth transistor M6 are NMOS transistors.

[0079] Optionally, based on Figure 9 and Figure 10 For an example, please refer to the following: Figure 12 , Figure 12 This is a schematic diagram of an embodiment of the falling edge delay unit provided in this application. In this embodiment, the falling edge delay unit includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a fifth resistor R5, and a sixth resistor R6.

[0080] In this configuration, the first terminal of the seventh transistor M7 receives a preset voltage, the second terminal of the seventh transistor M7 is connected to the first terminal of the fifth resistor R5, the second terminal of the fifth resistor R5 is connected to the first terminal of the eighth transistor M8, and the connection between the second terminal of the fifth resistor R5 and the first terminal of the eighth transistor M8 serves as the ninth node Q9. The second terminal of the eighth transistor M8 is grounded, and the control terminals of the seventh transistor M7 and the eighth transistor M8 serve as the input terminals of the falling edge delay unit. The ninth node Q9 is connected to the control terminals of the ninth transistor M9 and the tenth transistor M10. The first terminal of the ninth transistor M9 receives a preset voltage, the second terminal of the ninth transistor M9 is connected to the first terminal of the sixth resistor R6, the second terminal of the sixth resistor R6 is connected to the first terminal of the tenth transistor M10, the second terminal of the tenth transistor M10 is grounded, and the connection between the second terminal of the ninth transistor M9 and the first terminal of the sixth resistor R6 serves as the tenth node Q9. 10 The tenth node Q 10 As the output terminal of the falling edge delay unit; wherein, the seventh transistor M7 and the ninth transistor M9 are PMOS transistors, and the eighth transistor M8 and the tenth transistor M10 are NMOS transistors.

[0081] Optionally, this application further proposes a memory, see [link to relevant documentation]. Figure 13 , Figure 13 This is a schematic diagram of the structure of an embodiment of the memory provided in this application. Figure 13 As shown, the memory 200 of this embodiment includes the chip external driver circuit 100 of any of the above embodiments.

[0082] In this embodiment, the memory 200 can be random access memory (DRAM), static random access memory (SRAM), or pseudo static random access memory (PSRAM), and no limitation is imposed here.

[0083] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A chip external driver circuit, characterized in that, The external driver circuit for use in memory includes: A driving circuit is used to generate driving signals for the interface of the memory. A pull-up slew rate control circuit, connected to the drive circuit, is used to delay the falling edge of the first control signal and generate multiple first delay signals to adjust the pull-up slew rate of the drive signal. A pull-down slew rate control circuit, connected to the drive circuit, is used to delay the rising edge of the second control signal and generate multiple second delay signals to adjust the pull-down slew rate of the drive signal. The driving circuit includes multiple parallel driving sub-circuits. Each driving sub-circuit includes a first transistor coupled to the power supply voltage and a second transistor coupled to ground. When the pull-up slew rate control circuit adjusts the pull-up slew rate of the driving signal, multiple second delay signals control all second transistors in all driving sub-circuits to turn off simultaneously, and multiple first delay signals control the first transistors in each stage of the driving sub-circuit to turn on sequentially. And / or when the pull-down slew rate control circuit adjusts the pull-down slew rate of the driving signal, multiple first delay signals control all first transistors in all driving sub-circuits to turn off simultaneously, and multiple second delay signals control the second transistors in each stage of the driving sub-circuit to turn on sequentially.

2. The chip external driver circuit according to claim 1, characterized in that, Each of the aforementioned driving sub-circuits further includes a first resistor and a second resistor; The first transistor receives the power supply voltage at its first path terminal and receives a first delay signal at its control terminal. The first terminal of the first resistor is connected to the second path terminal of the first transistor. The first terminal of the second resistor is connected to the second terminal of the first resistor, and the connection between the first terminal of the second resistor and the second terminal of the first resistor serves as the output terminal of the driving sub-circuit. The first path terminal of the second transistor is connected to the second terminal of the second resistor, the control terminal of the second transistor receives a second delay signal, and the second path terminal of the second transistor is grounded. The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

3. The chip external driver circuit according to claim 1, characterized in that, The pull-up slew rate control circuit includes multiple series-connected first delay signal output modules. Each first delay signal output module is used to output a first delay signal, and the falling edge of the first delay signal output by the later first delay signal output module is time-shifted by a corresponding delay compared to the falling edge of the first delay signal output by the previous first delay signal output module.

4. The chip external driver circuit according to claim 3, characterized in that, The pull-up slew rate control circuit also includes a first control signal generation module, and each stage of the first delay signal output module is connected to the first control signal generation module. The first stage first delay signal output module includes a first inverter. The input terminal of the first inverter is connected to the first control signal generation module. The connection between the input terminal of the first inverter and the first control signal generation module serves as a first node. The output terminal of the first inverter serves as the output terminal of the first stage first delay signal output module to output the first stage first delay signal. All first delay signal output modules except the first stage include a first delay unit and a NAND gate unit. The input terminal of the first delay unit of the second stage first delay signal output module is connected to the first node. The input terminal of the first delay unit of the other first delay signal output modules is connected to the output terminal of the first delay unit of the previous stage first delay signal output module. In the other first delay signal output modules except the first stage, the first input terminal of the NAND gate unit is connected to the first control signal generation module, the second input terminal of the NAND gate unit is connected to the output terminal of the first delay unit, and the output terminal of the NAND gate serves as the output terminal of the corresponding first delay signal output module to output a first delay signal.

5. The chip external driver circuit according to claim 3, characterized in that, The pull-up slew rate control circuit also includes a first control signal generation module; The first stage first delay signal output module includes a second inverter. The input terminal of the second inverter is connected to the first control signal generation module. The connection point between the input terminal of the second inverter and the first control signal generation module is a second node. The output terminal of the second inverter serves as the output terminal of the first stage first delay signal output module to output the first stage first delay signal. All first delay signal output modules except the first stage include a rising edge delay unit and a second inverter. The input terminal of the rising edge delay unit of the second stage first delay signal output module is connected to the second node. The input terminal of the rising edge delay unit of the other first delay signal output modules is connected to the output terminal of the rising edge delay unit of the previous stage first delay signal output module. In the other first delay signal output modules except the first stage, the input terminal of the second inverter is connected to the output terminal of the rising edge delay unit, and the output terminal of the second inverter serves as the output terminal of the corresponding first delay signal output module to output a first delay signal.

6. The chip external driver circuit according to claim 3, characterized in that, The pull-up slew rate control circuit also includes a first control signal generation module; The first stage first delay signal output module includes a third inverter. The input terminal of the third inverter is connected to the first control signal generation module. The output terminal of the third inverter is a third node. The third node serves as the output terminal of the first stage first delay signal output module to output the first stage first delay signal. All first delay signal output modules except the first stage include a falling edge delay unit. The input terminal of the falling edge delay unit of the second stage first delay signal output module is connected to the third node. The input terminal of the falling edge delay unit of the other first delay signal output modules is connected to the output terminal of the falling edge delay unit of the previous stage first delay signal output module. In the other first delay signal output modules except the first stage, the output terminal of the falling edge delay unit serves as the output terminal of the corresponding first delay signal output module to output a first delay signal.

7. The chip external driver circuit according to claim 2, characterized in that, The pull-down slew rate control circuit includes multiple stages of second delay signal output modules connected in series. Each stage of the second delay signal output module is used to output a second delay signal, and the rising edge of the second delay signal output by the later stage of the second delay signal output module is time-shifted by a corresponding delay compared to the rising edge of the second delay signal output by the previous stage of the second delay signal output module.

8. The chip external driver circuit according to claim 7, characterized in that, The pull-down slew rate control circuit also includes a second control signal generation module, and each stage of the second delay signal output module is connected to the second control signal generation module. The first-stage second-delay signal output module includes a fourth inverter. The input terminal of the fourth inverter is connected to the second control signal generation module. The connection between the input terminal of the fourth inverter and the second control signal generation module serves as the fourth node. The output terminal of the fourth inverter serves as the output terminal of the first-stage second-delay signal output module, outputting the second-delay signal of the first stage. All second-delay signal output modules other than the first stage include a second delay unit and a NOR gate unit. The input terminal of the second delay unit of the second-stage second-delay signal output module is connected to the fourth node, and the input terminal of the second delay unit of the other second-delay signal output modules is connected to the output terminal of the second delay unit of the previous stage second-delay signal output module. In the other second-delay signal output modules other than the first stage, the first input terminal of the NOR gate unit is connected to the second control signal generation module, the second input terminal of the NOR gate unit is connected to the output terminal of the second delay unit, and the output terminal of the NOR gate unit outputs a second delay signal as the output terminal of the corresponding second-delay signal output module.

9. The chip external driver circuit according to claim 7, characterized in that, The pull-down slew rate control circuit also includes a second control signal generation module; The first-stage second-delay signal output module includes a fifth inverter. The input terminal of the fifth inverter is connected to the second control signal generation module. The connection point between the input terminal of the fifth inverter and the second control signal generation module is the fifth node. The output terminal of the fifth inverter serves as the output terminal of the first-stage second-delay signal output module, outputting the second-delay signal of the first stage. All second-delay signal output modules other than the first stage include a falling edge delay unit and the fifth inverter. The input terminal of the falling edge delay unit of the second-stage second-delay signal output module is connected to the fifth node. The input terminal of the falling edge delay unit of the other second-delay signal output modules is connected to the output terminal of the falling edge delay unit of the previous stage second-delay signal output module. In the other second-delay signal output modules other than the first stage, the input terminal of the fifth inverter is connected to the output terminal of the falling edge delay unit, and the output terminal of the fifth inverter serves as the output terminal of the corresponding second-delay signal output module to output a second-delay signal.

10. The chip external driver circuit according to claim 7, characterized in that, The pull-down slew rate control circuit also includes a second control signal generation module; The first-stage second-delay signal output module includes a sixth inverter. The input terminal of the sixth inverter is connected to the second control signal generation module. The output terminal of the sixth inverter is a sixth node. The sixth node serves as the output terminal of the first-stage second-delay signal output module to output the second-delay signal of the first stage. All second delay signal output modules except the first stage include a rising edge delay unit. The input terminal of the rising edge delay unit of the second stage second delay signal output module is connected to the sixth node. The input terminal of the rising edge delay unit of the other second delay signal output modules is connected to the output terminal of the rising edge delay unit of the previous stage second delay signal output module. In the other second delay signal output modules except the first stage, the output terminal of the rising edge delay unit serves as the output terminal of the corresponding second delay signal output module to output a second delay signal.

11. The chip external driver circuit according to claim 5 or 10, characterized in that, The rising edge delay unit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third resistor, and a fourth resistor; the first path terminal of the third transistor receives a preset voltage, the second path terminal of the third transistor is connected to the first terminal of the third resistor, the connection point of the second path terminal of the third transistor and the first terminal of the third resistor serves as a seventh node, the second terminal of the third resistor is connected to the first path terminal of the fourth transistor, the second path terminal of the fourth transistor is grounded, and the control terminals of the third transistor and the fourth transistor serve as the input terminals of the rising edge delay unit; the seventh node is connected to the control terminals of the fifth transistor and the sixth transistor, the first path terminal of the fifth transistor receives the preset voltage, the second path terminal of the fifth transistor is connected to the first terminal of the fourth resistor, the second terminal of the fourth resistor is connected to the first path terminal of the sixth transistor, the second path terminal of the sixth transistor is grounded, the connection point of the second terminal of the fourth resistor and the first path terminal of the sixth transistor serves as an eighth node, and the eighth node serves as the output terminal of the rising edge delay unit; wherein, the third transistor and the fifth transistor are PMOS transistors, and the fourth transistor and the sixth transistor are NMOS transistors.

12. The chip external driver circuit according to claim 6 or 9, characterized in that, The falling edge delay unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a fifth resistor, and a sixth resistor; the first terminal of the seventh transistor receives a preset voltage, the second terminal of the seventh transistor is connected to the first terminal of the fifth resistor, the second terminal of the fifth resistor is connected to the first terminal of the eighth transistor, the connection point between the second terminal of the fifth resistor and the first terminal of the eighth transistor serves as the ninth node, the second terminal of the eighth transistor is grounded, and the control terminals of the seventh transistor and the eighth transistor serve as the input terminals of the falling edge delay unit; the ninth node is connected to the control terminals of the ninth transistor and the tenth transistor, the first terminal of the ninth transistor receives the preset voltage, the second terminal of the ninth transistor is connected to the first terminal of the sixth resistor, the second terminal of the sixth resistor is connected to the first terminal of the tenth transistor, the second terminal of the tenth transistor is grounded, the connection point between the second terminal of the ninth transistor and the first terminal of the sixth resistor serves as the tenth node, and the tenth node serves as the output terminal of the falling edge delay unit; wherein, the seventh transistor and the ninth transistor are PMOS transistors, and the eighth transistor and the tenth transistor are NMOS transistors.

13. A memory, characterized in that, Includes the chip external driver circuit as described in any one of claims 1-12.

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