APB-based peripheral access system and access method, storage medium and chip

Abstract

The invention discloses an APB-based peripheral access system, an APB-based peripheral access method, a storage medium and a chip, and belongs to the technical field of chips. The Cross-Bar forwards the access request of the target host to the target APB DEMUX; the target APB DEMUX converts the access request into a shared signal and a PSEL signal and a PENAL signal of each peripheral, sends the shared signal to a gating unit of each peripheral, and sends the PSEL signal and the PENAL signal of each peripheral to the peripheral; when the corresponding peripheral is the target peripheral, the gating unit sends a sharing signal to the target peripheral; when the corresponding peripheral is not the target peripheral, shielding the shared signal from the peripheral; and the target peripheral communicates with the target host according to the PSEL signal, the PENABLE signal and the shared signal. According to the invention, unnecessary flipping of the combinational logic unit in the non-target peripheral due to flipping of the shared signal can be avoided, and power consumption can be saved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a peripheral access system, access method, storage medium, and chip based on APB. Background Art

[0002] Inside an Advanced Peripheral Bus (APB) peripheral, there is a configuration register array. The host reads and writes the configuration registers through the APB bus to complete the information interaction between the processor and the peripheral. As Figure 1 shown, the information interaction between multiple hosts and multiple peripherals is mainly implemented by cascading a Cross-Bar and an APB Demultiplexer (DEMUX). Specifically, the APB DEMUX decodes and splits a group of APB buses into multiple groups of APB buses according to specific address blocks to achieve time-sharing control and interaction between the host and the peripherals, which can reduce the design complexity of the Cross-Bar and achieve a balance between area and performance.

[0003] As Figure 2 shown, the address decoding unit in the APB DEMUX obtains the access requirements of the host for different peripherals, generates different PSEL signals and PENABLE signals for different peripherals according to the address decoding results generated by the access requirements, and shares other signals (such as PADDR, PWDATA, etc.) except the PSEL signal and the PENABLE signal with all peripherals.

[0004] Although multiple peripherals share the same access path through time-division multiplexing, which can effectively reduce the design complexity of the Cross-Bar, this will bring a broadcast effect to the shared signals (such as PADDR, PWDATA, etc.). For example, when the host writes data 0x55 to address 0xaa of peripheral 1, although the host is not accessing other peripherals at this time, due to the sharing of these shared signals, other peripherals can also see the flipping of the shared signals except PSEL and PENABLE. And the flipping of these shared signals will cause unnecessary power consumption waste for the peripherals. Summary of the Invention

[0005] This application provides a peripheral access system, access method, storage medium, and chip based on APB, which are used to solve the problem that when the host accesses a peripheral through the APB DEMUX, other peripherals will be affected by the flipped shared signals, resulting in unnecessary power consumption waste. The technical solutions are as follows:

[0006] According to a first aspect of the present application, a peripheral access system based on APB is provided. The peripheral access system includes multiple hosts, a crossbar matrix Cross-Bar, and at least one peripheral access group. The peripheral access group includes an APB demultiplexer DEMUX and at least one peripheral;

[0007] Each host is connected to an input terminal of the Cross-Bar. Each output terminal of the Cross-Bar is connected to the address decoding unit of the APB DEMUX in a peripheral access group. The address decoding unit is connected to a peripheral in the same group through each gating unit;

[0008] The target host is used to send an access request for the target peripheral to the Cross-Bar;

[0009] The Cross-Bar is used to determine the target APB DEMUX corresponding to the target peripheral according to the access request, and forward the access request to the target APB DEMUX through the APB bus;

[0010] The target APB DEMUX is used to convert the access request into a shared signal, and the PSEL signal and PENABLE signal of each peripheral through the address decoding unit, send the shared signal to the gating unit of each peripheral, and send the PSEL signal and PENABLE signal of each peripheral to the corresponding peripheral; wherein, the PSEL signal and PENABLE signal corresponding to the target peripheral are high-level signals, and the PSEL signals and PENABLE signals corresponding to other peripherals are low-level signals;

[0011] Each gating unit is used to send the shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and shield the shared signal from the peripheral when the corresponding peripheral is not the target peripheral;

[0012] The target peripheral is used to communicate with the target host according to the PSEL signal, the PENABLE signal, and the shared signal.

[0013] In a possible implementation manner, the target APB DEMUX is further used to send a control signal to each gating unit, and the control signal is the PSEL signal or the PENABLE signal;

[0014] The gating unit is used to send the shared signal to the target peripheral when the control signal is a high-level signal; and shield the shared signal from the peripheral when the control signal is a low-level signal.

[0015] In a possible implementation, the gating unit is located in the APB DEMUX. Then, the address decoding unit in one APB DEMUX is connected to each gating unit in the same group, and each gating unit is connected to a corresponding peripheral device.

[0016] In a possible implementation, the gating unit is located in the peripheral device. Then, the address decoding unit in one APB DEMUX is connected to the gating units in each peripheral device in the same group.

[0017] In a possible implementation, the peripheral device further includes a configuration register array. Each configuration register is connected to a combinational logic unit, and each combinational logic unit is connected to the corresponding gating unit and the address decoding unit;

[0018] The gating unit is used to send the shared signal to the combinational logic unit corresponding to the target peripheral device;

[0019] The address decoding unit is used to send the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral device;

[0020] The combinational logic unit is used to perform a logical operation on the PSEL signal, the PENABLE signal, and the shared signal, and send the operation result to the corresponding configuration register for corresponding read and write operations, so as to implement communication between the target peripheral device and the target host.

[0021] According to the second aspect of the present application, a method for accessing a peripheral device based on APB is provided for use in the peripheral device access system as described above. The method includes:

[0022] The target host sends an access request for a target peripheral device to the Cross-Bar;

[0023] The Cross-Bar determines the target APB DEMUX corresponding to the target peripheral device according to the access request, and forwards the access request to the target APB DEMUX through the APB bus;

[0024] The target APB DEMUX converts the access request into a shared signal and the PSEL signal and PENABLE signal of each peripheral device through the address decoding unit, sends the shared signal to the gating unit of each peripheral device, and sends the PSEL signal and PENABLE signal of each peripheral device to the corresponding peripheral device; wherein, the PSEL signal and PENABLE signal corresponding to the target peripheral device are high-level signals, and the PSEL signal and PENABLE signal corresponding to other peripheral devices are low-level signals;

[0025] When the corresponding peripheral of each gating unit is the target peripheral, the gating unit sends the shared signal to the target peripheral; when the corresponding peripheral is not the target peripheral, the gating unit shields the shared signal from the peripheral;

[0026] The target peripheral communicates with the host according to the PSEL signal, the PENABLE signal, and the shared signal.

[0027] In a possible implementation, the method further includes: the target APB DEMUX sends a control signal to each gating unit, and the control signal is the PSEL signal or the PENABLE signal;

[0028] Each gating unit sending the shared signal to the target peripheral when the corresponding peripheral is the target peripheral, and shielding the shared signal from the peripheral when the corresponding peripheral is not the target peripheral, includes:

[0029] Each gating unit sends the shared signal to the target peripheral when the control signal is a high-level signal, and shields the shared signal from the peripheral when the control signal is a low-level signal.

[0030] In a possible implementation, the method further includes:

[0031] When the peripheral further includes a configuration register array, the gating unit sends the shared signal to the combinational logic unit corresponding to the target peripheral;

[0032] The address decoding unit sends the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral;

[0033] The combinational logic unit performs a logical operation on the PSEL signal, the PENABLE signal, and the shared signal, and sends the operation result to the corresponding configuration register for corresponding read and write operations to implement communication between the target peripheral and the target host.

[0034] According to a third aspect of the present application, there is provided a computer-readable storage medium, in which at least one instruction is stored, and the at least one instruction is loaded and executed by a processor to implement the above-mentioned APB-based peripheral access method.

[0035] According to a fourth aspect of the present application, there is provided a chip, and the chip includes the above-mentioned APB-based peripheral access system.

[0036] The beneficial effects of the technical solution provided by the present application at least include:

[0037] By setting a gating unit between the APB DEMUX and each peripheral device, the transmission of the shared signal can be controlled by the gating unit. That is, when the peripheral device is the target peripheral device that the target host needs to access, the gating unit controls the shared signal to be visible to the peripheral device; when the peripheral device is not the target peripheral device that the target host needs to access, the gating unit controls the shared signal to be invisible to the peripheral device, which can avoid unnecessary flips of the combinational logic unit in the non-target peripheral device caused by the flip of the shared signal, thereby saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0039] Figure 1 is a schematic structural diagram of a peripheral device access based on APB shown according to the related art;

[0040] Figure 2 is a schematic connection diagram of an APB DEMUX and a peripheral device shown according to the related art;

[0041] Figure 3 is a schematic connection diagram of a configuration register array and a combinational logic unit in a peripheral device shown according to the related art;

[0042] Figure 4 is a structural diagram of a peripheral device access system based on APB provided by an embodiment of the present application;

[0043] Figure 5 is a schematic connection diagram of an APB DEMUX and a peripheral device provided by an embodiment of the present application;

[0044] Figure 6 is a schematic connection diagram of a configuration register array and a combinational logic unit in a peripheral device provided by an embodiment of the present application;

[0045] Figure 7 is a flowchart of a method for accessing a peripheral device based on APB provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings.

[0047] APB DEMUX is connected to multiple peripherals, each of which contains a configuration register array, which includes multiple configuration registers. The host can access each configuration register through the APB bus. The D pin in each configuration register is connected to a corresponding combinational logic unit, which includes a combination of logic devices such as AND gates, NOT gates, and OR gates. The corresponding combinational logic unit can be designed for each configuration register according to its actual needs.

[0048] like Figure 3 As shown, a combinatorial logic unit including comb1 and comb2 is used as an example. Among them, shared signals (such as PADDR / PWDATA / PWRITE / PSTRB / PPROT / PUSER, etc.) are input into comb1, and PSEL signal and PENABLE signal are input into comb2. When the shared signal is flipped, but the PSEL signal and PENABLE signal are not flipped, comb1 will still perform logic operations on the shared signal, causing unnecessary flipping of the combinatorial logic unit, thereby causing power consumption waste.

[0049] Among them, the PSEL (Peripheral Select) signal is a peripheral selection signal, and the peripheral can be activated by the PSEL signal. The PENABLE signal is an enable signal to notify the peripheral to start data transmission. The shared signal is a group of signals shared by multiple peripherals, which may include but are not limited to: PADDR, PWDATA, PWRITE, PSTRB, PPROT, PUSER. Among them, PADDR is the address signal, PWDATA is the write data signal, PWRITE is the write signal, PSTRB is the write pulse signal, PPROT is the protection type signal, and PUSER is a user-defined signal. In actual applications, the types of shared signals can be increased or decreased according to needs, and are not limited in this embodiment.

[0050] In order to solve this technical problem, a gating unit is added between the APB DEMUX and each peripheral in the present application, and the gating unit is used to determine whether to shield the shared signal of the peripheral. Specifically, when the host accesses a peripheral, the gating unit is used to unshield the peripheral so that the shared signal is visible to the peripheral; for other peripherals that are not accessed, the gating unit is used to shield the peripheral so that the shared signal is invisible to the peripheral.

[0051] like Figure 4As shown, it shows a block diagram of a peripheral access system based on APB provided by an embodiment of the present application. The peripheral access system based on APB includes: a plurality of hosts 410, a Cross-Bar 420, and at least one peripheral access group 430. The peripheral access group 430 includes an APB DEMUX 431 and at least one peripheral 432. The number of peripherals 432 in each peripheral access group 430 can be the same or different.

[0052] In this embodiment, each host 410 is connected to an input end of the Cross-Bar 420. Each output end of the Cross-Bar 420 is connected to the address decoding unit of the APB DEMUX 431 in a peripheral access group 430. The address decoding unit is connected to a peripheral 432 in the same group through each gating unit.

[0053] In one implementation, the gating unit is located in the APB DEMUX 431. Then, the address decoding unit in an APB DEMUX 431 is connected to each gating unit in the same group, and each gating unit is connected to a corresponding peripheral 432. As Figure 4 shown, if a peripheral access group 430 includes m peripherals, then the APB DEMUX 431 includes m gating units, and the address decoding unit is respectively connected to the m gating units; if another peripheral access group 430 includes n peripherals, then the APB DEMUX 431 includes n gating units, and the address decoding unit is respectively connected to the n gating units.

[0054] As Figure 5 shown, if a peripheral access group 430 includes an APB DEMUX 431 and three peripherals 432, then the address decoding unit in the APB DEMUX 431 is respectively connected to three gating units. The gating unit of peripheral 1 is connected to peripheral 1, the gating unit of peripheral 2 is connected to peripheral 2, and the gating unit of peripheral 3 is connected to peripheral 3.

[0055] In another implementation, the gating unit is located in the peripheral 432. Then, the address decoding unit in an APB DEMUX 431 is connected to the gating units in each peripheral 432 in the same group. That is, each peripheral 432 contains a gating unit, and the address decoding unit in the APB DEMUX 431 is connected to the gating units in each peripheral 432, Figure 4 not shown in the figure.

[0056] The access process of the peripheral access system will be described below.

[0057] (1) The target host 410 is used to send an access request for the target peripheral 432 to the Cross-Bar 420.

[0058] Each host 410 communicates with the Cross-Bar 420 through an Advanced eXtensible Interface (AXI) or an Advanced High-performance Bus (AHB), etc.

[0059] In this embodiment, the host accessing the peripheral is called the target host, and the peripheral to be accessed is called the target peripheral. Then, the target host 410 can generate an access request according to the address of the target peripheral 432 and the read / write requirement, and send the access request to the Cross-Bar 420 through the AXI bus or the AHB bus.

[0060] (2) The Cross-Bar 420 is used to determine the target APB DEMUX 431 corresponding to the target peripheral 432 according to the access request, and forward the access request to the target APB DEMUX 431 through the APB bus.

[0061] The Cross-Bar 420 communicates with each APB DEMUX 431 through the APB bus.

[0062] In this embodiment, the APB DEMUX corresponding to the target peripheral is called the target APB DEMUX. Then, the Cross-Bar 420 can determine the target APB DEMUX 431 corresponding to the target peripheral 432, and send the access request to the target APB DEMUX 431 through the APB bus.

[0063] (3) The target APB DEMUX 431 is used to convert the access request into a shared signal and the PSEL signal and PENABLE signal of each peripheral 432 through the address decoding unit, send the shared signal to the gating unit of each peripheral 432, and send the PSEL signal and PENABLE signal of each peripheral 432 to the corresponding peripheral 432; among them, the PSEL signal and PENABLE signal corresponding to the target peripheral 432 are high-level signals, and the PSEL signal and PENABLE signal corresponding to other peripherals 432 are low-level signals.

[0064] In this embodiment, each peripheral 432 in a peripheral access group 430 corresponds to a set of PSEL signals and PENABLE signals, and all peripherals 432 correspond to a set of shared signals. As Figure 5As shown, peripheral 1 corresponds to psel_out[0] and penable_out[0], peripheral 2 corresponds to psel_out[1] and penable_out[1], peripheral 3 corresponds to psel_out[2] and penable_out[2], and peripherals 1 - 3 all correspond to pwrite[31:0] and paddr[31:0].

[0065] Assume that the target peripheral 432 that the target host 410 needs to access is peripheral 1. Then, psel_out[0] and penable_out[0] are high - level signals, and psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low - level signals.

[0066] (4) Each gating unit is used to send a shared signal to the target peripheral 432 when the corresponding peripheral 432 is the target peripheral 432; and to mask the shared signal from the peripheral 432 when the corresponding peripheral 432 is not the target peripheral 432.

[0067] In this embodiment, the gating unit can be controlled by a control signal. Specifically, the target APB DEMUX 431 is also used to send the control signal to each gating unit. The control signal is a PSEL signal or a PENABLE signal; the gating unit is used to send a shared signal to the target peripheral 432 when the control signal is a high - level signal; and to mask the shared signal from the peripheral 432 when the control signal is a low - level signal.

[0068] Assume that the target peripheral 432 that the target host 410 needs to access is peripheral 1. Then, psel_out[0] and penable_out[0] are high - level signals, that is, the control signal is a high - level signal, which can control the gating unit to send a shared signal to peripheral 1; psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low - level signals, that is, the control signal is a low - level signal, which can control the two gating units to mask the shared signal from peripheral 2 and peripheral 3 respectively.

[0069] (5) The target peripheral 432 is used to communicate with the target host 410 according to the PSEL signal, PENABLE signal, and shared signal.

[0070] The target peripheral 432 can write the data sent by the target host 410 into the configuration register to implement a write operation; or, the target peripheral 432 can send the data in the configuration register to the target host 410 to implement a read operation.

[0071] In this embodiment, the peripheral device 432 further includes a configuration register array. Each configuration register is connected to a combinational logic unit, and each combinational logic unit is connected to a corresponding gating unit and address decoding unit. The gating unit is configured to send a shared signal to the combinational logic unit corresponding to the target peripheral device 432. The address decoding unit is configured to send the PSEL signal and PENABLE signal to the combinational logic unit corresponding to the target peripheral device 432. The combinational logic unit is configured to perform a logical operation on the PSEL signal, PENABLE signal, and shared signal, and send the operation result to the corresponding configuration register for corresponding read and write operations, so as to implement communication between the target peripheral device 432 and the target host 410.

[0072] As Figure 6 shown, still taking the combinational logic unit including comb1 and comb2 as an example, the shared signals (such as PADDR / PWDATA / PWRITE / PSTRB / PPROT / PUSER, etc.) are input into the gating unit, and the PSEL signal and PENABLE signal are input into the gating unit and comb2. Only when the PSEL signal and PENABLE signal input to the gating unit are inverted (to a high-level signal), the gating unit will output the shared signal to comb1, and comb1 and comb2 will perform a logical operation on the PSEL signal, PENABLE signal, and shared signal, so as to control the combinational logic unit to generate an inversion, so as to implement the read and write operations on the configuration register. When the PSEL signal and PENABLE signal input to the gating unit are not inverted (to a low-level signal), the gating unit will mask the shared signal for comb1, and comb1 and comb2 will not perform a logical operation on the shared signal, nor will it cause unnecessary inversion of the combinational logic unit, thus saving power consumption.

[0073] For an asynchronous APB bus, the PSEL signal and PENABLE signal are in the same clock domain (CLK Domain) as the peripheral device 432, and the shared signal belongs to another source clock domain. Static Timing Analysis (STA) can only ensure that the PSEL signal and PENABLE signal in the clock domain have stable outputs and there is no glitch phenomenon, and it cannot ensure that the shared signal in the source clock domain does not have a glitch phenomenon. Therefore, for the unaccessed peripheral device 432, by masking the shared signal through the gating unit, the glitch phenomenon of the peripheral device 432 caused by the shared signal can be avoided.

[0074] In summary, in the peripheral access system based on APB provided by the embodiments of the present application, by setting a gating unit between the APB DEMUX and each peripheral, it is possible to control the transmission of the shared signal by the gating unit, that is, when the peripheral is the target peripheral that the target host needs to access, the gating unit controls the shared signal to be visible to the peripheral; when the peripheral is not the target peripheral that the target host needs to access, the gating unit controls the shared signal to be invisible to the peripheral, which can avoid unnecessary flips of the combinational logic unit in the non-target peripheral caused by the flip of the shared signal, thereby saving power consumption.

[0075] As Figure 7 shown, it shows a flowchart of a method for accessing a peripheral based on APB provided by an embodiment of the present application. This method for accessing a peripheral based on APB can be applied to a chip. This method for accessing a peripheral based on APB may include:

[0076] Step 701, the target host sends an access request for the target peripheral to the Cross-Bar.

[0077] In this embodiment, the host accessing the peripheral is called the target host, and the peripheral to be accessed is called the target peripheral. Then, the target host can generate an access request according to the address and read / write requirements of the target peripheral, and send the access request to the Cross-Bar through the AXI bus or the AHB bus.

[0078] Step 702, the Cross-Bar determines the target APB DEMUX corresponding to the target peripheral according to the access request, and forwards the access request to the target APB DEMUX through the APB bus.

[0079] In this embodiment, the APB DEMUX corresponding to the target peripheral is called the target APB DEMUX. Then, the Cross-Bar can determine the target APB DEMUX corresponding to the target peripheral and send the access request to the target APB DEMUX through the APB bus.

[0080] Step 703, the target APB DEMUX converts the access request into a shared signal, and the PSEL signal and PENABLE signal of each peripheral through the address decoding unit, sends the shared signal to the gating unit of each peripheral, and sends the PSEL signal and PENABLE signal of each peripheral to the corresponding peripheral; wherein, the PSEL signal and PENABLE signal corresponding to the target peripheral are high-level signals, and the PSEL signal and PENABLE signal corresponding to other peripherals are low-level signals.

[0081] In this embodiment, each peripheral in a peripheral access group corresponds to a set of PSEL signals and PENABLE signals, and all peripherals correspond to a set of shared signals. AsFigure 5 As shown, peripheral 1 corresponds to psel_out[0] and penable_out[0], peripheral 2 corresponds to psel_out[1] and penable_out[1], peripheral 3 corresponds to psel_out[2] and penable_out[2], and peripherals 1-3 all correspond to pwrite[31:0] and paddr[31:0].

[0082] Assume that the target peripheral that the target host needs to access is peripheral 1. Then psel_out[0] and penable_out[0] are high-level signals, and psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low-level signals.

[0083] Step 704: Each gating unit sends a shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and shields the shared signal from the peripheral when the corresponding peripheral is not the target peripheral.

[0084] In this embodiment, the gating unit can be controlled by a control signal. Specifically, the target APB DEMUX sends the control signal to each gating unit, and the control signal is a PSEL signal or a PENABLE signal; then each gating unit sends a shared signal to the target peripheral when the control signal is a high-level signal; and shields the shared signal from the peripheral when the control signal is a low-level signal.

[0085] Assume that the target peripheral that the target host needs to access is peripheral 1. Then psel_out[0] and penable_out[0] are high-level signals, that is, the control signal is a high-level signal, which can control the gating unit to send a shared signal to peripheral 1; psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low-level signals, that is, the control signal is a low-level signal, which can control the two gating units to shield the shared signal from peripheral 2 and peripheral 3 respectively.

[0086] Step 705: The target peripheral communicates with the host according to the PSEL signal, PENENABLE signal and shared signal.

[0087] The target peripheral can write the data sent by the target host into the configuration register to implement a write operation; or, the target peripheral can send the data in the configuration register to the target host to implement a read operation.

[0088] In this embodiment, when the peripheral device further includes a configuration register array, the gating unit sends the shared signal to the combinational logic unit corresponding to the target peripheral device; the address decoding unit sends the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral device; the combinational logic unit performs a logical operation on the PSEL signal, the PENABLE signal, and the shared signal, and sends the operation result to the corresponding configuration register for corresponding read and write operations to implement communication between the target peripheral device and the target host.

[0089] As Figure 6 shown, still taking the combinational logic unit including comb1 and comb2 as an example, the shared signals (such as PADDR / PWDATA / PWRITE / PSTRB / PPROT / PUSER, etc.) are input into the gating unit, and the PSEL signal and the PENABLE signal are input into the gating unit and comb2. Only when the PSEL signal and the PENABLE signal input to the gating unit are inverted (to a high-level signal), the gating unit will output the shared signal to comb1, and comb1 and comb2 will perform a logical operation on the PSEL signal, the PENABLE signal, and the shared signal, so as to control the combinational logic unit to generate an inversion to implement the read and write operations of the configuration register. When the PSEL signal and the PENABLE signal input to the gating unit are not inverted (to a low-level signal), the gating unit will mask the shared signal for comb1, and comb1 and comb2 will not perform a logical operation on the shared signal, thus not causing unnecessary inversion of the combinational logic unit, thereby saving power consumption.

[0090] For an asynchronous APB bus, the PSEL signal and the PENABLE signal are in the same clock domain (CLKDomain) as the peripheral device, and the shared signal belongs to another source clock domain. Static Timing Analysis (STA) can only ensure stable output of the PSEL signal and the PENABLE signal in the clock domain without glitch phenomenon, and cannot ensure that the shared signal in the source clock domain does not have a glitch phenomenon. Therefore, for unaccessed peripheral devices, by masking the shared signal through the gating unit, it is possible to avoid the glitch phenomenon of the peripheral device caused by the shared signal.

[0091] In summary, for the peripheral access method based on APB provided by the embodiments of the present application, by setting a gating unit between the APB DEMUX and each peripheral, it is possible to control the transmission of shared signals by the gating unit. That is, when the peripheral is the target peripheral that the target host needs to access, the gating unit controls the shared signals to be visible to the peripheral; when the peripheral is not the target peripheral that the target host needs to access, the gating unit controls the shared signals to be invisible to the peripheral, which can avoid unnecessary flips of the combinational logic units in the non-target peripheral caused by the flipping of the shared signals, thereby saving power consumption.

[0092] An embodiment of the present application provides a computer-readable storage medium, in which at least one instruction is stored, and the at least one instruction is loaded and executed by a processor to implement the above-mentioned peripheral access method based on APB.

[0093] An embodiment of the present application provides a chip, and the chip includes any of the above-mentioned peripheral access systems based on APB.

[0094] It should be noted that: when the above-mentioned peripheral access system based on APB performs peripheral access based on APB, only the division of the above-mentioned functional modules is used for illustration. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the peripheral access system based on APB is divided into different functional modules to complete all or part of the functions described above. In addition, the above-mentioned peripheral access system based on APB provided by the embodiments and the embodiments of the peripheral access method based on APB belong to the same concept, and the specific implementation process is detailed in the method embodiments and will not be repeated here.

[0095] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0096] The above description is not intended to limit the embodiments of the present application. Any adjustment, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A peripheral access system based on APB, characterized in that: The peripheral access system includes a plurality of hosts, a crossbar switch matrix Cross-Bar and at least one peripheral access group, wherein the peripheral access group includes an APB demultiplexer DEMUX and at least one peripheral; Each host is connected to an input end of the Cross-Bar, each output end of the Cross-Bar is connected to an address decoding unit of an APB DEMUX in a peripheral access group, and the address decoding unit is connected to a peripheral in the same group through each gating unit; The target host is used to send an access request to the target peripheral device to the Cross-Bar; The Cross-Bar is used to determine the target APB DEMUX corresponding to the target peripheral device according to the access request, and forward the access request to the target APB DEMUX through the APB bus; The target APB DEMUX is used to convert the access request into a shared signal and a PSEL signal and a PENABLE signal of each peripheral through the address decoding unit, send the shared signal to the gating unit of each peripheral, and send the PSEL signal and the PENABLE signal of each peripheral to the corresponding peripheral; wherein the PSEL signal and the PENABLE signal corresponding to the target peripheral are high level signals, and the PSEL signal and the PENABLE signal corresponding to other peripherals are low level signals; Each gating unit is used to send the shared signal to the target peripheral device when the corresponding peripheral device is the target peripheral device; and shield the shared signal from the peripheral device when the corresponding peripheral device is not the target peripheral device; The target peripheral is used to communicate with the target host according to the PSEL signal, the PENABLE signal and the shared signal.

2. The APB-based peripheral access system according to claim 1, characterized in that: The target APB DEMUX is further used to send a control signal to each gating unit, wherein the control signal is the PSEL signal or the PENABLE signal; The gating unit is used for sending the shared signal to the target peripheral device when the control signal is a high-level signal; and shielding the shared signal from the peripheral device when the control signal is a low-level signal.

3. The APB-based peripheral access system according to claim 1, characterized in that: The gating unit is located in the APB DEMUX, and the address decoding unit in an APB DEMUX is connected to each gating unit in the same group, and each gating unit is connected to a corresponding peripheral.

4. The APB-based peripheral access system according to claim 1, characterized in that: The gating unit is located in the peripheral device, and the address decoding unit in one APB DEMUX is connected to the gating unit in each peripheral device in the same group.

5. The APB-based peripheral access system according to any one of claims 1 to 4, characterized in that: The peripheral device further comprises a configuration register array, each configuration register is connected to a combinational logic unit, each combinational logic unit is connected to a corresponding gating unit and the address decoding unit; The gating unit is used to send the shared signal to the combinational logic unit corresponding to the target peripheral device; The address decoding unit is used to send the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral device; The combinational logic unit is used to perform logic operations on the PSEL signal, the PENABLE signal and the shared signal, and send the operation results to the corresponding configuration registers for corresponding read and write operations, so as to realize communication between the target peripheral and the target host.

6. A peripheral access method based on APB, characterized in that: Used in the peripheral access system according to any one of claims 1 to 5, the method comprising: The target host sends an access request to the target peripheral device to the Cross-Bar; The Cross-Bar determines the target APB DEMUX corresponding to the target peripheral device according to the access request, and forwards the access request to the target APB DEMUX via an APB bus; The target APB DEMUX converts the access request into a shared signal and a PSEL signal and a PENABLE signal of each peripheral through the address decoding unit, sends the shared signal to the gating unit of each peripheral, and sends the PSEL signal and the PENABLE signal of each peripheral to the corresponding peripheral; wherein the PSEL signal and the PENABLE signal corresponding to the target peripheral are high level signals, and the PSEL signal and the PENABLE signal corresponding to other peripherals are low level signals; Each gating unit sends the shared signal to the target peripheral device when the corresponding peripheral device is the target peripheral device; and shields the shared signal from the peripheral device when the corresponding peripheral device is not the target peripheral device; The target peripheral communicates with the host according to the PSEL signal, the PENABLE signal, and the shared signal.

7. The APB-based peripheral access method according to claim 6, characterized in that: The method further includes: the target APB DEMUX sending a control signal to each gating unit, the control signal being the PSEL signal or the PENABLE signal; Each of the gating units sends the shared signal to the target peripheral device when the corresponding peripheral device is the target peripheral device; and shields the shared signal from the peripheral device when the corresponding peripheral device is not the target peripheral device, including: Each gate control unit sends the shared signal to the target peripheral device when the control signal is a high-level signal; and shields the shared signal from the peripheral device when the control signal is a low-level signal.

8. The APB-based peripheral access method according to claim 6, characterized in that: The method further comprises: When the peripheral device further includes a configuration register array, the gating unit sends the shared signal to a combinational logic unit corresponding to the target peripheral device; The address decoding unit sends the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral device; The combinational logic unit performs a logic operation on the PSEL signal, the PENABLE signal and the shared signal, and sends the operation result to the corresponding configuration register for corresponding read and write operations, so as to realize the communication between the target peripheral device and the target host.

9. A computer-readable storage medium, characterized in that: The storage medium stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the APB-based peripheral access method as described in any one of claims 6 to 8.

10. A chip, characterized in that: The chip includes: the APB-based peripheral access system as described in any one of claims 1 to 5.

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