A host bus adapter, a control method and related devices thereof

Abstract

The present invention provides a host bus adapter, a control method and related devices thereof, belonging to the field of computer technology, including: a first controller connected to a host through a peripheral component interconnect high-speed serial bus, configured to receive a target request sent by the host, request the host to allocate a target cache area, so as to store target protection information in the target cache area; the target protection information is protection information corresponding to a serial hard disk; a processing module, configured to parse the target request to obtain target parsing data, execute corresponding operations according to the target parsing data and the target protection information, and at the same time feedback an operation result to the host; a second controller connected to the serial hard disk through a serial bus, configured to convert the target request into a request conforming to a serial data transmission protocol, so as to assist the processing module to respond to the target request. This adapter can solve the technical problem in the related art that the integrity and accuracy of the serial hard disk cannot be guaranteed in the entire transmission path.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a host bus adapter, a control method and related devices thereof. Background Art

[0002] During the transmission of data in a storage system, it will pass through multiple components, various transmission channels and complex software processing. During this process, an error in any link may cause the data to be incorrect, and this kind of error is usually not detected immediately, but is discovered only when the subsequent application accesses the data. This kind of error that is difficult to detect immediately when the data is incorrect is called silent data corruption. Enterprise-level storage applications usually involve a large amount of critical data, such as financial transaction records, medical cases, important business documents, etc., and have extremely high requirements for the reliability and integrity of the data. Once silent data corruption occurs, it may lead to the loss or damage of critical data, thus affecting the normal operation and business decisions of the enterprise.

[0003] Currently, a serial advanced technology attachment (SATA) hard disk cannot prevent silent data corruption during data transmission, so it is difficult for a SATA hard disk to ensure the integrity and accuracy of the stored data inside it throughout the transmission path. Currently, there is no relatively effective solution to this technical problem.

[0004] Therefore, how to ensure the integrity and accuracy of the stored data in a SATA hard disk throughout the transmission path is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a host bus adapter, a control method and related devices thereof, so as to solve the technical problem in the related art that the integrity and accuracy of a SATA hard disk cannot be ensured throughout the transmission path.

[0006] To solve the above technical problem, the present invention provides a host bus adapter, including:

[0007] A first controller, connected to a host through a peripheral component interconnect express (PCIe) bus, configured to receive a target request sent by the host, and request the host to allocate a target cache area to store target protection information by using the target cache area; the target protection information is protection information corresponding to a SATA hard disk;

[0008] A processing module, configured to parse the target request to obtain target parsing data, and perform corresponding operations according to the target parsing data and the target protection information, and at the same time feedback an operation result to the host;

[0009] A second controller, connected to the serial hard disk through a serial bus, is configured to convert the target request into a request conforming to a serial data transmission protocol to assist the processing module in responding to the target request.

[0010] In a specific embodiment of the present invention, it further includes:

[0011] A cache module, configured to temporarily store the data and the target protection information generated by the first controller, the processing module, and the second controller.

[0012] In a specific embodiment of the present invention, the cache module includes:

[0013] A cache unit, configured to temporarily store the target protection information.

[0014] In a specific embodiment of the present invention, the size of each cache line in the cache unit is set according to the maximum payload of the Peripheral Component Interconnect Express Link and the length of the preset information; the length of the preset information is the length of the protection information corresponding to the target logical data block in the serial hard disk; the lengths of the protection information corresponding to all logical data blocks in the serial hard disk are equal; the target logical data block is any one of the logical data blocks in the serial hard disk.

[0015] In a specific embodiment of the present invention, the maximum payload of the Peripheral Component Interconnect Express Link is obtained by reading the configuration parameters of the high-speed serial computer expansion bus standard configuration register.

[0016] In a specific embodiment of the present invention, it further includes:

[0017] When the available storage space of the cache unit is less than a preset threshold, the stored data in the cache unit is deleted using a cache replacement algorithm so that the available storage space of the cache unit is greater than or equal to the preset threshold.

[0018] In a specific embodiment of the present invention, the cache replacement algorithm is specifically the Least Recently Used (LRU) algorithm.

[0019] In a specific embodiment of the present invention, the host includes:

[0020] A data submission queue, configured to store the target requests submitted to the first controller;

[0021] A data completion queue, configured to store the response execution results of the processing module for the target requests.

[0022] To solve the above technical problems, the present invention further provides a control method for a host bus adapter, which is applied to a processing module in the host bus adapter disclosed above, and includes:

[0023] Parse the target request to obtain target parsing data, perform corresponding operations according to the target parsing data and target protection information, and at the same time feedback the operation result to the host.

[0024] In a specific embodiment of the present invention, the parsing the target request to obtain target parsing data, performing corresponding operations according to the target parsing data and target protection information, and at the same time feedbacking the operation result to the host includes:

[0025] When the first controller stores the target request in the cache module, parse the command control word in the target request to obtain a parsing result;

[0026] If it is determined according to the parsing result that the target request is a write request, write the original data in the target request to the serial hard disk according to the command control word in the target request, store the protection information in the target request in the target cache area, and at the same time feedback the corresponding write operation result to the host;

[0027] If it is determined according to the parsing result that the target request is a read request, read data from the serial hard disk according to the command control word in the target request to obtain target read data, read protection information from the target cache area to obtain first protection information, and at the same time feedback the corresponding read operation result to the host according to the target read data and the first protection information.

[0028] In a specific embodiment of the present invention, the writing the original data in the target request to the serial hard disk according to the command control word in the target request, storing the protection information in the target request in the target cache area, and at the same time feedbacking the corresponding write operation result to the host includes:

[0029] Generate a first write operation command and a second write operation command, and respond to the first write operation command and the second write operation command; wherein, the first write operation command is used to instruct the second controller to write the original data in the target request to the serial hard disk according to the command control word in the target request; the second write operation command is used to instruct the first controller to store the protection information in the target request in the target cache area according to the command control word in the target request;

[0030] When the first write operation command and the second write operation command are executed, a first completion response word is generated, and the first completion response word is written into the cache module, so that the first controller returns the first completion response word in the cache module to the host.

[0031] In a specific embodiment of the present invention, the generating the first completion response word includes:

[0032] Generating the first completion response word according to the message format specified by the non-volatile memory standard.

[0033] In a specific embodiment of the present invention, the reading data from the serial hard disk according to the command control word in the target request to obtain target read data, reading protection information from the target cache area to obtain first protection information, and simultaneously feeding back corresponding read operation results to the host according to the target read data and the first protection information includes:

[0034] Generating a first read operation command and a second read operation command; wherein, the first read operation command is used to instruct the second controller to read data from the serial hard disk according to the command control word of the target request to obtain the target read data; the second read operation command is used to instruct the first controller to read protection information from the target cache area according to the command control word of the target request to obtain first protection information;

[0035] When the first read operation command and the second read operation command are executed, generating a second response word;

[0036] Obtaining the target read data and the first protection information;

[0037] Calculating protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information;

[0038] Judging whether the first protection information and the second protection information are consistent;

[0039] If the first protection information and the second protection information are consistent, it is determined that the target read data is not damaged;

[0040] If the first protection information and the second protection information are inconsistent, it is determined that the target read data is damaged;

[0041] Setting the value corresponding to the second response word according to the damage determination result of the target read data, and writing the second response word into the cache module, so that the first controller returns the second completion response word in the cache module to the host.

[0042] In a specific embodiment of the present invention, setting the value corresponding to the second response word according to the damage determination result of the target read data includes:

[0043] If it is determined that the target read data is not damaged, set the value corresponding to the second response word to zero;

[0044] If it is determined that the target read data is damaged, set the value corresponding to the second response word to a non-zero value.

[0045] In a specific embodiment of the present invention, calculating the protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information includes:

[0046] If the first protection information includes two types of check data, namely cyclic redundancy check code and application label, calculate the protection information corresponding to the target read data according to the cyclic redundancy check code, the application label and the target read data to obtain the second protection information.

[0047] In a specific embodiment of the present invention, calculating the protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information includes:

[0048] If the first protection information includes three types of check data, namely cyclic redundancy check code, application label and address check code, calculate the protection information corresponding to the target read data according to the cyclic redundancy check code, the application label, the address check code and the target read data to obtain the second protection information.

[0049] In a specific embodiment of the present invention, calculating the protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information includes:

[0050] If the first protection information includes four types of check data, namely cyclic redundancy check code, application label, address check code and digital signature, calculate the protection information corresponding to the target read data according to the cyclic redundancy check code, the application label, the address check code, the digital signature and the target read data to obtain the second protection information.

[0051] To solve the above technical problems, the present invention also provides a control device for a host bus adapter, including:

[0052] A memory for storing a computer program;

[0053] A processor for executing the computer program to implement the steps of a control method for a host bus adapter as disclosed above.

[0054] To solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of a control method for a host bus adapter as disclosed above.

[0055] To solve the above technical problems, the present invention also provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, they implement the steps of a control method for a host bus adapter as disclosed above.

[0056] Beneficial effects: In a host bus adapter provided by the present invention, a first controller, a processing module, and a second controller are provided. Among them, the first controller is connected to the host through a peripheral component interconnect high-speed serial bus, and is used to receive a target request sent by the host, and request the host to allocate a target cache area to store target protection information using the target cache area; the target protection information is protection information corresponding to the serial hard disk; the processing module is used to parse the target request to obtain target parsing data, and execute corresponding operations according to the target parsing data and the target protection information, and at the same time feedback the operation result to the host; the second controller is connected to the serial hard disk through a serial bus, and is used to convert the target request into a request that conforms to the serial data transmission protocol to assist the processing module in responding to the target request.

[0057] In this setting mode, the conversion from the NVMe (Non-Volatile Memory Express, non-volatile memory host controller interface specification) protocol to the SATA protocol can be achieved through the host bus adapter. Moreover, by using the target cache area in the host to store the target protection information, it is equivalent to storing the end-to-end data protection information that conforms to the NVMe standard in the target cache area of the host, thereby providing a complete end-to-end data protection mechanism for the serial hard disk. In this way, the host bus adapter can verify the integrity and accuracy of the stored data in the serial hard disk during data transmission according to the target protection information stored in the target cache area of the host, and thus ensure the integrity and accuracy of the stored data in the serial hard disk throughout the transmission path.

[0058] Moreover, when the protection information corresponding to the serial hard disk is stored in the target cache area on the host side, the execution efficiency of the host bus adapter in verifying the stored data in the serial hard disk can be further improved, and the working performance of the host bus adapter can be improved.

[0059] Correspondingly, a control method, a control device, a computer-readable storage medium, and a computer program product for a host bus adapter provided by the present invention also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0061] Figure 1 FIG. [X] is a structural diagram of a host bus adapter provided by an embodiment of the present invention.

[0062] Figure 2 FIG. [X] is a schematic diagram of the end-to-end data protection function of NVMe.

[0063] Figure 3 FIG. [X] is another structural diagram of a host bus adapter provided by an embodiment of the present invention.

[0064] Figure 4 FIG. [X] is a structural diagram of a cache unit.

[0065] Figure 5 FIG. [X] is a flowchart of the processing module in the host bus adapter when processing a target request.

[0066] Figure 6 FIG. [X] is a structural diagram of a control device for a host bus adapter provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0068] The terms "including" and "having" in the specification of the present invention and any variations related to "including" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0069] To enable those skilled in the art to better understand the solution of the present invention, the following will further describe the present invention in detail with reference to the drawings and specific embodiments.

[0070] Please refer to Figure 1 , Figure 1 , which is a structural diagram of a host bus adapter provided by an embodiment of the present invention. The host bus adapter 100 includes:

[0071] A first controller 101, which is connected to a host through a peripheral component interconnect high-speed serial bus, is configured to receive a target request sent by the host, and request the host to allocate a target cache area to store target protection information in the target cache area; the target protection information is protection information corresponding to a serial hard disk.

[0072] A processing module 102, which is configured to parse the target request to obtain target parsing data, perform corresponding operations according to the target parsing data and the target protection information, and feedback an operation result to the host at the same time.

[0073] A second controller 103, which is connected to the serial hard disk through a serial bus, is configured to convert the target request into a request that conforms to the serial data transmission protocol to assist the processing module 102 in responding to the target request.

[0074] In this embodiment, a host bus adapter 100 is provided. By using the host bus adapter 100, the integrity and accuracy of the stored data in the serial hard disk can be ensured during the entire transmission path. Before introducing the host bus adapter 100, the end-to-end data protection function (End-to-End Data Protection, E2E) of NVMe is briefly described first.

[0075] The end-to-end data protection function of NVMe aims to ensure the integrity and accuracy of data during the entire transmission path to prevent silent data corruption. The end-to-end data protection function of NVMe mainly adds additional protection information (Protection Information, PI) to the logical block data (LogicalBlock Data), and makes it transmitted together with the data as metadata of the data. After receiving the data, the host side and the non-volatile storage device (NVMe controller) can verify the integrity of the transmitted data according to the protection information added to the logical block data, thereby ensuring the availability and consistency of the transmitted data. Please refer to Figure 2 , Figure 2 , which is a schematic diagram of the end-to-end data protection function of NVMe. In Figure 2 , the data sent by the host to the non-volatile storage device includes 4096 bytes of user original data and 8 bytes of protection information.

[0076] NVMe HMB (Host Memory Buffer) is a feature introduced in the NVMe 1.2 standard. This feature allows the NVMe controller to use the host-side memory as a buffer, reducing the NVMe controller's demand for DRAM (Dynamic Random Access Memory). This not only reduces the manufacturing cost of the NVMe controller but also improves its performance. In other words, by leveraging the HMB feature, the NVMe controller can make full use of the memory in the host and reduce its dependence on DRAM.

[0077] Since the SATA standard protocol itself does not have an end-to-end data protection mechanism and cannot guarantee the accuracy and reliability of data during transmission, in this embodiment, to address this technical issue, a host bus adapter 100 is provided. Using this host bus adapter 100, not only can the conversion from the NVMe protocol to the SATA protocol be achieved, but also a complete end-to-end data protection mechanism can be provided for the serial hard disk. In this host bus adapter 100, a first controller 101, a processing module 102, and a second controller 103 are provided. Among them, the serial hard disk connected to the second controller 103 can be either one or multiple. And the serial hard disk is the user data storage area, storing the data that the user needs to store.

[0078] Among them, the first controller 101 is connected to the host through a peripheral component interconnect high-speed serial bus (PCIe bus), and is used to receive the target request sent by the host and request the host to allocate a target cache area to store the target protection information using the target cache area; the target protection information is the protection information corresponding to the serial hard disk. Since the first controller 101 is connected to the host through the PCIe bus, the first controller 101 supports the NVMe standard protocol. On the host side, the first controller 101 will appear as a standard NVMe device. That is to say, the first controller 101 is essentially an NVMe controller.

[0079] Since the first controller 101 has the HMB feature defined in the NVMe specification, the first controller 101 can request the host to allocate a target cache area for its own management and use, and use the target cache area to store the target protection information. In this setting mode, the first controller 101 can use the HMB feature of NVMe to store the target protection information in the target cache area of the host, which can reduce the demand of the host bus adapter 100 for the internal DRAM and lower the manufacturing cost of the host bus adapter 100. Moreover, by using the cache area of the host memory, the latency of the first controller 101 during data processing can also be reduced, further improving the processing speed of the first controller 101 when receiving requests.

[0080] The processing module 102 is the management center of the host bus adapter 100, mainly used to parse the target requests sent by the host to obtain the target parsing data, execute corresponding operations according to the target parsing data and the target protection information, and feedback the operation results to the host at the same time.

[0081] The second controller 103 is connected to the serial hard disk (SATA hard disk) through a serial bus (SATA bus), and is equivalent to a SATA controller, used to convert the target requests sent by the host into requests that conform to the serial data transmission protocol (SATA protocol) to assist the processing module 102 in responding to the target requests.

[0082] Obviously, after setting the first controller 101 and the second controller 103 in the host bus adapter 100, it can be connected to the host through the PCIe bus upstream of the host bus adapter 100 and connected to the serial hard disk through the SATA bus downstream, so as to realize the conversion from the NVMe protocol to the SATA protocol. That is to say, the host bus adapter 100 described in this embodiment uses the standard NVMe protocol upstream, which can be compatible with the existing NVMe system drivers on the host side, and uses a SATA controller downstream, which can be compatible with the existing SATA storage devices in the market. This design can not only effectively reduce the deployment difficulty of the system and enhance the scalability of the system, but also make the system upgrade process more flexible and simple.

[0083] Moreover, through the host bus adapter 100 provided in this embodiment, the complex end-to-end data protection function can be integrated in the same hardware device, which can not only simplify the design complexity of the storage system, but also the unified protection mechanism and compatibility help to simplify the maintenance work of the storage system and improve the stability and maintainability of the storage system.

[0084] In addition, when the first controller 101 stores the target protection information (the target protection information is the protection information corresponding to the serial hard disk) into the target cache area of the host, during the process that the first controller 101 receives the target request sent by the host and parses the target request, it can perform real-time detection and verification on the parsing result of the target request according to the target protection information stored in the host target cache area, so as to determine whether an error or abnormality occurs in the transmission data corresponding to the target request during the data transmission process. In this way, silent data corruption can be effectively prevented, and the integrity and accuracy of the data during the transmission process can be ensured. Moreover, the real-time verification function of the end-to-end data protection mechanism also helps to reduce the repeated transmission and processing caused by data errors, and thus can further improve the data processing efficiency of the system.

[0085] For enterprise-level storage applications involving a large amount of critical data, such as financial transaction records, medical cases, important business documents, etc., the host bus adapter 100 described in this embodiment can provide a complete data verification mechanism, which can significantly reduce the enterprise operation risk and business decision-making risk caused by silent data corruption.

[0086] In addition, when the host bus adapter 100 detects that the stored data in the serial hard disk is damaged, it can timely identify and feedback error information, so that the upper-layer application can perform corresponding processing according to the error situation, such as data retransmission, error recovery, etc. This can not only enhance the fault tolerance ability of the entire storage system, but also improve the availability and stability of the storage system.

[0087] In this setting mode, the conversion from the NVMe protocol to the SATA protocol can be achieved through the host bus adapter. Moreover, by using the target cache area in the host to store the target protection information, it is equivalent to storing the end-to-end data protection information conforming to the NVMe standard in the target cache area of the host, thereby providing a complete end-to-end data protection mechanism for the serial hard disk. In this way, the host bus adapter can verify the integrity and accuracy of the stored data in the serial hard disk during the data transmission process according to the target protection information stored in the target cache area of the host, and thus can ensure the integrity and accuracy of the stored data in the serial hard disk throughout the transmission path.

[0088] Based on the above embodiments, this embodiment further describes and optimizes the technical solution. Please refer to Figure 3 , Figure 3 which is the structural diagram of another host bus adapter provided by the embodiment of the present invention. As a preferred implementation manner, the above host bus adapter further includes:

[0089] The cache module 104 is used to temporarily store the data and target protection information generated by the first controller 101, the processing module 102, and the second controller 103.

[0090] In this embodiment, a cache module 104 is further provided in the host bus adapter, and the cache module 104 is used to temporarily store the relevant data and target protection information involved in the operation process of the first controller 101, the processing module 102, and the second controller 103. In this setting mode, it is more convenient for the first controller 101, the processing module 102, and the second controller 103 to schedule and manage data during the processing flow transaction.

[0091] As a preferred embodiment, the cache module 104 includes:

[0092] A cache unit for temporarily storing the target protection information.

[0093] In this embodiment, in order to further reduce the resource overhead of the host bus adapter when accessing the host and give full play to the transmission efficiency of the PCIe link between the host and the host bus adapter, a cache unit for temporarily storing the target protection information is further provided in the cache module.

[0094] In this setting mode, when the host bus adapter needs to use the target protection information, it does not need to read the target protection information from the target cache area of the host, but can directly read the target protection information from the cache unit, which can further improve the data processing efficiency of the host bus adapter.

[0095] As a preferred embodiment, the size of each cache line in the cache unit is set according to the maximum payload of the peripheral component interconnect express link and the length of the preset information; the length of the preset information is the length of the protection information corresponding to the target logical data block in the serial ATA hard disk; the lengths of the protection information corresponding to all logical data blocks in the serial ATA hard disk are equal; the target logical data block is any one of the logical data blocks in the serial ATA hard disk.

[0096] In this embodiment, the target protection information is the protection information corresponding to the serial ATA hard disk. In fact, the target protection information contains the protection information corresponding to each logical data block in the serial ATA hard disk, that is, the target protection information is the set of the protection information corresponding to all logical data blocks in the serial ATA hard disk.

[0097] It should be noted that, for the convenience of data processing, the lengths of the protection information corresponding to all logical data blocks in the serial ATA hard disk are equal. If the target logical data block is any one of the logical data blocks in the serial ATA hard disk, then the length of the protection information corresponding to the target logical data block is the length of the preset information.

[0098] When setting the size of each cache line in the cache unit, it can be set according to the maximum payload (Max Payload Size) of the Peripheral Component Interconnect Express (PCIe) link and the length of the preset information. Specifically, when setting the size of each cache line in the cache unit according to the maximum payload of the PCIe link and the length of the preset information, it is dynamically set according to the least common multiple of the maximum payload of the PCIe link and the length of the preset information.

[0099] Here is a specific example for illustration. If the length of the preset information is 8 bytes and the maximum payload of the PCIe link is 256 bytes, then the size of each cache line in the cache unit is 256 bytes. If the length of the preset information is 8 bytes and the maximum payload of the PCIe link is 512 bytes, then the size of each cache line in the cache unit is 512 bytes.

[0100] Please refer to Figure 4 , Figure 4 for the structure diagram of the cache unit. In Figure 4 the shown cache unit, multiple cache lines are set, and there is a one-to-one mapping relationship between each cache line and the data cached inside it.

[0101] Obviously, through the technical solution provided by this embodiment, it can maximize the data transferred from the cache line to the PCIe link in the cache unit, thereby reducing the resource overhead required during data transfer, improving the data transfer efficiency. Moreover, dynamically setting the size of each cache line in the cache unit can also reduce the replacement efficiency of the cache line, reduce the number of data accesses caused by cache misses, and reduce the overall latency of the system.

[0102] As a preferred implementation manner, the maximum payload of the Peripheral Component Interconnect Express link is obtained by reading the configuration parameters of the high-speed serial computer expansion bus standard configuration register.

[0103] In this embodiment, when obtaining the maximum payload of the Peripheral Component Interconnect Express (PCIe) link, during the initialization of the host bus adapter, the maximum payload of the PCIe link is obtained by reading the configuration parameters of the PCIe standard configuration register. Since when a PCIe device transmits data, its maximum payload is negotiated and determined by the PCIe standard configuration registers at both ends of the link, and each PCIe standard configuration register has two related parameters, one is the maximum payload supported by the device hardware (Max Payload Size Supported), and the other is the maximum payload actually used by the device (Max Payload Size). Therefore, during the initialization of the host bus adapter, the system software will set the maximum payload of the PCIe link according to the maximum payload supported by the PCIe standard configuration registers at both ends of the link.

[0104] Obviously, through the technical solution provided by this embodiment, the accuracy and reliability in setting the maximum payload of the PCIe link can be ensured.

[0105] As a preferred implementation manner, the above host bus adapter further includes:

[0106] When the available storage space of the cache unit is less than a preset threshold, the stored data in the cache unit is deleted using a cache replacement algorithm, so that the available storage space of the cache unit is greater than or equal to the preset threshold.

[0107] The cache unit is set in the cache module to further reduce the overhead of the host bus adapter when accessing the host memory. However, the storage space of the cache unit is limited, and sometimes it may not be possible to cache and store all the data in the target protected information.

[0108] In this case, to ensure that the data stored in the cache unit is all the data that is frequently accessed recently and reduce the adverse effects brought by insufficient storage space of the cache unit, part of the stored data in the cache unit can be deleted using a cache replacement algorithm. That is, when the available storage space of the cache unit is less than a preset threshold, the stored data in the cache unit can be deleted using a cache replacement algorithm, so that the available storage space of the cache unit is greater than or equal to the preset threshold.

[0109] Obviously, through the technical solution provided by this embodiment, the adverse effects brought by insufficient storage space of the cache unit can be relatively reduced.

[0110] As a preferred implementation, in practical applications, the cache eviction algorithm can be set to the Least Recently Used (LRU) algorithm. Since this algorithm can evict the data that has not been used for the longest time and preferentially retain the data that has been recently accessed, the utilization rate and hit rate of the cache can be effectively improved under this eviction mechanism. In this way, when the system processes a large amount of data, it can access the data it wants to access more quickly, thereby improving the overall performance of the system.

[0111] As a preferred implementation, the host includes:

[0112] A data submission queue for storing target requests submitted to the first controller.

[0113] A data completion queue for storing the response execution results of the processing module for the target requests.

[0114] In this embodiment, in order to improve the working performance of the host, a data submission queue (Submission Queue) and a data completion queue (Completion Queue) can also be set in the host. Among them, the data submission queue is used to store target requests submitted to the first controller in the host bus adapter, and the data completion queue is used to store the response execution results of the processing module for the target requests.

[0115] It can be envisioned that by setting a data submission queue and a data completion queue in the host, the host is allowed to process multiple requests in a batch manner simultaneously, rather than processing each request one by one. This batch data processing method can reduce the number of interruptions when the host and the host bus adapter process requests, reduce the required resource overhead, and reduce the latency time during data transmission.

[0116] Moreover, by setting a data submission queue and a data completion queue in the host, different operations can also be isolated in different queues. This isolation mechanism can effectively prevent errors from affecting each other between requests and completion operations, thereby improving the reliability of the host.

[0117] Obviously, through the technical solution provided by this embodiment, the working performance of the host can be further improved.

[0118] Correspondingly, an embodiment of the present invention also provides a control method for a host bus adapter, which is applied to a processing module in the foregoing disclosed host bus adapter, and includes:

[0119] Parse the target request to obtain target parsing data, and perform corresponding operations according to the target parsing data and target protection information, and at the same time feedback the operation result to the host.

[0120] A control method for a host bus adapter provided in an embodiment of the present invention corresponds to the control logic executed by the processing module in the foregoing embodiment, which will not be elaborated herein. For details, refer to the content disclosed in the foregoing embodiment.

[0121] Based on the foregoing embodiment, this embodiment further illustrates and optimizes the technical solution. Please refer to Figure 5 , Figure 5 which is a flowchart when the processing module in the host bus adapter processes a target request. As a preferred implementation manner, the above steps: parsing the target request to obtain target parsing data, and performing corresponding operations according to the target parsing data and target protection information, and at the same time feeding back an operation result to the host, including:

[0122] Step S11: When the first controller stores the target request in the cache module, parse the command control word in the target request to obtain a parsing result.

[0123] Step S12: If it is determined according to the parsing result that the target request is a write request, write the original data in the target request to the serial hard disk according to the command control word in the target request, store the protection information in the target request in the target cache area, and at the same time feed back a corresponding write operation result to the host.

[0124] Step S13: If it is determined according to the parsing result that the target request is a read request, read data from the serial hard disk according to the command control word in the target request to obtain target read data, and read protection information from the target cache area to obtain first protection information, and at the same time feed back a corresponding read operation result to the host according to the target read data and the first protection information.

[0125] In this embodiment, the execution logic of the processing module in the host bus adapter is specifically described. As the management center of the host bus adapter, the processing module is not only responsible for the identification and initialization of the serial hard disk connected downstream of the host bus adapter, planning the target cache area on the host side, and establishing the mapping relationship between each logical data block in the serial hard disk and its protection information, but also responsible for decomposing, scheduling, and converting the requests received by the first controller.

[0126] Specifically, when the first controller stores the target request in the cache module, the processing module will parse the command control word in the target request to obtain a parsing result. Among them, the host will write the target request into the data submission queue of the host and notify the first controller that there is a new request waiting to be processed. At this time, the first controller will store the target request in the cache module for the processing module to process.

[0127] When the processing module determines that the target request is a write request based on the parsing result, it indicates that the target request contains three parts: the command control word of the target request, the original data, and the protection information. At this time, the processing module will write the original data in the target request to the corresponding address of the serial hard disk according to the command control word in the target request, and store the protection information in the target request in the target cache area on the host side according to the command control word in the target request. At the same time, it will also feedback the corresponding write operation result to the host, that is, the processing module will feedback to the host whether the original data and protection information in the target request are successfully written to the serial hard disk and the target cache area on the host side respectively.

[0128] If the processing module determines that the target request is a read request based on the parsing result, it indicates that the target request only contains the command control word of the target request. At this time, the processing module will read data from the serial hard disk according to the command control word in the target request to obtain the target read data, so as to feedback the target read data to the host. And, the processing module will also read the protection information from the target cache area according to the command control word in the target request to obtain the first protection information, and judge whether there is an error or exception in the target read data during the data transmission process according to the first protection information. At the same time, the processing module will also feedback the corresponding read operation result to the host, that is, the processing module will feedback to the host whether the target read data and the first protection information are successfully returned to the host.

[0129] Obviously, through the technical solution provided by this embodiment, the host bus adapter can successfully respond to the request sent by the host.

[0130] As a preferred implementation manner, the above steps: writing the original data in the target request to the serial hard disk according to the command control word in the target request, storing the protection information in the target request in the target cache area, and at the same time feedbacking the corresponding write operation result to the host, include:

[0131] Generate a first write operation command and a second write operation command, and respond to the first write operation command and the second write operation command; wherein, the first write operation command is used to instruct the second controller to write the original data in the target request to the serial hard disk according to the command control word in the target request; the second write operation command is used to instruct the first controller to store the protection information in the target request in the target cache area according to the command control word in the target request.

[0132] When the first write operation command and the second write operation command are executed, generate a first completion response word, and write the first completion response word to the cache module, so that the first controller returns the first completion response word in the cache module to the host.

[0133] In this embodiment, the operation process of the write request sent by the host by the processing module is specifically described. When the processing module determines that the target request is a write request according to the parsing result, the processing module will first generate a first write operation command and a second write operation command, and respond to the first write operation command and the second write operation command. Among them, the first write operation command is used to instruct the second controller to write the original data in the target request into the serial hard disk according to the command control word in the target request, and the second write operation command is used to instruct the first controller to store the protection information in the target request into the target cache area on the host side according to the command control word in the target request.

[0134] It should be noted that when the target request is a write request, the processing module will obtain two addresses by parsing the command control word in the target request. One address is the storage address of the original data in the target request in the serial hard disk, and the other address is the storage address of the protection information in the target request in the target cache area on the host side. Therefore, the processing module can write the original data and protection information in the target request into the corresponding addresses in the serial hard disk and the target cache area respectively according to the command control word in the target request.

[0135] Since there is a corresponding mapping relationship between the original data and the protection information in the target request, when the processing module writes the original data in the target request into the serial hard disk, it can use the protection information in the target request to verify the data written into the serial hard disk and ensure the integrity and accuracy of the data written into the serial hard disk.

[0136] When the processing module finishes executing the first write operation command and the second write operation command, the processing module will generate a first completion response word and write the first completion response word into the cache module. When the processing module writes the first completion response word into the cache module, the first controller will return the first completion response word in the cache module to the data completion queue of the host, so that the host can clearly know the operation response result of the write request. So far, the processing flow of the write request with end-to-end protection function ends.

[0137] It should be noted that if the processing module successfully responds to the write request, the processing module will set the value corresponding to the first response word to zero; if the processing module does not successfully respond to the write request, the processing module will set the value corresponding to the first response word to a non-zero value, so that the host side can accurately know the response execution result of the host bus adapter to the write request.

[0138] Obviously, through the technical solution provided in this embodiment, not only can the host bus adapter successfully respond to the write request sent by the host side, but also the data written into the serial hard disk can be accurate and error-free.

[0139] As a preferred embodiment, the above step of generating the first completion response word includes:

[0140] Generating the first completion response word according to the message format specified by the non-volatile memory standard.

[0141] In this embodiment, when the processing module generates the first completion response word, it will generate the first completion response word according to the message format specified by the non-volatile memory standard (NVMe standard). Since the first controller in the host bus adapter establishes a communication connection with the host through the PCIe bus, the host bus adapter will fully support the NVMe standard protocol. Therefore, when the processing module returns the first response word to the host, it will generate the first completion response word based on the message format specified by the NVMe standard.

[0142] Obviously, through the technical solution provided by this embodiment, it can be ensured that data interaction between the host bus adapter and the host can proceed smoothly.

[0143] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. As a preferred embodiment, the above step of reading data from the serial hard disk according to the command control word in the target request to obtain the target read data, reading the protection information from the target buffer area to obtain the first protection information, and simultaneously feeding back the corresponding read operation result to the host according to the target read data and the first protection information includes:

[0144] Generating a first read operation command and a second read operation command; wherein, the first read operation command is used to instruct the second controller to read data from the serial hard disk according to the command control word of the target request to obtain the target read data; the second read operation command is used to instruct the first controller to read the protection information from the target buffer area according to the command control word of the target request to obtain the first protection information.

[0145] When the first read operation command and the second read operation command are executed, generate a second response word.

[0146] Obtain the target read data and the first protection information.

[0147] Calculate the protection information corresponding to the target read data according to the preset rule and the target read data to obtain the second protection information.

[0148] Judge whether the first protection information and the second protection information are consistent.

[0149] If the first protection information and the second protection information are consistent, it is determined that the target read data is not damaged.

[0150] If the first protection information and the second protection information are inconsistent, it is determined that the target read data is damaged.

[0151] Set the value corresponding to the second response word according to the corruption determination result of the data read from the target, and write the second response word into the cache module, so that the first controller returns the second completion response word in the cache module to the host.

[0152] In this embodiment, the operation process of the read request sent by the host by the processing module is specifically described. When the processing module determines that the target request is a read request according to the parsing result, it will first generate a first read operation command and a second read operation command; wherein, the first read operation command is used to instruct the second controller to read data from the serial hard disk according to the command control word of the target request to obtain the target read data; and the second read operation command is used to instruct the first controller to read the protection information from the target cache area on the host side according to the command control word of the target request to obtain the first protection information.

[0153] It should be noted that when the target request is a read request, after the processing module parses the command control word of the target request, two addresses will be obtained. One address is the storage location of the data corresponding to the read request in the serial hard disk, and the other address is the storage location of the protection information of the data corresponding to the read request in the target cache area on the host side. Therefore, after the processing module parses the command control word of the target request, it can read the target read data from the serial hard disk and read the first protection information from the target cache area on the host side.

[0154] When the processing module finishes executing the first read operation command and the second read operation command, it will generate a second response word, and will obtain the target read data and the first protection information. Then, the processing module will calculate the protection information corresponding to the target read data according to the preset rules and the target read data set in advance to obtain the second protection information, and will judge whether the first protection information and the second protection information are consistent. If the first protection information and the second protection information are consistent, it means that the target read data has not been corrupted during the data transmission process and is complete and error-free. If the first protection information and the second protection information are inconsistent, it means that the target read data has been corrupted during the data transmission process.

[0155] In this case, the value corresponding to the second response word can be set according to the damage determination result of the target read data, so that the second response word can accurately represent whether the host bus adapter has successfully responded to the read request sent by the host. After the processing module sets the value corresponding to the second response word according to the damage determination result of the target read data, the processing module can write the second response word into the cache module, so that the first controller can return the second response word in the cache module to the data completion queue of the host, and further enable the host to clearly know the operation response result of the read request. Thus, the processing flow of the entire read request with end-to-end protection function ends.

[0156] Obviously, through the technical solution provided by this embodiment, not only can the host bus adapter successfully respond to the read request sent by the host side, but also it can ensure that the data read from the serial hard disk is accurate and complete.

[0157] As a preferred implementation manner, the above step: setting the value corresponding to the second response word according to the damage determination result of the target read data includes:

[0158] If it is determined that the target read data is not damaged, the value corresponding to the second response word is set to zero.

[0159] If it is determined that the target read data is damaged, the value corresponding to the second response word is set to a non-zero value.

[0160] In this embodiment, when the processing module sets the value corresponding to the second response word according to the damage determination result of the target read data, if the processing module determines that the target read data is not damaged, that is, the first protection information and the second protection information are consistent, the processing module can set the value corresponding to the second response word to zero. If the processing module determines that the target read data is damaged, that is, the first protection information and the second protection information are inconsistent, the processing module can set the value corresponding to the second response word to a non-zero value.

[0161] In this setting method, the host can clearly know the operation response result of the read request through the second response word returned by the first controller in the host bus adapter. Moreover, this setting method of the second response word has a simple execution logic and is easy to operate, so that the processing performance of the host bus adapter can be further improved.

[0162] As a preferred implementation manner, the above step: calculating the protection information corresponding to the target read data according to the preset rule and the target read data to obtain the second protection information includes:

[0163] If the first protection information includes two types of verification data, namely cyclic redundancy check code and application label, then calculate the protection information corresponding to the target read data based on the cyclic redundancy check code, application label, and target read data to obtain the second protection information.

[0164] In this embodiment, if the first protection information includes two types of verification data, namely cyclic redundancy check (CRC) and application label, it indicates that the protection information stored in the target cache area is only used to protect user data and is applicable to application scenarios with relatively low requirements for data integrity.

[0165] In this case, the protection information corresponding to the target read data can be calculated based on the target read data and the cyclic redundancy check code and application label in the first protection information to obtain the second protection information, and the first protection information and the second protection information are used to determine whether the target read data is damaged during transmission.

[0166] As a preferred implementation manner, the above step: calculating the protection information corresponding to the target read data according to the preset rule and the target read data to obtain the second protection information includes:

[0167] If the first protection information includes three types of verification data, namely cyclic redundancy check code, application label, and address verification code, then calculate the protection information corresponding to the target read data based on the cyclic redundancy check code, application label, address verification code, and target read data to obtain the second protection information.

[0168] If the first protection information includes three types of verification data, namely cyclic redundancy check code, application label, and logical block address (LBA), it indicates that the protection information stored in the target cache area can not only be used to protect user data but also prevent user data from being written to the wrong address, and is applicable to application scenarios with relatively high requirements for data integrity.

[0169] In this case, the protection information corresponding to the target read data can be calculated based on the target read data and the cyclic redundancy check code, application label, and address verification code in the first protection information to obtain the second protection information, and the first protection information and the second protection information are used to determine whether the target read data is damaged during transmission.

[0170] As a preferred implementation manner, the above step: calculating the protection information corresponding to the target read data according to the preset rule and the target read data to obtain the second protection information includes:

[0171] If the first protection information includes four types of verification data, namely cyclic redundancy check code, application label, address check code, and digital signature, then calculate the protection information corresponding to the target read data based on the cyclic redundancy check code, application label, address check code, digital signature, and target read data to obtain the second protection information.

[0172] If the first protection information includes four types of verification data, namely cyclic redundancy check code, application label, address check code, and digital signature, it indicates that the protection information stored in the target cache area can not only protect user data but also prevent the user data from being written to the wrong address and calculate the digital signature of the user data and address check code through an encryption mechanism, thereby preventing the data from being tampered with during the transmission process. It is applicable to application scenarios with relatively high requirements for data integrity. For example: financial transactions and database operations, etc.

[0173] In this case, the protection information corresponding to the target read data can be calculated based on the target read data and the cyclic redundancy check code, application label, address check code, and digital signature in the first protection information to obtain the second protection information, and the first protection information and the second protection information are used to determine whether the target read data is damaged during the transmission process.

[0174] For the above three calculation methods of the second protection information, refer to the Type 1, Type 2, and Type 3 calculation and verification methods defined for the end-to-end data protection function in the NVMe specification, which will not be elaborated here.

[0175] Obviously, through the technical solution provided in this embodiment, the integrity and accuracy of the data read from the serial hard disk can be verified in different application scenarios.

[0176] Please refer to Figure 6 , Figure 6 which is the structural diagram of a control device for a host bus adapter provided by an embodiment of the present invention, including:

[0177] A memory 31 for storing computer programs.

[0178] A processor 32 for executing the computer program to implement the steps of a control method for a host bus adapter as disclosed above.

[0179] The control device for the host bus adapter provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer, etc.

[0180] Among them, the processor 32 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 32 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 32 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 32 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 32 may also include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0181] The memory 31 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 31 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 31 is at least used to store the following computer program 301. After the computer program is loaded and executed by the processor 32, it can implement the relevant steps of the control method of the host bus adapter disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 31 may also include an operating system 302 and data 303, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 302 may include Windows, Unix, Linux, etc. The data 303 may include, but is not limited to, the data involved in the control method of the host bus adapter.

[0182] In some embodiments, the control device of the host bus adapter may further include a display screen 33, an input / output interface 34, a communication interface 35, a power supply 36, and a communication bus 37.

[0183] Those skilled in the art can understand that Figure 6 the shown structure does not constitute a limitation on the control device of the host bus adapter, and it may include more or fewer components than shown in the figure.

[0184] It can be understood that if the methods in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), electrically erasable programmable ROMs, registers, hard disks, removable disks, CD-ROMs, magnetic disks, or optical discs.

[0185] The control device of a host bus adapter provided by an embodiment of the present invention has the beneficial effects of a control method of a host bus adapter disclosed above.

[0186] Correspondingly, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of a control method of a host bus adapter disclosed above.

[0187] The computer-readable storage medium provided by an embodiment of the present invention has the beneficial effects of a control method of a host bus adapter disclosed above.

[0188] Correspondingly, an embodiment of the present invention further provides a computer program product, including computer programs / instructions. When the computer programs / instructions are executed by a processor, they implement the steps of a control method of a host bus adapter disclosed above.

[0189] The computer program product provided by an embodiment of the present invention has the beneficial effects of a control method of a host bus adapter disclosed above.

[0190] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0191] The above has introduced in detail a host bus adapter, a control method and related devices provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A host bus adapter, characterized in that, Including: A first controller, connected to a host through a Peripheral Component Interconnect Express (PCIe) high-speed serial bus. The first controller supports the NVMe standard protocol and is an NVMe controller for receiving a target request sent by the host and requesting the host to allocate a target cache area to store target protection information using the target cache area. The target protection information is protection information corresponding to a serial ATA (SATA) hard disk. A processing module for parsing the target request to obtain target parsing data, performing corresponding operations based on the target parsing data and the target protection information, and simultaneously feeding back an operation result to the host. A second controller, connected to the SATA hard disk through a serial bus, for converting the target request into a request conforming to a serial data transmission protocol to assist the processing module in responding to the target request. The host bus adapter can not only implement the conversion from the NVMe protocol to the SATA protocol, but also provide a complete end-to-end data protection mechanism for the SATA hard disk. Further including: A cache module for temporarily storing data and the target protection information generated by the first controller, the processing module, and the second controller. The cache module includes: A cache unit for temporarily storing the target protection information. The size of each cache line in the cache unit is set according to the maximum payload of the Peripheral Component Interconnect Express (PCIe) link and the length of preset information. The length of the preset information is the length of the protection information corresponding to a target logical data block in the SATA hard disk. The lengths of the protection information corresponding to all logical data blocks in the SATA hard disk are equal. The target logical data block is any one of the logical data blocks in the SATA hard disk. When setting the size of each cache line in the cache unit according to the maximum payload of the PCIe link and the length of the preset information, it is dynamically set according to the least common multiple of the maximum payload of the PCIe link and the length of the preset information.

2. The host bus adapter according to claim 1, wherein The maximum payload of the PCIe link is obtained by reading the configuration parameters of the PCIe configuration register.

3. The host bus adapter according to claim 1, characterized in that, Further including: When the available storage space of the cache unit is less than a preset threshold, the stored data in the cache unit is deleted using a cache replacement algorithm to make the available storage space of the cache unit greater than or equal to the preset threshold.

4. The host bus adapter according to claim 3, wherein The cache replacement algorithm is specifically the Least Recently Used (LRU) algorithm.

5. A host bus adapter according to claim 1, characterized in that, The host includes: A data submission queue for storing the target requests submitted to the first controller. A data completion queue for storing the response execution results of the processing module for the target requests.

6. A control method for a host bus adapter, characterized in that, The processing module applied to a host bus adapter according to any one of claims 1 to 5 includes: Parsing a target request to obtain target parsing data, performing corresponding operations based on the target parsing data and the target protection information, and simultaneously feeding back an operation result to the host.

7. The control method of a host bus adapter according to claim 6, wherein Parsing the target request to obtain target parsing data, performing corresponding operations according to the target parsing data and target protection information, and feeding back the operation result to the host, including: When the first controller stores the target request in the cache module, parsing the command control word in the target request to obtain a parsing result; If it is determined according to the parsing result that the target request is a write request, writing the original data in the target request to the serial hard disk according to the command control word in the target request, storing the protection information in the target request in the target cache area, and feeding back the corresponding write operation result to the host; If it is determined according to the parsing result that the target request is a read request, reading data from the serial hard disk according to the command control word in the target request to obtain target read data, reading protection information from the target cache area to obtain first protection information, and feeding back the corresponding read operation result to the host according to the target read data and the first protection information.

8. The control method of a host bus adapter according to claim 7, characterized in that, The writing the original data in the target request to the serial hard disk according to the command control word in the target request, storing the protection information in the target request in the target cache area, and feeding back the corresponding write operation result to the host, includes: Generating a first write operation command and a second write operation command, and responding to the first write operation command and the second write operation command; wherein, the first write operation command is used to instruct the second controller to write the original data in the target request to the serial hard disk according to the command control word in the target request; the second write operation command is used to instruct the first controller to store the protection information in the target request in the target cache area according to the command control word in the target request; When the first write operation command and the second write operation command are executed, generating a first completion response word, and writing the first completion response word to the cache module, so that the first controller returns the first completion response word in the cache module to the host.

9. The control method of a host bus adapter according to claim 8, wherein The generating the first completion response word, includes: Generating the first completion response word according to the message format specified by the non-volatile memory standard.

10. The control method of a host bus adapter according to claim 7, characterized in that, The reading data from the serial hard disk according to the command control word in the target request to obtain target read data, reading protection information from the target cache area to obtain first protection information, and feeding back the corresponding read operation result to the host according to the target read data and the first protection information, includes: Generating a first read operation command and a second read operation command; wherein, the first read operation command is used to instruct the second controller to read data from the serial hard disk according to the command control word of the target request to obtain the target read data; the second read operation command is used to instruct the first controller to read protection information from the target cache area according to the command control word of the target request to obtain first protection information; When the first read operation command and the second read operation command are executed, a second response word is generated; Obtain the target read data and the first protection information; Calculate the protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information; Determine whether the first protection information and the second protection information are consistent; If the first protection information and the second protection information are consistent, it is determined that the target read data is not damaged; If the first protection information and the second protection information are inconsistent, it is determined that the target read data is damaged; Set the value corresponding to the second response word according to the damage determination result of the target read data, and write the second response word into the cache module, so that the first controller returns the second response word in the cache module to the host.

11. A control method for a host bus adapter according to claim 10, characterized in that, The setting the value corresponding to the second response word according to the damage determination result of the target read data includes: If it is determined that the target read data is not damaged, set the value corresponding to the second response word to zero; If it is determined that the target read data is damaged, set the value corresponding to the second response word to a non-zero value.

12. The control method of a host bus adapter according to claim 10, characterized in that, The calculating the protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information includes: If the first protection information includes two types of check data, namely a cyclic redundancy check code and an application tag, calculate the protection information corresponding to the target read data according to the cyclic redundancy check code, the application tag and the target read data to obtain the second protection information.

13. A control method for a host bus adapter according to claim 10, characterized in that, The calculating the protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information includes: If the first protection information includes three types of check data, namely a cyclic redundancy check code, an application tag and an address check code, calculate the protection information corresponding to the target read data according to the cyclic redundancy check code, the application tag, the address check code and the target read data to obtain the second protection information.

14. The control method of a host bus adapter according to claim 10, characterized in that, The calculating the protection information corresponding to the target read data according to a preset rule and the target read data to obtain second protection information includes: If the first protection information includes four types of check data, namely a cyclic redundancy check code, an application tag, an address check code and a digital signature, calculate the protection information corresponding to the target read data according to the cyclic redundancy check code, the application tag, the address check code, the digital signature and the target read data to obtain the second protection information.

15. A control device for a host bus adapter, characterized in that, including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of a control method of a host bus adapter according to any one of claims 6 to 14.

16. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of a control method of a host bus adapter as described in any one of claims 6 to 14 are implemented.

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