I2C equipment communication method and device, electronic equipment and storage medium

Abstract

The invention provides an I2C device communication method and device, an electronic device and a storage medium, relates to the technical field of communication, is applied to a first I2C device, the first I2C device is any one I2C device, the I2C devices are cascaded, and the method comprises the following steps: receiving a target slave address of a preceding-stage I2C device; and determining a target I2C device based on the target slave address and the device address of the first I2C device, so that the preceding-stage I2C device communicates with the target I2C device. According to the I2C communication method and device, I2C communication of any two I2C devices in the I2C network topology can be achieved under the condition that extra hardware resources are not occupied.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to an I2C device communication method, apparatus, electronic device, and storage medium. Background Art

[0002] The I2C (Inter-Integrated Circuit) protocol is a bus protocol for communication between a master device and a slave device using an I2C bus. The I2C bus includes a serial clock line (SCL) and a serial data line (SDA). The I2C protocol is widely used in the embedded field due to its simple operation and low pin resource consumption. As Figure 1 shown, in an application scenario, one master device is often used to connect multiple slave devices to achieve communication between a single master device and each slave device. However, as Figure 2 shown, in a special scenario, a single slave device needs to connect multiple slave devices, resulting in multiple master devices competing for the I2C bus.

[0003] In the prior art, the problem of multiple master devices competing for the I2C bus is generally solved by checking the bus busy flag before the master device starts communication. However, since the data transmission direction on the I2C bus is fixed, only communication between each master device and the slave device can be achieved, and communication between the master devices cannot be achieved. If communication between the master devices needs to be achieved, additional peripheral devices need to be connected, occupying additional hardware resources. For example, the master device as the initiator needs to provide an additional master control peripheral device, and the master device as the receiver needs to provide an additional controlled peripheral device, and the additional master control peripheral device and the additional controlled peripheral device need to be connected. Summary of the Invention

[0004] The present invention provides an I2C device communication method, apparatus, electronic device, and storage medium to solve the defect that communication between master devices cannot be achieved due to the fixed transmission direction in the prior art, and to achieve I2C communication between any two I2C devices in an I2C network topology without occupying additional hardware resources.

[0005] The present invention provides an I2C device communication method, which is applied to a first I2C device. The first I2C device is any I2C device, and the I2C devices are cascaded. The method includes:

[0006] Receiving a target slave address of a previous-stage I2C device;

[0007] Based on the target slave address and the device address of the first I2C device, determining a target I2C device to enable communication between the previous-stage I2C device and the target I2C device.

[0008] According to the I2C device communication method provided by the present invention, determining the target I2C device based on the target slave address and the device address of the first I2C device includes:

[0009] When the target slave address is inconsistent with the device address of the first I2C device, determining the target I2C device as the subsequent I2C device of the first I2C device, and connecting the master peripheral of the first I2C device to the controlled peripheral of the subsequent I2C device;

[0010] When the target slave address is consistent with the device address of the first I2C device, determining the target I2C device as the first I2C device.

[0011] According to the I2C device communication method provided by the present invention, the communication between the previous I2C device and the target I2C device includes:

[0012] When the target I2C device is the subsequent I2C device, calling the master peripheral of the first I2C device to send the target slave address and the operation flag to the subsequent I2C device.

[0013] According to the I2C device communication method provided by the present invention, the communication between the previous I2C device and the target I2C device further includes:

[0014] When the target I2C device is the subsequent I2C device and the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device, calling the controlled peripheral of the first I2C device to forward the first data to the previous I2C device; the controlled peripheral of the first I2C device is connected to the master peripheral of the previous I2C device;

[0015] When the target I2C device is the subsequent I2C device and the controlled peripheral of the first I2C device receives the second data sent by the previous I2C device, calling the master peripheral of the first I2C device to forward the second data to the subsequent I2C device.

[0016] According to the I2C device communication method provided by the present invention, the method further includes:

[0017] When the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device or the second data forwarded by the controlled peripheral of the first I2C device, setting the timeout duration;

[0018] When the master peripheral of the first I2C device receives new first data or new second data within the timeout duration, it sends the new first data to the slave peripheral of the first I2C device, or sends the new second data to the subsequent I2C device.

[0019] According to the I2C device communication method provided by the present invention, the method further includes:

[0020] When the master peripheral of the first I2C device does not receive the new first data or the new second data within the timeout duration, or when the slave peripheral of the first I2C device receives a stop signal sent by the previous I2C device, the master peripheral of the first I2C device is called to send a stop signal to the subsequent I2C device.

[0021] According to the I2C device communication method provided by the present invention, the method further includes:

[0022] When the target I2C device is the subsequent I2C device and the master peripheral of the first I2C device receives the first data or the second data, the master peripheral of the first I2C device is locked, and after the master peripheral of the first I2C device sends the stop signal to the subsequent I2C device, the master peripheral of the first I2C device is unlocked.

[0023] The present invention also provides an I2C device communication apparatus, which is applied to a first I2C device. The first I2C device is any one of the I2C devices, and the I2C devices are cascaded. The apparatus includes:

[0024] A receiving module, configured to receive the target slave address of the previous I2C device;

[0025] A determining module, configured to determine a target I2C device based on the target slave address and the device address of the first I2C device, so that the previous I2C device communicates with the target I2C device.

[0026] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the I2C device communication method described in any one of the above is implemented.

[0027] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the I2C device communication method described in any one of the above is implemented.

[0028] The I2C device communication method, device, electronic device, and storage medium provided by the present invention, in the case of cascading I2C devices, for the first I2C device, when the first I2C device receives the target slave address sent by the previous-stage I2C device, the target slave address is matched with the device address of the first I2C device, and the target I2C device is determined according to the matching result, so as to realize the communication between the previous-stage I2C device and the target I2C device, and further realize the I2C communication between any two I2C devices in the I2C network topology without occupying additional hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 is one of the connection diagrams of the I2C network topology provided by the prior art;

[0031] Figure 2 is another connection diagram of the I2C network topology provided by the prior art;

[0032] Figure 3 is a flowchart of the I2C device communication method provided by an embodiment of the present invention;

[0033] Figure 4 is a connection diagram of the I2C network topology provided by an embodiment of the present invention;

[0034] Figure 5 is one of the flowcharts of writing data provided by an embodiment of the present invention;

[0035] Figure 6 is one of the flowcharts of reading data provided by an embodiment of the present invention;

[0036] Figure 7 is another flowchart of writing data provided by an embodiment of the present invention;

[0037] Figure 8 is another flowchart of reading data provided by an embodiment of the present invention;

[0038] Figure 9 is a schematic diagram of continuous data writing provided by an embodiment of the present invention;

[0039] Figure 10 is a structural diagram of the I2C device communication device provided by an embodiment of the present invention;

[0040] Figure 11 It is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0041] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0042] Aiming at the problem that communication between master devices cannot be performed due to a fixed transmission direction in the prior art, an I2C device communication method is provided by an embodiment of the present invention, which is applied to a first I2C device. The first I2C device is any I2C device, and the I2C devices are cascaded. Figure 3 It is a schematic flowchart of the I2C device communication method provided by an embodiment of the present invention, as Figure 3 shown, the method includes:

[0043] Step 310: Receive the target slave address of the previous-stage I2C device.

[0044] Specifically, the first I2C device receives a start signal Start sent by the previous-stage I2C device. After receiving the start signal Start, the first I2C device continues to receive the target slave address sent by the previous-stage I2C device. The target slave address is the device address of the destination I2C device to which the previous-stage I2C device will write data or read data. The destination I2C device may be the first I2C device or other I2C devices other than the previous-stage I2C device and the first I2C device. At this time, the previous-stage I2C device serves as the master device, and the destination I2C device serves as the slave device. That is, the previous-stage I2C device and the destination I2C device may be directly connected or connected through at least one cascaded I2C device.

[0045] Optionally, the first I2C device is any I2C device in an I2C network topology, and the I2C network topology includes at least three I2C devices. Figure 4 It is a schematic connection diagram of the I2C network topology provided by an embodiment of the present invention, as Figure 4As shown in the figure, the I2C network topology includes N I2C (Inter-Integrated Circuit) devices, where N is an integer greater than or equal to 3. The I2C devices are cascaded to form a ring-shaped I2C network topology. For example, the controlled peripheral of I2C device 2 is connected to the master peripheral of I2C device 1, the master peripheral of I2C device 2 is connected to the controlled peripheral of I2C device 3, the controlled peripheral of I2C device 1 is connected to the master peripheral of I2C device N, and the connection relationships between other I2C devices and the previous and subsequent I2C devices are the same as those of I2C device 2, forming a ring-shaped I2C network topology.

[0046] It should be noted that the above-mentioned master peripheral and controlled peripheral can be understood as pins in hardware. In the prior art, two devices are connected through I2C pins. The device that actively initiates communication is the master device, and the device that receives data is the slave device. That is, if an I2C device only uses the master peripheral to communicate with other I2C devices, then this I2C device is the master device; if an I2C device only uses the controlled peripheral to communicate with other I2C devices, then this I2C device is the slave device. Generally, the master-slave role is determined during initialization and will not change thereafter. In the prior art, communication with other devices can only be achieved through the master peripheral or the controlled peripheral, and communication between master devices cannot be achieved. In the embodiments of the present invention, by using the master peripherals and controlled peripherals in each I2C device to cascade the I2C devices, communication between any two I2C devices in the I2C network topology can be achieved, regardless of whether the I2C device is a master device or a slave device. In addition, the I2C bus supports multi-slave device connections, that is, a master device can be connected to multiple I2C devices, and different slave devices are distinguished by device addresses. In the 7-bit addressing strategy, since the 0x0 address is unavailable, up to 127 device addresses are supported.

[0047] Optionally, while receiving the target slave address sent by the previous I2C device, the operation flag sent by the previous I2C device is also received. The operation flag can include a write data flag or a read data flag. The write data flag is used to indicate that the previous I2C device is going to write data to the target I2C device, and the read data flag is used to indicate that the previous I2C device is going to read data from the target I2C device.

[0048] Step 320: Based on the target slave address and the device address of the first I2C device, determine the target I2C device to enable communication between the previous I2C device and the target I2C device.

[0049] Specifically, after receiving the target slave address sent by the previous-stage I2C device, the device address of itself, that is, the device address of this first I2C device, is obtained. Then, the target slave address is matched with the device address, and according to the address matching result, it is determined whether the target I2C device is this first I2C device or other I2C devices except the previous-stage I2C device and the first I2C device. Through the communication between the previous-stage I2C device and the target I2C device, the communication between the previous-stage I2C device and the destination I2C device is further realized, that is, the communication between any two I2C devices in the I2C network topology is realized, and the problem that the master devices cannot communicate with each other due to the fixed data transmission direction in the prior art is solved.

[0050] Further, determining the target I2C device based on the target slave address and the device address of the first I2C device includes:

[0051] In the case where the target slave address is inconsistent with the device address of the first I2C device, it is determined that the target I2C device is the subsequent-stage I2C device of the first I2C device, and the master control end peripheral of the first I2C device is connected to the controlled end peripheral of the subsequent-stage I2C device;

[0052] In the case where the target slave address is consistent with the device address of the first I2C device, it is determined that the target I2C device is the first I2C device.

[0053] Specifically, if the target slave address is inconsistent with the device address of the first I2C device, it indicates that the target I2C device is not the first I2C device. At this time, the first I2C device determines that the target I2C device is the subsequent-stage I2C device of the first I2C device, and the master control end peripheral of this first I2C device is connected to the controlled end peripheral of the subsequent-stage I2C device. This first I2C device can forward the data sent by the previous-stage I2C device to the subsequent-stage I2C device. If the target slave address is consistent with the device address of the first I2C device, it indicates that the target I2C device is the first I2C device, that is, the destination I2C device for the previous-stage I2C device to write data or read data is the first I2C device. At this time, the data interaction between the master control end peripheral of the previous-stage I2C device and the slave control end of the first I2C device can be used to realize reading data or writing data.

[0054] It should be noted that the target I2C device can be understood as the I2C device that this first I2C device believes needs to communicate with the previous-stage I2C device. The target I2C device can be the destination I2C device or not. For example, Figure 4As shown in the figure, taking the previous I2C device as I2C device 1, the first I2C device as I2C device 2, and the destination I2C device as I2C device 4 as an example, the target I2C device determined by the first I2C device is I2C device 3. During the communication process between the previous I2C device and I2C device 3, the first I2C device plays a role in data forwarding. After the target slave address is forwarded from I2C device 2 to I2C device 3, I2C device 3 continues to perform address matching and determine the target I2C device, and it can be determined that the target I2C device is I2C device 4. At this time, the target I2C device determined by I2C device 3 is the same as the destination I2C device. Through the data forwarding of I2C device 2 and I2C device 3, the communication between the previous I2C device and I2C device 4 can be realized without occupying additional hardware resources.

[0055] Optionally, Figure 5 is one of the schematic diagrams of the process of writing data provided by the embodiments of the present invention. As Figure 5 shown, when the target I2C device or the destination I2C device is the first I2C device, the previous I2C device only calls the main control end peripheral to communicate with the controlled end peripheral of the first I2C device. If the operation flag received by the first I2C device is the write data flag, the process of writing data between the previous I2C device and the first I2C device is as follows:

[0056] 1) The previous I2C device calls the main control end peripheral to send a start signal Start to the controlled end peripheral of the first I2C device.

[0057] 2) The previous I2C device calls the main control end peripheral to send address data to the controlled end peripheral of the first I2C device. The address data includes a 7-bit target slave address and a 1-bit write data flag, and the target slave address is the device address of the first I2C device.

[0058] 3) The first I2C device matches the target slave address with the device address. After the address matching is successful, the first I2C device sends an ACK (Acknowledge character) signal to the previous I2C device. At this time, the ACK signal indicates that the received target slave address matches successfully and the write data flag is correct.

[0059] 4) After receiving the ACK signal, the previous I2C device continues to send an 8-bit register address to the first I2C device.

[0060] 5) After receiving the register address, the first I2C device sends an ACK signal to the previous I2C device. At this time, the ACK signal indicates that the received register address is correct.

[0061] 6) After the front - end I2C device receives the ACK signal, it continues to send 8 - bit data to be written to the first I2C device.

[0062] 7) After the first I2C device receives the data to be written and writes the data to the corresponding register address, it sends an ACK signal to the front - end I2C device. At this time, the ACK signal indicates that the data to be written is successfully written.

[0063] 8) After the front - end I2C device receives the ACK signal, it can repeat steps 4) to 7) above, or it can send a stop signal Stop to the first I2C device to indicate the end of the data - writing process.

[0064] It should be noted that during the data - writing process, the register address and the data to be written need to be sent in pairs. That is, before writing each data to be written, the register address corresponding to the data to be written needs to be sent first. If a new data to be written needs to be written, the new register address corresponding to the new data to be written needs to be sent first.

[0065] Optionally, Figure 6 is one of the schematic diagrams of the data - reading process provided by the embodiments of the present invention. As Figure 6 shown, when the target I2C device or the destination I2C device is the first I2C device, the front - end I2C device only calls the master - side peripheral to communicate with the slave - side peripheral of the first I2C device. When the first I2C device receives a data - reading flag as the operation flag, the data - reading process between the front - end I2C device and the first I2C device is as follows:

[0066] 1) The front - end I2C device calls the master - side peripheral to send a start signal Start to the slave - side peripheral of the first I2C device.

[0067] 2) The front - end I2C device calls the master - side peripheral to send address data to the slave - side peripheral of the first I2C device. The address data includes a 7 - bit target slave address and a 1 - bit data - reading flag, and the target slave address is the device address of the first I2C device.

[0068] 3) The first I2C device matches the target slave address with the device address. After the address matching is successful, the first I2C device sends an ACK (Acknowledge character) signal to the front - end I2C device. At this time, the ACK signal indicates that the received target slave address matches successfully and the data - reading flag is correct.

[0069] 4) After the front - end I2C device receives the ACK signal, it continues to send an 8 - bit register address to the first I2C device.

[0070] 5) After receiving the register address, the first I2C device sends an ACK signal to the previous I2C device. At this time, the ACK signal indicates that the received register address is correct.

[0071] 6) Repeat steps 1) to 3). The first I2C device reads the data to be read corresponding to the register address and sends the data to be read to the previous I2C device.

[0072] 7) After receiving the data to be read, the previous I2C device may send a NO ACK signal to the first I2C device. The NO ACK signal is used to indicate that the reading of the data to be read is completed. After that, the above steps 4) to 6) can be repeated to continue obtaining the data to be read corresponding to other register addresses, or the previous I2C device sends a stop signal Stop to the first I2C device to indicate the end of the data reading process.

[0073] It should be noted that during the data reading process, the register address and the address data need to be sent in pairs. That is, before reading each data to be read, the register address corresponding to the data to be read needs to be sent first, and then the address data is sent again. If a new data to be read needs to be read, the new register address corresponding to the new data to be written needs to be sent first, and then the address data is sent again.

[0074] Further, the communication between the previous I2C device and the target I2C device includes:

[0075] When the target I2C device is the subsequent I2C device, the master peripheral of the first I2C device is called to send the target slave address to the subsequent I2C device.

[0076] Specifically, when the first I2C device determines that the target I2C device is the subsequent I2C device, it indicates that it is in the communication process between the previous I2C device and the target I2C device, and the first I2C device plays a role in data forwarding during the communication process between the previous I2C device and the target I2C device, rather than the normal communication process between the first I2C device and the subsequent I2C device. At this time, the target slave address can be forwarded from the controlled peripheral of the first I2C device to the master peripheral of the first I2C device. Since the master peripheral of the first I2C device is connected to the controlled peripheral of the subsequent I2C device, the master peripheral of the first I2C device can be called to send the target slave address to the slave control end of the subsequent I2C device, which is convenient for the subsequent I2C device to continue to determine a new target I2C device based on the target slave address and the device address of the subsequent I2C device.

[0077] Further, the communication between the previous I2C device and the target I2C device further includes:

[0078] When the target I2C device is the subsequent I2C device and the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device, the slave peripheral of the first I2C device is called to forward the first data to the previous I2C device; the slave peripheral of the first I2C device is connected to the master peripheral of the previous I2C device;

[0079] When the target I2C device is the subsequent I2C device and the slave peripheral of the first I2C device receives the second data sent by the previous I2C device, the master peripheral of the first I2C device is called to forward the second data to the subsequent I2C device.

[0080] Specifically, when the first I2C device determines that the target I2C device is the subsequent I2C device, the first I2C device plays a role in data forwarding during the communication between the previous I2C device and the subsequent I2C device. Therefore, after calling the master peripheral of the first I2C device to forward the target slave address to the subsequent I2C device, if the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device, the first data is first forwarded from the master peripheral of the first I2C device to the slave peripheral of the first I2C device, and the slave peripheral of the first I2C device is called to forward the first data to the master peripheral of the previous I2C device. If the slave peripheral of the first I2C device receives the second data sent by the previous I2C device, the second data is first forwarded from the slave peripheral of the first I2C device to the master peripheral of the first I2C device, and the master peripheral of the first I2C device is called to forward the second data to the subsequent I2C device.

[0081] Optionally, when the previous I2C device writes data to the destination I2C device, the first data may be an ACK signal sent by the subsequent I2C device, and the second data may be a register address or data to be written sent by the previous I2C device.

[0082] Exemplary, Figure 7 is the second schematic diagram of the data writing process provided by the embodiments of the present invention. As Figure 7 shown, taking the I2C network topology including a total of 3 cascaded I2C devices, namely I2C device 1, I2C device 2, and I2C device 3, where the previous I2C device is I2C device 1 and the first I2C device is I2C device 2 as an example, the process of the previous I2C device writing data to the destination I2C device is as follows:

[0083] 1) I2C device 1 calls the master peripheral to send a start signal Start to the slave peripheral of I2C device 2, and sends the target slave address and the write data flag to I2C device 2. The target slave address is the device address of I2C device 3.

[0084] 2) The I2C device 2 matches the target slave address with its own device address. After the address matching fails, the I2C device 2 calls the master peripheral of the I2C device 2 to send a start signal Start, the target slave address, and a write data flag to the controlled peripheral of the I2C device 3. The I2C device 3 matches the target slave address with its own device address. After the address matching is successful, the I2C device 3 calls the controlled peripheral to send an ACK signal to the master peripheral of the I2C device 2. At this time, this ACK signal indicates that the received target slave address matches successfully and the write data flag is correct. The I2C device 2 forwards the ACK signal from the master peripheral to the controlled peripheral and calls the controlled peripheral to forward the ACK signal to the master peripheral of the I2C device 1.

[0085] 3) After receiving the ACK signal, the I2C device 1 continues to send the register address to the controlled peripheral of the I2C device 2. After receiving the register address, the controlled peripheral of the I2C device 2 first forwards the register address from the controlled peripheral to the master peripheral and calls the master peripheral to forward this register address to the I2C device 3. After receiving the register address, the I2C device 3 sends an ACK signal to the master peripheral of the I2C device 2. At this time, this ACK signal indicates that the received register address is correct. The I2C device 2 forwards the ACK signal from the master peripheral to the controlled peripheral and calls the controlled peripheral to forward this ACK signal to the I2C device 1.

[0086] 4) After receiving the ACK signal, the I2C device 1 continues to send the data to be written to the I2C device 2. The I2C device 2 forwards the data to be written from the controlled peripheral to the master peripheral and calls the master peripheral to forward the data to be written to the I2C device 3. After receiving the data to be written and writing this data to the corresponding register address, the I2C device 3 sends an ACK signal to the master peripheral of the I2C device 2. At this time, this ACK signal indicates that the data to be written is successfully written. The I2C device 2 first forwards this ACK signal from the master peripheral to the controlled peripheral and calls the controlled peripheral to forward this ACK signal to the I2C device 1.

[0087] 5) After receiving the ACK signal, the I2C device 1 can send a NO ACK signal to the I2C device 2. At this time, this NO ACK signal indicates that the data to be written is written completely. After that, the above steps 3)-4) can be repeated to continuously write data to the I2C device 3, or send a stop signal Stop to the controlled peripheral of the I2C device 2 to indicate the end of the write data process.

[0088] Optionally, when the front - end I2C device reads data from the target I2C device, the first data may be the ACK signal sent by the back - end I2C device or the data to be read corresponding to the register address.

[0089] Exemplarily, Figure 8 is the second schematic diagram of the process of reading data provided by an embodiment of the present invention. As Figure 8 shown, taking an I2C network topology including a total of 3 cascaded I2C devices, namely I2C device 1, I2C device 2, and I2C device 3, where the front - end I2C device is I2C device 1 and the first I2C device is I2C device 2 as an example, the first 3 steps in the process of the front - end I2C device reading data from the target I2C device are the same as the first 3 steps in the process of writing data. The differences between reading data and writing data are as follows:

[0090] 1) After I2C device 1 receives the ACK signal corresponding to the register address, it continues to send the target slave address and the read - data flag to I2C device 2. When the address of I2C device 2 fails to match and the address of I2C device 3 matches successfully, I2C device 3 calls the controlled - end peripheral to send an ACK signal to the master - end peripheral of I2C device 2. I2C device 2 forwards the ACK signal from the master - end peripheral to the controlled - end peripheral and calls the controlled - end peripheral to forward the ACK signal to the master - end peripheral of I2C device 1.

[0091] 2) I2C device 3 reads the data to be read corresponding to the register address and sends the data to be read to the master - end peripheral of I2C device 2. I2C device 2 forwards the data to be read from the master - end peripheral to the controlled - end peripheral and calls the controlled - end peripheral to forward the data to be read to the master - end peripheral of I2C device 1.

[0092] 3) After receiving the data to be read, I2C device 1 sends a NO ACK signal to I2C device 2. The NO ACK signal is used to indicate that the reading of the data to be read is completed. After exceeding the timeout duration, I2C device 2 calls the master - end peripheral to send a NO ACK signal to I2C device 3.

[0093] 4) Repeat sending the register address and steps 1) to 3). I2C device 1 can continuously read the data to be read corresponding to different register addresses in I2C device 3, or I2C device 1 sends a stop signal Stop to the slave - controlled end of I2C device 2, indicating the end of the data - reading process. After exceeding the timeout duration, I2C device 2 calls the master - end peripheral to send a stop signal Stop to I2C device 3.

[0094] Furthermore, the method further includes:

[0095] When the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device or the second data forwarded by the slave peripheral of the first I2C device, a timeout duration is set.

[0096] When the master peripheral of the first I2C device receives new first data or new second data within the timeout duration, the new first data is sent to the slave peripheral of the first I2C device, or the new second data is sent to the subsequent I2C device.

[0097] Specifically, when the previous I2C device continuously writes data to the destination I2C device or continuously reads data from the destination I2C device, when the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device to the previous I2C device, or the slave peripheral of the first I2C device receives the second data sent by the previous I2C device to the subsequent I2C device, a timeout duration is set. If new first data or new second data is received within the timeout duration, the new first data is continuously forwarded to the previous I2C device, or the new second data is continuously forwarded to the subsequent I2C device.

[0098] Further, the method further includes:

[0099] When the master peripheral of the first I2C device does not receive the new first data or the new second data within the timeout duration, or when the slave peripheral of the first I2C device receives the stop signal Stop sent by the previous I2C device, the master peripheral of the first I2C device is called to send the stop signal Stop to the subsequent I2C device.

[0100] Exemplarily, Figure 9 is a schematic diagram of continuous data writing provided by an embodiment of the present invention. As Figure 9As shown, taking the example where the previous I2C device continuously writes data to the destination I2C device, the timestamp when Data2 is forwarded to the main control peripheral of the first I2C device is within the timeout duration, and the timestamp when Data3 is forwarded to the main control peripheral of the first I2C device exceeds the timeout duration. When the main control peripheral of the first I2C device receives Data1 forwarded by the controlled peripheral, the timeout duration is set. If the time interval between the timestamp when Data2 is forwarded from the controlled peripheral of the first I2C device to the main control peripheral and the timestamp when the main control peripheral of the first I2C device receives Data1 is less than or equal to the timeout duration, the main control peripheral of the first I2C device is called to forward Data2 to the subsequent I2C device. At this time, the timeout duration is also set. If the time interval between the timestamp when the main control peripheral of the first I2C device receives Data3 and the timestamp when it receives Data2 is greater than the timeout duration, Data3 is not forwarded to the subsequent I2C device. When this time interval exceeds the timeout duration, the main control peripheral of the first I2C device is called to send a stop signal Stop to the subsequent I2C device.

[0101] In addition, as Figure 7 or Figure 8 shown, after the previous I2C device sends a stop signal Stop to the controlled peripheral of the first I2C device, after exceeding the timeout duration, the first I2C device calls the main control peripheral of the first I2C device to send a stop signal Stop to the subsequent I2C device, indicating the end of writing data or the end of reading data.

[0102] Furthermore, the method further includes:

[0103] When the target I2C device is the subsequent I2C device and the main control peripheral of the first I2C device receives the first data or the second data, the main control peripheral of the first I2C device is locked, and after the main control peripheral of the first I2C device sends the stop signal Stop to the subsequent I2C device, the main control peripheral of the first I2C device is unlocked.

[0104] Specifically, when the target I2C device is a subsequent I2C device, and during the process of the previous I2C device writing data to the target I2C device or reading data from the target I2C device, the master peripheral of the first I2C device needs to determine whether the current operation is a normal communication between the first I2C device and the subsequent I2C device, or data forwarding during the communication process between the previous I2C device and the subsequent I2C device. Therefore, the master peripheral of the first I2C device cannot be interrupted during the entire data writing or reading process. Therefore, when the master peripheral of the first I2C device receives the first data or the second data, the master peripheral of the first I2C device is locked. After the entire data writing or reading process ends, that is, after the master peripheral of the first I2C device sends a stop signal Stop to the subsequent I2C device, the master peripheral of the first I2C device is unlocked. After the master peripheral of the first I2C device is unlocked, it can then forward the data of other I2C devices or communicate normally with the subsequent I2C device. For example, as Figure 4 shown, taking the I2C device as the first I2C device and the I2C device 1 as the previous I2C device as an example, during the process of the I2C device 1 writing the first data to be written to the I2C device 3, the master peripheral of the I2C device 2 is locked. When the first data to be written is written to the I2C device 3 and the master peripheral of the I2C device 2 does not receive new first data or second data within the timeout duration, the master peripheral of the I2C device 2 sends a stop signal Stop to the I2C device 3. At this time, the master peripheral of the I2C device 2 is unlocked. After the master peripheral of the I2C device 2 is unlocked, the master peripheral of the I2C device 2 can forward the second data to be written that was first forwarded from the I2C device N to the I2C device 1 and then forwarded from the I2C device 1 to the I2C device 2. The master peripheral of the I2C device 2 can forward the second data to be written to the I2C device 3. During the process of writing the second data to be written to the I2C device 3, the master peripheral of the I2C device 2 is also in a locked state. By setting the timeout duration, the data of each I2C device can be cross-transmitted, avoiding the I2C bus being occupied for a long time, resulting in the data transmission of other devices being continuously delayed.

[0105] Optionally, the entire data writing process or the entire data reading process can be encapsulated into a function to implement the locking and unlocking of the master peripheral of the first I2C device.

[0106] In addition, since the master peripheral of the first I2C device is in a locked state during the scheduling process, it can ensure the integrity of the data forwarded by the master peripheral of the first I2C device. Therefore, during the process of the controlled peripheral of the first I2C device waiting for a reply from the subsequent I2C device after forwarding the data, the master peripheral of the previous I2C device will not send new data to the controlled peripheral of the first I2C device.

[0107] It should be noted that the locking operation is all software program operations, that is, the software code corresponding to the sending process of the master control terminal peripherals is locked. This locking operation is to ensure that the function of the sending process is not called by other threads before it ends, so as to ensure that the data sent this time is not interrupted.

[0108] In the I2C device communication method provided by the embodiments of the present invention, in the case where I2C devices are cascaded, for the first I2C device, when the first I2C device receives the target slave address sent by the previous-stage I2C device, the target slave address is matched with the device address of the first I2C device, and the target I2C device is determined according to the matching result, so as to realize the communication between the previous-stage I2C device and the target I2C device, and further realize the I2C communication between any two I2C devices in the I2C network topology without occupying additional hardware resources.

[0109] The I2C device communication device provided by the present invention will be described below. The I2C device communication device described below can be correspondingly referred to the I2C device communication method described above.

[0110] An embodiment of the present invention provides an I2C device communication device, which is applied to the first I2C device. The first I2C device is any one of the I2C devices, and the I2C devices are cascaded. Figure 10 is a schematic structural diagram of the I2C device communication device provided by the embodiments of the present invention, as Figure 10 shown, the I2C device communication device 1000 includes: a receiving module 1010 and a determining module 1020, where:

[0111] The receiving module 1010 is configured to receive the target slave address of the previous-stage I2C device;

[0112] The determining module 1020 is configured to determine the target I2C device based on the target slave address and the device address of the first I2C device, so that the previous-stage I2C device communicates with the target I2C device.

[0113] In the I2C device communication device provided by the embodiments of the present invention, in the case where I2C devices are cascaded, for the first I2C device, when the first I2C device receives the target slave address sent by the previous-stage I2C device, the target slave address is matched with the device address of the first I2C device, and the target I2C device is determined according to the matching result, so as to realize the communication between the previous-stage I2C device and the target I2C device, and further realize the I2C communication between any two I2C devices in the I2C network topology without occupying additional hardware resources.

[0114] Optionally, the determining module 1020 is specifically configured to:

[0115] In the case where the target slave address is inconsistent with the device address of the first I2C device, determine that the target I2C device is a subsequent I2C device of the first I2C device, and connect the master peripheral of the first I2C device to the controlled peripheral of the subsequent I2C device;

[0116] In the case where the target slave address is consistent with the device address of the first I2C device, determine that the target I2C device is the first I2C device.

[0117] Optionally, the determining module 1020 is specifically configured to:

[0118] In the case where the target I2C device is the subsequent I2C device, call the master peripheral of the first I2C device to send the target slave address to the subsequent I2C device.

[0119] Optionally, the determining module 1020 is specifically configured to:

[0120] In the case where the target I2C device is the subsequent I2C device and the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device, call the controlled peripheral of the first I2C device to forward the first data to the previous I2C device; the controlled peripheral of the first I2C device is connected to the master peripheral of the previous I2C device;

[0121] In the case where the target I2C device is the subsequent I2C device and the controlled peripheral of the first I2C device receives the second data sent by the previous I2C device, call the master peripheral of the first I2C device to forward the second data to the subsequent I2C device.

[0122] Optionally, the I2C device communication device 1000 further includes: a forwarding module, and the forwarding module is specifically configured to:

[0123] In the case where the master peripheral of the first I2C device receives the first data sent by the subsequent I2C device or the second data forwarded by the controlled peripheral of the first I2C device, set a timeout duration;

[0124] In the case where the master peripheral of the first I2C device receives new first data or new second data within the timeout duration, send the new first data to the controlled peripheral of the first I2C device, or send the new second data to the subsequent I2C device.

[0125] Optionally, the forwarding module is specifically configured to:

[0126] When the master peripheral of the first I2C device does not receive the new first data or the new second data within the timeout duration, or the slave peripheral of the first I2C device receives the stop signal sent by the previous I2C device, the master peripheral of the first I2C device is called to send a stop signal to the subsequent I2C device.

[0127] Optionally, the I2C device communication device 1000 further includes: a locking module, which is specifically used for:

[0128] When the target I2C device is the subsequent I2C device and the master peripheral of the first I2C device receives the first data or the second data, the master peripheral of the first I2C device is locked, and after the master peripheral of the first I2C device sends the stop signal to the subsequent I2C device, the master peripheral of the first I2C device is unlocked. The locking operation is a software program operation, that is, the software code corresponding to the sending process of the master peripheral is locked. This locking behavior is to ensure that the function of the sending process is not called by other threads before it ends, so as to ensure that the data sent this time is not interrupted.

[0129] Figure 11 It is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. As Figure 11 shown, the electronic device may include: a processor 1110, a communication interface 1120, a memory 1130, and a communication bus 1140. Among them, the processor 1110, the communication interface 1120, and the memory 1130 communicate with each other through the communication bus 1140. The processor 1110 may call the logical instructions in the memory 1130 to execute the I2C device communication method, and this method includes:

[0130] Receiving the target slave address of the previous I2C device;

[0131] Based on the target slave address and the device address of the first I2C device, determining the target I2C device to enable the previous I2C device to communicate with the target I2C device.

[0132] In addition, when the logical instructions in the above-mentioned memory 1130 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0133] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the I2C device communication method provided by the above-mentioned various methods. The method includes:

[0134] Receiving the target slave address of the previous-stage I2C device;

[0135] Based on the target slave address and the device address of the first I2C device, determining the target I2C device so that the previous-stage I2C device communicates with the target I2C device.

[0136] In yet another aspect, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is implemented to execute the I2C device communication method provided by the above-mentioned various methods. The method includes:

[0137] Receiving the target slave address of the previous-stage I2C device;

[0138] Based on the target slave address and the device address of the first I2C device, determining the target I2C device so that the previous-stage I2C device communicates with the target I2C device.

[0139] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0140] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.

Claims

1. An I2C device communication method, characterized in that, applied to a first I2C device, the first I2C device being any one of the I2C devices, and the I2C devices being cascaded, the method comprising: receiving a target slave address of a previous-stage I2C device; determining a target I2C device based on the target slave address and the device address of the first I2C device, so that the previous-stage I2C device communicates with the target I2C device.

2. The I2C device communication method according to claim 1, characterized in that, the determining a target I2C device based on the target slave address and the device address of the first I2C device includes: when the target slave address is inconsistent with the device address of the first I2C device, determining that the target I2C device is a subsequent-stage I2C device of the first I2C device, and connecting the main control peripheral of the first I2C device to the controlled peripheral of the subsequent-stage I2C device; when the target slave address is consistent with the device address of the first I2C device, determining that the target I2C device is the first I2C device.

3. The I2C device communication method according to claim 2, characterized in that, the previous-stage I2C device communicating with the target I2C device includes: when the target I2C device is the subsequent-stage I2C device, invoking the main control peripheral of the first I2C device to send the target slave address to the subsequent-stage I2C device.

4. The I2C device communication method according to claim 3, characterized in that, the previous-stage I2C device communicating with the target I2C device further includes: when the target I2C device is the subsequent-stage I2C device and the main control peripheral of the first I2C device receives the first data sent by the subsequent-stage I2C device, invoking the controlled peripheral of the first I2C device to forward the first data to the previous-stage I2C device; the controlled peripheral of the first I2C device is connected to the main control peripheral of the previous-stage I2C device; when the target I2C device is the subsequent-stage I2C device and the controlled peripheral of the first I2C device receives the second data sent by the previous-stage I2C device, invoking the main control peripheral of the first I2C device to forward the second data to the subsequent-stage I2C device.

5. The I2C device communication method according to any one of claims 2-4, characterized in that, the method further includes: when the main control peripheral of the first I2C device receives the first data sent by the subsequent-stage I2C device or the second data forwarded by the controlled peripheral of the first I2C device, setting a timeout duration; when the main control peripheral of the first I2C device receives new first data or new second data within the timeout duration, sending the new first data to the controlled peripheral of the first I2C device, or sending the new second data to the subsequent-stage I2C device.

6. The I2C device communication method according to claim 5, It is characterized in that The method further includes: When the master peripheral of the first I2C device does not receive the new first data or the new second data within the timeout period, or the slave peripheral of the first I2C device receives the stop signal sent by the previous I2C device, the master peripheral of the first I2C device is called to send a stop signal to the subsequent I2C device.

7. The I2C device communication method according to claim 6, It is characterized in that The method further includes: When the target I2C device is the subsequent I2C device and the master peripheral of the first I2C device receives the first data or the second data, the master peripheral of the first I2C device is locked, and after the master peripheral of the first I2C device sends the stop signal to the subsequent I2C device, the master peripheral of the first I2C device is unlocked.

8. An I2C device communication apparatus, It is characterized in that Applied to a first I2C device, the first I2C device is any one of the I2C devices, and the I2C devices are cascaded. The apparatus includes: A receiving module, configured to receive the target slave address of the previous I2C device; A determining module, configured to determine a target I2C device based on the target slave address and the device address of the first I2C device, so that the previous I2C device communicates with the target I2C device.

9. An electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, It is characterized in that When the processor executes the program, the I2C device communication method according to any one of claims 1-7 is implemented.

10. A computer-readable storage medium, on which a computer program is stored, It is characterized in that When the computer program is executed by a processor, the I2C device communication method according to any one of claims 1-7 is implemented.

Images