Optical computing chip data transmission method based on Type-C interface

Abstract

The invention discloses an optical computing chip data transmission method based on a Type-C interface. The method comprises the following steps: S1, providing ESP32-S3 and main hardware components; s2, connecting a Type-C to TTL (Transistor-Transistor Logic) interface and completing signal conversion; s3, adjusting the electric signal and transmitting the electric signal to an optical computing chip; s4, optical computing chip data processing and photoelectric conversion; s5, establishing a development environment and configuring a tool; s6, compiling a protocol analysis module; s7, developing a data processing module; and S8, testing and optimizing the system. By combining the optical computing chip and the Type-C interface, efficient, compatible and safe data transmission and processing are realized, and the bottleneck problems of the traditional technology in the aspects of data format conversion, transmission rate, delay and safety are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission and processing technologies, and in particular, to a data transmission method for an optical computing chip based on a Type-C interface. Background Art

[0002] With the rapid development of information technology and communication technology, the demand for data transmission and processing has shown an explosive growth. From the real-time data collection of Internet of Things devices, to the large-scale data transmission in high-performance computing environments, and then to the high-efficiency requirements for data processing in cloud computing and big data storage application scenarios, the limitations of traditional electronic data transmission and processing methods have gradually emerged. Especially in the context of the gradual maturity of optical computing technology, how to combine the high-efficiency performance of optical computing chips with a general data transmission interface has become an important problem that urgently needs to be solved in the industry.

[0003] Currently, mainstream data transmission and processing technologies rely on electronic signal transmission. Although the performance of chips is continuously improved and algorithms are optimized, electronic data transmission can still meet basic requirements in specific scenarios. However, in an environment with high bandwidth, large data volume, and low latency requirements, traditional electronic transmission technologies are gradually becoming inadequate. Specifically, in a big data environment, the transmission rate of traditional interfaces is restricted by the physical limitations of electronic signals and it is difficult to break through the existing bandwidth bottleneck. At the same time, the signal integrity in the data transmission process also faces challenges. Especially in the process of long-distance and high-rate transmission, the attenuation and interference problems of electronic signals increase significantly, affecting the quality of data transmission.

[0004] For this reason, optical computing chips have become a potential solution to these problems due to their high-efficiency data processing capabilities and low-power consumption characteristics. However, the interface technologies of existing optical computing chips are diverse and lack a unified standard, resulting in poor compatibility between devices. Additional conversion modules or adapters are required between different devices, which not only increases the hardware cost but also enhances the design complexity of the system. In addition, in the process of data transmission and storage, the existing interface technologies also have relatively limited solutions for data format standardization, compression of transmitted data, and protection of data security. Due to the lack of a flexible and efficient data preprocessing and protection mechanism, the existing technologies cannot well adapt to the diverse application scenario requirements.

[0005] High-speed data transmission interfaces represented by the Type-C interface have become widely used interface standards due to their support for high data rates, strong forward and reverse plug compatibility, and multi-protocol support. However, there are currently several technical challenges in the direct combination of the Type-C interface and optical computing chips. On the one hand, the functions of existing Type-C interface data processing modules are relatively single, and they can only achieve simple signal conversion, making it difficult to complete efficient data format adaptation and processing. On the other hand, security functions such as data encryption are mostly completed through external modules, and embedded security protection cannot be achieved during interface transmission. In addition, although traditional encryption algorithms can enhance data security, in high-bandwidth transmission environments, their encryption efficiency and dynamics are insufficient, making it difficult to meet the dual requirements of real-time and security.

[0006] There are also obvious limitations in the format conversion of data transmission in the prior art. Traditional technologies usually adopt static format standards and have poor adaptability to dynamic environments. In a multi-protocol collaborative environment, the data formats of different devices are diverse, but existing data processing modules are difficult to achieve rapid format conversion, resulting in a decrease in transmission efficiency. In terms of data compression, existing solutions mostly adopt a single compression algorithm and lack optimization strategies for multi-level data, making it difficult to balance the compression ratio and processing speed. This limitation is particularly significant in the application scenarios of optical computing chips.

[0007] Therefore, how to provide a data transmission method for optical computing chips based on the Type-C interface is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0008] An object of the present invention is to propose a data transmission method for optical computing chips based on the Type-C interface. The present invention adopts dynamic format adaptation, multi-level data compression, and an innovative encryption mechanism. By combining the high-efficiency computing power of optical computing chips with the high-speed data transmission performance of the Type-C interface, the implementation processes of data format conversion, compression, and encryption are described in detail. The present invention has the advantages of strong compatibility, high transmission efficiency, and good security. At the same time, it effectively reduces the complexity of system design and improves the adaptability and stability of data in multi-scenario applications.

[0009] A data transmission method for an optical computing chip based on the Type-C interface according to an embodiment of the present invention includes the following steps:

[0010] S1. Provide an ESP32-S3 microcontroller as the core control unit, connect its power supply terminal through a power supply circuit, and at the same time prepare a Type-C to TTL interface, a CH340N chip, a multi-channel voltage source module, and an optical computing chip as the main hardware components;

[0011] S2. Connect the Type-C to TTL interface to the ESP32-S3 microcontroller through hardware, and use the CH340N chip to complete the conversion between the Type-C interface signal and the UART serial port signal; connect the TX pin of the Type-C to TTL interface to the RX pin of the ESP32-S3, and connect the RX pin of the Type-C to TTL interface to the TX pin of the ESP32-S3;

[0012] S3. Transmit the electrical signal output by the ESP32-S3 microcontroller to the multi-channel voltage source module, adjust the voltage amplitude and parameters of the electrical signal through the multi-channel voltage source module to meet the input requirements of the optical computing chip, and then transmit the adjusted electrical signal to the input end of the optical computing chip;

[0013] S4. The optical computing chip processes the input electrical signal to generate a corresponding optical signal, and converts the output optical signal into an electrical signal through the optoelectronic conversion module;

[0014] S5. Set up the development environment, select Arduino IDE as the development tool, and configure the development environment of the ESP32-S3;

[0015] S6. Write the communication protocol parsing module program, parse and verify the received data packet based on the Type-C interface protocol, and generate a data format adapted to the optical computing chip;

[0016] S7. Develop the data processing module program, perform format conversion, compression and encryption processing on the parsed data to meet the system's requirements for data transmission and storage, and verify the overall data transmission performance;

[0017] S8. Conduct comprehensive testing on the system, including communication interface compatibility testing, data transmission rate verification and overall function testing, and finally complete system optimization and integration.

[0018] Optionally, the S2 specifically includes:

[0019] S21. Connect the Type-C end of the Type-C to TTL interface to an external Type-C device;

[0020] S22. Confirm the positions and functions of the TX and RX pins on the Type-C to TTL interface, and clarify their corresponding connection rules;

[0021] S23. Connect the TX pin of the Type-C to TTL interface to the RX pin of the ESP32-S3 microcontroller through hardware;

[0022] S24. Connect the RX pin of the Type-C to TTL interface to the TX pin of the ESP32-S3 microcontroller through hardware;

[0023] S25. Check whether the signal level output by the Type-C to TTL interface matches the input level of the ESP32-S3 microcontroller. If there is a difference, use a level conversion circuit for adjustment;

[0024] S26. Test the complete path of the signal from the Type-C interface, through the Type-C to TTL interface and transmitted to the ESP32-S3, and then from the ESP32-S3 output signal back to the Type-C to TTL interface.

[0025] Optionally, the S3 specifically includes:

[0026] S31. Connect the signal output pin of the ESP32-S3 microcontroller to the input end of the multi-channel voltage source module, and check the integrity of the connection line;

[0027] S32. Configure the output parameters of the ESP32-S3 microcontroller, including signal type, frequency and voltage range, to make its output signal match the input requirements of the multi-channel voltage source module;

[0028] S33. Transmit the electrical signal output by the ESP32-S3 microcontroller to the multi-channel voltage source module, adjust the characteristics of the input signal through the dynamic calibration resistor, and optimize the input signal by combining the non-linear calibration function to generate the signal parameters suitable for the optical computing chip:

[0029]

[0030] Among them, V out_module is the output voltage of the multi-channel voltage source module, V out_ESP32 is the output voltage of the ESP32 microcontroller, R calibrate is the calibration resistor of the module, t is the time variable, G module is the gain of the module, B module is the voltage offset value of the module, μ is the calibration coefficient, and σ is the modulation frequency;

[0031] S34. Debug the multi-channel voltage source module, calibrate the amplitude and characteristics of the output signal by adjusting the gain parameter and voltage amplitude setting inside the module, so that the output signal meets the electrical input specifications of the optical computing chip;

[0032] S35. Connect the output end of the multi-channel voltage source module to the signal input end of the optical computing chip, and ensure that the connection is firm without loose connection;

[0033] S36. Test the electrical parameters of the signal output from the ESP32-S3 after being adjusted by the multi-channel voltage source module, and verify the stability and accuracy of the signal after being transmitted to the input end of the optical computing chip.

[0034] Optionally, S4 specifically includes:

[0035] S41. Receive the electrical signal transmitted from the multi-channel voltage source module to the input end of the optical computing chip, and receive and preliminarily detect the input signal;

[0036] S42. Inside the optical computing chip, analyze the amplitude, frequency, and phase characteristics of the input electrical signal through the data processing unit;

[0037] S43. Use the operation module of the optical computing chip to perform non-linear modulation and multi-parameter coding on the analyzed electrical signal, and generate an optical signal through dynamic frequency calibration and time attenuation control. Among them, non-linear modulation combines the signal amplitude, frequency, phase characteristics, and dynamic calibration frequency, and time attenuation is used to simulate the influence of signal energy change with transmission conditions:

[0038] S modulated (t)=A in ·sin(ω mod t + φ mod +β·sin(ω cal t))·e -γt ;

[0039] Among them, S modulated (t) represents the modulated optical signal generated by the optical computing chip, A in is the amplitude of the input signal, ω mod is the angular frequency of the modulation signal, φ mod is the phase offset of the modulation signal, β is the non-linear calibration coefficient, ω cal is the calibration frequency, e -γt is the exponential decay factor, γ is the time attenuation coefficient, and t represents the time dimension of the signal generation process;

[0040] S44. Output the optical signal generated by the optical computing chip to the photoelectric conversion module, receive the optical signal through the photodetector and perform photoelectric conversion to generate the corresponding electrical signal;

[0041] S45. Perform gain adjustment and filtering processing on the electrical signal output by the photoelectric conversion module to increase the signal amplitude and signal-to-noise ratio and optimize the output signal quality.

[0042] Optionally, S6 specifically includes:

[0043] S61. Receive the data packet transmitted through the Type-C interface, and extract the header information of the data packet, including the identifier, length field, and check code;

[0044] S62. Analyze the content of the data packet according to the Type-C interface protocol standard, and identify the type, target address, and payload information of the data packet;

[0045] S63. Verify the check code in the data packet, and detect errors or data loss during the transmission process by comparing the check code with the data packet content;

[0046] S64. Perform format adaptation on the data packet that passes the verification through dynamic mapping rules. Combine multi-dimensional data reorganization operations and weight control to adjust, convert the format, and sort the priorities of the fields in the data packet. At the same time, dynamically generate matching results according to the target format requirements of the optical computing chip:

[0047]

[0048] where, Data output is the generated output data, N is the total data volume, w i is the weight of the i-th data conversion step, T i is the i-th data conversion operation function, Payload type is the payload part of the input data packet, λ is the dynamic regulation coefficient, F chip is the target format of the optical computing chip, D map is the dynamic mapping rule, Φ is the dynamic format matching function;

[0049] S65. Generate the target data format adapted to the optical computing chip, output it to the input end of the optical computing chip, and record the error information during the parsing and conversion process for diagnosis and optimization.

[0050] Optionally, the specific steps of S7 include:

[0051] S71. Receive the parsed data, identify its original format and structure, and perform preliminary analysis;

[0052] S72. Perform format conversion on the data content, and reorganize the original data into the target format that meets the system transmission and storage requirements, including adjusting the field arrangement, converting the data type, and standardizing the format;

[0053] S73. Perform data compression operations, reduce the data volume by deleting redundant information, optimizing the data structure, and applying compression algorithms;

[0054] S74. Perform dynamic encryption processing on the data after format conversion and compression. Adopt the Advanced Encryption Standard algorithm, combine the dynamic key generation and adaptive initialization vector mechanism, and generate encrypted data that meets the data transmission and storage requirements through multi-level preprocessing and performance regulation:

[0055] Data encrypted = E AES (C pre (Data compressed )K dynamic ,IVadaptive )δ·T enc ;

[0056] Among them, Data compressed represents the compressed data, C pre is the preprocessing function, E AES is the AES encryption function, K dynamic is the dynamically generated key, IV adaptive is the adaptive initialization vector, δ is the encryption performance regulation coefficient, T enc is the time delay term of the encryption process, Data encrypted is the finally generated encrypted data;

[0057] S75. Verify the overall performance of the data processing module, output the processed data to the target device or storage system by testing the integrity, rate, and encryption / decryption efficiency of data transmission.

[0058] The beneficial effects of the present invention are as follows:

[0059] Through the technical solution of the present invention, multiple deficiencies in the prior art are overcome, and remarkable beneficial effects are achieved. The present invention combines the high - efficiency computing power of the optical computing chip with the versatility and high - speed transmission performance of the Type - C interface through dynamic format adaptation, multi - level data compression, and innovative encryption mechanisms, significantly improving the efficiency of data transmission and processing. The dynamic format adaptation technology enables data to be flexibly converted according to the requirements of different devices, achieving fast adaptation in a multi - protocol environment and solving the compatibility deficiencies of existing interfaces; multi - level data compression effectively reduces the occupation of transmission bandwidth and storage resources, while ensuring the integrity of the compressed data, providing an efficient solution for large - data - volume scenarios; the innovative encryption mechanism, through dynamic key management, adaptive initialization vector, and multi - level preprocessing, not only improves the security of data but also takes into account real - time requirements, making up for the deficiencies of traditional encryption methods in terms of dynamics and performance optimization.

[0060] In addition, the present invention optimizes the collaborative working mechanism between the Type-C interface and the optical computing chip. Through data format standardization and dynamic calibration technology, the computing potential of the optical computing chip is fully released, enabling it to better serve high-bandwidth and low-latency application scenarios. Compared with the prior art, the present invention significantly reduces the hardware cost of interface adaptation, reduces the need for additional conversion modules, and improves the reliability and stability of the overall system through an embedded data processing mechanism. Due to the highly integrated design of the present invention, the data transmission process is more compact and efficient, which is not only applicable to complex scenarios such as the Internet of Things and high-performance computing, but also provides a low-cost and high-performance solution for data processing in consumer electronic devices. Thus, the present invention realizes a comprehensive improvement in compatibility, efficiency, and security, solves the bottleneck problems of the prior art under diverse application requirements, and lays a solid foundation for the popularization and application of optical computing technology in practical scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used in conjunction with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0062] Figure 1 is a flowchart of a data transmission method for an optical computing chip based on a Type-C interface proposed by the present invention;

[0063] Figure 2 is a schematic diagram of data format adaptation and dynamic format conversion of a data transmission method for an optical computing chip based on a Type-C interface proposed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0064] Now, the present invention will be further described in detail with reference to the drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present invention in a schematic manner, so they only show the components related to the present invention.

[0065] Referring to Figure 1-2 , a data transmission method for an optical computing chip based on a Type-C interface includes the following steps:

[0066] S1. Provide an ESP32-S3 microcontroller as the core control unit, connect its power supply terminal through a power supply circuit, and at the same time prepare a Type-C to TTL interface, a CH340N chip, a multi-channel voltage source module, and an optical computing chip as the main hardware components;

[0067] S2. Connect the Type-C to TTL interface to the ESP32-S3 microcontroller through hardware, and use the CH340N chip to complete the conversion between the Type-C interface signal and the UART serial port signal; connect the TX pin of the Type-C to TTL interface to the RX pin of the ESP32-S3, and connect the RX pin of the Type-C to TTL interface to the TX pin of the ESP32-S3;

[0068] S3. Transmit the electrical signal output by the ESP32-S3 microcontroller to the multi-channel voltage source module, adjust the voltage amplitude and parameters of the electrical signal through the multi-channel voltage source module to meet the input requirements of the optical computing chip, and then transmit the adjusted electrical signal to the input end of the optical computing chip;

[0069] S4. The optical computing chip processes the input electrical signal to generate a corresponding optical signal, and converts the output optical signal into an electrical signal through the optoelectronic conversion module;

[0070] S5. Set up the development environment, select Arduino IDE as the development tool, and configure the development environment of the ESP32-S3;

[0071] S6. Write the communication protocol parsing module program, parse and verify the received data packet based on the Type-C interface protocol, and generate a data format adapted to the optical computing chip;

[0072] S7. Develop the data processing module program, perform format conversion, compression and encryption processing on the parsed data to meet the system's requirements for data transmission and storage, and verify the overall data transmission performance;

[0073] S8. Conduct comprehensive testing on the system, including communication interface compatibility testing, data transmission rate verification and overall function testing, and finally complete system optimization and integration.

[0074] In this embodiment, the S2 specifically includes:

[0075] S21. Connect the Type-C end of the Type-C to TTL interface to an external Type-C device;

[0076] S22. Confirm the positions and functions of the TX and RX pins on the Type-C to TTL interface, and clarify their corresponding connection rules;

[0077] S23. Connect the TX pin of the Type-C to TTL interface to the RX pin of the ESP32-S3 microcontroller through hardware;

[0078] S24. Connect the RX pin of the Type-C to TTL interface to the TX pin of the ESP32-S3 microcontroller through hardware;

[0079] S25. Check whether the signal level output by the Type-C to TTL interface matches the input level of the ESP32-S3 microcontroller. If there is a difference, use a level conversion circuit for adjustment;

[0080] S26. Test the complete path of the signal from the Type-C interface, through the Type-C to TTL interface and transmitted to the ESP32-S3, and then from the ESP32-S3 output signal back to the Type-C to TTL interface.

[0081] In this embodiment, the S3 specifically includes:

[0082] S31. Connect the signal output pin of the ESP32-S3 microcontroller to the input end of the multi-channel voltage source module, and check the integrity of the connection line;

[0083] S32. Configure the output parameters of the ESP32-S3 microcontroller, including signal type, frequency, and voltage range, to make its output signal match the input requirements of the multi-channel voltage source module;

[0084] S33. Transmit the electrical signal output by the ESP32-S3 microcontroller to the multi-channel voltage source module, adjust the characteristics of the input signal through the dynamic calibration resistor, and optimize the input signal in combination with the nonlinear calibration function to generate signal parameters adapted to the optical computing chip:

[0085]

[0086] Among them, V out_module is the output voltage of the multi-channel voltage source module, V out_ESP32 is the output voltage of the ESP32 microcontroller, R calibrate is the calibration resistor of the module, t is the time variable, G module is the gain of the module, B module is the voltage offset value of the module, μ is the calibration coefficient, and σ is the modulation frequency;

[0087] S34. Debug the multi-channel voltage source module, calibrate the amplitude and characteristics of the output signal by adjusting the gain parameter and voltage amplitude setting inside the module, so that the output signal meets the electrical input specifications of the optical computing chip;

[0088] S35. Connect the output end of the multi-channel voltage source module to the signal input end of the optical computing chip, and ensure that the connection is firm without loose connection;

[0089] S36. Test the electrical parameters of the signal output from the ESP32-S3 after being adjusted by the multi-channel voltage source module, and verify the stability and accuracy of the signal after being transmitted to the input end of the optical computing chip.

[0090] In this embodiment, S4 specifically includes:

[0091] S41. Receive the electrical signal transmitted from the multi-channel voltage source module to the input end of the optical computing chip, and receive and preliminarily detect the input signal;

[0092] S42. Inside the optical computing chip, parse the amplitude, frequency, and phase characteristics of the input electrical signal through the data processing unit;

[0093] S43. Use the operation module of the optical computing chip to perform non-linear modulation and multi-parameter encoding on the parsed electrical signal, generate an optical signal through dynamic frequency calibration and time attenuation control, where the non-linear modulation combines the signal amplitude, frequency, phase characteristics, and dynamic calibration frequency, and the time attenuation is used to simulate the influence of signal energy change with transmission conditions:

[0094] S modulated (t) = A in ·sin(ω mod t + φ mod + β·sin(ω cal t))·e -γt ;

[0095] Among them, S modulated (t) represents the modulated optical signal generated by the optical computing chip, A in is the amplitude of the input signal, ω mod is the angular frequency of the modulation signal, φ mod is the phase offset of the modulation signal, β is the non-linear calibration coefficient, ω cal is the calibration frequency, e -γt is the exponential decay factor, γ is the time attenuation coefficient, and t represents the time dimension of the signal generation process;

[0096] S44. Output the optical signal generated by the optical computing chip to the optoelectronic conversion module, receive the optical signal through the photodetector and perform optoelectronic conversion to generate the corresponding electrical signal;

[0097] S45. Perform gain adjustment and filtering processing on the electrical signal output by the optoelectronic conversion module to increase the signal amplitude and signal-to-noise ratio and optimize the output signal quality.

[0098] In this embodiment, S6 specifically includes:

[0099] S61. Receive the data packet transmitted through the Type-C interface, and extract the header information of the data packet, including the identifier, length field, and check code;

[0100] S62. Parse the content of the data packet according to the Type-C interface protocol standard to identify the type, target address, and payload information of the data packet;

[0101] S63. Verify the checksum in the data packet, and detect errors or data loss during the transmission process by comparing the checksum with the data packet content;

[0102] S64. Perform format adaptation on the data packet that passes the checksum verification. Combine multi-dimensional data reorganization operations and weight control to adjust, convert the format, and prioritize the fields of the data packet. At the same time, dynamically generate a matching result according to the target format requirements of the optical computing chip:

[0103]

[0104] where Data output is the generated output data, N is the total amount of data, w i is the weight of the i-th data conversion step, T i is the i-th data conversion operation function, Payload type is the payload part of the input data packet, λ is the dynamic regulation coefficient, F chip is the target format of the optical computing chip, D map is the dynamic mapping rule, and Φ is the dynamic format matching function;

[0105] S65. Generate the target data format adapted to the optical computing chip, output it to the input end of the optical computing chip, and record the error information during the parsing and conversion process for diagnosis and optimization.

[0106] In this embodiment, the specific steps of S7 include:

[0107] S71. Receive the parsed data, identify its original format and structure, and perform preliminary analysis;

[0108] S72. Perform format conversion on the data content, and reorganize the original data into a target format that meets the system transmission and storage requirements, including adjusting field arrangement, converting data types, and standardizing formats;

[0109] S73. Perform data compression operations, reduce the data volume by deleting redundant information, optimizing the data structure, and applying compression algorithms;

[0110] S74. Perform dynamic encryption processing on the data after format conversion and compression. Adopt the Advanced Encryption Standard algorithm, combine dynamic key generation and adaptive initialization vector mechanism, and generate encrypted data that meets the data transmission and storage requirements through multi-level preprocessing and performance regulation:

[0111] Data encrypted = E AES (c pre (Data compressed )Kdynamic , IV adaptive ) δ·T enc ;

[0112] Wherein, Data compressed represents the compressed data, C pre is the preprocessing function, E AES is the AES encryption function, K dynamic is the dynamically generated key, IV adaptive is the adaptive initialization vector, δ is the encryption performance regulation coefficient, T enc is the time delay term of the encryption process, Data encrypted is the finally generated encrypted data;

[0113] S75. Verify the overall performance of the data processing module, output the processed data to the target device or storage system by testing the integrity, rate, and encryption and decryption efficiency of data transmission.

[0114] Example 1:

[0115] To verify the feasibility of the present invention in implementation, the present invention is applied to remote diagnosis in a certain intelligent medical care. In the medical scenario, the health monitoring devices worn by patients will generate a large amount of real-time data, including heart rate, blood pressure, blood oxygen level, and body temperature, etc. These data need to be uploaded to the cloud through the data processing system for further analysis, and preprocessing needs to be completed on the device side to quickly respond in case of emergencies. However, the traditional data transmission and processing methods have problems such as slow data transmission rate, format incompatibility, and insufficient security in this scenario. Especially the high privacy and real-time requirements of medical data make it difficult for the existing technologies to meet.

[0116] The present invention provides a solution for this scenario through the combination of an optical computing chip and a Type-C interface. The patient device uploads real-time data in various formats to the optical computing chip through the Type-C interface. First, the dynamic format adaptation module of the present invention standardizes these data. For example, it converts the heart rate data from the CSV format to the binary format and converts the blood oxygen data from the XML format to the standard JSON format. After completing the format conversion, the data enters the multi-level compression module for processing. The volume of the original data is usually 50MB, and after compression, it is reduced to 15MB, with a compression rate as high as 70%, significantly reducing the transmission bandwidth requirements.

[0117] To ensure the privacy of medical data during transmission, the dynamic encryption module of the present invention encrypts data through the AES-256 algorithm. By adopting the dynamic key generation and adaptive initialization vector mechanism, a unique encryption key and initialization vector are used for each transmission to ensure the security of the encrypted data. In actual tests, no repeated patterns were found in the transmitted data packets, and the encryption efficiency is relatively high, with the encryption time for each time not exceeding 1.5 ms.

[0118] During the test, the amount of medical data processed per day reached 2 TB. The data transmission rate was increased from 150 Mbps of the traditional method to 400 Mbps, and the transmission delay was reduced from 35 ms to 15 ms. It was also found in the test that through the optimization process of the present invention, the data analysis efficiency was increased by 20%, and the response time for patients' emergencies was shortened from an average of 2 minutes to 50 seconds, significantly improving the response speed of the medical system.

[0119] Table 1 Comparison of the performance of the intelligent medical data transmission system

[0120]

[0121] Table 2 Comparative tests of data compression and encryption

[0122]

[0123] Table 1 shows the performance comparison between the present invention and the traditional solution in the intelligent medical scenario. The present invention increases the data transmission rate from 150 Mbps to 400 Mbps, with an increase rate of 167%. At the same time, the average transmission delay is reduced from 35 ms to 15 ms, a reduction of 57%. This improvement significantly optimizes the data transmission efficiency and real-time performance. In addition, the data compression rate is increased from the traditional 20% to 70%, reducing the resource consumption during storage and transmission. The encryption time is shortened by 50%, from 3 ms to 1.5 ms, and the patient response time is also shortened from 120 seconds to 50 seconds, showing faster medical processing capabilities. These data indicate that the present invention not only solves the problem of low data processing efficiency in the traditional solution but also improves the security and emergency response capabilities of the system.

[0124] Table 2 details the compression and encryption effects of different types of medical data. The compression rate of heart rate data, blood oxygen data, blood pressure data, and body temperature data all reaches 70%. For example, the heart rate data is reduced from 10 MB to 3 MB, and the blood pressure data is compressed from 20 MB to 6 MB. The encryption time is controlled between 1.1 ms and 1.4 ms, indicating that the encryption module of the present invention takes into account both high efficiency and security. Overall, the compression and encryption technologies of the present invention significantly reduce the resource consumption during transmission and storage, while ensuring data privacy and security, providing a more efficient and reliable solution for the medical scenario.

[0125] In summary, the present invention not only addresses the deficiencies of traditional solutions in terms of rate, latency, and compression ratio, but also significantly enhances data security and real-time performance through efficient encryption techniques. These excellent performance manifestations fully demonstrate the remarkable value of the present invention in the intelligent medical scenario, providing technical support for the efficient operation and reliability of the medical system.

[0126] The above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, making equivalent substitutions or changes, should be covered by the protection scope of the present invention.

Claims

1. A method for transmitting data on an optical computing chip based on a Type-C interface, characterized in that: The steps include: S1. Provide ESP32-S3 microcontroller as the core control unit and connect its power supply end through the power circuit. At the same time, prepare Type-C to TTL interface, CH340N chip, multi-channel voltage source module and optical computing chip as the main hardware components; S2. Connect the Type-C to TTL interface to the ESP32-S3 microcontroller through hardware, and use the CH340N chip to complete the conversion between the Type-C interface signal and the UART serial port signal; connect the TX pin of the Type-C to TTL interface to the RX pin of the ESP32-S3, and connect the RX pin of the Type-C to TTL interface to the TX pin of the ESP32-S3; S3, transmitting the electrical signal output by the ESP32-S3 microcontroller to the multi-channel voltage source module, adjusting the voltage amplitude and parameters of the electrical signal through the multi-channel voltage source module to meet the input requirements of the optical computing chip, and then transmitting the adjusted electrical signal to the input end of the optical computing chip; S4, the optical computing chip performs data processing on the input electrical signal to generate a corresponding optical signal, and converts the output optical signal into an electrical signal through the photoelectric conversion module; S5. Build the development environment, select ArduinoIDE as the development tool, and configure the development environment of ESP32-S3; S6. Write a communication protocol parsing module program to parse and verify the received data packets based on the Type-C interface protocol, and generate a data format adapted to the optical computing chip; S7. Develop a data processing module program to convert, compress and encrypt the parsed data to meet the system's requirements for data transmission and storage, and verify the overall data transmission performance; S8. Conduct comprehensive testing on the system, including communication interface compatibility testing, data transmission rate verification and overall functional testing, and finally complete system optimization and integration.

2. According to the method of optical computing chip data transmission based on Type-C interface in claim 1, it is characterized in that: The S2 specifically includes: S21, connecting the Type-C end of the Type-C to TTL interface to an external Type-C device; S22. Confirm the position and function of the TX pin and RX pin on the Type-C to TTL interface, and clarify their corresponding connection rules; S23, connect the TX pin of the Type-C to TTL interface to the RX pin of the ESP32-S3 microcontroller through hardware; S24. Connect the RX pin of the Type-C to TTL interface to the TX pin of the ESP32-S3 microcontroller through hardware. S25. Check whether the signal level output by the Type-C to TTL interface matches the input level of the ESP32-S3 microcontroller. If there is a difference, use the level conversion circuit to adjust it. S26, the complete path of the test signal entering from the Type-C interface, being transmitted to ESP32-S3 via the Type-C to TTL interface, and returning from the ESP32-S3 output signal to the Type-C to TTL interface.

3. According to the method of optical computing chip data transmission based on Type-C interface in claim 1, it is characterized in that: The S3 specifically includes: S31. Connect the signal output pin of the ESP32-S3 microcontroller to the input of the multi-channel voltage source module and check the integrity of the connection line. S32, configure the output parameters of the ESP32-S3 microcontroller, including signal type, frequency, and voltage range, so that its output signal matches the input requirements of the multi-channel voltage source module; S33, transmit the electrical signal output by the ESP32-S3 microcontroller to the multi-channel voltage source module, adjust the characteristics of the input signal through dynamic calibration resistance, and optimize the input signal in combination with the nonlinear calibration function to generate signal parameters adapted to the optical computing chip: Among them, V out_module is the output voltage of the multi-channel voltage source module, V out_ESP32 is the output voltage of the ESP32 microcontroller, R calibrate is the module’s calibration resistance, t is the time variable, G module is the gain of the module, B module is the voltage offset value of the module, μ is the calibration coefficient, and σ is the modulation frequency; S34, debugging the multi-channel voltage source module, calibrating the amplitude and characteristics of the output signal by adjusting the gain parameters and voltage amplitude settings inside the module, so that the output signal meets the electrical input specifications of the optical computing chip; S35, connecting the output end of the multi-channel voltage source module to the signal input end of the optical computing chip, and the connection is firm without loose connection; S36. Test the electrical parameters of the signal output from ESP32-S3 after adjustment by the multi-channel voltage source module, and verify the stability and accuracy of the signal after it is transmitted to the input end of the optical computing chip.

4. According to the method of optical computing chip data transmission based on Type-C interface in claim 1, it is characterized in that: The S4 specifically includes: S41, receiving an electrical signal transmitted from the multi-channel voltage source module to the input end of the optical computing chip, and receiving and preliminarily detecting the input signal; S42, within the optical computing chip, analyzing the amplitude, frequency and phase characteristics of the input electrical signal through a data processing unit; S43. Using the computing module of the optical computing chip to perform nonlinear modulation and multi-parameter encoding on the analyzed electrical signal, an optical signal is generated through dynamic frequency calibration and time attenuation control, wherein the nonlinear modulation combines the signal amplitude, frequency, phase characteristics and the dynamic calibration frequency, and the time attenuation is used to simulate the influence of the signal energy changing with the transmission conditions: S modulated (t)=A in ·sin(ω mod t+φ mod +β·sin(ω cal t))·e -γt ; Among them, S modulated (t) represents the modulated optical signal generated by the optical computing chip, A in is the amplitude of the input signal, ω mod is the angular frequency of the modulation signal, φ mod is the phase shift of the modulation signal, β is the nonlinear calibration coefficient, ω cal is the calibration frequency, e -γt is the exponential decay factor, γ is the time decay coefficient, and t represents the time dimension of the signal generation process; S44, outputting the optical signal generated by the optical computing chip to the photoelectric conversion module, receiving the optical signal through the photoelectric detector and performing photoelectric conversion to generate a corresponding electrical signal; S45, performing gain adjustment and filtering processing on the electrical signal output by the photoelectric conversion module to improve the signal amplitude and signal-to-noise ratio and optimize the output signal quality.

5. According to the method of optical computing chip data transmission based on Type-C interface in claim 1, it is characterized in that: The S6 specifically includes: S61, receiving a data packet transmitted through the Type-C interface, and extracting header information of the data packet, including an identifier, a length field, and a check code; S62, parsing the content of the data packet according to the Type-C interface protocol standard, identifying the type, target address, and payload information of the data packet; S63, verifying the check code in the data packet, and detecting errors or data loss during transmission by comparing the check code with the data packet content; S64, adapt the format of the data packets that have passed the verification through dynamic mapping rules, adjust the fields of the data packets, convert the formats and sort the priorities in combination with multi-dimensional data reorganization operations and weight control, and dynamically generate matching results according to the target format requirements of the optical computing chip: Among them, Data output is the generated output data, N is the total amount of data, w i is the weight of the i-th data transformation step, T i is the ith data conversion operation function, Payload type is the payload part of the input data packet, λ is the dynamic control coefficient, F chip The target format for optical computing chips, D map is the dynamic mapping rule, Φ is the dynamic format matching function; S65. Generate a target data format adapted to the optical computing chip, output it to the input end of the optical computing chip, and record error information during the parsing and conversion process for diagnosis and optimization.

6. According to the method of optical computing chip data transmission based on Type-C interface in claim 1, it is characterized in that: The S7 specifically includes: S71, receiving the parsed data, identifying its original format and structure, and performing preliminary analysis; S72, performing format conversion on the data content, reorganizing the original data into a target format that meets the transmission and storage requirements of the system, including field arrangement adjustment, data type conversion, and format standardization; S73, performing data compression operations to reduce data volume by deleting redundant information, optimizing data structure, and applying compression algorithms; S74. Dynamically encrypt the format-converted and compressed data, using the Advanced Encryption Standard algorithm, combined with dynamic key generation and adaptive initialization vector mechanism, through multi-level preprocessing and performance regulation, to generate encrypted data that meets data transmission and storage requirements: Data encrypted =E AES (C pre (Data compressed )K dynamic ,IV adaptive )δ·T enc ; Among them, Data compressed Indicates the compressed data, C pre is the preprocessing function, E AES is the AES encryption function, K dynamic For dynamically generated keys, IV adaptive is the adaptive initialization vector, δ is the encryption performance control coefficient, T enc is the time delay term of the encryption process, Data encrypted The encrypted data finally generated; S75. Verify the overall performance of the data processing module by testing the integrity, rate, and encryption and decryption efficiency of data transmission, and output the processed data to the target device or storage system.

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