A core circuit for ultra-large-scale in-memory computing that solves the IR-Drop problem

Abstract

This invention discloses a core circuit for ultra-large-scale in-memory computing that solves the IR-Drop problem, belonging to the fields of microelectronics and artificial intelligence. By analyzing the intrinsic physical equations of the line-resistance network, this invention determines that the accuracy degradation caused by line resistance is an approximately linear error. Analysis of the approximate analytical formula reveals that the linear error is only related to the parameters of the line-resistance network. This means that different input voltage vectors produce the same approximately linear error in the column output current. Therefore, this invention adjusts the row and column line resistances through the coordinated design of devices, layout, and circuitry to maximize the linearization of the error. These errors are eliminated through adjacent differential pair readout design and sampling resistor trimming. Simultaneously, combined with the adjacent differential readout circuit, a fully differential ADC is designed to achieve isolated current sampling and line resistance error compensation.

Description

Technical Field

[0001] This invention belongs to the fields of microelectronics technology and artificial intelligence, and more specifically, relates to a core circuit for ultra-large-scale in-memory computing that solves the IR-Drop problem. Background Technology

[0002] With the rapid development of artificial intelligence technology, especially driven by deep learning algorithms, computing hardware is facing ever-increasing performance demands. Computing-In-Memory (CIM) technology has attracted much attention because it integrates storage and computing in the same location. Due to its significant advantages in providing high computing power, high energy efficiency, and low latency, it has become one of the key technologies for solving the computing power needs of AI.

[0003] Memristors, as non-volatile storage devices, possess dual functions of storage and computation. Their unique physical characteristics make them highly promising for in-memory computing applications. By combining data storage and processing operations in the same location, memristors can significantly reduce data transmission distances, lower power consumption, and improve computational efficiency. Therefore, memristors are often used as a core component of CIM (Computational In-Memory) technology, and their unique data storage and processing capabilities enable the realization of high-performance, energy-efficient, and low-latency AI hardware.

[0004] However, as the size of memristor arrays increases, the voltage drop (IR-Drop) between memristor array nodes accumulates due to the interconnect resistance between wires, significantly impacting the voltage distribution within the array and hindering the application of in-memory computing technology. Increasing the array size can directly reduce the power consumption and area ratio of peripheral circuits, leading to improved throughput and efficiency. However, the IR-drop problem caused by the line resistance between memory cells limits improvements in both scale and accuracy.

[0005] Currently, there are two main technical approaches to address the line resistance problem. One approach is a hardware solution, which includes the redistribution of memristor conductance and circuit compensation. The redistribution scheme generates a redistribution of memristor conductance related to line resistance through an iterative algorithm, thus making the matrix calculation results consistent with a memristor array without line resistance. However, the conductance redistribution requires additional computational load and a continuously distributed range of resistance states. The hardware compensation scheme uses additional digital modules in the peripheral digital circuitry to correct the ADC output, which increases circuitry costs and time. The dual-supply scheme alleviates the line resistance problem by inputting positive and negative voltages to two adjacent rows, but its single-core size is still only 144k. This scheme does not fundamentally solve the line resistance problem for larger-scale arrays. Another approach is hardware-software co-training. This method introduces a line resistance network during neural network training. This method heavily relies on the joint training of the algorithm and hardware, which hinders the rapid deployment of the algorithm and requires the memristors to have greater durability. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a core circuit for ultra-large-scale in-memory computing that solves the IR-Drop problem, thereby solving the IR-drop problem caused by the line resistance between memory cells in the array.

[0007] To achieve the above objectives, according to a first aspect of the present invention, a line-resistance network circuit for a non-volatile memory array is provided, comprising:

[0008] A DAC module includes M DACs and voltage drivers connected to them, forming M DAC channels;

[0009] A two-dimensional 1T1R array has its word line control terminal WL parallel to the column current output terminal SL, and its bit line voltage signal input terminal BL perpendicular to WL and SL. Two adjacent 1T1R columns form a differential pair column, which is used to store neural network weights.

[0010] The ADC module includes N ADC channels, and each ADC channel includes a two-terminal differential readout circuit and an ADC connected in sequence.

[0011] The DAC module is connected to the BL terminal of the two-dimensional 1T1R array, and the SL terminal of the two-dimensional 1T1R array is connected to the ADC module. The size of the two-dimensional 1T1R array is m×n. One ADC channel is shared by the i-th row of the array and is controlled in a time-division manner through a switch array. One DAC is shared by the j-th column of the array and is controlled in a time-division manner through a switch array, and j>i.

[0012] According to a second aspect of the present invention, an electronic device is provided, comprising: a computer-readable storage medium and a processor;

[0013] The computer-readable storage medium is used to store executable instructions;

[0014] The processor is configured to read executable instructions stored in the computer-readable storage medium and execute the method as described in the first aspect.

[0015] According to a third aspect of the invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to perform the method as described in the first aspect.

[0016] According to a fourth aspect of the invention, a computer program product is provided, comprising a computer program or instructions that, when executed by a processor, implement the method described in the first aspect.

[0017] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0018] This invention analyzes the intrinsic physical equations of the line-resistance network to determine that the accuracy degradation caused by line resistance is an approximately linear error. Analysis of the approximate analytical formula reveals that the linear error is only related to the parameters of the line-resistance network. This means that different input voltage vectors produce the same approximately linear error in the column output current. Therefore, this invention adjusts the row and column line resistances through the coordinated design of devices, layout, and circuitry to maximize the linearization of the error. These errors are eliminated through adjacent differential pair readout design and sampling resistor trimming. Simultaneously, combined with the adjacent differential readout circuit, a fully differential ADC is designed and applied to achieve isolated current sampling and line resistance error compensation. Using the above circuit design, taking a 128-row, 128-column two-dimensional 1T1R array with M=128 and N=64 as an example, simulation verification shows that this invention achieves a 5Mb-level ultra-large-scale array with a computational efficiency exceeding 13 TOPS / W and a computational throughput exceeding 0.41 TOPS. Attached Figure Description

[0019] Figure 1 In the above, (a), (b), (c), and (d) are respectively one of the in-memory calculation schematic diagrams, another of the in-memory calculation schematic diagrams, one of the upper electrode voltage distribution diagrams, and another of the upper electrode voltage distribution diagrams provided in the embodiments of the present invention.

[0020] Figure 2 In the above, (a), (b), (c), and (d) are respectively a schematic diagram of the line resistance output current fitting of a memristor array with a scale of 128 rows and 128 columns provided in the embodiments of the present invention, a schematic diagram of the linear fitting error, a schematic diagram of the line resistance network model ignoring column line resistance RSL, and a schematic diagram of the line resistance network model being a 1D π-type line resistance network model.

[0021] Figure 3 In the above, (a), (b), (c), and (d) are respectively schematic diagrams of the differential current output results when RBL=RSL, the differential current output results after linear compensation, the differential current output results when RBL>RSL, and the differential current output results after linear compensation provided in the embodiments of the present invention.

[0022] Figure 4 This is a schematic diagram of the core circuit for in-memory analog matrix calculation provided in an embodiment of the present invention;

[0023] Figure 5 (a), (b), (c), and (d) in the embodiments of the present invention are respectively a schematic diagram of the 1T1R array, a schematic diagram of the first readout circuit, a schematic diagram of the second readout circuit, and a trimming resistor adjustment circuit in the core circuit for in-memory analog matrix calculation.

[0024] Figure 6 (a), (b), (c), and (d) in the embodiments of the present invention are respectively one of the circuit-layout collaborative optimization layout design diagrams, another of the layout design diagrams, a schematic diagram of the memristor unit device structure in 1T1R, and a schematic diagram of the simulation results. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0026] A memristor array with line resistance (m rows and n columns) is a large-scale line-resistance network with 2^mn nodes, which can be divided into two dimensions: rows and columns. The Kirchhoff's Current Law (KCL) equation for a node (i, j) in a memory cell is:

[0027] Ip(i, j)=Im(i, j+1)+Ip(i, j+1)(1)

[0028] Where Ip(i, j) is the line resistance current in the i-th row and j-th column, Im(i, j+1) is the memory cell current in the i-th row and (j+1)-th column, and Ip(i, j+1) is the line resistance current in the i-th row and (j+1)-th column. The KCL equations for all top nodes in the i-th row are combined. After simulating the line resistance network using the Spectre simulator, the voltage distribution at the top electrode shows a similar decreasing trend with different input voltages, meaning the array's output current exhibits a high degree of linearity.

[0029] Multiple different voltage vectors Vin are randomly input into the memristor array, and linear fitting is performed on the column output current. The linear fitting results of the output current are as follows:

[0030] (2)

[0031] in, It is the current in the j-th column under different input voltage vectors, and This represents the current in the j-th column without line resistance. Analysis of the linear fitting results of formula (2) shows that the relative error of the output current in all columns is less than 1%, indicating that the column current error has a high degree of linearity. To maximize the linearization of the error, a line resistance network ignoring column line resistance was analyzed. Therefore, the two-dimensional line resistance network is reduced to a one-dimensional row line resistance network. The row line resistance network is a one-dimensional π-type resistor network. For this one-dimensional π-type resistor network, the voltage solution of the electrodes on the memory cell can be obtained by solving the following second-order difference equation and boundary conditions.

[0032] (3)

[0033] in, Let represent the average conductance of the memristor array. The analytical solution can be expressed as:

[0034]

[0035] (4)

[0036] In formula (4), h and the function F are polynomial functions related to GBL and Gmean. The voltage solution Vt(i,j) in the i-th row reveals that all top node voltages are related to Vin(i) and the coefficient kj, where kj is independent of Vin(i). Therefore, the voltage solutions for all electrodes on the memory cells are:

[0037] (5)

[0038] Where Vt is the voltage vector of all top nodes, Vin is the input vector, and K is the coefficient vector derived from kj in formula (4). The above derivation of the top node voltages shows that the column output current error exhibits high linearity under different Vin inputs. At the same time, it can also be concluded that the column line resistance RSL only affects the bias b of the linear error in formula (2). This analysis provides a method for circuit compensation. By reducing the column line resistance RSL, the error can achieve higher linearity. In addition, by using adjacent columns as difference pairs to store weights, the current output result can be expressed as:

[0039] (6)

[0040] In formula (6), and These represent the positive and negative column output currents of the differential pair, respectively. This is the ideal current without line resistance after linear compensation. Due to the adjacent differential pair structure, the bias b of the linear error is eliminated, and the remaining linear error coefficient k can be corrected using the sampling resistor. The neural network weights are mapped to a memristor array with line resistance, where adjacent columns store weights in differential pairs. When RBL > RSL, the accuracy after linear compensation reaches 92.4%, proving the feasibility of the differential linear compensation scheme.

[0041] Based on this, embodiments of the present invention provide a line-resistance network circuit for a non-volatile memory array, comprising:

[0042] A DAC module includes M DACs and voltage drivers connected to them, forming M DAC channels;

[0043] A two-dimensional 1T1R array has its word line control terminal WL parallel to the column current output terminal SL, and its bit line voltage signal input terminal BL perpendicular to WL and SL. Two adjacent 1T1R columns form a differential pair column, which is used to store neural network weights.

[0044] The ADC module includes N ADC channels, and each ADC channel includes a two-terminal differential readout circuit and an ADC connected in sequence.

[0045] The DAC module is connected to the BL terminal of the two-dimensional 1T1R array, and the SL terminal of the two-dimensional 1T1R array is connected to the ADC module. The size of the two-dimensional 1T1R array is m×n. One ADC channel is shared by the i-th row of the array and is controlled in a time-division manner through a switch array. One DAC is shared by the j-th column of the array and is controlled in a time-division manner through a switch array, and j>i.

[0046] Specifically, the circuit provided by the present invention includes:

[0047] M input DAC and driver circuit channels are used to convert digital domain input vectors into analog voltage input vectors.

[0048] The 1T1R non-volatile memory array structure based on memristors features a word line control terminal (WL) parallel to the column current output terminal (SL), and a bit line voltage signal input terminal (BL) perpendicular to WL and SL. Adjacent 1T1R columns form a differential pair for storing neural network weights. The array layout employs a layout-circuit co-design, resolving the IR-drop problem caused by line resistance and enabling ultra-large-scale circuit design with a computing power greater than 0.4 TOPS@int8 and a computing efficiency greater than 13 TOPS / W@int8. Specifically, the 1T1R array uses a structure where WL is parallel to the column current output terminal (SL), and the bit line voltage signal input terminal (BL) is perpendicular to WL and SL. The voltage signal is preloaded onto the BL terminal, and then a pulse signal is applied to WL for matrix operations in the analog domain. Adjacent 1T1R columns form a differential pair for storing neural network weights.

[0049] The N-channel dual-ended differential readout circuit and ADC compensate for the voltage drop error caused by line resistance by adjusting the trimming resistor.

[0050] M DACs and their input channels are connected to the BL terminal of the storage array described in section b, applying voltage to the array. The SL terminal of the array described in section b is connected to the ADC and readout circuit described in section c, for signal readout.

[0051] The storage array is m rows and n columns. A DAC and its driver circuit channel are shared by row i in the array, controlled in a time-division multiplexing manner using a switch array. An ADC and its readout circuit channel are shared by column j in the array, also controlled in a time-division multiplexing manner using a switch array. To ensure compensation, j must be greater than i, thus making the row line resistance greater than the column line resistance.

[0052] Preferably, the two-dimensional 1T1R array is set as a rectangle on the layout, and the length of the rectangle is greater than its width.

[0053] Specifically, using Design-Process Co-operation (DTCO), the 1T1R memory cell is laid out as a rectangle with a length greater than its width, making the line resistance of BL greater than that of SL. This design maximizes the linearization of errors caused by line resistance, facilitating error compensation by subsequent peripheral circuits.

[0054] Preferably, the dual-ended differential readout circuit uses a folded cascode input stage and an NMOS as the cascode output stage to perform voltage clamping and current isolation sampling on two adjacent 1T1R columns. The sampled current is converted into voltage through a trimming resistor adjustment circuit.

[0055] Specifically, the dual-ended differential readout circuit performs voltage clamping and current isolation sampling on two adjacent columns 1T1R. Then, the sampled current is converted into voltage through the trimming resistor, which not only compensates for the line resistance error, but also samples the ADC.

[0056] The dual-ended differential readout circuit uses a folded cascode input stage and an NMOS transistor as the common-source amplifier output stage to clamp the voltage at the SL terminal of the array for differential readout. Additionally, the output stage uses an NMOS mirror transistor for isolated current sampling, which is then output to the ADC for quantization. The sampled current passes through a trimming resistor adjustment circuit to compensate for line resistance errors. The bias term of the linearity error is eliminated by subtracting the differential pairs, and the proportional term of the linearity error is compensated by the trimming resistor adjustment circuit.

[0057] Preferably, the DAC is a C-2C DAC, and the voltage driver is a Class AB output operational amplifier.

[0058] A C-2C DAC is used to convert the original digital signal into an analog voltage signal, and then a Class AB output op-amp is used as a voltage driver to drive the BL terminal of the array.

[0059] Preferably, SL is implemented using a top metal layer, and its sheet resistance is lower than that of the bottom metal layer used in BL; BL is implemented using an M2 or M3 metal layer; SL is implemented using a top M6 metal layer.

[0060] Figure 1 This demonstrates in-memory computation based on a non-volatile memory array, where the array size is 128 rows and 128 columns, and both the row line resistance RBL and column line resistance RSL are 1 ohm. Figure 1 As shown in (a) and (b), a voltage excitation is applied to the left end of the cross array (i.e., the bit line voltage signal input terminal) BL, and then the lower end of the array (i.e., the column current output terminal) SL is clamped to a fixed level. Matrix multiplication in the analog domain is performed according to Kirchhoff's theorem, and the final result is the output current at the SL terminal. Figure 1 Figures (c) and (d) show the voltage distribution of the upper electrode. After mapping the upper electrode voltage onto a two-dimensional plane, a similar voltage distribution trend can be observed. This distribution trend reveals the presence of output current.

[0061] Figure 2 The linear fitting results of the line resistance output current are shown. Figure 2 (a) shows a memristor array with a size of 128 rows and 128 columns, whose output current is given by formula (2). The fitting is defined as follows: K is the linear coefficient of the linear fit, and b is the linear bias of the linear fit. Figure 2(b) shows the error of the linear fit, which is less than 1%. This fully demonstrates the linearity of the output current. Figure 2 (c) shows a line resistance network model that ignores the column line resistance RSL. Through the analysis of... Figure 2 Separate the network model in (c) in the middle. Figure 2 Figure (d) shows that the line resistance network model is a one-dimensional π-type line resistance network model. By solving the difference equation (3) of the one-dimensional π-type line resistance network, the analytical solution of the voltage distribution of the electrodes on the memory cell can be obtained. The analytical solution result is shown in equation (4), which proves that the current result can be highly linearized, but its core lies in how to reduce the column line resistance.

[0062] Figure 3 The comparison of current results for linear compensation is shown. From Figure 2 The results obtained show that increasing the row line resistance RBL and decreasing the column line resistance RSL can achieve maximum linearization of the line resistance error. Figure 3 (a) shows the differential current output results with RBL=RSL, where the error due to line resistance reaches 60%. Even after using a linear compensation scheme, the error due to line resistance still reaches 50%. Figure 3 (c) shows the layout optimization results for RBL > RSL. Without a line resistance compensation scheme, the error caused by line resistance reaches 43%. Figure 3 Figure (d) shows the result after applying the linear compensation scheme, where the error caused by line resistance is less than 7.6%. This simulation result proves that the linear error compensation scheme after layout optimization is indeed feasible.

[0063] Figure 4 This invention demonstrates the in-memory analog matrix computation core circuit provided by the linear compensation scheme described above. Taking a 128-row, 128-column two-dimensional 1T1R array with M=128 and N=64 as an example, this invention designs and verifies a 5 Mb array matrix operation core through layout-circuit co-optimization. This matrix operation core achieves superior computational throughput and efficiency while meeting computational accuracy requirements. Based on SIMC 55nm technology, the CIM macro design is as follows... Figure 4 As shown. To satisfy the condition that RBL is greater than RSL, the design employs M DAC input channels and N ADC and readout circuit channels, as follows. Figure 4 As shown. Since the area of ​​the DAC and ADC is significantly larger than that of a 1T1R cell, one DAC input channel is shared by i rows. The subarray selected by the switch control circuit participates in the single-cycle calculation, while the word lines (WLs) of other columns are turned off. Figure 5 As shown in (a), adjacent columns of 1T1R form differential pairs, resulting in a total of j / 2 differential pairs. The output current readout circuit design is as follows. Figure 5 As shown in (b) above. Two clamping operational amplifiers are used to read the differential pair current consisting of two columns, which is then converted to voltage by two Rtriming circuits and sampled by the ADC. Figure 5 As shown in (c), the Vout port of the clamping operational amplifier is used to clamp the column outputs of the array to Vclamp, where its output stage NMOS mirrors the current Iout. Therefore, the column output current is isolated and sampled. Figure 5 As shown in (d) in the figure, linear compensation of the column output current is achieved by adjusting the sampling Rtriming.

[0064] Through Design Technology Co-optimization (DTCO), collaborative design is performed on the circuit, layout, and device levels. Figure 6 This invention demonstrates the results of circuit-layout co-optimization. Based on error analysis results, to maximize the linearity of the error, this invention employs... Figure 6 The layout designs shown in (a) and (b) are illustrated. By designing the 1T1R cell as a rectangle, the source line (SL) width is made larger than the bit line (BL) width. Simultaneously, the SL uses a top metal layer, whose sheet resistance is lower than that of the bottom metal layer used by the BL. Figure 6 As shown in (c), BL in the array uses M2 & M3 metal layers, while SL in the array uses the top M6 metal layer, resulting in lower sheet resistance. The memristor cells in the 1T1R use... Figure 6 The device structure shown in (c) is illustrated. Post-simulation of the circuit was performed, and the extracted parasitic parameters were incorporated into a neural network simulation model based on a memristor-based in-memory computing core. The results showed that the neural network's recognition rate was restored.

[0065] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A line-resistance network circuit for a non-volatile memory array, characterized in that, include: A DAC module includes M DACs and voltage drivers connected to them, forming M DAC channels; A two-dimensional 1T1R array has its word line control terminal WL parallel to the column current output terminal SL, and its bit line voltage signal input terminal BL perpendicular to WL and SL. Two adjacent 1T1R columns form a differential pair column, which is used to store neural network weights. The ADC module includes N ADC channels, and each ADC channel includes a two-terminal differential readout circuit and an ADC connected in sequence. The DAC module is connected to the BL terminal of the two-dimensional 1T1R array, and the SL terminal of the two-dimensional 1T1R array is connected to the ADC module. The size of the two-dimensional 1T1R array is m×n. One ADC channel is shared by the i-th row of the array and is controlled in a time-division manner through a switch array. One DAC is shared by the j-th column of the array and is controlled in a time-division manner through a switch array, and j>i. The two-dimensional 1T1R array is set as a rectangle on the layout, and the length of the rectangle is greater than its width; The dual-ended differential readout circuit uses a folded common-source common-gate as the differential input stage and an NMOS as the common-source amplifier output stage. It is used to perform voltage clamping and current isolation sampling on two adjacent columns of 1T1R. The sampled current is converted into voltage through a trimming resistor adjustment circuit.

2. The circuit as described in claim 1, characterized in that, The DAC is a C-2C DAC, and the voltage driver is a Class AB output operational amplifier.

3. The circuit as described in claim 1, characterized in that, SL is implemented using a top metal layer, and its sheet resistance is lower than that of BL, which uses a bottom metal layer.

4. The circuit as described in claim 1, characterized in that, BL is implemented using M2 or M3 metal layers.

5. The circuit as described in claim 1, characterized in that, SL is achieved using a top M6 metal layer.

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