Comprehensive method and device for optimizing chip area, equipment and storage medium

Abstract

The invention discloses a comprehensive method and device for optimizing a chip area, equipment and a storage medium, and belongs to the technical field of chip design. The method comprises the following steps: acquiring an original time sequence constraint and a hardware description file, wherein the hardware description file is used for describing the function and the structure of a chip circuit; amplifying a clock period in the original time sequence constraint to obtain an amplified time sequence constraint; based on the amplification time sequence constraint, executing a logic comprehensive process on the hardware description file to obtain a logic netlist, the logic netlist being used for indicating a logic structure of a chip circuit; and based on the logic netlist and the original time sequence constraint, executing a physical comprehensive process to obtain a physical netlist, the physical netlist being used for indicating the logic structure of the chip circuit and the physical position information of each circuit element in the chip circuit. By relaxing the time sequence constraint in the logic synthesis stage and using the original time sequence constraint in the physical synthesis stage, the problem of chip area increase caused by the logic synthesis stage is solved under the condition of ensuring the time sequence.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a comprehensive method, device, equipment and storage medium for optimizing chip area. Background Art

[0002] In the field of chip design, synthesis is the process of converting hardware description language code into a netlist, including logic synthesis and physical synthesis. Logic synthesis is the process of converting hardware description language code into a logic netlist. Physical synthesis is the process of converting a logic netlist into a physical netlist. The logic netlist is used to describe the logical structure of the chip circuit, such as which circuit elements are included, which circuit elements are connected, and so on. In addition to the logical structure, the physical netlist is also used to describe the physical location of each circuit element. In the synthesis process, a balance needs to be struck between timing and chip area.

[0003] However, before physical synthesis, the synthesis tool mainly relies on logic information and estimated physical information for optimization in the absence of physical information. However, due to the lack of physical information, in the optimization stage of logic synthesis, in order to leave enough timing margin for subsequent physical synthesis, the circuit elements will be increased as much as possible to ensure the subsequent timing margin, but this also means that the chip area will increase unreasonably.

[0004] Therefore, it is necessary to improve the synthesis method to more effectively control the chip area while ensuring the timing. Summary of the invention

[0005] The present application provides a comprehensive method, device, equipment and storage medium for optimizing chip area, and the technical solution is as follows: According to one aspect of the present application, a comprehensive method for optimizing chip area is provided, the method comprising: Obtaining original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits; Enlarging the clock cycle in the original timing constraint to obtain an enlarged timing constraint; Based on the amplified timing constraints, a logic synthesis process is performed on the hardware description file to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit; Based on the logic netlist and the original timing constraints, a physical synthesis process is executed to obtain a physical netlist, where the physical netlist is used to indicate the logic structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0006] According to another aspect of the present application, a comprehensive device for optimizing chip area is provided, the device comprising: An acquisition module, used to acquire original timing constraints and hardware description files, wherein the hardware description files are used to describe the functions and structures of chip circuits; an amplification module, used for amplifying the clock cycle in the original timing constraint to obtain an amplified timing constraint; A logic synthesis module, used to execute a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit; A physical synthesis module is used to execute a physical synthesis process based on the logic netlist and the original timing constraints to obtain a physical netlist, wherein the physical netlist is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0007] According to another aspect of the present application, a computer device is provided. The computer device includes a processor and a memory. A computer program is stored in the memory. The computer program is loaded and executed by the processor to implement a comprehensive method for optimizing chip area.

[0008] According to another aspect of the present application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and the computer program is loaded and executed by a processor to implement a comprehensive method for optimizing chip area.

[0009] According to another aspect of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium, the processor reading and executing the computer program from the computer-readable storage medium to implement a comprehensive method for optimizing chip area.

[0010] The beneficial effects of the technical solution provided by this application include at least: By amplifying the clock cycle in the logic synthesis stage, and performing the logic synthesis process based on the amplified timing constraints after the amplified clock cycle; and after the logic synthesis process is completed and the logic netlist is obtained, the physical synthesis process is executed using the original timing constraints in the layout stage (also called the physical synthesis stage) to obtain the physical netlist. By amplifying the clock cycle in the logic synthesis stage, the timing constraints are made more relaxed, so as to avoid the unreasonable increase of at least one of the total number of components and the chip area due to the excessively tight timing in the logic synthesis stage. In the physical synthesis stage, the original timing constraints are still used on the one hand to ensure that the original settings of the user are not changed, and on the other hand, since the physical synthesis stage will simulate the physical position of each circuit element in the logic netlist, the physical position of the circuit element can be adjusted to make it meet the original timing constraints (without adding circuit elements). Therefore, the use of the tighter original timing constraints in this stage can optimize the chip area and the total number of components of the chip circuit as close to the real scene as possible on the basis of ensuring the original timing constraints. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 An architectural diagram of a computer system provided by an exemplary embodiment of the present application is shown; Figure 2 A flowchart of a comprehensive method for optimizing chip area provided by an exemplary embodiment of the present application is shown; Figure 3 A flowchart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application is shown; Figure 4 A flowchart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application is shown; Figure 5 A flowchart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application is shown; Figure 6 An overall flow chart of a comprehensive method for optimizing chip area provided by an exemplary embodiment of the present application is shown; Figure 7 An overall flow chart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application is shown; Figure 8A schematic diagram of a first integrated process provided by an exemplary embodiment of the present application is shown; Fig. 9 A schematic diagram of a second integrated process provided by an exemplary embodiment of the present application is shown; Fig.10 A schematic diagram of a third comprehensive process provided by an exemplary embodiment of the present application is shown; Fig.11 A structural block diagram of a comprehensive device for optimizing chip area provided by an exemplary embodiment of the present application is shown; Fig.12 A schematic diagram of the structure of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0013] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0014] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0015] The terms used in the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The singular forms "a", "said" and "the" used in the present disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0016] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the information such as setting operations involved in this application is obtained with full authorization.

[0017] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0018] First, the relevant terms involved in this application are introduced.

[0019] Synthesis: The process of converting a description language into a specific circuit implementation. It includes two main stages: logic synthesis and physical synthesis. The description language can be a hardware description language or other programming languages. The present application embodiment is described by taking the description language as a hardware description language as an example, but this is not limited to this.

[0020] (1) Logic synthesis: The process of converting hardware description language code into a logic netlist. Logic synthesis requires syntax checking and parsing of the hardware description language code, optimizing the logic expressions in the hardware description language code, mapping the optimized logic expressions to a specific process library, etc.

[0021] (2) Physical synthesis: the process of converting a logical netlist into a physical netlist. Physical synthesis includes processes such as placement, routing, and optimization. Placement is the process of determining the physical location information of circuit elements in the logical netlist on the chip circuit. The goal of layout is to optimize the placement of cells to reduce the length of the connection and timing delay. Routing is to complete the connection between all circuit elements in the chip circuit based on layout. Routing needs to consider signal integrity, electromagnetic compatibility, and design rule constraints.

[0022] Hardware Description Language (HDL): A programming language used to describe electronic systems and integrated circuits. It can describe the logical structure, behavior, function, and timing characteristics of a circuit in detail in text form without the need to draw a circuit diagram directly. HDL provides a standardized method to describe and design complex digital circuits and systems.

[0023] Timing constraints: In digital circuit design, specifications that limit and constrain signal transmission time and timing relationships. Timing constraints that can be set by users include at least one of the following: clock period; duty cycle; generated clock; input delay; output delay.

[0024] The clock cycle is the time it takes for a clock signal to complete a full cycle (from high to low and back to high). It is a measure of the inverse of the clock frequency. It determines the rate at which data is transferred and processed in a circuit. In IC design, the clock cycle is usually measured in nanoseconds (ns) or picoseconds (ps). For example, if a clock has a frequency of 100MHz, then its clock cycle is 10 nanoseconds.

[0025] The duty cycle of a clock refers to the ratio of the duration of the high level of the clock signal in one cycle to the entire cycle time. Usually expressed as a percentage, a clock signal with a duty cycle of 50% means that in one cycle, the high level and the low level each last half of the time. For example, if a clock signal has a cycle of 10 nanoseconds and a high level lasts for 5 nanoseconds, then its duty cycle is 50%.

[0026] Generated clock refers to the sub-clock signal derived from the main clock. Generated clock usually comes from the clock management unit of the circuit module, such as MMCM (Mixed-Mode Clock Manager) or PLL (Phase-Locked Loop). The clock management unit can generate clock signals of different frequencies to meet the clock frequency requirements of different circuit modules in the design; as well as ensure the clock synchronization between different circuit modules, it can eliminate clock skew and jitter, and ensure the stability and consistency of the clock signal; and it also supports dynamic phase adjustment function, which can shift the phase of the clock signal as needed to optimize the timing performance. There can be multiple relationships between the generated clock and the main clock, including frequency division, frequency multiplication, non-integer frequency, phase shift, duty cycle switching, and a combination of these relationships. The main advantage of the generated clock is that when the main clock changes, the generated clock will change synchronously, thereby maintaining the consistency of the clock relationship. In the timing constraints, the definition of the generated clock needs to be performed after the definition of the main clock.

[0027] Input delay is the delay from the clock edge of the upstream chip to the external input port of the downstream chip, such as FPGA (Field-Programmable Gate Array). It includes chip output delay (Tco) and board delay (Trace Delay or Board Delay). Chip output delay refers to the time required for the chip output signal to reach the input port of the next chip. Board delay refers to the transmission delay of the signal on the PCB (Printed Circuit Board), which is affected by factors such as signal path length and material properties. Users define input delay to ensure that the external input signal can arrive and stabilize before the register capture clock edge of the downstream chip, meeting the requirements of setup time and hold time.

[0028] Output delay is the delay from the clock edge of the internal register to the external output port. It describes the time characteristics of the internal signal transmitted to the output port. It includes internal combinational logic delay and output drive delay. Internal combinational logic delay refers to the delay of the signal transmitted in the internal logic circuit. Output drive delay refers to the delay of the signal output from the internal register to the external port. Users define output delay to ensure that the internal signal can reach the external output port before the register capture clock edge of the external chip and meet the setup time and hold time requirements of the external chip.

[0029] Netlist: A file used to describe the connection relationship between circuit components. Usually a text file containing the following core parts.

[0030] Component Instances: Each circuit element (such as transistors, resistors, capacitors, logic gates, etc.) appears as an "instance" in the netlist, and each instance has a unique identifier so that it can be uniquely identified in the circuit.

[0031] Ports and connection points (Pins / Ports): The connection point (port) of each component is the "interface" of the circuit element. The number and nature of the ports depend on the type of component.

[0032] Nets: Nets describe the connection relationship between components and can be regarded as the "signal path" in the circuit. Signals can be transmitted between components through the net.

[0033] Attributes: The netlist may also contain some additional information, such as component packaging, special properties, voltage, frequency, load, etc. These parameters help designers perform simulation and analysis.

[0034] Process library: A database that describes and stores standard cells and related parameters under a specific process node. It contains detailed information and characteristics of various logic cells (such as logic gates, triggers, etc.) under specific process conditions. For example, the function, area, power consumption, timing characteristics (such as setup time, hold time, propagation delay, etc.) of each standard cell; characteristics such as resistance and capacitance of the connection, which are used to estimate the propagation delay of the signal on the connection; process parameters, voltage and temperature range of the process node, etc.

[0035] Layout: The physical geometric description of the circuit design, including the size, number, position, and dimensions of transistors, the size and position of wires, etc., and follows a series of design rules and process conditions.

[0036] Figure 1 The computer system architecture diagram provided by an exemplary embodiment of the present application is shown. The computer system includes a computer device 110 .

[0037] Optionally, the computer device 110 may be a terminal or a server.

[0038] Optionally, the terminal includes but is not limited to mobile phones, tablet computers, intelligent voice interaction devices, game consoles, wearable devices, multimedia playback devices, PCs (Personal Computers), vehicle-mounted terminals, smart home appliances and other electronic devices. Optionally, a comprehensive tool can be installed and run in the terminal, which supports and assists users in converting hardware description files written in hardware description languages ​​into physical netlists or other representations of chip circuits. Optionally, the comprehensive tool can be a set of tools, and each software in the set of tools is used to execute different processes in the comprehensive process, such as one software for logic synthesis and one software for physical synthesis respectively; the comprehensive tool can also be a tool, that is, the logic synthesis process and the physical synthesis process are integrated into the same tool.

[0039] Optionally, the synthesis tool may have a GUI (Graphical User Interface); or it may be driven by a user directly using instructions. When the synthesis tool has a GUI, the synthesis method for optimizing chip area provided in the embodiment of the present application can be integrated into a method corresponding to a control, that is, when the user triggers the control, the synthesis method for optimizing chip area provided in the embodiment of the present application is executed. When the user is required to directly use instructions to drive, the synthesis method for optimizing chip area provided in the embodiment of the present application can be integrated into one or more instructions, such as one instruction corresponding to all steps in the synthesis method for optimizing chip area provided in the embodiment of the present application, or, integrated into multiple instructions, that is, one or more steps in the synthesis method for optimizing chip area provided in the embodiment of the present application correspond to one instruction respectively. That is, the embodiment of the present application does not limit the driving method of the synthesis method for optimizing area.

[0040] Optionally, the server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), as well as big data and artificial intelligence platforms, but is not limited to these.

[0041] Optionally, the server may be a server that provides background services for the synthesis tool in the terminal. That is, the terminal uploads the original timing constraints and hardware description files input by the user to the server, and the server generates a physical network based on the original timing constraints and hardware description files. Optionally, the server may provide background services for the synthesis tools in multiple terminals.

[0042] Optionally, the terminal may communicate with the server via a network, such as a wireless or wired network.

[0043] In the absence of a layout in the early stage, for designs with large areas, complex logic, and tight timing, the number of circuit components and chip area after logic synthesis optimization will increase unreasonably due to the estimation deviation of the synthesis tool for layout and routing. In the early logic synthesis process, when the logic is complex and the timing is tight, the synthesis tool will optimize the timing from the perspective of equivalent logic replacement, which will lead to an increase in the number of components in the circuit. Because the early design tools lack physical information, the increase in area caused by the increase in the number of components is somewhat unreasonable. During logic synthesis, some commonly used convergence timing strategies will aggravate its irrationality. For example, generally, by increasing the value of clock uncertainty or moderately increasing the clock frequency, the tool will optimize the logic structure as much as possible to meet the timing requirements, and even leave sufficient timing margin for subsequent layout and routing.

[0044] Figure 2 FIG. 1 is a flowchart of a comprehensive method for optimizing chip area provided by an exemplary embodiment of the present application. The method is executed by a computer device, which may be a computer device such as Figure 1 The computer device shown in. The method comprises the following steps.

[0045] Step 210: Obtain original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits.

[0046] The original timing constraints are set by the user; or, the original timing constraints are default values ​​set by the developer.

[0047] Optionally, the hardware description file stores a hardware description language code, which is a code written in a hardware description language. The hardware description language code is used to describe the function and structure of the chip circuit.

[0048] Exemplarily, the hardware description language code includes module definition and behavior description. The module definition is used to describe the structure of the chip circuit, such as the various circuit modules (also called circuit entities) included in the chip circuit. The behavior description is used to describe the function of the chip circuit, such as the behavior of each circuit module in the chip circuit, that is, which circuit modules are called to participate in calculation and which modules are called to participate in judgment in order to achieve a certain function, and so on.

[0049] Optionally, obtain original timing constraints and hardware description files; or obtain original timing constraints and hardware description language codes.

[0050] Step 220: Enlarge the clock period in the original timing constraint to obtain an enlarged timing constraint.

[0051] The original timing constraint includes a clock cycle, which may be referred to as an original clock cycle. Optionally, the original timing constraint may also include at least one of the following parameters: duty cycle; generated clock; input delay; output delay.

[0052] Optionally, the enlarged timing constraint is obtained by enlarging the clock period in the original timing constraint, that is, the enlarged timing constraint includes the enlarged clock period. The enlarged timing constraint may also include at least one of the following parameters: a duty cycle of the clock; a generated clock; an input delay; an output delay. The other parameters in the enlarged timing constraint except the clock period may be the same as or different from the original timing constraint.

[0053] Exemplarily, the generated clock in the amplified timing constraint is the same as or different from the generated clock in the original timing constraint. For example, the original master clock is 200MHz, that is, the original clock period is 5ns, and the generated clock requires 200MHz, so the multiplier is set to 1. If the clock period becomes 10ns after the clock period is amplified, the master clock becomes 100MHz. In order to keep the generated clock at 200MHz, the multiplier should be adjusted to 2. At this time, the generated clock in the amplified timing constraint is different from the generated clock in the original timing constraint. The duty cycle in the amplified timing constraint is the same as the duty cycle in the original timing constraint; or, the input delay in the amplified timing constraint is the same as the input delay in the original timing constraint; or, the output delay in the amplified timing constraint is the same as the output delay in the original timing constraint.

[0054] Step 230: Based on the amplified timing constraints, a logic synthesis process is performed on the hardware description file to obtain a logic netlist, which is used to indicate the logic structure of the chip circuit.

[0055] In the process of executing the logic synthesis flow on the hardware description file, the timing is judged by using the amplified timing constraints to obtain the logic netlist.

[0056] Optionally, the logic netlist is used to indicate the logical structure of the chip circuit. That is, the logic netlist is used to indicate the circuit elements included in the chip circuit and the connection relationship between the various circuit elements. However, the connection relationship between these circuit elements is directly based on the circuit modules and the functions of the circuit modules indicated in the hardware description file. That is, the connection relationship indicated in the logic netlist is a functional or behavioral connection relationship, and the physical relationship between these circuit elements on the circuit board is not considered. Among them, for the circuit module indicated in the hardware description file, it can be implemented using one circuit element or multiple circuit elements, depending on the complexity of the function of the circuit module.

[0057] Optionally, the circuit elements in the logic netlist are general gate circuits, or gate circuits in a target process library. The target process library may be a default process library set by a developer, or a process library set by a user. General gate circuits are unit circuits for implementing basic logic operations, such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, XNOR gates, and the like.

[0058] Optionally, based on the relaxed clock cycle, the first logic netlist is obtained by executing the logic synthesis process on the hardware description file; the total number of elements corresponding to the first logic netlist is less than the total number of elements corresponding to the second logic netlist; or, the chip area corresponding to the first logic netlist is less than the chip area corresponding to the second logic netlist; or, the total number of elements corresponding to the first logic netlist is less than the total number of elements corresponding to the second logic netlist, and the chip area corresponding to the first logic netlist is less than the chip area corresponding to the second logic netlist. The second logic netlist is obtained by executing the logic synthesis process on the hardware description file based on the original timing constraints. It should be noted that at least one of the total number of elements and the chip area mentioned above can be at least one of the estimated total number of elements and the estimated chip area estimated by the computer device according to the logic netlist. It can also be at least one of the actual total number of elements and the actual chip area of ​​the chip circuit obtained after executing the subsequent process (such as layout, etc.) based on the first logic netlist and the second logic netlist. In this case, it should be ensured that the subsequent processes executed by the first logic netlist and the second logic netlist and the parameters used in the subsequent processes are the same or similar.

[0059] Step 240: Based on the logic netlist and the original timing constraints, execute the physical synthesis process to obtain the physical netlist, which is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0060] A physical synthesis process is performed on the logic netlist, and the original timing constraints are used in the physical synthesis process to determine the timing to obtain the physical netlist; or, a physical synthesis process is performed on the logic netlist, and the original timing constraints are used in the physical synthesis process to determine or optimize the timing to obtain the physical netlist.

[0061] Optionally, based on the logical netlist and the original timing constraints, a layout process is executed to obtain a physical netlist; or, based on the logical netlist and the timing constraints, a layout process and a routing process are executed to obtain a physical netlist; or, based on the logical netlist and the timing constraints, a physical synthesis process is executed to obtain a physical netlist. If the routing process is executed, the physical netlist is also used to indicate the physical connection of each circuit element in the chip circuit. The physical connection includes the placement of each circuit element (such as orientation), the path and width of the wire, and so on. When indicating, the logical netlist indicates the connection relationship between each circuit element, such as the a port of circuit element 1 is connected to the a port of circuit element 2, and so on.

[0062] Optionally, the physical synthesis process includes a layout process. Or, the physical synthesis process includes a layout process and a routing process. Or, the physical synthesis process includes a layout process, a routing process and an optimization process.

[0063] It should be noted that the execution of the corresponding process in the embodiment of the present application can be called by the computer device itself. For example, after the user triggers the comprehensive method for optimizing the area, the computer device executes each process according to the execution order of the process shown in the above steps 210 to 240. In the process of the computer device executing each process, the call of instructions may be involved. If the user does not directly trigger the comprehensive method for optimizing the area, but directly uses these instructions to execute the comprehensive process, the effect of the comprehensive method for optimizing the area shown in the embodiment of the present application can also be achieved, that is, the above steps 210 to 240 are no longer actively called by the computer device according to the program, but are executed in response to the user's instruction trigger operation. However, it should be emphasized that this method also belongs to the protection scope of the embodiment of the present application.

[0064] In summary, the method provided by the embodiment of the present application shows a synthesis method. This method performs a logic synthesis process by amplifying the clock cycle in the logic synthesis stage, and performing a logic synthesis process based on the amplified timing constraints after the clock cycle is amplified; and after the logic synthesis process is completed and the logic netlist is obtained, the physical synthesis process is executed using the original timing constraints in the layout stage (also referred to as the physical synthesis stage) to obtain the physical netlist. By amplifying the clock cycle in the logic synthesis stage, the timing constraints are made more relaxed, so as to avoid the unreasonable increase of at least one of the total number of components and the chip area due to the excessively tight timing in the logic synthesis stage. In the physical synthesis stage, the original timing constraints are still used on the one hand to ensure that the original settings of the user are not changed, and on the other hand, since the physical synthesis stage will simulate the physical position of each circuit element in the logic netlist, the physical position of the circuit element can be adjusted to meet the original timing constraints (without adding circuit elements), so the use of the relatively tight original timing constraints in this stage can optimize the chip area and the total number of components of the chip circuit as close to the real scene as possible on the basis of ensuring the original timing constraints.

[0065] Based on Figure 2 In an optional embodiment, if Figure 3 The above step 220 can be implemented as steps 221 to 223.

[0066] Step 221: Determine the enlarged adjustment interval of the clock cycle in the original timing constraints.

[0067] Optionally, the amplification adjustment interval of the clock cycle is a value interval of the clock cycle. The amplification adjustment interval of the clock cycle is set by the developer; or, the amplification adjustment interval of the clock cycle is determined based on the original timing constraints and the amplification ratio interval set by the developer; or, the amplification adjustment interval of the clock cycle is determined based on the original timing constraints and the amplification ratio interval set by the user; or, the amplification adjustment interval of the clock cycle is determined based on the original timing constraints set by the user and the hardware description file.

[0068] Optionally, the amplification adjustment interval of the clock cycle is a value interval of the amplification ratio of the clock cycle (i.e., the amplification ratio interval). The amplification adjustment interval of the clock cycle is set by the developer; or, the amplification adjustment interval of the clock cycle is set by the user; or, the amplification adjustment interval of the clock cycle is determined based on the original timing constraints set by the user and the hardware description file.

[0069] That is, the embodiment of the present application does not limit the form of expression of the amplification adjustment interval of the clock cycle.

[0070] Exemplarily, the developer provides at least one magnification adjustment interval, and the user can select the magnification adjustment interval to be used from the at least one magnification adjustment interval by triggering methods such as inputting instructions and clicking controls; or, the developer provides at least one magnification ratio interval, and the magnification ratio interval includes an upper limit of the magnification ratio and a lower limit of the magnification ratio, and the magnification ratio is used to magnify the clock cycle. For example, when amplifying the clock cycle, the amplified clock cycle = the amplification ratio × the original clock cycle (that is, the clock cycle in the original timing constraint), and the amplification ratio is a value greater than 1; or, the amplified clock cycle = (1 + magnification ratio) × the original clock cycle, and the amplification ratio is a value greater than 0 and less than 1.

[0071] Exemplarily, the enlarged adjustment interval of the clock cycle is determined based on the original timing constraints and hardware description files set by the user. That is, after the user starts the synthesis process, or after the user inputs the original timing constraints and hardware description files, the computer device determines the enlarged adjustment interval of the clock cycle in the original timing constraints of the hardware description file based on the original timing constraints and the hardware description file.

[0072] Optionally, the amplified adjustment interval of the clock cycle is the effective adjustment interval of the clock cycle, that is, for the clock cycle within the effective adjustment interval of the clock cycle, as the value of the clock cycle increases, at least one of the total number of components and the chip area corresponding to the logic netlist obtained after executing the above-mentioned synthesis process will decrease accordingly. However, in some embodiments, the amplified adjustment interval of the clock cycle may include the effective adjustment interval of the clock cycle, or the amplified adjustment interval of the clock cycle is a part of the effective adjustment interval of the clock cycle. That is, the relationship between the amplified adjustment interval of the clock cycle and the effective adjustment interval of the clock cycle can be a true subset, a true superset, equal, and the like.

[0073] Step 222: Determine the optimal clock cycle from the amplification adjustment interval of the clock cycle.

[0074] Optionally, based on the amplification adjustment interval of the clock cycle, an amplified clock cycle is selected from small to large, and it is determined whether the amplified clock cycle is an optimal clock cycle.

[0075] Optionally, the optimal clock cycle is a clock cycle that makes the area parameter of the generated logic netlist less than the target area parameter; or, the optimal clock cycle is a clock cycle that makes the area parameter of the generated physical netlist less than the target area parameter; or, the optimal clock cycle is a clock cycle that makes the area parameter of the generated logic netlist less than or equal to the target area parameter; or, the optimal clock cycle is a clock cycle that makes the area parameter of the generated physical netlist less than or equal to the target area parameter. Wherein, the area parameter includes at least one of the total number of components and the chip area. Optionally, the target area parameter can be set by the developer, or can be set based on expert experience, or can be set by the user. Optionally, the target area parameter includes at least one of the target total number of components and the target chip area. That is, the optimal clock cycle refers to the clock cycle that makes the total number of components of the generated logic netlist less than or equal to the target total number of components; or, the optimal clock cycle refers to the clock cycle that makes the chip area of ​​the generated logic netlist less than or equal to the target chip area; or, the optimal clock cycle refers to the clock cycle that makes the total number of components of the generated logic netlist less than or equal to the target total number of components and makes the chip area of ​​the generated logic netlist less than or equal to the target chip area. Or, the optimal clock cycle refers to the clock cycle that makes the total number of elements of the generated physical netlist less than or equal to the target total number of elements; or, the optimal clock cycle refers to the clock cycle that makes the chip area of ​​the generated physical netlist less than or equal to the target chip area; or, the optimal clock cycle refers to the clock cycle that makes the total number of elements of the generated physical netlist less than or equal to the target total number of elements, and makes the chip area of ​​the generated physical netlist less than or equal to the target chip area. Among them, the physical netlist can be obtained after executing the physical synthesis process based on the original timing constraints, or it can be obtained after executing the physical synthesis process based on the amplified timing constraints corresponding to the optimal clock cycle. It should be noted that the physical netlist here represents the physical netlist involved in the optimal clock cycle judgment process, rather than the physical netlist obtained after executing the synthesis method for optimizing the chip area in the above step 240, that is, in the judgment process of the optimal clock cycle, it can be judged based on at least one of the estimated total number of elements and the estimated chip area corresponding to the logical netlist, or it can be judged based on at least one of the estimated total number of elements and the estimated chip area corresponding to the physical netlist. Generally speaking, since physical information is used in the physical synthesis process, at least one of the estimated total number of components and the estimated chip area corresponding to the obtained physical netlist is more accurate than the estimated total number of components and the estimated chip area corresponding to the logical netlist. Therefore, the judgment is based on at least one of the estimated total number of components and the estimated chip area corresponding to the physical netlist.

[0076] Step 223: Based on the optimal clock cycle, obtain the amplification timing constraint.

[0077] Optionally, the clock cycle in the original timing constraint is adjusted to the optimal clock cycle to obtain the enlarged timing constraint. Alternatively, the clock cycle in the original timing constraint is adjusted to the optimal clock cycle, and based on the optimal clock cycle, the relevant parameters in the original timing constraint are adjusted to obtain the enlarged timing constraint, such as adjusting the frequency division coefficient and the frequency multiplication coefficient corresponding to the generated clock, etc. The relevant parameters refer to the parameters affected by the adjustment of the clock cycle.

[0078] In summary, the method provided by the embodiment of the present application shows a method of first determining an amplification adjustment range of a clock cycle, then determining an optimal clock cycle from the amplification adjustment range, and obtaining an amplification timing constraint based on the optimal clock cycle. By obtaining the amplification timing constraint through this method, and then executing the synthesis process based on the amplification timing constraint, compared with the method of randomly obtaining an amplification timing constraint, the clock cycle can be more reasonably relaxed in the synthesis process, so as to achieve at least one of the total number of components and the chip area as much as possible while satisfying the timing constraint.

[0079] Next, it is shown how to determine the enlarged adjustment interval of the clock cycle based on the original timing constraints and the hardware description file, how to determine the optimal clock cycle from the enlarged adjustment interval of the clock cycle, and the improvement of the logic synthesis process.

[0080] 1. Determination of the enlarged adjustment range.

[0081] Based on Figure 3 In an optional embodiment, if Figure 4 As shown, the above step 221 can be implemented as steps 310 to 360.

[0082] Step 310: Determine original area parameters based on original timing constraints.

[0083] The original area parameter includes at least one of the original total number of components and the original chip area. That is, at least one of the original total number of components and the original chip area is determined based on the original timing constraints.

[0084] In some embodiments, step 310 can be implemented as follows: based on the original timing constraints, executing a first logic synthesis process and a layout process on the hardware description file to obtain original area parameters; or, based on the original timing constraints, executing a first logic synthesis process on the hardware description file to obtain original area parameters; or, based on the original timing constraints, executing a first logic synthesis process, a layout process, and a routing process on the hardware description file to obtain original area parameters; or, based on the original timing constraints, executing a first logic synthesis process and a physical synthesis process on the hardware description file to obtain original area parameters.

[0085] That is, based on the original timing constraints, a first logic synthesis process and a layout process are executed on the hardware description file to obtain at least one of the original total number of components and the original chip area; or, based on the original timing constraints, a first logic synthesis process is executed on the hardware description file to obtain at least one of the original total number of components and the original chip area; or, based on the original timing constraints, a first logic synthesis process, a layout process, and a routing process are executed on the hardware description file to obtain at least one of the original total number of components and the original chip area; or, based on the original timing constraints, a first logic synthesis process and a physical synthesis process are executed on the hardware description file to obtain at least one of the original total number of components and the original chip area.

[0086] Optionally, the first logic synthesis process includes an optimization process, which is used to adjust the estimated area parameters corresponding to the logic netlist based on the timing constraints, that is, the optimization process is used to adjust at least one of the estimated total number of components and the estimated chip area corresponding to the logic netlist based on the timing constraints. In the case where the physical synthesis process also includes an optimization process, the optimization process included in the first logic synthesis process can be called a first optimization process, and the optimization process in the physical synthesis can be called a second optimization process. The first optimization process is used to adjust at least one of the estimated total number of components and the estimated chip area corresponding to the logic netlist based on the timing constraints. The second optimization process is used to adjust at least one of the estimated total number of components and the estimated chip area corresponding to the physical netlist based on the timing constraints. In the above step 310 and its corresponding optional embodiments, the first optimization process and the second optimization process both use the original timing constraints.

[0087] Step 320: Determine the i-th magnification ratio, where i is a positive integer.

[0088] Optionally, the initial value of i is 1.

[0089] Optionally, the first magnification ratio is an initial value set by a user; or, the first magnification ratio is a default value set by a developer.

[0090] Optionally, the first amplification ratio is used to indicate a lower limit of an amplification adjustment interval of a clock cycle.

[0091] Exemplarily, the method further includes: acquiring a first amplification ratio; and determining a lower limit of the amplification adjustment interval of the clock cycle based on the first amplification ratio. The first amplification ratio is set by a user.

[0092] Optionally, when i is greater than 1, the i-th amplification ratio is greater than the i-1-th amplification ratio.

[0093] In some embodiments, when i is greater than 1, the i-th magnification ratio is determined based on at least one of the 1st magnification ratio and the (i-1)th magnification ratio.

[0094] For example, for the n magnification ratios determined in n cycles, an arithmetic progression is satisfied, and n is a positive integer. That is, when i is greater than 1, the i-th magnification ratio = the i-1-th magnification ratio + d; or, the i-th magnification ratio = the 1-th magnification ratio + (i-1) × d. Where d is the tolerance, and generally d is a positive number, and the tolerance can be set by the user or by the developer.

[0095] For example, the n magnification ratios determined in n cycles satisfy a geometric progression. That is, when i is greater than 2, the i-th magnification ratio = the i-1-th magnification ratio × q; or, the i-th magnification ratio = the 1st magnification ratio × q i-1 . Wherein, q is a common ratio, and generally speaking, q is a positive number greater than 1, and the common ratio can be set by a user or a developer.

[0096] For example, for the n magnification ratios determined in n cycles, the exponential growth law is satisfied. That is, when i is greater than 1, the i-th magnification ratio = the 1st magnification ratio × e k×(i-1) , where e is the base of the natural logarithm and k is the growth constant. k can be set by the user or by the developer.

[0097] It should be noted that the n magnification ratios determined in n cycles can also be set based on other growth laws, such as logarithmic growth law, power law growth law, etc. That is, the embodiment of the present application does not limit the setting method of the i-th magnification ratio. Developers or users can use the corresponding magnification ratio determination formula based on actual needs. The embodiment of the present application will not list the magnification ratio determination formula one by one, but the protection scope of the embodiment itself is not limited to this.

[0098] Step 330: Based on the i-th amplification ratio, amplify the clock period in the original timing constraint to obtain the i-th amplified timing constraint.

[0099] Optionally, based on the i-th amplification ratio, the clock cycle in the original attribute constraint is amplified to obtain the i-th clock cycle; based on the i-th clock cycle and the original timing constraint, the i-th amplified timing constraint is obtained.

[0100] Exemplarily, the original clock cycle in the original timing constraint is replaced with the i-th clock cycle to obtain the i-th amplified timing constraint; or, the original clock cycle in the original timing constraint is replaced with the i-th clock cycle, and the relevant parameters in the original timing constraint are adjusted based on the i-th clock cycle to obtain the i-th amplified timing constraint, such as adjusting the division coefficient, multiplication coefficient, etc. corresponding to the generated clock.

[0101] Step 340: Determine the i-th area parameter based on the i-th amplification timing constraint.

[0102] Optionally, at least one of the i-th total number of components and the i-th chip area is determined based on the i-th amplification timing constraint.

[0103] Optionally, step 340 can be implemented as: based on the i-th amplification timing constraint, executing the first logic synthesis process and the layout process to obtain the i-th area parameter; or, based on the i-th amplification timing constraint, executing the first logic synthesis process to obtain the i-th area parameter; or, based on the i-th amplification timing constraint, executing the first logic synthesis process, the layout process and the routing process to obtain the i-th area parameter; or, based on the i-th amplification timing constraint, executing the first logic synthesis process and the physical synthesis process to obtain the i-th area parameter.

[0104] Optionally, based on the i-th amplification timing constraint, a first logic synthesis process and a layout process are executed to obtain at least one of the total number of i-th components and the i-th chip area; or, based on the i-th amplification timing constraint, the first logic synthesis process is executed to obtain at least one of the total number of i-th components and the i-th chip area; or, based on the i-th amplification timing constraint, the first logic synthesis process, the layout process and the routing process are executed to obtain at least one of the total number of i-th components and the i-th chip area; or, based on the i-th amplification timing constraint, the first logic synthesis process and the physical synthesis process are executed to obtain at least one of the total number of i-th components and the i-th chip area.

[0105] Optionally, the first logic synthesis process includes an optimization process, which is used to adjust the expected area parameters corresponding to the logic netlist based on the timing constraints, that is, the optimization process is used to adjust at least one of the expected total number of components and the expected chip area corresponding to the logic netlist based on the timing constraints. In the case where the physical synthesis process also includes an optimization process, the optimization process included in the first logic synthesis process can be called a first optimization process, and the optimization process in the physical synthesis can be called a second optimization process. The first optimization process is used to adjust at least one of the expected total number of components and the expected chip area corresponding to the logic netlist based on the timing constraints. The second optimization process is used to adjust at least one of the expected total number of components and the expected chip area corresponding to the physical netlist based on the timing constraints. In the above step 340 and its corresponding optional embodiments, the first optimization process and the second optimization process both use the i-th amplified timing constraint; or, the first optimization process uses the i-th amplified timing constraint, and the second optimization process uses the original timing constraint. The embodiment of the present application is described by taking the i-th amplified timing constraint used in the first optimization process and the second optimization process as an example, but it is not limited to this.

[0106] It should be noted that in the first logic synthesis process and the physical synthesis process, other processes besides the optimization process may also need to use timing constraints. In this case, these processes will use the same timing constraints as the optimization process. That is, the timing constraints used by these processes can refer to the timing constraints used by the first optimization process and the second optimization process mentioned above. The timing constraints used by other processes will not be described in detail in the embodiments of the present application.

[0107] Step 350: Determine an i-th area parameter reduction value based on at least one of the original area parameter and the i-th area parameter.

[0108] Optionally, at least one of the i-th component total number reduction value and the i-th chip area reduction value is determined based on at least one of the original component total number, the original chip area, the i-th component total number and the i-th chip area.

[0109] Optionally, the decrease value of the total number of i-th components is determined based on at least one of the original total number of components and the i-th total number of components; or, the decrease value of the i-th chip area is determined based on at least one of the original chip area and the i-th chip area; or, the decrease value of the total number of i-th components is determined based on at least one of the original total number of components and the i-th total number of components, and the decrease value of the i-th chip area is determined based on at least one of the original chip area and the i-th chip area.

[0110] In some embodiments, step 350 can be implemented as follows: when i is 1, based on the original area parameter and the first area parameter, determine the first area parameter decrease value; when i is greater than 1, based on the i-th area parameter and the i-1-th area parameter, determine the i-th area parameter decrease value; wherein the i-1-th area parameter is determined based on the i-1-th amplification timing constraint corresponding to the i-1-th amplification ratio.

[0111] Optionally, when i is 1, the first total number of components is determined based on the original total number of components and the first total number of components; or, the first chip area is determined based on the original chip area and the first chip area; or, the first total number of components is determined based on the original total number of components and the first total number of components, and the first chip area is determined based on the original chip area and the first chip area. When i is greater than 1, the i-th total number of components is determined based on the i-th total number of components and the i-1th total number of components; or, the i-th chip area is determined based on the i-th chip area and the i-1th chip area; or, the i-th total number of components is determined based on the i-th total number of components and the i-1th total number of components, and the i-th chip area is determined based on the i-th chip area and the i-1th chip area. The i-1th total number of components is determined based on the i-1th amplification timing constraint corresponding to the i-1th amplification ratio; the i-1th chip area is determined based on the i-1th amplification timing constraint corresponding to the i-1th amplification ratio.

[0112] The method for determining at least one of the i-1th total number of components and the i-1th chip area based on the i-1th amplification timing constraint may refer to the above step 340 and will not be described in detail here.

[0113] Exemplarily, the decrease value of the total number of the first components is equal to the difference between the total number of the first components and the original total number of components; or, the decrease value of the total number of the first components is equal to the absolute value of the difference between the total number of the first components and the original total number of components. The decrease value of the area of ​​the first chip is equal to the difference between the area of ​​the first chip and the area of ​​the original chip; or, the decrease value of the area of ​​the first chip is equal to the absolute value of the difference between the area of ​​the first chip and the area of ​​the original chip. The decrease value of the total number of the i-th components is equal to the difference between the total number of the i-th components and the total number of the i-1th components; or, the decrease value of the total number of the i-th components is equal to the absolute value of the difference between the total number of the i-th components and the total number of the i-1th components. The decrease value of the i-th chip area is equal to the difference between the area of ​​the i-th chip and the area of ​​the i-1th chip; or, the decrease value of the i-th chip area is equal to the absolute value of the difference between the area of ​​the i-th chip and the area of ​​the i-1th chip.

[0114] Step 360: When the decrease value of the i-th element area parameter does not satisfy the first condition, set i=i+1, and restart the step of determining the i-th amplification ratio until the decrease value of the i-th area parameter satisfies the first condition, and determine the i-th amplification ratio as the upper limit of the amplification adjustment range of the clock cycle.

[0115] Optionally, when at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area does not satisfy the first condition, let i=i+1, and restart the step of determining the i-th amplification ratio until at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area satisfies the first condition, and the i-th amplification ratio is determined to be the upper limit of the amplification adjustment range of the clock cycle.

[0116] Optionally, when at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area does not meet the first condition, set i=i-1, and restart the execution from the above step 320 until at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area meets the first condition, and determine that the i-th amplification ratio is the upper limit of the amplification adjustment range of the clock cycle.

[0117] In some embodiments, when at least one of the i-th component total number decrease value and the i-th chip area decrease value meets the first condition, the i-1-th amplification ratio can also be used as the lower limit of the amplification adjustment range of the clock cycle, and the embodiment itself does not limit this.

[0118] Optionally, the first condition includes at least one of the following: the i-th area parameter decrease value is less than a first threshold value; the i-th area parameter decrease value is equal to 0. It should be noted that when judging whether the area parameter meets the condition, the embodiment of the present application does not limit the equal situation, that is, the first condition may also be that the first area parameter decrease value is less than or equal to the first threshold value, and the judgment of other conditions is similar, which will not be repeated here.

[0119] Optionally, the area parameter includes at least one of the total number of components and the chip area. In the case where the area parameter includes the total number of components and the chip area, the threshold corresponding to the decrease value of the i-th total number of components and the threshold corresponding to the decrease value of the i-th chip area may be the same or different. For example, optionally, the first condition includes at least one of the following: the decrease value of the i-th total number of components is less than threshold 1; the decrease value of the i-th chip area is less than threshold 2; the decrease value of the i-th total number of components is equal to 0; the decrease value of the i-th chip area is equal to 0. Threshold 1 and threshold 2 may be the same or different.

[0120] Optionally, when the method for determining the amplification adjustment interval for the clock cycle only considers the total number of components, the first condition includes at least one of the following: the i-th total number of components decreases less than a threshold value 1; the i-th total number of components decreases equal to 0. When the method for determining the amplification adjustment interval for the clock cycle only considers the chip area, the first condition includes at least one of the following: the i-th chip area decreases less than a threshold value 2; the i-th chip area decreases equal to 0. When the method for determining the amplification adjustment interval for the clock cycle considers both the total number of components and the chip area, the first condition includes at least one of the following: the i-th total number of components decreases less than a threshold value 1; the i-th chip area decreases less than a threshold value 2; the i-th total number of components decreases equal to 0; the i-th chip area decreases equal to 0.

[0121] Optionally, when the i-th component total number decrease value does not satisfy the first condition, let i=i+1, and start again from the step of determining the i-th amplification ratio until the i-th component total number decrease value satisfies the first condition, and the i-th amplification ratio is determined to be the upper limit of the amplification adjustment interval of the clock cycle. Alternatively, when the i-th chip area decrease value does not satisfy the first condition, let i=i+1, and start again from the step of determining the i-th amplification ratio until the i-th chip area decrease value satisfies the first condition, and the i-th amplification ratio is determined to be the upper limit of the amplification adjustment interval of the clock cycle. Alternatively, when the i-th component total number decrease value and the i-th chip area decrease value do not satisfy the first condition, let i=i+1, and start again from the step of determining the i-th amplification ratio until the i-th component total number decrease value and the i-th chip area decrease value satisfy the first condition, and the i-th amplification ratio is determined to be the upper limit of the amplification adjustment interval of the clock cycle.

[0122] The first threshold may be set by a developer, or by a user, or based on expert experience. For example, the first threshold is 5%×the original area parameter.

[0123] In summary, the method provided by the embodiment of the present application obtains the enlarged adjustment range of the clock cycle that meets the conditions by executing the synthesis process based on the original timing constraints and the hardware description file. Compared with the enlarged adjustment range directly set based on experience, since in the process of determining the enlarged adjustment range, a complete synthesis process is directly executed according to the enlarged timing constraints to obtain at least one of the total number of components and the chip area after synthesis, it is judged whether it is supported to continue to enlarge the clock cycle to reduce at least one of the total number of components and the chip area. In this way, an enlarged adjustment range that can achieve the best result can be determined as much as possible. In addition, in this process, the logic synthesis process used is the first synthesis process, that is, the synthesis process including the optimization process. Due to the lack of physical information, at least one of the total number of components and the chip area obtained based on the first synthesis process will be larger than the second synthesis process that does not perform the optimization process. However, because of this feature, the enlarged adjustment range obtained based on the first synthesis process can be larger, and it is ensured as much as possible that it can include the enlarged adjustment range that can achieve the best result.

[0124] 2. Determination of the optimal clock period.

[0125] Based on Figure 3 In an optional embodiment, if Figure 5 As shown, the above step 222 can be implemented as steps 410 to 460.

[0126] Step 410: Determine the first clock cycle based on the lower limit of the amplification adjustment interval of the clock cycle.

[0127] Optionally, the amplification adjustment interval of the clock cycle is the value interval of the clock cycle; the lower limit of the amplification adjustment interval of the clock cycle is determined as the first clock cycle, that is, the first clock cycle is the lower limit of the amplification adjustment interval of the clock cycle. Or, the amplification adjustment interval of the clock cycle is the amplification ratio interval corresponding to the clock cycle; based on the lower limit of the amplification adjustment interval of the clock cycle, the minimum amplification ratio is determined, and based on the minimum amplification ratio and the original clock cycle, the first clock cycle is determined.

[0128] Step 420: Determine a first enlarged timing constraint based on the first clock cycle and the original timing constraint; and obtain a first area parameter based on the first enlarged timing constraint.

[0129] Optionally, based on the first clock cycle and the original timing constraint, a first enlarged timing constraint is determined; and based on the first enlarged timing constraint, at least one of a first total number of components and a first chip area is obtained.

[0130] Optionally, based on the first clock cycle and the original timing constraint, the first amplified timing constraint may be determined by referring to the above step 223 or step 330, which will not be described in detail herein.

[0131] In some embodiments, based on the first enlarged timing constraint, a first area parameter is obtained, including: based on the first enlarged timing constraint, executing a second logic synthesis process and a layout process on the hardware description file to obtain the first area parameter; or, based on the first enlarged timing constraint, executing a second synthesis process on the hardware description file to obtain the first area parameter; or, based on the first enlarged timing constraint, executing a second synthesis process, a layout process and a routing process on the hardware description file to obtain the first area parameter; or, based on the first enlarged timing constraint, executing a second logic synthesis process and a physical synthesis process on the hardware description file to obtain the first area parameter.

[0132] In some embodiments, based on the first enlarged timing constraint, at least one of the first total number of components and the first chip area is obtained, including: based on the first enlarged timing constraint, executing a second logic synthesis process and a layout process on the hardware description file to obtain at least one of the first total number of components and the first chip area; or, based on the first enlarged timing constraint, executing a second synthesis process on the hardware description file to obtain at least one of the first total number of components and the first chip area; or, based on the first enlarged timing constraint, executing a second synthesis process, a layout process and a routing process on the hardware description file to obtain at least one of the first total number of components and the first chip area; or, based on the first enlarged timing constraint, executing a second logic synthesis process and a physical synthesis process on the hardware description file to obtain at least one of the first total number of components and the first chip area.

[0133] In some embodiments, the second logic synthesis process does not include an optimization process. The optimization process is used to adjust the estimated total number of components and the estimated chip area corresponding to the logic netlist based on the timing constraints. Optionally, the physical synthesis process includes an optimization process. Each process in the physical synthesis flow, including the optimization process, can use the first amplified timing constraints or the original timing constraints, which is not limited in the embodiments of the present application.

[0134] Step 430: Determine the j-th clock cycle based on the amplification adjustment interval of the clock cycle, where j is a positive integer greater than 1.

[0135] Optionally, the initial value of j is 2.

[0136] In some embodiments, the amplification adjustment interval of the clock cycle is the value interval of the clock cycle; the jth clock cycle is determined based on the amplification adjustment interval of the clock cycle. Or, the amplification adjustment interval of the clock cycle is the amplification ratio interval corresponding to the clock cycle; the jth amplification ratio is determined based on the amplification adjustment interval of the clock cycle, and the jth clock cycle is determined based on the jth amplification ratio and the original clock cycle.

[0137] Optionally, when j is greater than 1, the j-th magnification ratio is greater than the j-1-th magnification ratio.

[0138] In some embodiments, when j is greater than 1, the jth clock cycle is determined based on at least one of the 1st clock cycle and the j-1th clock cycle.

[0139] For example, for the n clock cycles determined in n cycles, an arithmetic progression is satisfied, and n is a positive integer. That is, when j is greater than 1, the jth clock cycle = the j-1th clock cycle + d; or, the jth clock cycle = the 1st clock cycle + (j-1) × d. d is the tolerance, and generally d is a positive number, which can be set by the user or by the developer.

[0140] For example, for the n clock cycles determined in n cycles, a geometric progression is satisfied. That is, when j is greater than 2, the jth clock cycle = the j-1th clock cycle × q; or, the jth clock cycle = the 1st clock cycle × q j-1 . Wherein, q is a common ratio, and generally speaking, q is a positive number greater than 1, and the common ratio can be set by a user or a developer.

[0141] For example, for the n clock cycles determined in n cycles, the exponential growth law is satisfied. That is, when j is greater than 1, the jth clock cycle = the first clock cycle × e k×(j-1) , where e is the base of the natural logarithm and k is the growth constant. k can be set by the user or by the developer.

[0142] It should be noted that the n clock cycles determined in n cycles can also be set based on other growth laws, such as logarithmic growth law, power law growth law, etc. That is, the embodiment of the present application does not limit the setting method of the j-th clock cycle. Developers or users can use the corresponding clock cycle determination formula based on actual needs. The embodiment of the present application will not list the clock cycle determination formula one by one, but the protection scope of the embodiment itself is not limited to this.

[0143] Step 440: Determine the jth enlarged timing constraint based on the jth clock cycle and the original timing constraint; and obtain the jth area parameter based on the jth enlarged timing constraint.

[0144] Optionally, based on the jth clock cycle and the original timing constraint, a jth enlarged timing constraint is determined; and based on the jth enlarged timing constraint, at least one of a jth total number of components and a jth chip area is obtained.

[0145] Optionally, based on the j-th clock cycle and the original timing constraint, the j-th amplification timing constraint may be determined by referring to the above step 223 or step 330, which will not be described in detail herein.

[0146] In some embodiments, based on the j-th amplification timing constraint, obtaining the j-th area parameter includes: based on the j-th amplification timing constraint, executing a second logic synthesis process and a layout process on the hardware description file to obtain the j-th area parameter; or, based on the j-th amplification timing constraint, executing a second logic synthesis process on the hardware description file to obtain the j-th area parameter; or, based on the j-th amplification timing constraint, executing a second synthesis process, a layout process and a routing process on the hardware description file to obtain the j-th area parameter; or, based on the j-th amplification timing constraint, executing a second logic synthesis process and a physical synthesis process on the hardware description file to obtain the j-th area parameter.

[0147] In some embodiments, based on the j-th amplification timing constraint, at least one of the j-th total number of components and the j-th chip area is obtained, including: based on the j-th amplification timing constraint, executing a second logic synthesis process and a layout process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area; or, based on the j-th amplification timing constraint, executing a second logic synthesis process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area; or, based on the j-th amplification timing constraint, executing a second synthesis process, a layout process, and a routing process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area; or, based on the j-th amplification timing constraint, executing a second logic synthesis process and a physical synthesis process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area.

[0148] In some embodiments, the second logic synthesis process does not include an optimization process. The optimization process is used to adjust the estimated total number of components and the estimated chip area corresponding to the logic netlist based on the timing constraints. Optionally, the physical synthesis process includes an optimization process. Each process in the physical synthesis flow, including the optimization process, can use the j-th amplified timing constraint or the original timing constraint, which is not limited in the embodiments of the present application.

[0149] Step 450: Determine a jth area parameter decrease value based on at least one of the first area parameter and the jth area parameter.

[0150] Optionally, at least one of a jth component total number reduction value and a jth area reduction value is determined based on at least one of the first component total number, the first chip area, the jth component total number and the jth chip area.

[0151] Optionally, based on at least one of the total number of the 1st elements and the total number of the jth elements, the decrease value of the total number of the jth elements is determined; or, based on at least one of the 1st chip area and the jth chip area, the decrease value of the jth chip area is determined; or, based on at least one of the 1st total number of elements and the total number of the jth elements, the decrease value of the total number of the jth elements is determined, and based on at least one of the 1st chip area and the jth chip area, the decrease value of the jth chip area is determined.

[0152] In some embodiments, step 450 can be implemented as follows: when j is 2, based on the first area parameter and the second area parameter, determine the second area parameter decrease value; when j is greater than 2, based on the jth area parameter and the j-1th area parameter, determine the jth area parameter; wherein the j-1th area parameter is determined based on the j-1th amplification timing constraint.

[0153] Optionally, when j is 2, the decrease value of the total number of the second components is determined based on the total number of the first components and the total number of the second components; or, the decrease value of the area of ​​the second chip is determined based on the area of ​​the first chip and the area of ​​the second chip; or, the decrease value of the total number of the second components is determined based on the total number of the first components and the total number of the second components, and the decrease value of the area of ​​the second chip is determined based on the area of ​​the first chip and the area of ​​the second chip. When j is greater than 2, the decrease value of the total number of the jth components is determined based on the total number of the jth components and the total number of the j-1th components; or, the decrease value of the area of ​​the jth chip is determined based on the area of ​​the j-1th chip and the area of ​​the j-1th chip; or, the decrease value of the total number of the jth components is determined based on the total number of the jth components and the total number of the j-1th components, and the decrease value of the area of ​​the jth chip is determined based on the area of ​​the j-1th chip and the area of ​​the j-1th chip. Wherein, the total number of the j-1th components is determined based on the j-1th amplification timing constraint; the area of ​​the j-1th chip is determined based on the j-1th amplification timing constraint.

[0154] The method for determining at least one of the total number of j-1th components and the area of ​​the j-1th chip based on the j-1th amplification timing constraint may refer to the above step 440 and will not be described in detail herein.

[0155] The calculation of the second component total number reduction value, the second chip area reduction value, the j-th component total number reduction value and the j-th chip area reduction value may refer to the above step 350 and will not be repeated here.

[0156] Step 460: When the j-th area parameter decrease value does not satisfy the second condition, set j=j+1, and start again from the step of determining the j-th clock cycle based on the clock cycle amplification adjustment interval until the j-th area parameter decrease value satisfies the second condition, and determine that the j-th clock cycle is the optimal clock cycle.

[0157] Optionally, when at least one of the j-th component total decrease value and the j-th chip area decrease value does not meet the second condition, set j=j+1, and restart the step of determining the j-th clock cycle based on the clock cycle amplification adjustment interval until at least one of the j-th component total decrease value and the j-th chip area decrease value meets the second condition, and determine the j-th clock cycle as the optimal clock cycle.

[0158] Optionally, when at least one of the j-th component total decrease value and the j-th chip area decrease value does not meet the second condition, set j=j+1, and restart execution from step 430 until at least one of the j-th component total decrease value and the j-th chip area decrease value meets the second condition, and determine that the j-th clock cycle is the optimal clock cycle.

[0159] In some embodiments, when at least one of the j-th component total number decrease value and the j-th chip area decrease value meets the first condition, the j-1-th clock cycle may also be used as the optimal clock cycle, which is not limited in this embodiment.

[0160] Optionally, the second condition includes at least one of the following: the j-th area parameter decrease value is less than a second threshold value; the j-th area parameter decrease value is equal to 0.

[0161] Optionally, the area parameter includes at least one of the total number of components and the chip area. When the area parameter includes the total number of components and the chip area, the threshold corresponding to the jth total number of components decrease value and the threshold corresponding to the jth chip area decrease value may be the same or different. For example, the second condition includes at least one of the following: the jth total number of components decrease value is less than threshold 1; the jth chip area decrease value is less than threshold 2; the jth total number of components decrease value is equal to 0; the jth chip area decrease value is equal to 0. Threshold 1 and threshold 2 may be the same or different. It should be noted that the first threshold, the second threshold, threshold 1, threshold 2, etc. shown in the embodiments of the present application are only for illustration, and in different embodiments, the same description may also use different values. That is, in "1. Determination of the amplification adjustment interval" and "2. Determination of the optimal clock cycle", threshold 1 is used as the threshold for both the i-th total number of components decrease value and the j-th total number of components decrease value, but for the i-th total number of components decrease value and the j-th total number of components decrease value, the corresponding values ​​may be the same or different. The same applies to threshold 2.

[0162] Optionally, when only the total number of components is considered in the determination method for the optimal clock period, the second condition includes at least one of the following: the jth total number of components decreases less than a threshold value 1; the jth total number of components decreases equal to 0. When only the chip area is considered in the determination method for the optimal clock period, the second condition includes at least one of the following: the jth chip area decreases less than a threshold value 2; the jth chip area decreases equal to 0. When both the total number of components and the chip area are considered in the determination method for the optimal clock period, the second condition includes at least one of the following: the jth total number of components decreases less than a threshold value 1; the jth chip area decreases less than a threshold value 2; the jth total number of components decreases equal to 0; the jth chip area decreases equal to 0.

[0163] Optionally, when the jth total number of components decreases and the second condition is not satisfied, let j=j+1, and start again from the step of determining the jth clock cycle based on the amplification adjustment interval of the clock cycle, until the jth total number of components decreases and the second condition is satisfied, and the jth amplification ratio is determined to be the upper limit of the amplification adjustment interval of the clock cycle. Alternatively, when the jth chip area decreases and the second condition is not satisfied, let j=j+1, and start again from the step of determining the jth clock cycle based on the amplification adjustment interval of the clock cycle, until the jth chip area decreases and the second condition is satisfied, and the jth amplification ratio is determined to be the upper limit of the amplification adjustment interval of the clock cycle. Alternatively, when the jth total number of components decreases and the jth chip area decreases and the second condition is not satisfied, let j=j+1, and start again from the step of determining the jth clock cycle based on the amplification adjustment interval of the clock cycle, until the jth total number of components decreases and the jth chip area decreases and the second condition is satisfied, and the jth amplification ratio is determined to be the upper limit of the amplification adjustment interval of the clock cycle.

[0164] In addition, it should be noted that during the execution of the above-mentioned step 430, it should be ensured that the j-th clock cycle is less than the upper limit of the adjustment interval of the clock cycle. That is, when the j-th clock cycle exceeds the adjustment interval of the clock cycle and the second condition is still not met, the judgment of the optimal timing constraint should be terminated and an error message should be displayed.

[0165] In summary, the method provided in the embodiment of the present application shows a method for determining the optimal clock cycle. The optimal clock cycle refers to a clock cycle that can make the physical netlist obtained after executing the synthesis process an optimal result. In the process of determining the optimal clock cycle, the clock cycle is gradually increased from the lower limit of the amplified adjustment range. The larger the clock cycle, the looser the timing constraint. At this time, a smaller total number of components and chip area will be obtained in the logic synthesis process. However, since there is a physical synthesis process in the follow-up, the physical synthesis process is based on the original timing constraint. The original timing constraint is a tight timing constraint. Based on the tighter timing constraint, more total number of components and chip area will be obtained. That is, in the process of determining the optimal clock cycle, it is a process of first loosening and then releasing. In this process, there will be an optimal result that can meet the timing constraint and achieve a smaller total number of components and chip area. The clock cycle corresponding to this optimal result is the optimal clock cycle. In the process of determining the optimal clock cycle, the synthesis process executed is consistent with the final synthesis process, which can ensure that the optimal clock cycle is applied to the above Figure 3 The method shown in its optional embodiment can also achieve the best result, ensuring the reliability of the method.

[0166] 3. Improvement of logic synthesis process.

[0167] In some embodiments, the above step 230 includes: based on the amplified timing constraints, executing a second logic synthesis process on the hardware description file to obtain a logic netlist; wherein the second logic synthesis process does not include an optimization process, and the optimization process is used to adjust the estimated area parameters corresponding to the logic netlist based on the timing constraints.

[0168] Optionally, the optimization process is used to adjust at least one of an estimated total number of components and an estimated chip area corresponding to the logic netlist based on the timing constraints.

[0169] Optionally, since the optimization process is based on the timing constraints to adjust at least one of the total number of components and the estimated chip area corresponding to the logic netlist. Generally speaking, relaxed timing constraints (such as a larger clock cycle) make it easier to meet the timing constraints during the generation of the logic netlist, that is, there is no need to add additional circuit elements (such as registers) between circuit modules to make each circuit module meet the timing constraints, that is, generally speaking, a logic netlist with a smaller total number of components and a smaller chip area can be generated under relaxed timing constraints. However, for the optimization process in the logic synthesis process, since it is impossible to know the physical information corresponding to the chip circuit, it can only be optimized based on the logic structure of the existing chip circuit. Therefore, during the optimization, in order to ensure that the subsequent physical synthesis process can more easily meet the timing constraints, a relatively loose optimization policy will be adopted to ensure that each circuit module or timing path in the chip circuit can have a larger timing margin, which will correspondingly lead to an increase in the total number of components and an increase in at least one of the chip area. However, in fact, in the physical synthesis process, there is a more accurate optimization process (because the optimization process can obtain physical information), so the optimization process that causes an unreasonable increase in at least one of the total number of components and the chip area can be omitted in the logic synthesis stage, that is, the second logic synthesis process is executed here.

[0170] It should be noted that the above “1. Determination of the amplification adjustment interval” and “2. Determination of the optimal clock period” can be implemented as independent embodiments or as a combined embodiment.

[0171] The embodiment of the present application increases the clock cycle to relax the problem of unreasonable increase in circuit elements and area caused by unreasonable over-optimization of logic circuits during synthesis. The range in which the clock cycle can be enlarged is found through iteration. Then, by adjusting the steps of the synthesis process, the clock cycle is enlarged in the early stage of synthesis, and the clock cycle is retracted in the later stage, and it is iterated within the adjustable range of the clock cycle. Under the condition of meeting the timing results, the result with the minimum number of circuit elements and area is iterated, thereby achieving the result of optimizing the chip area without affecting the final timing results. For example, Figure 6 and Figure 7 shown.

[0172] For example, first, the amplification adjustment range of the clock cycle needs to be determined, such as Figure 6 shown.

[0173] Step 1, execute the first synthesis process to obtain the total number of original components and the original chip area.

[0174] Exemplarily, the first comprehensive process is as follows Figure 8 As shown, the first synthesis flow includes a first logic synthesis flow 10 and a physical synthesis flow 20. In the whole process of the first synthesis flow, the original timing constraints 30 are used.

[0175] Specifically, the first logic synthesis process 10 includes a refinement process 11, a general mapping process 12, a mapping process 13 and a logic optimization process 14. Among them, each process corresponds to a different instruction. It should be noted that the following instructions for each process and the description of each instruction are only for illustration. For different synthesis tools, the instructions used and the functions corresponding to the instructions may be different, but the protection scope of the embodiment itself is not limited to this.

[0176] For example, the instruction of refinement flow 11 is the elaborate instruction, which creates a design hierarchy consisting of a top-level design and its referenced sub-designs from Verilog or System Verilog modules or VHDL entities / architectures. If a top-level design is not specified, all modules that are not instantiated by other modules are elaborated as top-levels and elaborated together with the sub-designs. This instruction converts each module / architecture into a design represented in the form of a structured netlist. It also performs semantic checking, sequential register (flip-flop / latch) inference, and high-level HDL optimization. Instances of undefined modules or entities are marked as unresolved, and the corresponding modules / entities are reported as black boxes.

[0177] The instruction for the generic mapping flow 12 is syn_generic. This instruction takes a detailed and fully constrained design as input and synthesizes it into a netlist of generic gates by performing high-level RTL (Register Transfer Level) and datapath optimization.

[0178] The instruction for mapping flow 13 is syn_map. This instruction maps the design from generic gates to the process library while optimizing for best performance, power, and area. Multiple implementations of a given logic cone are evaluated and the one that minimizes area and power while meeting timing constraints is selected. After the initial mapping phase, further refinement is performed by progressively optimizing the netlist to recover area and power while maintaining timing.

[0179] The directive for the logic optimization flow14 is syn_opt. This directive takes a mapped design as input and optimizes timing, area, and power incrementally. If you do not specify spatial or physical flow options, syn_opt will perform pure logic optimizations, even when called on a design database generated by physically-aware mapping.

[0180] Specifically, the physical synthesis process 20 includes a placement and physical optimization process 21, and the corresponding instruction is place&opt. A pre-CTS (Clock Tree Synthesis) process with placement and pre-clock tree synthesis optimization is executed. Using place_opt_design, the user only needs to run one command to complete the placement and pre-CTS optimization.

[0181] Step 2, setting the initial amplification ratio a% of the clock cycle and the total number of components decreasing threshold.

[0182] It should be noted that, here the judgment is made based on the decrease value of the total number of components as an example, but it can also be made based on at least one of the decrease value of the total number of components and the decrease value of the chip area. At this time, it is necessary to set at least one of the decrease threshold of the total number of components and the decrease threshold of the chip area.

[0183] Step 3, execute the second comprehensive process.

[0184] Among them, the second comprehensive process is as follows Fig. 9 As shown, the second synthesis process is similar to the first synthesis process, and will not be described in detail here. The difference between the second synthesis process and the first synthesis process is that the second synthesis process uses the enlarged timing constraint 31 with enlarged clock period in the whole process.

[0185] After executing the second synthesis process, the total number of components after the clock cycle is amplified is obtained.

[0186] Step 4, determine the total number of components reduction value.

[0187] Based on the original component count and the component count after the amplified clock period, a component count reduction value is determined.

[0188] Step 5: Determine whether the total number of components decreased by a value greater than a threshold.

[0189] Determine whether the total number of components decreases above the total number of components decrease threshold. If the total number of components decreases above the total number of components decrease threshold, execute step 6; if the total number of components decreases below the total number of components decrease threshold, jump to execute step 7.

[0190] Step 6: Increase the clock cycle amplification ratio.

[0191] The method for determining the clock cycle amplification ratio may refer to the above step 320 and will not be described in detail here.

[0192] Step 7, determine the amplification adjustment range of the clock cycle.

[0193] When the total number of components decreases not higher than the total number of components decrease threshold, the current clock cycle is determined as the upper limit of the amplification adjustment range of the clock cycle, thereby obtaining the amplification adjustment range.

[0194] After the amplification adjustment range is determined, the optimal clock period that can achieve the best result can be determined from the amplification adjustment range.

[0195] Step 1: determining an initial clock cycle based on a lower limit of the amplification adjustment range.

[0196] The initial clock period is determined as the lower limit of the amplification adjustment range.

[0197] Step 2, the third comprehensive process.

[0198] The third comprehensive process is as follows Fig.10 As shown. The third synthesis process includes a second logic synthesis process 40 and a physical synthesis process 20. Compared with the first logic synthesis process 10, the second logic synthesis process 40 removes the logic optimization process to avoid the unreasonable increase in the total number of components and the increase in chip area caused by the logic optimization process. The physical synthesis process 20 included in the third synthesis process uses the original timing constraints and the logic net report obtained based on the second synthesis process 40 to perform the layout and physical optimization process.

[0199] Step 3: Determine whether the timing constraints are met.

[0200] After executing the third synthesis flow, determine whether the generated physical netlist meets the timing constraints. If not, jump to step 7; if yes, continue to step 4.

[0201] Step 4, determine whether the total number of components is reduced.

[0202] Determine whether the total number of components in the physical netlist generated by the third synthesis process is reduced compared to the physical netlist generated after the last execution of the third synthesis process. If reduced, continue to execute step 5; if not reduced, jump to execute step 7.

[0203] Step 5, zoom in on the clock period.

[0204] Continue to amplify the clock cycle. For details, please refer to the above step 430, which will not be repeated here.

[0205] Step 6, determining whether the amplified clock cycle is still within the amplification adjustment range.

[0206] Determine whether the amplified clock period is still within the amplification adjustment range. If not, execute step 7; if still within the amplification adjustment range, jump to step 2.

[0207] Step 7, end.

[0208] After obtaining the optimal clock cycle, the third synthesis process is executed to obtain the best result.

[0209] Please refer to Fig.11 , which shows a block diagram of a comprehensive device for optimizing chip area provided by an exemplary embodiment of the present application. The device has the function of implementing the above-mentioned comprehensive method example for optimizing chip area, and the function can be implemented by hardware, or by hardware executing corresponding software. The device can be the computer device described above, or it can be set in a computer device. Fig.11 As shown, the device may include: an acquisition module 510 , an amplification module 520 , a logic synthesis module 530 , and a physical synthesis module 540 .

[0210] The acquisition module 510 is used to acquire original timing constraints and a hardware description file, where the hardware description file is used to describe the function and structure of the chip circuit.

[0211] The amplification module 520 is used to amplify the clock cycle in the original timing constraint to obtain an amplified timing constraint.

[0212] The logic synthesis module 530 is used to execute a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist, and the logic netlist is used to indicate the logic structure of the chip circuit.

[0213] The physical synthesis module 540 is used to execute the layout process based on the logical netlist and the original timing constraints to obtain a physical netlist, wherein the physical netlist is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0214] In some embodiments, the amplification module 520 includes a determination submodule and an amplification submodule.

[0215] The determination submodule is used to determine the enlarged adjustment interval of the clock cycle in the original timing constraint.

[0216] The determination submodule is further used to determine the optimal clock cycle from the amplification adjustment interval of the clock cycle, and the optimal clock cycle is a clock cycle that makes the area parameter of the generated logical netlist or the physical netlist smaller than the target area parameter.

[0217] The amplification submodule is used to obtain the amplification timing constraint based on the optimal clock cycle.

[0218] In some embodiments, the determination submodule is also used to determine the original area parameter based on the original timing constraint; determine the i-th amplification ratio, where i is a positive integer; based on the i-th amplification ratio, amplify the clock cycle in the original timing constraint to obtain the i-th amplified timing constraint; based on the i-th amplified timing constraint, determine the i-th area parameter; based on at least one of the original area parameter and the i-th area parameter, determine the i-th area parameter decrease value; if the i-th area parameter decrease value does not meet the first condition, set i=i+1, and restart the step of determining the i-th amplification ratio until the i-th area parameter decrease value meets the first condition, and determine that the i-th amplification ratio is the upper limit of the amplification adjustment interval of the clock cycle.

[0219] In some embodiments, the determination submodule is also used to determine the first area parameter decrease value based on the original area parameter and the first area parameter when i is 1; and to determine the i-th area parameter decrease value based on the i-th area parameter and the i-1-th area parameter when i is greater than 1; wherein the i-1-th area parameter is determined based on the i-1-th amplification timing constraint corresponding to the i-1-th amplification ratio.

[0220] In some embodiments, the determination submodule is further used to execute the first logic synthesis process and the physical synthesis process on the hardware description file based on the original timing constraints to obtain the original area parameter.

[0221] In some embodiments, the determination submodule is further used to execute the first logic synthesis process and the physical synthesis process based on the i-th amplification timing constraint to obtain the i-th area parameter.

[0222] In some embodiments, the first logic synthesis flow includes an optimization flow for adjusting an estimated area parameter corresponding to the logic netlist based on a timing constraint.

[0223] In some embodiments, the acquisition module 510 is further configured to acquire a first amplification ratio; and determine a lower limit of the amplification adjustment interval of the clock cycle based on the first amplification ratio.

[0224] In some embodiments, the first condition includes at least one of the following: the i-th area parameter decrease value is less than a first threshold; the i-th area parameter decrease value is equal to zero.

[0225] In some embodiments, the determination submodule is further used to determine the first clock cycle based on the lower limit of the amplification adjustment interval of the clock cycle; determine the first amplification timing constraint based on the first clock cycle and the original timing constraint; and obtain the first area parameter based on the first amplification timing constraint; determine the jth clock cycle based on the amplification adjustment interval of the clock cycle, where j is a positive integer greater than 1; determine the jth amplification timing constraint based on the jth clock cycle and the original timing constraint; and obtain the jth area parameter based on the jth amplification timing constraint; determine the jth area parameter decrease value based on at least one of the first area parameter and the jth area parameter; if the jth area parameter decrease value does not meet the second condition, set j=j+1, and start again from the step of determining the jth clock cycle based on the amplification adjustment interval of the clock cycle until the jth area parameter decrease value meets the second condition, and determine that the jth clock cycle is the optimal clock cycle.

[0226] In some embodiments, the determination submodule is further used to execute a second logic synthesis process and a physical synthesis process on the hardware description file based on the first amplification timing constraint to obtain the first area parameter.

[0227] In some embodiments, the determination submodule is further used to execute the second logic synthesis process and the physical synthesis process on the hardware description file based on the j-th amplification timing constraint to obtain the j-th area parameter.

[0228] In some embodiments, the determination submodule is also used to determine the second area parameter decrease value based on the first area parameter and the second area parameter when j is 2; and to determine the jth area parameter decrease value based on the jth area parameter and the j-1th area parameter when j is greater than 2; wherein the j-1th area parameter is determined based on the j-1th amplification timing constraint.

[0229] In some embodiments, the second condition includes at least one of the following: the j-th area parameter decrease value is less than a second threshold; the j-th area parameter decrease value is equal to 0.

[0230] In some embodiments, the logic synthesis module 530 is further used to execute a second logic synthesis process on the hardware description file based on the amplified timing constraints to obtain the logic netlist; wherein the second logic synthesis process does not include an optimization process, and the optimization process is used to adjust the estimated area parameters corresponding to the logic netlist based on the timing constraints.

[0231] It should be noted that: when the device provided in the above embodiment realizes its function, only the division of the above functional modules is used as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0232] Fig.12 A schematic diagram of the structure of a computer device provided by an exemplary embodiment of the present application is shown.

[0233] The computer device 800 includes a central processing unit (CPU) 801, a system memory 804 including a random access memory (RAM) 802 and a read-only memory (ROM) 803, and a system bus 805 connecting the system memory 804 and the central processing unit 801. The computer device 800 also includes a basic input / output system (I / O system) 806 for facilitating information transmission between various components in the computer device, and a large-capacity storage device 807 for storing an operating system 813, application programs 814, and other program modules 815.

[0234] The basic input / output system 806 includes a display 808 for displaying information and an input device 809 such as a mouse and a keyboard for user inputting information. The display 808 and the input device 809 are connected to the central processing unit 801 through an input / output controller 810 connected to the system bus 805. The basic input / output system 806 may also include an input / output controller 810 for receiving and processing inputs from a plurality of other devices such as a keyboard, a mouse, or an electronic stylus. Similarly, the input / output controller 810 also provides output to a display screen, a printer, or other types of output devices.

[0235] The mass storage device 807 is connected to the central processing unit 801 via a mass storage controller (not shown) connected to the system bus 805. The mass storage device 807 and its associated computer-readable storage medium provide non-volatile storage for the computer device 800. That is, the mass storage device 807 may include a computer-readable storage medium (not shown) such as a hard disk or a compact disc read-only memory (CD-ROM) drive.

[0236] Without loss of generality, the computer-readable storage medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable storage instructions, data structures, program modules or other data. Computer storage media include RAM, ROM, Erasable Programmable Read Only Memory (EPROM), Electronically Erasable Programmable Read-Only Memory (EEPROM), flash memory or other solid-state storage technology, CD-ROM, Digital Versatile Disc (DVD) or other optical storage, cassettes, tapes, disk storage or other magnetic storage devices. Of course, those skilled in the art will know that the computer storage medium is not limited to the above. The above-mentioned system memory 804 and mass storage device 807 can be collectively referred to as memory.

[0237] The memory stores one or more programs, and the one or more programs are configured to be executed by one or more central processing units 801. The one or more programs contain instructions for implementing the above-mentioned method embodiments. The central processing unit 801 executes the one or more programs to implement the methods provided by the above-mentioned method embodiments.

[0238] According to various embodiments of the present application, the computer device 800 can also be connected to a remote computer device on a network through a network such as the Internet. That is, the computer device 800 can be connected to a network 812 through a network interface unit 811 connected to the system bus 805, or the network interface unit 811 can be used to connect to other types of networks or remote computer device systems (not shown).

[0239] The memory also includes one or more programs, which are stored in the memory and include steps executed by a computer device in the method provided in the embodiment of the present application.

[0240] In an exemplary embodiment, the present application provides a chip, which includes at least one of a programmable logic circuit and a program instruction, and when the chip runs on a computer device, is used to implement the comprehensive method for optimizing chip area provided by the above method embodiment.

[0241] In an exemplary embodiment, a non-transitory computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the integrated method for optimizing chip area is implemented.

[0242] In an exemplary embodiment, a computer program product is also provided. When the computer program product is executed by a processor, it is used to implement the above-mentioned comprehensive method for optimizing chip area.

[0243] It should be understood that the "multiple" mentioned in this article refers to two or more. The character " / " generally indicates that the objects associated with each other are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to that shown in the figure. The embodiments of the present application do not limit this.

[0244] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A comprehensive method for optimizing chip area, characterized in that: The method comprises: Obtaining original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits; Enlarging the clock cycle in the original timing constraint to obtain an enlarged timing constraint; Based on the amplified timing constraints, a logic synthesis process is performed on the hardware description file to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit; Based on the logic netlist and the original timing constraints, a physical synthesis process is executed to obtain a physical netlist, where the physical netlist is used to indicate the logic structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

2. The method according to claim 1, characterized in that The step of enlarging the clock cycle in the original timing constraint to obtain the enlarged timing constraint includes: Determine an enlarged adjustment interval of the clock cycle in the original timing constraint; Determine an optimal clock cycle from the amplification adjustment interval of the clock cycle, the optimal clock cycle being a clock cycle that makes the area parameter of the generated logic netlist or the physical netlist smaller than a target area parameter; The amplification timing constraint is obtained based on the optimal clock period.

3. The method according to claim 2, characterized in that The determining of the enlarged adjustment interval of the clock cycle in the original timing constraint includes: Based on the original timing constraints, determining an original area parameter; Determine the i-th magnification ratio, where i is a positive integer; Based on the i-th amplification ratio, amplify the clock period in the original timing constraint to obtain an i-th amplified timing constraint; Determining an i-th area parameter based on the i-th amplification timing constraint; Determining an i-th area parameter decrease value based on at least one of the original area parameter and the i-th area parameter; When the i-th area parameter decrease value does not satisfy the first condition, set i=i+1, and restart the step of determining the i-th amplification ratio until the i-th area parameter decrease value satisfies the first condition, and determine the i-th amplification ratio as the upper limit of the amplification adjustment range of the clock cycle.

4. The method according to claim 3, characterized in that The step of determining the i-th area parameter decrease value based on at least one of the original area parameter and the i-th area parameter comprises: When i is 1, based on the original area parameter and the first area parameter, a first area parameter reduction value is determined; When i is greater than 1, determining the i-th area parameter decrease value based on the i-th area parameter and the i-1-th area parameter; The i-1th area parameter is determined based on the i-1th amplification timing constraint corresponding to the i-1th amplification ratio.

5. The method according to claim 3, characterized in that: The determining of the original area parameter based on the original timing constraint includes: Based on the original timing constraints, executing a first logic synthesis process and the physical synthesis process on the hardware description file to obtain the original area parameter; The determining the i-th area parameter based on the i-th amplification timing constraint includes: Based on the i-th amplification timing constraint, the first logic synthesis process and the physical synthesis process are executed to obtain the i-th area parameter.

6. The method according to claim 5, characterized in that The first logic synthesis process includes an optimization process, and the optimization process is used to adjust the estimated area parameter corresponding to the logic netlist based on the timing constraint.

7. The method according to claim 3, characterized in that The method further comprises: Acquiring a first amplification ratio; and determining a lower limit of the amplification adjustment interval of the clock cycle based on the first amplification ratio.

8. The method according to claim 3, characterized in that The first condition includes at least one of the following: the i-th area parameter decrease value is less than a first threshold; the i-th area parameter decrease value is equal to 0.

9. The method according to any one of claims 2 to 8, characterized in that: The determining the optimal clock cycle from the amplification adjustment interval of the clock cycle includes: Determining a first clock cycle based on a lower limit of the amplification adjustment interval of the clock cycle; Determine a first enlarged timing constraint based on the first clock cycle and the original timing constraint; and obtain a first area parameter based on the first enlarged timing constraint; Determining a j-th clock cycle based on the amplification adjustment interval of the clock cycle, where j is a positive integer greater than 1; Based on the jth clock cycle and the original timing constraint, determining a jth amplification timing constraint; and based on the jth amplification timing constraint, obtaining a jth area parameter; Determining a jth area parameter decrease value based on at least one of the first area parameter and the jth area parameter; When the j-th area parameter decrease value does not satisfy the second condition, set j=j+1, and start again from the step of determining the j-th clock cycle based on the amplification adjustment interval of the clock cycle until the j-th area parameter decrease value satisfies the second condition, and determine that the j-th clock cycle is the optimal clock cycle.

10. The method according to claim 9, characterized in that The obtaining of a first area parameter based on the first amplification timing constraint includes: Based on the first amplification timing constraint, executing a second logic synthesis process and the physical synthesis process on the hardware description file to obtain the first area parameter; Based on the j-th amplification timing constraint, a j-th area parameter is obtained, including: Based on the j-th amplification timing constraint, the second logic synthesis process and the physical synthesis process are executed on the hardware description file to obtain the j-th area parameter.

11. The method according to claim 9, characterized in that Determining a jth area parameter decrease value based on at least one of the first area parameter and the jth area parameter comprises: When j is 2, based on the first area parameter and the second area parameter, a second area parameter decrease value is determined; When j is greater than 2, determining the jth area parameter decrease value based on the jth area parameter and the j-1th area parameter; The j-1th area parameter is determined based on the j-1th amplification timing constraint.

12. The method according to claim 9, characterized in that The second condition includes at least one of the following: the j-th area parameter decrease value is less than a second threshold; the j-th area parameter decrease value is equal to 0.

13. The method according to any one of claims 1 to 8, characterized in that: The step of performing a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist includes: Based on the amplified timing constraint, executing a second logic synthesis process on the hardware description file to obtain the logic netlist; The second logic synthesis flow does not include an optimization process, and the optimization process is used to adjust the estimated area parameters corresponding to the logic netlist based on timing constraints.

14. A comprehensive device for optimizing chip area, characterized in that: The device comprises: An acquisition module, used to acquire original timing constraints and hardware description files, wherein the hardware description files are used to describe the functions and structures of chip circuits; an amplification module, used for amplifying the clock cycle in the original timing constraint to obtain an amplified timing constraint; A logic synthesis module, used to execute a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit; A physical synthesis module is used to execute a physical synthesis process based on the logic netlist and the original timing constraints to obtain a physical netlist, wherein the physical netlist is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

15. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the comprehensive method for optimizing chip area according to any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the comprehensive method for optimizing chip area according to any one of claims 1 to 13.

Images