Construction method and system of high-speed differential signal transmission model

Abstract

The invention relates to the technical field of electronic circuits, in particular to a construction method and system of a high-speed differential signal transmission model. The method comprises the following steps: acquiring design data of the printed circuit board, and extracting differential signal line data; constructing a high-speed differential signal transmission model according to the differential signal line data; performing signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; identifying a crosstalk source position based on the high-speed differential signal transmission data to obtain a crosstalk source coordinate; detecting via hole dislocation based on the crosstalk source coordinates to obtain via hole dislocation data, and evaluating a heat accumulation degree based on the via hole dislocation data; identifying an electrical fault area of the circuit board based on the heat accumulation degree; and extracting stack structure information according to the printed circuit board design data. Based on the electronic circuit technology, the precision and reliability of the high-speed differential signal transmission model are improved, and the signal transmission quality and the electrical fault detection rate are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly relates to a method and system for constructing a high-speed differential signal transmission model. Background Art

[0002] A printed circuit board (PCB) includes circuit design and wiring technologies, involving multi-layer wiring, differential signal routing, impedance control, routing length matching, wiring topology, etc., which are used to ensure the transmission quality and synchronization of high-speed signals. In the modeling process of traditional high-speed differential signal transmission models, the physical structure characteristics (such as trace width, line spacing, via structure, reference layer change, etc.) in the signal transmission path are not comprehensively considered, and it is easy to ignore the fine extraction of parasitic parameters on the critical path of high-speed differential signals, resulting in low model accuracy; when dealing with complex electromagnetic coupling problems such as time-domain reflection, frequency-domain loss, and crosstalk effect in high-speed signals, idealized assumptions are often used, making it difficult to truly reflect the transmission behavior of differential signals in actual multi-layer PCB boards or high-speed interconnect structures; the model construction process highly depends on manual operations and expert experience, lacks a unified automated modeling process, has low efficiency, and is easily interfered by human factors; there is a lack of an adaptive evaluation mechanism for model accuracy, making it difficult to flexibly adjust parameters or correct model errors for different application scenarios, thus restricting its popularization and application in high-bandwidth, high-rate, and high-density interconnect designs. Summary of the Invention

[0003] Based on this, it is necessary for the present invention to provide a method and system for constructing a high-speed differential signal transmission model to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for constructing a high-speed differential signal transmission model includes the following steps: Step S1: Obtain printed circuit board design data, and extract differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; Step S2: Identify the positions of crosstalk sources based on the high-speed differential signal transmission data to obtain crosstalk source coordinates; detect via misalignment based on the crosstalk source coordinates to obtain via misalignment data, and evaluate the degree of heat accumulation based on the via misalignment data; identify the electrical fault areas of the circuit board based on the degree of heat accumulation; Step S3: Extract stack-up structure information according to the printed circuit board design data; perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; optimize the pad layout according to the interlayer delamination data; Step S4: Reconstruct the signal routing according to the electrical fault areas of the circuit board; perform differential equal-length compensation on the pad layout according to the signal routing to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0005] The present invention constructs an automated modeling and optimization method for high-speed differential signal transmission scenarios, which can effectively improve the modeling accuracy of differential signals, the authenticity of transmission simulation, and the fault recognition ability. In the modeling stage, differential signal line information is directly extracted based on printed circuit board design data, and physical structure features such as trace width, line spacing, via structure, and reference layer change are integrated, enabling the high-speed differential signal transmission model to comprehensively reflect the actual wiring structure, improving the accuracy of parasitic parameter extraction and the integrity of transmission path modeling. In the signal simulation stage, by simulating signal transmission on the model, differential signal behavior data under actual operating conditions is obtained, providing high-precision input for subsequent crosstalk identification and avoiding errors caused by overly idealized assumptions in traditional models. Combining the crosstalk source coordinates to detect via misalignment, and then calculating the degree of heat accumulation based on the current path perturbation in the misaligned area, makes the identification of electrical fault areas more targeted and structurally relevant, solving the problem of incomplete manual judgment. By further extracting stack-up structure information to achieve interlayer delamination detection, the integrity of the internal structure can be refined, and based on this, the pad layout can be dynamically optimized to effectively avoid the hidden impact of structural failure points on signal connection. Finally, through signal routing reconstruction guided by the fault area and start point offset compensation control, the differential signal path is made more balanced, significantly improving the peer-to-peer transmission effect and synchronization of signals, and feeding back the compensation data to the high-speed differential signal transmission model to achieve adaptive optimization and update. The overall process integrates three types of data features: structure perception, transmission perception, and fault perception, breaking the limitation of the traditional modeling process dominated by human experience and lacking fine structural parameter input, and realizing the full-process automated closed-loop from the construction to the optimization of the high-speed differential signal transmission model, improving the accuracy, reliability, and application promotion efficiency of the model.

[0006] Preferably, this specification also provides a construction system based on the high-speed differential signal transmission model for executing the construction method of the high-speed differential signal transmission model as described above. The construction system based on the high-speed differential signal transmission model includes: A signal transmission simulation module, configured to obtain printed circuit board design data and extract differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; An electrical fault identification module, configured to identify the position of the crosstalk source based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detect via misalignment based on the crosstalk source coordinates to obtain via misalignment data, and evaluate the degree of heat accumulation based on the via misalignment data; identify the electrical fault area of the circuit board based on the degree of heat accumulation; The pad layout optimization module is used to extract the stack structure information according to the printed circuit board design data; perform interlayer peeling detection based on the stack structure information to obtain interlayer peeling data; optimize the pad layout according to the interlayer peeling data; The differential equal - length compensation module is used to reconstruct the signal routing according to the electrical fault area of the circuit board; perform differential equal - length compensation on the pad layout according to the signal routing to obtain equal - length compensation data, and upload it to the high - speed differential signal transmission model to generate an optimized model.

[0007] The construction system of the high - speed differential signal transmission model of the present invention can implement any construction method of the high - speed differential signal transmission model of the present invention. It is used as a medium for coordinating the operations and signal transmissions between various modules to complete the construction method of the high - speed differential signal transmission model. The internal modules of the system cooperate with each other, improving the accuracy and reliability of the high - speed differential signal transmission model, and significantly enhancing the signal transmission quality and the electrical fault detection rate. Brief Description of the Drawings

[0008] By reading the detailed description of the non - restrictive embodiments with reference to the following drawings, other features, objects, and advantages of the present invention will become more obvious: Figure 1 It is a schematic flow chart of the steps of a construction method of a high - speed differential signal transmission model of the present invention; Figure 2 It is a detailed schematic flow chart of step S1 in the present invention; Figure 3 It is a detailed schematic flow chart of step S16 in the present invention; The realization of the purpose of the present invention, functional characteristics, and advantages will be further described with reference to the embodiments and the drawings. Detailed Embodiments

[0009] The technical method of the present invention patent will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0010] In addition, the drawings are only schematic diagrams of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, so the repeated description of them will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0011] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0012] To achieve the above object, please refer to Figures 1 to 3 , the present invention provides a method for constructing a high-speed differential signal transmission model, and the method includes the following steps: Step S1: Obtain printed circuit board design data and extract differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; In this embodiment, all design data is obtained from the PCB design file. The design data can be extracted by importing Gerber files or IPC-2581 file formats. Use design software (such as Allegro PCB Designer, KiCad or OrCAD) to read these files and extract the differential signal line data therein. The extraction of the differential signal line data includes identifying the two signal lines of the differential signal pair. According to the definition of the differential signal pair, parameters such as the spacing, width, hierarchical structure, and trace length between these two lines need to be recorded in detail. To accurately extract this data, special attention is paid to the line spacing and line width, and the current impedance test method is used to verify whether the signal lines meet the design standards. The parameters of the line spacing and line width are set according to the IPC-2221 standard, the line width is 0.25 mm, and the spacing is 0.2 mm. At this time, the geometric and electrical parameters of all differential signal lines have been extracted from the design file. Next, a high-speed differential signal transmission model is constructed according to the extracted differential signal line data. This process uses transmission line theory (such as microstrip line theory) and uses the dielectric constant of the PCB material and the signal frequency to calculate the impedance characteristics, delay, and loss of signal transmission. For differential signals, first, the characteristic impedance of each signal line needs to be calculated. Generally, the differential impedance is set to 100 Ω, and using the formula Z = Calculate the impedance value using (where L is the inductance and C is the capacitance), and L and C can be calculated from the geometric parameters of the transmission line. Use transmission line simulation software, such as Ansys HFSS or Keysight ADS, to simulate the constructed transmission model and analyze the signal propagation delay, signal attenuation, and its performance within the frequency range. During the simulation, set the simulation frequency range from 1 MHz to 10 GHz to cover common high-speed signal frequency bands and evaluate the transmission characteristics at different frequencies. Through the high-speed differential signal transmission model, obtain the signal propagation data, including information such as signal delay, amplitude loss, and phase change, which will provide the basic data for the subsequent identification of crosstalk sources and electrical fault detection.

[0013] Step S2: Identify the crosstalk source location based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detect the via misalignment based on the crosstalk source coordinates to obtain the via misalignment data, and evaluate the degree of thermal accumulation based on the via misalignment data; identify the electrical fault area of the circuit board based on the degree of thermal accumulation; In this embodiment, a spectrum analysis tool (such as Keysight VNA or Ansys HFSS) is used to analyze the signal data, and the crosstalk amplitude of each signal is calculated. The threshold of the crosstalk amplitude is set to -20 dB. If the crosstalk amplitude of a certain signal pair exceeds this threshold, then this signal pair is determined as a potential crosstalk source. At this time, the position of the crosstalk source needs to be identified through the specific coordinates of the signal path. The export function in the PCB design software (such as Allegro or KiCad) is used to extract the path coordinate information of the differential pair, and the specific position of the crosstalk source is marked. After identifying the position of the crosstalk source, the detection of via misalignment is carried out. By extracting via data, the PCB is inspected using an X-ray scanning device to obtain the image data of the vias, and the image processing software (such as MATLAB or OpenCV) is used to process the via images to detect whether there is misalignment of the vias. The standard for via misalignment is set that an offset greater than 0.1 mm is considered an offset. If the via offset exceeds this standard, it is recorded as a misaligned via. According to the via misalignment data, the degree of heat accumulation is evaluated. By setting up a heat conduction simulation model, finite element analysis software (such as ANSYS or COMSOL) is used for thermal stress analysis. The initial heat source temperature is set to 70 °C, and the via misalignment data is used as input to calculate the temperature distribution in the via area. The diffusion process of heat in the PCB is simulated through the heat conduction equation to determine the heat concentration area. The degree of heat accumulation is evaluated by the temperature change in the area around each via. The temperature change threshold is set to 5 °C. If the temperature change exceeds this threshold, it is considered that there is a risk of heat accumulation in this area. Based on the heat accumulation degree data, the electrical fault area of the circuit board is identified. By evaluating the electrical performance of the heat accumulation area and combining the influence of heat, an electrical simulation tool (such as CST Studio) is used to further analyze the electrical fault area of the circuit. The identification standard for the electrical fault area is electrical failure or unstable signal transmission, and it is calibrated in combination with the simulation results to determine the position of the fault area.

[0014] Step S3: Extract the stack-up structure information according to the printed circuit board design data; perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; optimize the pad layout according to the interlayer delamination data; In this embodiment, first, the stack-up structure information is extracted from the PCB design file. The number of layers, the material type and thickness of each layer are obtained through Gerber files or IPC-2581 standard files. The standard stack-up structure is set to 8 layers, the material is selected as FR4, and the interlayer dielectric constant is 4.2. By parsing the layer information in the design file, the thickness and material properties of each layer are extracted, and the distance between layers and material types are recorded. According to the stack-up structure information, interlayer delamination detection is performed. The interlayer delamination detection is carried out by an X-ray CT scanner to obtain the cross-sectional images of each layer and analyze the bonding situation between layers. If the bonding layer of a certain layer is broken or separated, and the delamination standard is set as more than 10% of the layer area showing delamination, it is considered that there is interlayer delamination in this area. Image processing software (such as MATLAB) is used to analyze the X-ray images, calculate the area and position of the delamination area, and obtain the interlayer delamination data. Based on the interlayer delamination data, the pad layout is optimized. The goal of pad layout optimization is to ensure that the pad area avoids overlapping with the delamination area. By modifying the size and position of the pads and adjusting the relative position of the pads and signal lines, problems such as stress concentration or poor conductivity are avoided. The pad size is set according to the standard IPC-2221, the pad diameter is selected as 1 mm, and the margin is 0.5 mm. The PCB design tool (such as Allegro or KiCad) is used to adjust the pad layout and regenerate the optimized design file.

[0015] Step S4: Reconstruct the signal routing according to the electrical fault area of the circuit board; perform differential equal-length compensation on the pad layout according to the signal routing to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0016] In this embodiment, according to the signal path planning algorithm, the signal lines are redesigned using a routing tool (such as Allegro PCB Designer or KiCad) to avoid the fault area. During the reconstruction process, it is necessary to ensure the impedance matching of the signal lines. The differential signal line impedance is set to 100 Ω, and the same line width and spacing are adopted (for example, the line width is 0.25 mm and the spacing is 0.2 mm) to ensure stable signal transmission. Differential equal-length compensation is performed on the pad layout according to the signal routing. The compensation step adjusts the length of the signal lines by comparing the length differences of the differential pair signal lines to ensure that the lengths of the two signal lines are the same. Specifically, if the length difference between the two signal lines is 5 mm, a 5-mm extension part is added to the shorter signal line to ensure that the lengths of the two signal lines are exactly equal. The compensation data is verified through a simulation tool (such as Ansys HFSS) to ensure that the compensated signal lines can achieve the best impedance matching and transmission efficiency.

[0017] Preferably, step S1 is specifically: Step S11: Obtain the printed circuit board design data and extract the differential signal line data; In this embodiment, the design data of the printed circuit board (PCB) is imported. This data is usually provided in Gerber file format or IPC-2581 format and contains all the design information of the circuit board, including signal line layout, via positions, layer stack structure, etc. Use PCB design software (such as Allegro PCB Designer, KiCad or OrCAD) to read the design file to ensure that all necessary data can be extracted. The core task of extracting differential signal line data is to identify and extract all differential pair signal lines. These differential pairs consist of a pair of signal lines, usually located on the same layer, maintaining a fixed spacing from each other. Specifically, search for all line pairs defined as differential signals in the design file and record the geometric characteristics of each line, such as line width, spacing, and routing path. For each signal line, the line width and spacing information need to be extracted according to the standard PCB design requirements (such as IPC-2221). If the line width is 0.25 mm and the spacing of the differential pair is 0.2 mm, these parameters need to be recorded one by one. In addition, the layer information where the signal line is located needs to be extracted, usually a two-layer or multi-layer structure.

[0018] Step S12: Restore the signal propagation path based on the differential signal line data; In this embodiment, based on the extracted differential signal line data, the signal propagation path needs to be restored first. To this end, first map the data of the differential signal lines to the actual layout of the PCB to determine the specific propagation path of the signal from the source point to the target point. Use signal integrity analysis tools (such as Ansys HFSS, Keysight ADS or CST Studio) to simulate the signal propagation. Input the geometric parameters of the differential signal lines, including line width, spacing, signal frequency, etc., and combine the dielectric constant, conductivity of the PCB material and the signal frequency to perform the simulation of the signal propagation path. The simulation tool will calculate the path of the signal propagating from the starting point along the differential signal lines to the target point, and consider factors such as the electrical characteristics between different dielectric layers, signal delay, loss, etc. During this process, special attention needs to be paid to issues such as the electrical length, propagation speed, and signal reflection of each signal line to ensure the accuracy of the signal propagation path.

[0019] Step S13: Identify the impedance mutation regions according to the signal propagation path; Adjust the differential signal line spacing based on the impedance mutation regions; In this embodiment, impedance mutations usually occur where the geometric structure of the signal line changes, such as at via locations, where the width of the signal line changes, or in the transition region between different material layers. To identify these mutation regions, it is necessary to analyze the reflection coefficient (S11) and transmission loss of the signal in combination with the simulation data. The reflection coefficient threshold is set to -10 dB. When the reflection coefficient is higher than this threshold, it indicates that there is a problem with the impedance matching of the signal, and thus there is an impedance mutation region. By accurately measuring the impedance value of the signal line, the region with obvious impedance change is found. After identifying these regions, it is necessary to adjust the spacing of the differential signal lines to restore impedance matching. The adjustment of the differential signal line spacing is based on the standard impedance value, and the target impedance is usually set to 100 Ω. According to the impedance mutation situation in different regions, the spacing of the signal lines is adjusted to ensure that the impedance of the signal lines remains stable within the mutation region. Usually, the spacing adjustment range is from 0.1 mm to 0.3 mm to meet the target impedance requirements.

[0020] Step S14: Identify and calculate the trace delay based on the signal propagation path; adjust the length of the differential signal lines based on the trace delay; In this embodiment, the trace delay refers to the propagation time of the signal from the source point to the target point, which is usually determined by the signal propagation speed and the length of the signal line. Through simulation tools (such as Ansys HFSS or Keysight ADS), a detailed analysis of the signal propagation path is carried out to obtain the propagation delay of each signal line. The formula for calculating the delay is: Delay = Trace Length / Signal Propagation Speed, where the signal propagation speed is related to the dielectric constant of the PCB and is usually calculated by the formula: ; where is the speed of light, is the dielectric constant. According to the simulation results, the propagation delay of each signal line is calculated, and the delay time of each signal line is recorded. To ensure synchronous signal transmission, especially for high-speed differential signals, the delay of the signal pair should be kept as consistent as possible. Therefore, for each differential signal line, the length of the signal line is appropriately adjusted according to the actually measured delay. If the delay difference between the two signal lines exceeds 5 ns, it is necessary to adjust the length of one of the signal lines to ensure the delay matching of the differential signal pair. When adjusting the length of the signal line, it is necessary to ensure that the impedance of the signal line remains stable and is not affected. The length adjustment is usually achieved by extending or contracting the path of a certain signal line, and the standard range of length adjustment is usually ±10 mm. During the adjustment process, the impedance of each signal line needs to be carefully monitored to avoid affecting the signal quality.

[0021] Step S15: Construct a high-speed differential signal transmission model based on the differential signal line spacing and the differential signal line length; In this embodiment, geometric parameters of each group of differential pair signal lines are extracted based on the actual wiring data in the printed circuit board, including the line width of each signal line, the line spacing between differential pairs, the trace length, and the PCB layer where the wiring is located. The electrical parameters of the base material medium used in this PCB are collected, including basic material properties such as dielectric constant, loss factor, and conductor resistivity. According to the extracted structural parameters of a line width of 0.25 mm and a line spacing of 0.2 mm, and referring to the design constraint of the standard differential impedance control target of 100 Ω, each group of differential pairs in the transmission path is parametrically modeled in the structural modeling tool. During the model construction process, the simulation analysis tool Ansys HFSS based on the finite element method in the frequency domain is selected, and the dielectric constant of the PCB board is defined as 4.5 in the environment settings. At the same time, the boundary conditions of the model are clearly set, such as the reference layer definition, port excitation type, frequency scan range, etc. In the model, the relative position relationship between the transmission line and the reference ground layer is constructed layer by layer according to the PCB stack structure to ensure that the electric field boundary is reasonably closed. An excitation signal is applied at the input end of the transmission path, and the working frequency range is set to cover the frequency bandwidth required for the rising time of the transmission signal. For example, the working frequency is set in the range of 5 GHz to 20 GHz. The electromagnetic field simulation calculation is run in the model to extract the transmission parameters of each differential signal path at the corresponding frequency, including key indicators such as differential mode impedance, common mode impedance, delay characteristics, insertion loss, and phase change. At the same time, the coupling strength between wirings and the crosstalk risk are evaluated; to further analyze the influence of the multi-layer structure on the signal quality, it is also necessary to accurately describe the thickness distance between each signal layer and its upper and lower reference grounds in the model, and consider the inductance effect of the via section and the impedance change of the dielectric transition band in the interlayer conduction structure modeling to ensure that the model still has a true reflection ability at high frequencies. Finally, the complete transmission parameter data of this group of differential pairs in the target frequency band is output as the basic data source for subsequent differential pair wiring optimization and timing control.

[0022] Step S16: Perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data.

[0023] In this embodiment, a simulation software (such as Ansys HFSS, Keysight ADS, CST Studio) is used to simulate the signal transmission process. Information such as the frequency, amplitude, and signal source of the differential signal is input, and the signal transmission situation in the PCB is simulated. During the simulation, the frequency range is selected from 1 MHz to 10 GHz, covering common high-speed signal frequency bands. The simulation results will include information such as signal propagation delay, signal amplitude attenuation, phase change, and crosstalk. Various electrical parameters during the signal transmission process are calculated through the simulation tool to obtain signal transmission data. These data include impedance values, signal attenuation rates, delay times, etc. of each differential signal pair at different frequencies, which are used to evaluate and optimize the signal transmission characteristics and provide a basis for subsequent design optimization.

[0024] Preferably, step S16 is specifically as follows: Step S161: Import the high-speed differential signal transmission model into the signal simulation software; In this embodiment, the high-speed differential signal transmission model needs to be imported into the simulation software, such as Ansys HFSS or Keysight ADS, etc. This process first requires associating the existing PCB design data with the electromagnetic simulation model (including differential signal lines, impedance characteristics, routing paths, etc.) and importing them into the simulation environment. During the import process, confirm the compatibility between the design file format and the simulation software to ensure that the hierarchical information, routing paths, and electrical characteristics in the design file are correctly identified and loaded. After the import, conduct necessary checks to ensure that the electrical characteristics of all models, such as impedance values, signal source settings, and signal propagation paths, are correct.

[0025] Step S162: Set the signal frequency range to 100 MHz - 10 GHz, the signal amplitude range to 0.5 V - 3.3 V, and the signal waveform to a sine wave in the simulation software; In this embodiment, the signal frequency range needs to be set from 100 MHz to 10 GHz. Such a frequency range covers the working frequency bands of typical high-speed differential signals. The signal amplitude range is set from 0.5 V to 3.3 V, which can simulate the signal transmission characteristics at different voltage levels. The signal waveform is set to a sine wave, which is a common signal waveform and is used to simplify the spectral characteristic analysis of signals in high-speed signal simulation. When setting the frequency and amplitude, the specific values should be selected through experiments or design requirements to ensure that these parameters meet the actual design needs during the simulation process. After setting these parameters in the simulation software, a preliminary verification is required to confirm that the signal waveform, frequency, and amplitude meet the expectations.

[0026] Step S163: Set the differential impedance range to 80 Ω - 120 Ω and the single-ended impedance range to 40 Ω - 60 Ω in the simulation software; In this embodiment, the differential impedance in the simulation software is set to 80Ω to 120Ω, and the single - ended impedance is set to 40Ω to 60Ω. The differential impedance refers to the impedance between two signal lines, while the single - ended impedance is the impedance between each signal line and the ground. To ensure the complete transmission of signals, these impedance ranges need to be consistent with the physical design used in the actual circuit design. When setting, these impedance values are derived by analyzing physical parameters such as the trace width, spacing, and dielectric constant in the PCB layout. If it is found in the simulation that the actually measured impedance does not match the set value, then the spacing or width of the signal lines in the design needs to be adjusted until the simulated impedance is consistent with the set value.

[0027] Step S164: Set the signal source type as differential signal pair, the transmission line type as microstrip line, the signal transmission line length as 10mm - 300mm, and the signal line spacing range as 0.1mm - 1.0mm in the simulation software; In this embodiment, differential signal pairs are particularly important in high - speed signal transmission because they can effectively reduce crosstalk and signal interference. In this step, the signal transmission line length is set to 10mm to 300mm, and the signal line spacing range is set to 0.1mm to 1.0mm. The transmission line length directly affects the propagation delay and transmission characteristics of the signal, and the spacing of the signal lines has a direct impact on the differential impedance. Therefore, according to the signal frequency, design requirements, and other electrical characteristics, the length and spacing of the signal lines are reasonably selected. The setting of these parameters is based on the signal frequency, the high - speed characteristics of the signal, and the requirements of the circuit design to ensure the reliability of the simulation results.

[0028] Step S165: Run the signal transmission simulation program in the simulation software and output high - speed differential signal transmission data.

[0029] In this embodiment, the signal transmission simulation program in the simulation software starts to run, and a detailed electromagnetic field simulation is performed on the set differential signal lines through a parser. During this process, the transmission characteristics of the signal (such as delay, reflection, attenuation, etc.) are calculated according to the simulation model, and transmission data is output. The output data includes information such as the delay, crosstalk, voltage waveform, and reflection loss of each signal line. These data are crucial for subsequent signal optimization design. After the simulation is completed, it is necessary to analyze the output data to verify whether the signal transmission characteristics meet the design requirements and identify any potential signal problems, such as impedance mismatch, excessive reflection loss, etc.

[0030] Preferably, the specific method for identifying the crosstalk source position in step S2 is: Extract low - transmission - efficiency signal data based on the high - speed differential signal transmission data; In this embodiment, it is necessary to analyze the simulation results of high-speed differential signal transmission and extract the regions with low signal transmission efficiency. These regions usually exhibit excessive signal attenuation, uneven delay, or strong reflection. In the simulation data, the signal regions with low transmission efficiency are usually represented by the abnormal values of parameters such as signal transmission loss, reflection loss, and transmission delay. For example, the signal loss is higher than the set threshold (such as the loss exceeding -3 dB), or the signal delay deviates from the expected value by more than the specified standard (such as exceeding 5 ns). By analyzing these data, the corresponding low-efficiency transmission regions are extracted and further marked as low-transmission-efficiency signal data.

[0031] Based on the low-transmission-efficiency signal data, the low-transmission-efficiency printed circuit board is represented, and an image of the low-transmission-efficiency printed circuit board is acquired to obtain the low-transmission-efficiency printed circuit board image; In this embodiment, according to the analysis results of the signal transmission data, the design of the PCB is screened, the regions with low transmission efficiency are identified, and these regions are marked on the PCB design drawing. Then, a high-resolution camera or scanner (such as an optical microscope or a CT scanning device) is used to acquire images of these calibrated regions. The accuracy of image acquisition should ensure that the specific wire routing layout of the circuit board can be clearly displayed, and the specific width, spacing, and connected components of the wire routing can be distinguished. During the image acquisition process, it is necessary to select an appropriate magnification and focal length according to the size of the PCB and the distribution of the calibrated regions to ensure that the acquired images have sufficient clarity and details.

[0032] Based on the low-transmission-efficiency printed circuit board image, the wire routing path is identified; the wire spacing is calculated according to the wire routing path; In this embodiment, image processing is performed on the acquired circuit board image. Usually, image processing software (such as OpenCV or Matlab) is used for edge detection to identify the wire routing path in the circuit board. Through preprocessing methods such as grayscale conversion and binarization, the wire routing path becomes more obvious, facilitating subsequent analysis. After image processing, the path information of the wire is extracted through an algorithm, and the starting point and ending point of the wire routing are identified to complete the extraction of the wire routing path. Measurements are made on the identified wire routing path to calculate the minimum distance between the wires. The calculation of the wire spacing can be completed by measuring the distance between the paths. Usually, the vertical distance between two wires is measured using an image processing tool to calculate its minimum value. According to different design requirements and standards, a reasonable spacing threshold is set, such as 0.2 mm. The regions exceeding this threshold can be regarded as having too large or too small spacing, which in turn affects the signal transmission efficiency. At this time, the calculation result of the spacing needs to be compared with the design standard to determine whether there are design problems.

[0033] The wire routing angle is calculated according to the wire routing path, and the sharp turning region of the wire routing in the low-transmission-efficiency printed circuit board image is identified based on the wire routing angle; In this embodiment, based on the wiring path data in the image, the wiring angle of each signal line needs to be calculated. This can be achieved by identifying the corner points or turning points on the path and calculating the change in the path direction. Through angle calculation, areas with sharp turning angles are identified, such as areas where the angle is greater than 45°. Sharp turning angle areas of the wiring usually cause uneven signal transmission, so the identification of these areas is crucial for further analysis and optimization.

[0034] Identify the small wiring spacing areas in the sharp turning angle areas of the wiring according to the wiring spacing; In this embodiment, the sharp turning angle areas need to be further subdivided to identify the small wiring spacing areas within these areas. Small spacing areas generally refer to areas where the distance between two wirings is less than the design standard (such as less than 0.2 mm). This step can be achieved by detailed measurement of the wiring spacing within the sharp turning angle areas to identify areas with too small spacing. These small spacing areas are prone to signal interference and crosstalk, so special attention is required.

[0035] Perform electromagnetic field simulation based on the small wiring spacing areas to obtain electromagnetic field simulation data; In this embodiment, electromagnetic field simulation is performed on the identified small wiring spacing areas. Simulation software (such as Ansys HFSS or Keysight ADS) is used to simulate the distribution of the electromagnetic field in this area, usually based on the finite element analysis (FEA) or finite difference time domain (FDTD) method. The electromagnetic field simulation data includes parameters such as electric field strength, magnetic field distribution, and corresponding crosstalk and reflection. During the simulation process, factors such as signal frequency, impedance characteristics of the wiring, and dielectric materials are considered to generate the electromagnetic field distribution map of this area. The simulation accuracy and parameter selection need to meet the requirements of the actual circuit design to ensure the high accuracy of the simulation results.

[0036] Identify the electromagnetic field enhancement areas according to the electromagnetic field simulation data; In this embodiment, the electromagnetic field simulation results are analyzed to identify areas with higher electromagnetic field strength, and these areas are the electromagnetic field enhancement areas. Through post-processing of the simulation data, the electromagnetic field strength of each area is calculated, and areas where the electric field strength exceeds a certain threshold (such as 100 V / m) are marked as electromagnetic field enhancement areas. Electromagnetic field enhancement areas usually indicate positions with more serious signal interference and require further design optimization.

[0037] Map the electromagnetic field enhancement areas to the small wiring spacing areas to obtain the crosstalk source areas, and record them as crosstalk source coordinates.

[0038] In this embodiment, the electromagnetic field enhancement region is matched with the small trace pitch region. Through the spatial coordinate system, the electromagnetic field enhancement region is mapped to the corresponding small trace pitch region, so as to identify the region causing crosstalk. During the mapping process, based on the positional relationship on the coordinate axes, the overlapping part between the electromagnetic field enhancement region and the small trace pitch region is determined. These overlapping regions are the crosstalk source regions. Finally, the coordinates of the crosstalk source regions are recorded and these coordinate data are saved for subsequent optimization design and analysis.

[0039] Preferably, the degree of heat accumulation in step S2 is specifically: Extract the via coordinates based on the crosstalk source coordinates; In this embodiment, the via coordinates involved in signal interference are extracted through the coordinate data of the identified crosstalk source regions. These vias are usually located on the critical paths of the circuit board and cause crosstalk problems. Use the interlayer interconnection information in the PCB design file to check the positions of the vias. By calibrating the coordinate points of the vias one by one in the design drawing, the via regions related to the crosstalk source are identified, ensuring that the extraction process is carried out according to the design standards (such as the minimum via pitch and diameter) to avoid omission or misidentification.

[0040] Perform X-ray scanning according to the via coordinates to obtain via X-ray scanning data; reconstruct the 3D image of the via based on the via X-ray scanning data; In this embodiment, first, locate these vias in the circuit board according to the extracted via coordinates. Use X-ray imaging technology for scanning, and the scanning parameters should be selected according to the via size, material, and circuit board thickness. For example, the energy range of the X-ray can be set from 50 keV to 100 keV to ensure that it can penetrate the circuit board and accurately detect the via structure. The image data obtained by X-ray scanning can clearly show the internal structure, shape of the via, and its connection with the circuit board. The scanning accuracy should reach 0.01 mm to ensure that the size and position of the via can be accurately recorded. Integrate the multi-angle X-ray data obtained by scanning, and use computer tomography (CT) algorithms or stereoscopic reconstruction techniques for data processing to generate a 3D image of the via. During the reconstruction process, combine information such as the geometric features of the via and the X-ray transmittance to obtain a precise 3D structure model of the via. The accuracy of this process should be controlled within 0.05 mm to ensure the reliability of the 3D image.

[0041] Divide the via penetration amount based on the via 3D image to obtain local penetrated via data and global penetrated via data; In this embodiment, according to the three-dimensional structural image of the via hole, the via hole is divided into different regions (such as local regions and global regions). The local penetration amount usually refers to the penetration depth of the via hole within a small range and is affected by local material properties; the global penetration amount represents the overall penetration performance of the via hole. During the processing, an algorithm (such as an image segmentation algorithm) is used to divide each region of the via hole and calculate the penetration depth of each region. For example, the local via hole penetration data can be obtained by measuring the relationship between the diameter and depth of a certain part of the via hole, while the global via hole penetration data is calculated based on the overall size and depth of the via hole.

[0042] Calculate the lateral position offset based on the local via hole penetration data; In this embodiment, according to the local via hole penetration data, calculate the lateral offset of the via hole in the PCB. The lateral offset reflects the degree of deviation of the via hole from the design center line and is usually determined by comparing the difference between the actual position and the theoretical design position of the via hole. The parameters involved in this calculation include the actual coordinates, design coordinates of the via hole, and the allowable deviation range (such as 0.1 mm). The calculation formula for the lateral offset can use the Euclidean distance formula for accurate calculation.

[0043] Calculate the depth misalignment offset based on the global via hole penetration data; In this embodiment, according to the global via hole penetration data, calculate the depth offset of the via hole. The depth misalignment offset represents the difference between the actual depth and the design depth of the via hole and is usually calculated by comparing the difference between the actual position and the design position of the via hole between different layers. This calculation needs to consider the manufacturing tolerance and thermal expansion effect of the via hole, and the calculation result of the depth offset should be compared with the tolerance standard in the design specification (for example, 0.2 mm) to determine whether it exceeds the allowable error range.

[0044] Integrate the lateral position offset and the depth misalignment offset to obtain the via hole misalignment data; In this embodiment, integrate the lateral position offset and the depth misalignment offset to obtain the comprehensive via hole misalignment data. This data represents the degree of deviation of the via hole in three dimensions and is usually obtained by taking the square root of the sum of the squares of the lateral offset and the depth offset to get the comprehensive deviation value of the via hole misalignment. This comprehensive deviation value should be compared with the allowable deviation standard in the design. For example, the comprehensive deviation of the via hole misalignment should not exceed 0.3 mm.

[0045] Determine the thermal expansion coefficient of the via hole material based on the via hole misalignment data; perform a thermal conduction simulation of the circuit board according to the thermal expansion coefficient of the via hole material to obtain the circuit board thermal conduction data; In this embodiment, according to the via hole misalignment data, calculate the thermal expansion coefficient of the via hole material using the thermal expansion theory. According to the calculation formula of the thermal expansion coefficient: ; where represents the length change, represents the coefficient of thermal expansion, represents the original length, represents the temperature change. By actually measuring the relationship between the via misalignment data and the temperature change, the coefficient of thermal expansion of the via material is inversely calculated. This process requires controlling the range of temperature change. For example, the temperature change can be set to increase from 25°C to 125°C to ensure the accuracy of the results. Use a heat conduction simulation software (such as ANSYS or COMSOL) to perform the heat conduction simulation of the circuit board. During the simulation, parameters such as the geometric structure of the circuit board, material properties (including the coefficient of thermal expansion of the via material), and temperature gradient need to be input. The simulation results will show the heat distribution of the circuit board under temperature change conditions and output the corresponding heat conduction data, such as the temperature change in a specific area. During the simulation process, the temperature gradient can be set from 25°C to 125°C, and the heat source position and heat flux density can be adjusted according to the actual application conditions.

[0046] Perform a thermal stress detection on the via misalignment data based on the circuit board heat conduction data to obtain the via thermal stress data; evaluate the degree of via tearing based on the via thermal stress data; In this embodiment, first, according to the heat conduction data of the circuit board, calculate the thermal stress in the area where the via is located. Thermal stress is usually generated by the uneven expansion of materials caused by temperature change. When calculating, combine the geometric shape of the via, material properties, and coefficient of thermal expansion, and use the thermal stress formula ; for calculation, where is the thermal stress, is the elastic modulus of the material, is the coefficient of thermal expansion, is the temperature change amount. Through this formula, the thermal stress distribution data of the via can be obtained. The degree of via tearing is usually evaluated by calculating the area where the thermal stress exceeds a certain threshold. If the thermal stress exceeds the set tearing threshold (such as 50 MPa), it is considered that there is a risk of tearing for this via. This evaluation process involves the thermal stress distribution map and the setting of the tearing threshold, which need to be set according to the properties and standards of the via material.

[0047] Identify the heat accumulation area according to the degree of via tearing; evaluate the degree of heat accumulation based on the heat accumulation area.

[0048] In this embodiment, high-temperature regions around vias are identified through thermal stress data. These regions typically exhibit relatively high thermal stress values, leading to damage to the via structure. During this process, a thermal stress threshold, such as a thermal stress value exceeding 60 MPa, is set as the calibration standard. Then, these regions are identified and marked as heat accumulation regions. By analyzing the thermal stress distribution within these heat accumulation regions, the degree of thermal accumulation in this region is evaluated. The method for evaluating the degree of thermal accumulation is to perform a time integration of the thermal stress to obtain the total heat in this region, thereby reflecting the thermal load situation that this region has endured during long-term use and providing a basis for subsequent design optimization.

[0049] Preferably, step S2 for identifying the electrical fault region of the circuit board is specifically as follows: Evaluate the welding quality based on the degree of thermal accumulation to obtain welding data; In this embodiment, based on the thermal stress integral value within the heat accumulation region obtained in the previous step, an analysis of the long-term thermal energy change trend of the heat accumulation region is carried out. Combining parameters such as the spatial range, heat accumulation intensity, and temperature peak duration of each heat accumulation region, the thermal distribution characteristics of the welding region are extracted. By setting a thermal energy accumulation threshold, such as when the thermal stress time integral value reaches 1.2×10 6 Pa·s or more, the thermal load level of this region is calibrated. Compare the thermal load level with the welding process parameters. For example, the welding temperature is 260°C and the welding duration is 3 seconds. Calculate the heat capacity absorption capacity at this position and conduct a comparative analysis in combination with the thermophysical property parameters of the welding material, such as the thermal conductivity (unit: W / m·K) and thermal diffusivity (unit: mm² / s). Finally, determine the welding quality evaluation grade at this place. The quality grade is classified into three categories: overheating, insufficient heat, or uniform heat, and the welding data is output.

[0050] Statistically calculate the solder usage based on the welding data; calculate the solder accumulation volume based on the solder usage; determine the solder filling state based on the solder accumulation volume; evaluate the solder joint firmness based on the solder filling state; predict the solder joint detachment risk based on the solder joint firmness; In this embodiment, by performing a combined operation on the heat input power, duration, and welding range area of each welding point in the welding data, the flow range and solidification cross-sectional area of the solder after heating are estimated. Combining the initial density and distribution characteristics of the solder paste type, the actual mass of solder consumed at each solder joint is statistically calculated. For example, when using Sn63Pb37 solder with a density of 8.4 g / cm³, the volume of solder is calculated based on the solder joint area and the solder layer thickness (such as a thickness of 0.15 mm), and then the mass is calculated by combining with the density. Finally, the solder usage is output. When calculating the solder accumulation volume based on the solder usage, dividing the solder mass obtained in the previous stage by the solder density can obtain the accumulation volume of solder at each solder joint. Taking Sn63Pb37 solder as an example, with a density of 8.4 g / cm³, if the solder usage at a certain solder joint is 0.0126 g, the accumulation volume is 0.0015 cm³. Further confirm whether there are characteristics such as excessive accumulation, uniform distribution, or welding voids of the solder in combination with the geometric shape of the solder joint. Judge the filling state according to the ratio between the theoretical welding space size and the actual solder volume of each solder joint. If the ratio is between 0.9 and 1.1, it is determined as normal filling; if it is less than 0.9, it is determined as insufficient filling; if it is greater than 1.1, it is determined as excessive solder accumulation. The filling state data is recorded in the welding database, indicating the state values and corresponding geometric coordinates of each solder joint. Through a composite calculation combining the filling state and the solder joint area contact rate, the solder joint firmness is calibrated using a percentage scoring system with three weight indicators: filling ratio, contact area rate, and heat distribution consistency. For example, the filling ratio weight accounts for 50%, the area contact rate weight accounts for 30%, and the heat consistency weight accounts for 20%. Each indicator is scored according to the quantitative scoring standard and then weighted and synthesized to output the firmness score and classify and mark it. Using a stepped risk judgment standard, when the solder joint firmness score is lower than 60 points, it is calibrated as a high risk; when the score is between 60 and 75, it is calibrated as a medium risk; when the score is above 75, it is calibrated as a low risk. By extracting the positions of all high-risk solder joints, a solder joint detachment risk list is formed, along with the risk level, coordinates, and score details of each solder joint.

[0051] Extract the solder joint detachment positions according to the solder joint detachment risks; obtain the signal trace positions on the circuit board; map the signal trace positions to the solder coverage areas according to the solder joint detachment positions to obtain the solder coverage area data; In this embodiment, all the coordinates of high-risk solder joints are screened out from the solder joint detachment risk list as the solder joint detachment positions, and these coordinates will be used as the key input parameters in the subsequent mapping operation. The recognized wiring paths in the circuit board image recognition data are called, and the two-dimensional coordinate point set of the wiring vector path in the PCB board plan view is extracted. After coordinate conversion, the path data is unified into the same reference coordinate system as the solder joint coordinates to ensure the accuracy of subsequent matching. The shortest distance between the solder joint detachment coordinates and the signal wiring path is calculated, and 3 mm is set as the matching threshold range. If any line segment on a certain signal path is less than the threshold distance from the solder joint detachment coordinates, it is considered that the wiring is covered by the corresponding solder joint. These wiring areas are extracted to form a solder coverage area data set, and the start and end point coordinates of the path segment and the corresponding solder joint numbers are marked.

[0052] According to the solder coverage area data, a resistance conduction test is performed to obtain resistance conduction data; In this embodiment, for the solder coverage path segment, a multi-channel four-probe conduction test device is used to apply a fixed voltage (such as 1 V) to both ends of the aforementioned solder coverage area and measure the passing current, and the resistance value is calculated according to Ohm's law. The upper limit standard of the resistance value is set to 0.5 Ω. If the measured resistance value exceeds this upper limit, it is determined that the conduction is abnormal, and this path segment is recorded as an abnormal conduction segment, and the corresponding coordinates and the measured resistance value data are saved to form a resistance conduction data table.

[0053] Determine the electrical fault area of the circuit board according to the resistance conduction data.

[0054] In this embodiment, position clustering processing is performed on the abnormal conduction segments. If multiple abnormal segments are concentrated in a certain area and the area exceeds 100 mm², it is determined as an electrical fault area. The coordinates of this area are used to generate the minimum bounding rectangle through the boundary points of multiple abnormal path segments, and compared with the signal wiring diagram to determine the affected signal category and the position where signal distortion occurs. Finally, the spatial coordinates and area of the electrical fault area and the statistical data of abnormal resistance values are output.

[0055] Preferably, step S3 is specifically as follows: Step S31: Extract the stack structure information according to the printed circuit board design data; In this embodiment, the design layer number, thickness of each layer, dielectric material type, copper foil thickness, and specific positions of signal layers and ground layers for high-speed differential signal transmission of the PCB are obtained from the Gerber design file and the BOM (Bill of Materials) list. In the specific extraction operation, a CAD parsing tool is used to parse the structures of files such as.Drl,.GTL,.GBL, and.GTS in the Gerber file, identify the functional attributes of each layer (signal layer, ground layer, power layer, etc.), and record the thickness parameters, dielectric constant (for example, the dielectric constant of FR4 material is 4.5), loss factor (for example, tanδ = 0.02), and interlayer adhesive thickness (for example, 0.1 mm) of each layer in an XML structure. All structural information needs to be uniformly converted into a stack coordinate system in the Z-axis direction for subsequent processing paths and mechanical simulations.

[0056] Step S32: Determine the edge milling process based on the stack structure information; perform via edge milling simulation according to the edge milling process to obtain via edge milling data; In this embodiment, the stack thickness and material hardness data are read. According to the IPC-2221A standard, the edge milling method is specified for plates with different thicknesses and materials. For example, when the total thickness is less than 1.6 mm, a single high-speed milling method is used, and when the total thickness exceeds 2.4 mm, a multi-layer and multi-segment milling method is used. The edge milling tool selects a tungsten carbide milling cutter with a diameter of 0.8 mm, the spindle speed is set to 40000 rpm, and the feed rate is set to 1200 mm / min. A finite element cutting force simulation tool (such as Abaqus or ANSYS Mechanical) is used to perform local mesh division around the via (the element size does not exceed 0.01 mm), input the above parameters for cutting force path simulation, and extract the stress state distribution diagram of each layer, edge breakage morphology data, and local via wall deformation conditions. The output data format is uniformly a three-dimensional matrix form containing coordinates (x, y, z), maximum shear stress, and cutting heat source distribution as the via edge milling data.

[0057] Step S33: Screen via edge milling samples according to the via edge milling data, and irradiate the via edge milling samples with a high-energy electron beam to obtain high-energy electron beam irradiation data; capture diffraction patterns based on the high-energy electron beam irradiation data; identify crystal morphologies according to the diffraction patterns; determine grain deformation according to the crystal morphologies to obtain grain deformation data; evaluate the residual stress of edge milling based on the grain deformation data; In this embodiment, area samples with the peak shear stress exceeding 220 MPa are selected from the milling edge data and prepared into small samples with the size of 2 mm × 2 mm × PCB thickness. The cross-section of the sample is cut using FIB (Focused Ion Beam) technology and irradiated by a high-energy electron beam in TEM (Transmission Electron Microscope) mode. The beam current energy is set to 200 keV, the beam current density is controlled within 10 A / cm², the exposure time is controlled within 5 seconds, and the diffraction pattern is collected. The change in the crystal arrangement angle in the diffraction pattern is identified by means of Selected Area Electron Diffraction (SAED). If the lattice rotation is found to be greater than 2° and the change in the crystal plane spacing exceeds 0.05 Å, it is marked as grain deformation. The dislocation density inside the grain is recorded and converted into Mises equivalent stress (using Taylor factor M = 3.06). Finally, the residual stress value (unit: MPa) of each grain unit is output and bound to the coordinates to form grain deformation data and milling edge residual stress data.

[0058] Step S34: Perform lamination crack analysis on the lamination structure information based on the milling edge residual stress to obtain lamination crack data; In this embodiment, the residual stress data is used as the input boundary condition and imported into the three-dimensional lamination structure finite element model. The Cohesive Zone Modeling (bonded zone model) is defined for the interfaces between layers, and the shear strength threshold of each layer interface is set to 45 MPa, and the critical fracture energy is 0.25 N / mm. By calculating the stress action value of the residual stress on each layer bonding surface and comparing it with the interface strength threshold, the interface area with signs of shear failure or peeling is located. In the analysis output result, the three-dimensional position, failure mode (shear, tension, crushing), and interface number of each failed element are marked. The crack points are clustered and connected into a crack path using the Delaunay triangulation method to form a complete lamination crack data set.

[0059] Step S35: Predict the interlayer peeling risk based on the lamination crack data to obtain interlayer peeling data.

[0060] In this embodiment, the total crack length of the interfaces between layers is statistically calculated from the crack path data and the ratio is calculated with the total interface length of each layer. The peeling risk determination criterion is set: when the crack length ratio exceeds 30% and the crack depth exceeds 1 / 3 of the total layer thickness, it is marked as a high peeling risk. Each peeling area is output as peeling volume data with three-dimensional coordinate marks and includes the crack starting point, crack path direction, and surrounding material hardness comparison data, constituting the interlayer peeling data set.

[0061] Step S36: Optimize the pad layout according to the interlayer peeling data.

[0062] In this embodiment, the high-risk areas in the delamination dataset are overlaid with the wiring diagrams of the signal layers in the PCB design to identify the solder joints whose pad areas are located in the high-risk delamination areas. According to the IPC-7095 standard, for the transmission paths of high-speed differential signals, the pad pitch should be greater than 0.25 mm, and the signal turning angle should not be less than 135°. For the pads in the high-risk areas, the layout is reconstructed by offsetting them to the low-stress areas. The offset distance is set according to the crack gradient direction. For example, if the maximum shear stress direction of the gradient direction is the X-axis direction, then a Y-axis offset of 0.3 mm is made to avoid the delamination path. The newly added positions of the pads should meet the requirement that the consistency error of the original wiring length does not exceed ±5%. Finally, an updated pad layout file (in the format of ODB++ or IPC2581) is output for the symmetric and consistent processing of the high-speed differential signal paths.

[0063] Preferably, step S36 is specifically as follows: Step S361: Calculate the delamination depth based on the interlayer delamination data; calculate the delamination length based on the interlayer delamination data; calculate the interlayer delamination area based on the delamination depth and the delamination length; In this embodiment, the interlayer delamination data is obtained by performing layer-by-layer tomographic scanning on the PCB stack structure using an X-ray interlayer scanner (model YXLON FF35 CT). The image resolution is set to 5 μm, and the scanning depth is set to 2 mm. The scanned images are processed by an image processing algorithm for edge detection. The Sobel operator combined with the Canny edge extraction method is used to identify the starting and ending points of the interlayer delamination. The pixel distances measured in the image coordinate system are converted through the system calibration parameters (each pixel represents 5 μm) to obtain the actual physical dimensions of the delamination area. The calculation of the delamination depth is based on the vertical pixel difference of the Z-axis scan, combined with the layer thickness standard (the thickness of each dielectric layer is 0.1 mm), to calculate the physical thickness of the delamination section in the vertical direction. The delamination length is calculated based on the maximum boundary span of the delamination area in the XY plane. The contour tracking technique (using the findContours function in OpenCV) is used to extract the delamination contour, and the main axis of the contour is fitted (using the least squares ellipse fitting method) to extract its major axis length as the delamination length. Finally, the interlayer delamination area is calculated based on the product of the delamination length and the delamination depth. The calculation formula is: delamination area A = delamination length L × delamination depth D, where L and D are in millimeters. For example, in a certain stack area, the measured delamination length is 3.2 mm and the delamination depth is 0.1 mm, then the delamination area is 0.32 mm².

[0064] Step S362: Mark the interlayer delamination area based on the interlayer delamination area; perform risk classification based on the interlayer delamination area. If the interlayer delamination area is greater than or equal to 30% of the interlayer delamination area, a high-risk interlayer delamination area is obtained; if the interlayer delamination area is less than 30% of the interlayer delamination area, a low-risk interlayer delamination area is obtained. In this embodiment, the delamination area is marked by setting a fixed rasterized area. The entire PCB plane is rasterized in units of 10mm×10mm, and each grid cell is used as a delamination detection area. The coordinates of the delamination area are mapped to the grid coordinate system through the GIS spatial mapping method (using the RasterToPolygon tool in ArcPy), and the ratio of the cumulative delamination area in each grid to the total grid area is calculated. Based on the standard judgment threshold, if the ratio of the delamination area to the total area of the grid is greater than or equal to 30%, it is marked as a high-risk interlayer delamination area; if it is less than 30%, it is marked as a low-risk interlayer delamination area. For example, in a 10mm×10mm grid, the cumulative delamination area reaches 3.5mm², and the delamination area ratio of this area is 3.5%, which is determined as a low-risk area according to the threshold; while if the delamination area in a grid is 35mm² and the ratio is 35%, it is marked as a high-risk area.

[0065] Step S363: Adjust the pad size based on the low-risk interlayer delamination area to obtain pad size data; In this embodiment, the initial pad size is set to a diameter of 0.5mm according to the design standard. To reduce the reflection interference of electrical signals and improve signal integrity in the low-risk areas, the pad size is adjusted according to the minimum distance from the pad center to the edge of the delamination area in these areas. If the distance is greater than 2mm, the pad diameter is adjusted to 0.6mm; if it is between 1.5mm and 2mm, the pad size remains 0.5mm; if it is less than 1.5mm, the pad diameter is adjusted to 0.4mm. This adjustment operation is completed using the "Pad Stack Manager" module in the EDA tool Altium Designer. After batch reading the coordinates of the low-risk areas, the "pad template mapping function" is called to match and update the target pad size. The adjusted size data is exported as a CSV format file, and the fields include pad ID, coordinates, size before adjustment, size after adjustment, and the risk area level where it is located.

[0066] Step S364: Adjust the pad material based on the high-risk interlayer delamination area to obtain pad material data; In this embodiment, the initial pad material is copper (Cu), and the material conductivity is 5.8×10 7 S / m. According to the requirements of high-speed differential signal transmission for antioxidant properties and mechanical stress, a metal material with higher peel strength is used instead, such as nickel-gold alloy (ENIG), whose conductivity is 2.2×107 S / m, the anti-peeling strength is increased by about 35%. The high-risk pad numbers are identified by laser marking (the laser device model is Keyence ML-Z9510), and material replacement marks are made at the corresponding positions of the high-risk pads. Chemical plating process is used for material replacement. A nickel layer (with a thickness controlled at 5 μm) is applied on the surface of the original copper pad, and then a gold layer (with a thickness controlled at 0.05 μm) is applied. After each batch replacement, SEM (scanning electron microscope) is used for interface bonding detection to ensure that the boundary of the replacement area is clear, without voids and microcracks. The data of the replaced pad materials includes pad numbers, positions, original materials, new materials, and replacement thickness information, which are uniformly recorded in the structural material form and linked with the subsequent welding temperature parameters for control.

[0067] Step S365: Integrate the pad size data and the pad material data, and determine the optimized pad layout.

[0068] In this embodiment, a script tool (such as Python combined with Altium API) is used to merge the aforementioned pad size CSV and pad material data, and an inner join match is performed with the pad ID as the primary key to output an optimized pad layout list. The fields include: pad ID, X coordinate, Y coordinate, diameter, metal type, and risk level. The optimized pad layout file is exported in Gerber format, which complies with the IPC-2581 standard, and DRC (design rule check) verification is carried out to ensure that the adjusted pads do not conflict with the surrounding electrical structures such as traces and vias. After verification, the pad layout file is bound and imported into the differential pair routing module together with the differential signal routing scheme to complete the final layout of the high-speed differential signal path.

[0069] Preferably, step S4 is specifically: Step S41: Reconstruct the signal routing according to the electrical fault area of the circuit board; extract the differential signal line routing based on the signal routing; In this embodiment, based on the electrical fault detection results, the two-dimensional coordinate information of the fault area is loaded in the wiring design platform. The fault area is marked as an impassable area on the circuit diagram, and at the same time, wiring reconstruction rules are set: it is prohibited for any newly built signal path to pass through the space within 5 millimeters of the boundary of the fault area. Subsequently, in the wiring editing tool, manually or with the help of an automatic wiring plug-in, the existing differential signal lines are adjusted for obstacle avoidance wiring to ensure that the path length is controlled within the range of ±3% of the original wiring length, the wiring width is uniformly set to 5 mils, and it is not allowed to cross or overlap with other existing signal layers. After wiring is completed, all differential pair signal lines are renumbered through the signal network grouping function, and the path node coordinate sequence of each pair of signal lines is extracted to form routing data. When extracting the routing, the path nodes must be extracted strictly in the order of the physical layout, and the start and end points and corner point coordinates of each path segment are completely retained for subsequent spatial relationship analysis with the pad area.

[0070] Step S42: Calculate the pad pitch based on the pad layout; In this embodiment, the position coordinates of the centers of all pads are used as reference points for numbering, and the numbering is based on the logical network grouping order. Using the graphic analysis module in the wiring design tool, by calling the straight-line distance analysis function between coordinate points, the center distances between the pads at both ends of all differential pairs are analyzed in turn. The analysis results of the pitch of each pair of pads are marked with the actual physical length, and the unit is uniformly millimeters, and the precision is reserved to three decimal places. When measuring, it is also necessary to check whether the unit is consistent with the wiring drawing. If there is a scaling ratio, it needs to be converted according to the actual ratio. After measuring the pitches of all differential pads, a comparison table containing the pad pair numbers and pitch values is established as the structural basis for differential signal impact analysis.

[0071] Step S43: Identify the differential signal line impact area based on the routing of the differential signal lines to obtain differential signal line impact area data; In this embodiment, the routing coordinate sequence of the differential signal lines is compared with the pad positions, and each signal line path segment is extended and identified. A strip area is established along the routing of the signal line, and the width of this area is set to 0.5 millimeters. The pad numbers whose center coordinates fall into this strip area are selected. Each differential pair signal line needs to mark the influence ranges of its left line and right line respectively to form two independent strip coverage areas. During the identification process, the relative positions of each pad and the signal line path are recorded. If the center point is less than 0.25 millimeters away from the path line, it is determined to be affected by this signal line. Finally, all the pad numbers, path numbers, and start and end coordinate ranges within the influence band of each signal line are packed into an influence area data set to guide the subsequent identification operation of the start end.

[0072] Particularly importantly, step S43 includes the following steps: Step S431: Extract the coordinates of differential signal lines according to the routing of differential signal lines; In this embodiment, based on the differential signal line information extracted from the printed circuit board (PCB) design data, the routing of differential signal lines on the circuit board is determined. Differential signal lines usually consist of two parallel signal lines, and their spacing, length, layout, and routing all have an important impact on the signal transmission performance. In this step, it is necessary to extract the signal routing data from the PCB design file (such as Gerber file) or CAD software. By parsing the file, the starting and ending coordinates of the signal lines are extracted, and the intermediate point information of each path is recorded. The extraction of differential signal line coordinates needs to ensure accuracy, usually requiring the accuracy of coordinate points to be at the micron level to ensure the accuracy of subsequent calculations. During the data extraction process, according to the layout rules of the circuit, the starting end, routing, connection method of the signal line, and its relative position to other lines should be comprehensively recorded.

[0073] Step S432: Statistically calculate the outer edge spacing of pads based on the pad spacing; In this embodiment, by analyzing the pad layout in the PCB design diagram, the geometric dimension information of the pads is extracted. The outer edge spacing of pads refers to the distance between the outer edges of adjacent pads, and this data is very crucial for analyzing the influence area of differential signal lines. In this step, first, the geometric data of each pad, including the diameter or width, is extracted from the design file. Then, based on the extracted pad position data, the distance between the outer edges of adjacent pads is calculated. This distance is obtained by subtracting the radius or diameter of each pad from the distance between the center points of the two pads. This process requires high-precision distance calculation to avoid signal crosstalk or electrical short circuit caused by too small pad spacing. When statistically calculating the outer edge spacing of pads, the multi-layer design of the PCB should be considered to ensure that the pad spacing of each layer is independently statistically calculated and recorded, so as to provide accurate basic data for subsequent identification of the signal influence area.

[0074] Step S433: Perform a minimum distance calculation on the outer edge spacing of pads according to the differential signal line coordinates to obtain the minimum distance data; In this embodiment, for each differential signal line, determine its relative position with respect to the pads at both ends and calculate the shortest distance from each pad outer edge to the differential signal line. During this process, the differential signal line is regarded as two parallel lines, and the pads are regarded as structures with circular or elliptical edges. To calculate the minimum distance, the distance formula in geometry is used to analyze the distance between the differential signal line and the pad outer edge. In actual operation, this calculation can be automatically completed through PCB design software or a custom calculation program, using high-precision floating-point arithmetic to ensure the accuracy of distance calculation. For each pair of differential signal lines and pad outer edges, record the minimum distance value as the basic data for subsequent identification of the signal influence area.

[0075] Step S434: Mark the differential signal line influence area according to the minimum distance data to obtain the differential signal line influence area data.

[0076] In this embodiment, the influence area refers to those areas that are close to the differential signal line and are affected by signal transmission. At this time, an influence threshold needs to be set, which is usually determined by design rules or signal quality requirements. For example, if the minimum distance is less than the set threshold, it is considered that the pad or area is affected by the differential signal line. In actual operation, a certain range around each pad is marked through programming to form influence area data. The size of this area is related to the spacing of the signal lines and the electrical characteristics in the PCB design. The marking of the influence area is based on the calculated minimum distance data and combines the routing information of the differential signal line to draw the geometric shape of the affected area. During this process, the visualization function of computer-aided design (CAD) software can be used to intuitively display the influence area and conduct further analysis. These data are ultimately used for subsequent signal optimization and layout adjustment to ensure signal integrity and transmission quality.

[0077] Step S44: Identify the starting end of the differential signal line according to the differential signal line influence area data; In this embodiment, by comparing the starting point coordinates in the differential signal line routing data with the positions of each pad in the influence area, find the pair of pad points with the closest distance, and determine them as the starting pads of the differential pair signal line. If there are multiple pad centers with equal distances from the starting point, these pads are prioritized according to their numbering order, and the pad with the earlier number is preferentially selected as the starting end. This operation needs to be verified point by point through the pad management tool in the routing editor to ensure that the starting end pad has the same associated logic network number as the signal path. The identified starting end pad number, coordinates, and the signal line number where it is located are written into the identification result table together, providing an accurate reference point for the starting point offset before compensation.

[0078] Step S45: Calculate the starting point offset according to the starting end of the differential signal line; In this embodiment, after selecting the starting end of each pair of differential signal lines, measure the distance between the starting positions of their two paths. Use the path node reading function to extract the starting coordinates of the first segment of the two differential signal lines respectively. Measure the spatial offset between these two starting points in the plane, and record its offset length and relative direction. If the offset direction is a non-vertical angle, the offset angle also needs to be recorded as an auxiliary parameter. This offset value serves as the core calculation benchmark for equal-length compensation, and all differential pairs need to perform this operation. Finally, a set of compensation basic parameters are formed, including the number of each differential line, the coordinates of the two starting points, the offset distance, and the offset direction, which serve as the input basis for the differential pair compensation routing process.

[0079] Step S46: Perform differential equal-length compensation based on the starting point offset to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0080] In this embodiment, the compensation method selects the serpentine folding wiring process, introduces a folding path segment within the allowable range of the wiring length, and the interval length of each folding path is determined according to the offset, which shall not be less than 5 mils. During the layout of the folding path, it is necessary to avoid areas with dense components, power supply wiring areas, and high-frequency signal interference areas. At the same time, keep the wiring width consistent with the main line, and round corners should be used at the corners to reduce the risk of signal reflection. After the compensation wiring is completed, call the equal-length verification function module to detect the length difference before and after compensation to ensure that the difference does not exceed 5 mils. The compensation wiring data includes the coordinates, length, and direction information of the newly added path segment, and all are written into the structure parameter concentrator of the high-speed differential signal transmission model. Finally, call the model reconstruction function to load the updated signal network structure containing the compensation path to realize the structural reconstruction of the high-speed differential transmission path.

[0081] Particularly importantly, step S46 includes the following steps: Step S461: Calculate the compensation path length based on the starting point offset; In this embodiment, extract the starting physical coordinate positions of each pair of differential signal lines from the high-speed differential wiring design diagram. This coordinate needs to be parsed from the PCB design file, and the design file format is the standard ODB++ or IPC-2581 format. By parsing the wiring layer (Layer) definition area, obtain the starting point data of the line segment corresponding to the signal line number. The starting position of the signal line is usually automatically assigned by the wiring tool, but due to the asymmetric arrangement of logic chips or connector pins during the layout process, there are often cases where the starting positions of the two lines in a differential pair have a physical offset. The extracted coordinate data is formatted in a unified unit (such as millimeters), and then the distance between the starting ends of the two differential lines is measured by the grid comparison method. This measurement is based on the point-to-point comparison operation in the two-dimensional image coordinate system. By using a script to extract the two endpoints of each pair of signal lines one by one, without relying on model calculation, record their horizontal difference and vertical difference, and the wiring control module combines the two parts of the length to finally generate a compensation length task list. The task list records the number of each pair of differential lines and the path length that needs to be compensated, with the unit accurate to 0.01 millimeters, and is marked to enter the compensation operation queue.

[0082] Step S462: Perform serpentine compensation wiring according to the compensation path length; In this embodiment, after the path compensation length task table is generated, the compensation length required for each differential signal pair is assigned to the routing engine for serpentine line generation. The routing process is based on predefined design rules, including line width setting, routing spacing, turning clearance, routing layer selection, etc. The routing engine uses the "Differential Equal-Length Function Module" in the Cadence Allegro PCB Designer system for automatic routing. The compensation method is limited to local serpentine line compensation. The serpentine unit adopts a U-shaped folding structure, and each compensation structure includes a forward routing section and two U-shaped turns. The compensation routing interval is preferably selected in the blank area after the start section of the differential pair to avoid overlapping the routing of other networks or components. The compensation path is designed with equal spacing and equal length. The length of a single section structure is a fixed value, such as 0.6 mm. The line width is uniformly set to 0.15 mm, and the minimum spacing between serpentine lines is 0.25 mm to ensure that the electrical isolation distance meets the high-speed design specifications. The routing tool will automatically push the number of serpentine units within the local space according to the compensation length until the length requirement indicated in the task table is met. The turning point coordinates of each serpentine structure are completely recorded for subsequent compensation verification and simulation analysis.

[0083] Step S463: Route the path compensation differential signal line according to the serpentine line layout to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0084] In this embodiment, after the layout is completed, the total length of the routing paths of all differential signal lines will be recalculated to ensure that the overall routing lengths of the positive and negative lines reach strict consistency after the compensation operation. This verification process is completed by the routing verification tool, which uses the routing analysis function within the same platform to perform segmented scanning and length accumulation on each section of the routing, output the complete path lengths of the positive and negative lines, and record them in the differential pair compensation log file. If the error exceeds the allowable threshold (for example, 0.05 mm), the position or number of serpentine sections will be readjusted until the lengths are consistent. The routed data after compensation is exported in the form of a standard intermediate file format (such as DXF or GDSII) through the routing export tool. The routing trajectory, number of compensation sections, coordinate information of each section, line width parameter, and routing layer data of each pair of signal lines will be archived as a structured data table and recorded in CSV format. This compensation data, as a key constraint item in the high-speed differential signal transmission model, is imported into the high-speed signal modeling environment through the data interface. The signal modeling tool uses the Keysight ADS system to model the transmission channel, automatically analyzes the differential line structure data and serpentine section structure, and converts them into an equivalent transmission line model of the channel. This model is then embedded into the differential channel simulation module and used as the input basis for multiple simulation modules such as electromagnetic field calculation, crosstalk analysis, and impedance distribution analysis, thus completing a round of structural optimization process for the high-speed signal path.

[0085] Preferably, this specification also provides a construction system for a high-speed differential signal transmission model, which is used to execute the method for constructing a high-speed differential signal transmission model as described above. The construction system for a high-speed differential signal transmission model includes: A signal transmission simulation module, configured to obtain printed circuit board design data and extract differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; An electrical fault identification module, configured to identify the position of crosstalk sources based on the high-speed differential signal transmission data to obtain crosstalk source coordinates; detect via misalignment based on the crosstalk source coordinates to obtain via misalignment data, and evaluate the degree of thermal accumulation based on the via misalignment data; identify the electrical fault area of the circuit board based on the degree of thermal accumulation; A pad layout optimization module, configured to extract stack-up structure information according to the printed circuit board design data; perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; optimize the pad layout according to the interlayer delamination data; A differential equal-length compensation module, configured to reconstruct the signal routing according to the electrical fault area of the circuit board; perform differential equal-length compensation on the pad layout according to the signal routing to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0086] Therefore, from any perspective, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to encompass all changes that fall within the meaning and scope of the equivalent elements of the application documents within the present invention.

[0087] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features invented herein.

Claims

1. A method for constructing a high-speed differential signal transmission model, characterized in that: The following steps are involved: Step S1: Obtain printed circuit board design data and extract differential signal line data; Construct a high-speed differential signal transmission model based on differential signal line data; Perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; Step S2: identifying the location of the crosstalk source based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detecting the via misalignment based on the crosstalk source coordinates to obtain the via misalignment data, and evaluating the degree of heat accumulation based on the via misalignment data; Identify electrical fault areas on the circuit board based on the degree of heat accumulation; Step S3: extracting stacking structure information according to the printed circuit board design data; performing interlayer peeling detection based on the stacking structure information to obtain interlayer peeling data; Optimize pad layout based on interlayer peeling data; Step S4: reconstruct the signal wiring according to the electrical fault area of ​​the circuit board; perform differential equal-length compensation on the pad layout according to the signal wiring, obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

2. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that: Step S1 is specifically as follows: Step S11: obtaining printed circuit board design data and extracting differential signal line data; Step S12: restoring the signal propagation path based on the differential signal line data; Step S13: identifying an impedance mutation region according to the signal propagation path; and adjusting the differential signal line spacing based on the impedance mutation region; Step S14: calculating the routing delay according to the signal propagation path identification; adjusting the differential signal line length based on the routing delay; Step S15: constructing a high-speed differential signal transmission model according to the differential signal line spacing and the differential signal line length; Step S16: Perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data.

3. The method for constructing a high-speed differential signal transmission model according to claim 2, characterized in that: Step S16 is specifically as follows: Step S161: importing the high-speed differential signal transmission model into the signal simulation software; Step S162: setting the signal frequency range to 100 MHz-10 GHz, the signal amplitude range to 0.5 V-3.3 V, and the signal waveform to a sine wave in the simulation software; Step S163: setting the differential impedance range to 80Ω-120Ω and the single-ended impedance range to 40Ω-60Ω in the simulation software; Step S164: in the simulation software, set the signal source type to a differential signal pair, the transmission line type to a microstrip line, the signal transmission line length to 10 mm-300 mm, and the signal line spacing range to 0.1 mm-1.0 mm; Step S165: Run the signal transmission simulation program in the simulation software and output high-speed differential signal transmission data.

4. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that: The specific steps of identifying the location of the crosstalk source in step S2 are: Extracting low transmission efficiency signal data based on high-speed differential signal transmission data; Representing a circuit board with low transmission efficiency according to the low transmission efficiency signal data, and performing image acquisition on the circuit board with low transmission efficiency to obtain an image of the circuit board with low transmission efficiency; Identify the wiring path based on the image of the low transmission efficiency circuit board; calculate the wiring spacing based on the wiring path; Calculate the routing angle according to the routing path, and identify the routing sharp corner area of ​​the circuit board image with low transmission efficiency based on the routing angle; Identify the small spacing area of ​​the routing in the sharp corner area based on the routing spacing; Perform electromagnetic field simulation based on the small spacing area of ​​the routing to obtain electromagnetic field simulation data; Identify electromagnetic field enhancement areas based on electromagnetic field simulation data; The electromagnetic field enhancement area is mapped to the small spacing area of ​​the routing to obtain the crosstalk source area, and recorded as the crosstalk source coordinates.

5. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that: The heat accumulation degree in step S2 is specifically: Extract via coordinates based on crosstalk source coordinates; Perform X-ray scanning according to the via coordinates to obtain via X-ray scanning data; Reconstructing a three-dimensional image of the via based on the via X-ray scanning data; Divide the penetration amount of vias based on the three-dimensional image of vias to obtain local penetration data of vias and global penetration data of vias; Calculate the lateral position offset based on the local penetration via data; Calculate the depth misalignment offset based on the global penetration via data; Integrate the lateral position offset and the depth misalignment offset to obtain the via misalignment data; Determine the thermal expansion coefficient of the via material based on the via misalignment data; perform a circuit board thermal conduction simulation based on the thermal expansion coefficient of the via material to obtain the circuit board thermal conduction data; Perform thermal stress detection on via misalignment data according to the thermal conduction data of the circuit board to obtain thermal stress data of the via; Evaluate via tearing based on via thermal stress data; Identify heat accumulation areas based on via tearing levels; Assess the extent of heat accumulation based on areas where heat is concentrated.

6. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that: Step S2 identifies the electrical fault area of ​​the circuit board as follows: Evaluate welding quality based on heat accumulation and obtain welding data; Count the amount of solder used based on welding data; calculate the volume of solder accumulation based on the amount of solder used; determine the solder filling status based on the solder accumulation volume; evaluate the firmness of the solder joint based on the solder filling status; Predict the risk of solder joint falling off based on the firmness of the solder joint; Extract the solder joint falling position according to the risk of solder joint falling off; obtain the signal routing position of the circuit board; map the solder coverage area of ​​the signal routing position according to the solder joint falling position to obtain the solder coverage area data; Perform a resistance continuity test based on the solder coverage area data to obtain resistance continuity data; Determine the electrical fault area of ​​the circuit board based on the resistance continuity data.

7. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that: Step S3 is specifically as follows: Step S31: extracting stacking structure information according to printed circuit board design data; Step S32: determining the milling process based on the stacked structure information; performing via milling simulation according to the milling process to obtain via milling data; Step S33: screening the via-hole milling samples according to the via-hole milling data, and irradiating the via-hole milling samples with a high-energy electron beam to obtain high-energy electron beam irradiation data; capturing the diffraction pattern based on the high-energy electron beam irradiation data; and identifying the crystal morphology according to the diffraction pattern; Determine the grain deformation according to the crystal morphology and obtain the grain deformation data; Evaluate the residual stress of milling edge based on grain deformation data; Step S34: performing stacking crack analysis on the stacking structure information according to the milling residual stress to obtain stacking crack data; Step S35: predicting the interlayer delamination risk according to the stacking crack data to obtain interlayer delamination data; Step S36: Optimizing pad layout according to the interlayer peeling data.

8. The method for constructing a high-speed differential signal transmission model according to claim 7, characterized in that: Step S36 is specifically as follows: Step S361: Calculate the peeling depth according to the interlayer peeling data; calculate the peeling length according to the interlayer peeling data; calculate the interlayer peeling area according to the peeling depth and the peeling length; Step S362: marking the interlayer peeling region based on the interlayer peeling area; Risk classification is performed based on the interlayer debonding area. If the interlayer debonding area is greater than or equal to 30% of the interlayer debonding area, a high-risk interlayer debonding area is obtained; If the interlayer debonding area is less than 30% of the interlayer debonding region, a low-risk interlayer debonding region is obtained; Step S363: adjusting the pad size based on the low-risk interlayer peeling area to obtain pad size data; Step S364: adjusting the pad material based on the high-risk interlayer delamination area to obtain pad material data; Step S365: Integrate the pad size data and the pad material data, and determine the optimized pad layout.

9. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that: Step S4 is specifically as follows: Step S41: reconstructing the signal wiring according to the electrical fault area of ​​the circuit board; extracting the direction of the differential signal line based on the signal wiring; Step S42: Calculating the pad spacing based on the pad layout; Step S43: identifying the differential signal line influence area of ​​the pad spacing according to the differential signal line direction, and obtaining differential signal line influence area data; Step S44: identifying the start end of the differential signal line according to the differential signal line influence area data; Step S45: Calculate the starting point offset according to the starting end of the differential signal line; Step S46: Perform differential pair equal length compensation based on the starting point offset to obtain equal length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

10. A construction system based on a high-speed differential signal transmission model, characterized in that: The method for constructing a high-speed differential signal transmission model according to claim 1 is used to construct a high-speed differential signal transmission model, and the construction system based on the high-speed differential signal transmission model includes: The signal transmission simulation module is used to obtain the printed circuit board design data and extract the differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; An electrical fault identification module is used to identify the location of the crosstalk source based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detect the via misalignment based on the crosstalk source coordinates to obtain the via misalignment data, and evaluate the degree of heat accumulation based on the via misalignment data; and identify the electrical fault area of ​​the circuit board based on the heat accumulation degree; The pad layout optimization module is used to extract the stacking structure information according to the printed circuit board design data; perform interlayer peeling detection based on the stacking structure information to obtain interlayer peeling data; and optimize the pad layout according to the interlayer peeling data; The differential pair equal length compensation module is used to reconstruct the signal wiring according to the electrical fault area of ​​the circuit board; perform differential pair equal length compensation on the pad layout according to the signal wiring, obtain the equal length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

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