Physical layer PIPE interface enhancement verification method based on PCIE protocol

Abstract

The invention provides a physical layer PIPE interface enhanced verification method based on a PCIE protocol, a PIPEWRAPPER architecture is set, interaction with the outside is carried out through a phymacpipe interface and a phypcspipe interface, the PIPEWRAPPER architecture comprises a plurality of modules which are respectively responsible for PIPE interface verification work in different aspects, and the PIPEWRAPPER architecture is used for verifying the PIPE interface in different aspects. The PIPEWRAPPER framework comprises a Pipe signal initial value checking module, a Pipe signal data insertion module, a Pipe interaction signal delay control module, a Pipe signal EQ process checking module, a Pipe signal low power consumption process checking module and a Pipe signal Lanemargin checking module. The PIPE interface is verified comprehensively and carefully from the aspects of signal initial value, data insertion, time sequence control, balancing process, low power consumption mode, channel allowance and the like through cooperative work of a plurality of modules, the reliability, stability and performance of a PCIe system physical layer are ensured, and the quality and usability of the whole system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer chips, and particularly relates to an enhanced verification method for the physical layer PIPE interface based on the PCIE protocol. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) technology, as a computer expansion bus standard, has been widely applied in multiple fields. Especially with the rapid development of AI technology, more and more chips need to integrate PCIe interfaces. In the field of chip design, the corresponding verification requirements for PCIe interfaces are also getting higher and higher.

[0003] The protocol architecture framework of the PCIE interface is as Figure 1 shown, where the physical layer protocol includes a logical sub-layer protocol and an electrical sub-layer protocol. The pipe protocol is the interface between the logical sub-layer protocol and the electrical sub-layer protocol. In chip design, the physical layer pipe protocol in the PCIE interface requires relevant verification.

[0004] During the chip development process, the involved protocols are complex and the implementation methods are not unified, resulting in the relevant verification work based on the pipe protocol interface has always been the key and difficult point in the verification of PCIe interface chips. Although some solutions have been given in the prior art, there are still some problems: there is a lack of a unified interface assertion technology, which cannot timely check the correctness and error of signals; for some key signals that need to interact in the pipe protocol, there is no effective debugging means; for the equalization process of the physical layer, there is no appropriate means to assist in positioning and debugging; low-power verification cannot be effectively carried out; it is necessary to combine with PMA to determine whether the physical layer controller is reasonably designed. The above problems seriously affect the debugging efficiency and positioning efficiency in the verification and development of PCIe chip design. Summary of the Invention

[0005] The purpose of the present invention is to propose an enhanced verification method for the physical layer PIPE interface based on the PCIE protocol to solve the technical problems of low debugging efficiency and positioning efficiency of the prior art proposed in the above background art. The present invention can effectively improve the efficiency of development and verification based on the pipe protocol.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] A method for enhancing the verification of the physical layer PIPE interface based on the PCIE protocol, which sets up the PIPE_WRAPPER architecture and interacts with the outside through the phy_mac_pipe interface and the phy_pcs_pipe interface. The PIPE_WRAPPER architecture includes multiple modules, which are respectively responsible for the verification work of different aspects of the PIPE interface. The PIPE_WRAPPER architecture includes: a Pipe signal initial value check module, a Pipe signal data insertion module, a Pipe interaction signal delay control module, a Pipe signal EQ process check module, a Pipe signal low-power process check module, and a Pipe signal Lane_margin check module.

[0008] Further, the Pipe signal initial value check module checks the initial values of the signals of the PIPE interface during the system startup or initialization phase. The signal names checked by the Pipe signal initial value check module include: PhyStatus, TxDetectRx / Loopback, TxElecIdle, TxCompliance, RxPolarity, PowerDown, TxMargin, TxDeemp, Rate. The corresponding reset initial value check rules are: PhyStatus is pulled high, TxDetectRx / Loopback is pulled low, TxElecIdle is pulled high, TxCompliance is pulled low, RxPolarity is pulled low, PowerDown == 4'b0010, TxMargin == 3'b000, TxDeemp == 1, Rate == 2.5G.

[0009] Further, the Pipe signal data insertion module includes a signal name modification timing module, a data sequence value modification module, and a configuration modification sequence value module. The signal name modification timing module is used to determine when to modify the name of the Pipe signal. The data sequence value modification module is responsible for modifying a large number of data sequence values. The configuration modification sequence value module is used to configure the specific modification values of the data sequence values.

[0010] Preferably, the data sequence value modification module supports modifying 16 * 33 symbols, and the value range provided by the configuration modification sequence value module is 0 to 16 * 33.

[0011] Further, the timing and method for modifying the signal name provided by the signal name modification timing module are as follows:

[0012] rx_data modification timing:

[0013] mode0: When the rate changes from gen2 to gen3, modify rx_data;

[0014] mode1: Modify rx_data when the rate changes from gen4 to gen5;

[0015] mode2: Modify rx_data when the rate changes from gen5 to gen6;

[0016] Timing for modifying tx_data:

[0017] mode0: Modify tx_data when the rate changes from gen2 to gen3;

[0018] mode1: Modify tx_data when the rate changes from gen4 to gen5;

[0019] mode2: Modify tx_data when the rate changes from gen5 to gen6.

[0020] Furthermore, the Pipe interaction signal delay control module is used for MAC and PHY interaction debugging, and realizes the delay control of the pipe interaction signal by setting the MAC output signal control module and the PHY output signal control module.

[0021] Furthermore, the Pipe signal EQ process inspection module is used to inspect the EQ process of the PIPE interface signal. The rules of the Pipe signal EQ process inspection module are as follows:

[0022] ① Local Local Preset Coefficients update:

[0023] First, the M2P interface issues a write to the PHYTX Control5 register, and then, checks the P2M write acknowledge signal;

[0024] ② Local Local FS / LF update:

[0025] First, the P2M interface issues writes to the PHYTX Control3 and PHYTX Control4 registers. Secondly, checks the P2M write acknowledge signal. Finally, checks that the phystatus signal is pulled low.

[0026] Furthermore, the Pipe signal low-power process inspection module is used to verify the working condition of the PIPE interface in the low-power mode. The rules of the Pipe signal low-power process inspection module are as follows:

[0027] ① When entering the L0s state from L0, there are the following signal changes and inspection steps in sequence:

[0028] TXdata issues EIOS, checks if TXelec_idle is pulled high, checks if power_down equals 2'b01, and checks if phystatus is pulled high;

[0029] ② When L0s enters the L0 state, the following signal changes and check steps occur in sequence:

[0030] phystatus is pulled low, TXdata issues FTS, and checks if TXelec_idle is pulled low;

[0031] ③ When L0 enters the L1 state, the following signal changes and check steps occur in sequence:

[0032] TXdata issues EIOS, checks if TXelec_idle is pulled high, checks if power_down equals 2'b10, and checks if phystatus is pulled high;

[0033] ④ When L1 enters the L0 state, the following signal changes and check steps occur in sequence:

[0034] phystatus is pulled low, TXdata issues TS1 / TS2, and checks if TXelec_idle is pulled low.

[0035] Furthermore, the Pipe signal Lane_margin check module is used to check the channel margin of the PIPE interface signals, and the rules of the Pipe signal Lane_margin check module are as follows:

[0036] ① Start the Lane Margin command:

[0037] First, the M2P signal interface issues a write to the Rx_margin contol register, and then the P2M signal write acknowledgment signal;

[0038] ② Margin signal PHY update check:

[0039] First, the P2M signal interface issues a write to the Rx_margin status register, and then the M2P signal write acknowledgment signal.

[0040] Through the collaborative work of multiple modules, the present invention comprehensively and meticulously verifies the PIPE interface from multiple aspects such as signal initial value, data insertion, timing control, equalization process, low-power mode, and channel margin, which helps to ensure the reliability, stability, and performance of the PCIe system physical layer, and improves the quality and usability of the entire system.

[0041] The present invention has the following beneficial effects:

[0042] The present invention proposes a method for checking the initial value of pipe signals, which improves the efficiency of pipe signal debugging and the efficiency of problem location; proposes a method for inserting key signals of pipe signals, which solves the current situation that it is difficult to debug key signals during the chip verification process; proposes a method for delaying pipe interaction signals, which solves the debugging difficulty of the timing debugging of pipe interface interaction signals; proposes a method for checking the EQ process of pipe signals, which improves the efficiency of pipe signal EQ process debugging and the efficiency of problem location; proposes a method for checking the low-power process of pipe signals, which improves the efficiency of pipe signal low-power process debugging and the efficiency of problem location; proposes a method for checking the Lane margin process of pipe signals, which improves the efficiency of pipe signal Lanemargin process debugging and the efficiency of problem location. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1 It is a schematic diagram of the PCIE protocol architecture;

[0045] Figure 2 It is a schematic diagram of the overall architecture of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0047] Refer to Figure 2 As shown, a method for enhancing the verification of the physical layer PIPE interface based on the PCIE protocol sets up a PIPE_WRAPPER architecture and interacts with the outside through the phy_mac_pipe interface and the phy_pcs_pipe interface. The PIPE_WRAPPER architecture includes multiple modules, which are respectively responsible for the verification work of different aspects of the PIPE interface, specifically including: a Pipe signal initial value check module, a Pipe signal data insertion module, a Pipe interaction signal delay control module, a Pipe signal EQ process check module, a Pipe signal low-power process check module, and a Pipe signal Lane_margin check module.

[0048] The phy_mac_pipe interface and the phy_pcs_pipe interface are the channels through which the PIPE_WRAPPER interacts with other parts of the external physical layer (PHY). The phy_mac_pipe interface is connected to the media access control (MAC) part of the physical layer and is responsible for handling functions such as data interaction with the upper protocol stack and link management; the phy_pcs_pipe interface is connected to the physical coding sublayer (PCS) and is responsible for data encoding, decoding, and other related functions of the physical layer. Through these two interfaces, the PIPE_WRAPPER can obtain and inject signals of the PIPE interface, realizing comprehensive verification and monitoring of the entire physical layer PIPE interface.

[0049] The Pipe signal initial value check module checks the initial values of the signals of the PIPE interface during system startup or initialization. Ensuring that the initial signal state meets expectations is the basis for subsequent normal communication. For example, checking whether the reset signal is correctly reset and whether some control signals are in the default safe state. If the initial value is incorrect, it may lead to abnormal subsequent data transmission or even the system cannot start normally.

[0050] The main check specifications of the Pipe signal initial value check module are shown in Table 1:

[0051]

[0052]

[0053] Table 1 PIPE Signal Initial Value Check Table

[0054] PhyStatus signal

[0055] PhyStatus is pulled high: PhyStatus is the status signal of the physical layer (PHY). Pulling it high indicates that the physical layer is in a certain specific initial state after reset. For example, it may indicate that the hardware circuit of the physical layer has been initialized or some key modules are ready to enter the working state. By checking whether this signal is pulled high, it is possible to initially judge whether the reset process of the physical layer is normal and whether subsequent operations and communications can be carried out.

[0056] TxDetectRx / Loopback signal

[0057] TxDetectRx / Loopback Pull - down: This signal is related to the function of the transmitter detecting the receiver or loop - back testing. The pulled - down initial value means that after reset, these functions are in an off or disabled state, avoiding unnecessary signal interference or incorrect operations during system initialization. For example, when the system starts up, it is not desired to automatically enter the loop - back test mode. Instead, a normal initialization and configuration process is carried out first, so this signal is set to the pulled - down initial value.

[0058] TxElecIdle signal

[0059] TxElecIdle Pull - up: TxElecIdle is the transmitter electrical idle signal. Pulling it up means that after reset, the transmitter is in an electrical idle state, that is, no valid data signal is being transmitted. This ensures that there is no unexpected data transmission when the system starts up and also prepares for subsequent normal data transmission.

[0060] TxCompliance signal

[0061] TxCompliance Pull - down: TxCompliance is related to the compliance or standard compliance of the transmitter. The pulled - down initial value indicates that after reset, certain compliance checks or standard - related functions of the transmitter are in an off or inactive state. This is to simplify operations during system initialization, avoid unnecessary compliance checks from affecting the startup speed, or set these functions to the default off state before performing specific tests or configurations.

[0062] RxPolarity signal

[0063] RxPolarity Pull - down: RxPolarity is the receive polarity signal. The pulled - down initial value means that the polarity setting of the receiver is in a default state after reset. In high - speed serial communication, the correct setting of the receive polarity is very important for correct data reception.

[0064] PowerDown signal

[0065] PowerDown == P1(4’b0010): The PowerDown signal is used to control the power - consumption state. The reset initial value is set to 4 - bit binary 0010 (P1), indicating that after reset, the system enters a specific power - consumption mode. This power - consumption mode is an intermediate state, neither completely off nor full - power operation. It is to gradually wake up each module during system startup or to maintain a low - power but quickly responsive state while waiting for further instructions and configurations.

[0066] TxMargin signal

[0067] TxMargin == 3’b000: TxMargin is related to the margin setting of the transmitter. The reset initial value is 3-bit binary 000, which means that the margin setting of the transmitter is in a minimum or default state after reset. Margin setting is usually used to adjust parameters such as the strength and driving ability of the transmitted signal to adapt to different link conditions and transmission requirements. The minimum margin setting after reset provides a safe starting point during system initialization, and can be adjusted later according to actual link tests and performance optimization.

[0068] TxDeemp signal

[0069] TxDeemp == 1: TxDeemp is related to the de-emphasis setting of the transmitter. The reset initial value is 1, which means that the de-emphasis function of the transmitter is in a specific enabled or set state after reset. De-emphasis is a technique used to compensate for the attenuation of high-frequency components of the signal during transmission. By preprocessing the signal at the transmitter, the quality and reliability of the signal at the receiver can be improved. The specific de-emphasis setting after reset is determined according to the default configuration of the system or common link characteristics, and can be fine-tuned later according to the actual link situation.

[0070] Rate signal

[0071] Rate == 2.5G: The Rate signal represents the data transmission rate. The reset initial value is 2.5 Gbps (gigabits per second), which is the default data transmission rate setting of the system after reset. In high-speed serial communication, the data transmission rate is an important parameter that determines the data transmission capacity and performance of the system.

[0072] The above reset initial value check rules for Pipe signals are an important guarantee to ensure the normal startup and operation of the system after reset. By checking the initial values of these signals, problems in the hardware initialization process can be detected in a timely manner, providing a reliable basis for subsequent system configuration and data transmission.

[0073] The implementation process of checking the initial value of the pipe signal. After the Pipe interface is reset, the PIPE signal initial value check table starts to be executed.

[0074] The Pipe signal data insertion module is used during testing and debugging to autonomously modify the values of the pipe interface signals according to verification requirements. For example, inserting error data to detect the error handling mechanism of the system, or inserting specific test mode data to verify the correctness of the data transmission path. There is no need to modify the configuration of the PCIE MAC controller to modify the values of the pipe interface signals, which speeds up the positioning and simulation of chip verification and improves the efficiency of chip verification.

[0075] The Pipe signal data insertion module includes a signal name modification timing module, a data sequence value modification module, and a configuration modification sequence value module. The signal name modification timing module is used to determine when to modify the name of the Pipe signal. This is related to factors such as the operating state of the system, specific event triggers, time periods, etc. For example, when the system switches from one working mode to another, it may be necessary to modify the names of some Pipe signals to adapt to the signal meanings and processing methods in the new mode; or at a specific time point after the system starts, modify the signal names according to the requirements of the initialization process. The data sequence value modification module is responsible for modifying a large number of data sequence values. These data sequence values are the actual data content transmitted in the Pipe signal. For example, in a communication system, it may be the payload part in a data packet. By modifying these data sequence values, it can be used to test the performance of the system under different data conditions, verify the correctness of data processing algorithms, simulate various fault scenarios, etc. The modification of data sequence values in the present invention supports modifying 16 * 33 symbols. The configuration modification sequence value module is used to configure the specific modification values of the data sequence values. It provides a value range (0 to 16 * 33), and a specific value within this range can be specified for each data sequence value according to the system requirements and test purposes. For example, during stress testing, some data sequence values may be configured as larger values to simulate high-load data transmission situations; during error injection testing, some data sequence values may be configured as incorrect values to check the error detection and recovery capabilities of the system.

[0076] The signal name modification timing module provides several timing and methods for modifying the signal name, which are as follows:

[0077] Modification timing of received data (rx_data):

[0078] mode0: When the rate changes from gen2 to gen3, rx_data needs to be modified. This is because different rate generations (gen) may have differences in signal characteristics, data encoding, etc. at the physical layer. To ensure that the receiving end can correctly process the data, it is necessary to modify the signal names related to rx_data when the rate switches, so that the subsequent processing modules can perform corresponding operations according to the new signal names. For example, it may be necessary to modify the signal names related to received data sampling and decoding to adapt to the rate requirements and signal formats of gen3.

[0079] mode1: When the rate changes from gen4 to gen5, modify rx_data. The rate change from gen4 to gen5 may be larger, and the requirements for processing received data are also higher. It may involve adjustments to more complex signal equalization, clock recovery and other mechanisms. Therefore, the modification of the signal name is to match these new processing mechanisms to ensure the accuracy and stability of data reception.

[0080] mode2: When the rate changes from gen5 to gen6, modify rx_data. As the rate is further increased, problems such as signal integrity of the physical layer become more prominent. New signal processing technologies and algorithms may be required. The modification of the signal name is to identify these new processing flows and parameters to facilitate system debugging and maintenance.

[0081] Modification timing of transmitted data (tx_data):

[0082] mode0: When the rate changes from gen2 to gen3, tx_data needs to be modified. When the transmitting end switches the rate, it needs to adjust parameters such as the data transmission format and pre-emphasis. The modification of the signal name enables the transmitting module to obtain the correct configuration information and control signals according to the new name, so as to ensure that the transmitted data can be correctly transmitted at the new rate.

[0083] mode1: When the rate changes from gen4 to gen5, modify tx_data. The rate increase from gen4 to gen5 may require optimization of the transmission clock, data packaging, etc. The modification of the signal name helps the transmitting module to accurately perform these optimization operations to ensure that the transmitted data matches the requirements of the receiving end.

[0084] mode2: When the rate changes from gen5 to gen6, modify tx_data. At this time, more refined adjustments may be required for the electrical characteristics of the transmission link. The modification of the signal name can clearly identify the signals and parameters involved in these adjustments to facilitate the overall coordination and management of the system.

[0085] The above settings of the modification timing and method are to ensure that the signal transmission remains stable and reliable during the switching of different rate modes, and to avoid problems such as data transmission errors or performance degradation caused by rate changes.

[0086] The Pipe interaction signal delay control module is used to control the delay (delay) between interaction signals in the pipe interface during debugging, which is convenient for constructing the timing relationship between various interactions. This is very important for verifying the performance and stability of the system under different timing conditions. For example, when simulating high-speed data transmission, by adjusting the signal delay, the transmission of signals on transmission lines of different lengths can be simulated, so as to check whether the system can work properly under various timing constraints and whether data errors caused by timing violations will occur.

[0087] The Pipe interaction signal delay control module is mainly used for MAC and PHY interaction debugging. If it is necessary to control the interaction signals output by the MAC, especially when timing interaction is required, it is very difficult to accurately control the delay of the interaction signals. The present invention realizes the delay control of the pipe interaction signals by setting the MAC output signal control module and the PHY output signal control module.

[0088] The list of MAC output interaction signals of the MAC output signal control module is shown in Table 2:

[0089] Table 2 MAC Output Interaction Signal List

[0090] Signal Name Register Control Delay Interactive Signal Meaning TxElecIdle Through register control delay (0 to 256) beats MAC controls the PHY to output an electrical idle signal PowerDown Through register control delay (0 to 256) beats MAC controls the PHY low-power state signal RxStandBy Through register control delay (0 to 256) beats MAC controls the PHY standby signal

[0091] The TxElecIdle signal can control the delay through a register, and the delay range is (0 to 256) beats, that is, the delay of this signal can be set within the range of 0 to 256 clock cycles. This signal is an electrical idle signal output by the Media Access Control (MAC) to control the Physical Layer (PHY). In high-speed serial buses such as PCIe, when the device has no data to send, it will send the TxElecIdle signal, and the receiving end can judge the link status according to this signal.

[0092] The Power-Down signal can control the delay through a register, and the delay range is (0 to 256) beats. This signal is used for the MAC to control the PHY to enter the low-power state. When the system is idle or does not require high-speed data transmission, the MAC can send the Power Down signal to the PHY to indicate that the PHY enters the low-power mode to reduce the power consumption of the entire system. For example, in some mobile devices or systems sensitive to power consumption, reasonably controlling the delay and status of the Power Down signal can effectively extend the battery life or meet the power consumption requirements of the system.

[0093] The RxStandBy signal can be controlled for delay through a register, and the delay range is (0 to 256) beats. This signal is used by the MAC to control the PHY to enter the standby state. When the MAC does not need the PHY to receive data, it can send the RxStandBy signal to make the PHY enter the standby state, reducing unnecessary power consumption and resource consumption. For example, in some scenarios of intermittent data transmission, the MAC can send the RxStandBy signal in a timely manner according to the data transmission requirements to control the working state of the PHY, achieving efficient operation and power management of the system.

[0094] The above MAC output interaction signals play an important role in the Pipe interaction signal delay control module. By controlling the delay through a register, the signal timing can be adjusted more flexibly to adapt to different system requirements and working scenarios, ensuring accurate and efficient interaction between the MAC and the PHY, while achieving power optimization and performance improvement of the system.

[0095] The list of PHY output interaction signals of the PHY output signal control module is shown in Table 3:

[0096] Table 3 PHY Output Interaction Signal List

[0097]

[0098] The RxStandbyStatus signal can be controlled for delay through a register, and the delay range is (0 to 256) beats. This signal is the electrical idle signal status output by the PHY, used to indicate whether the PHY is currently in the electrical idle state. For example, when the PHY does not receive a valid data signal, it will output the RxStandbyStatus signal to indicate that it is in the electrical idle state, which is very important for the MAC layer or other upper-layer modules to understand the current state of the link, so as to perform corresponding operations and controls, such as adjusting the power consumption mode or monitoring the link status.

[0099] The Phystatus signal can be controlled for delay through a register, and the delay range is (0 to 256) beats. This signal is the status signal output by the PHY, which can contain various physical layer status information, such as the link connection status, signal quality, error detection status, etc. Upper-layer modules (such as the MAC layer) can obtain the real-time status of the physical layer according to the Phystatus signal, and then make corresponding decisions. For example, if the Phystatus signal indicates a problem with the link connection, the MAC layer may try to re-initialize the link or take other error recovery measures.

[0100] The RxElecIdle signal can be controlled for delay through a register, and the delay range is (0 to 256) clock cycles. This signal represents the electrical idle state signal received by the PHY. When the PHY detects that the received signal is in the electrical idle state, it will output the RxElecIdle signal. This is very crucial for the status monitoring and control of the entire communication system. For example, the receiving end can determine whether the sending end is idle based on this signal, and then decide whether to perform some specific operations, such as waking up the sending end or adjusting its own receiving status, etc.

[0101] The RxStatus signal can be controlled for delay through a register, and the delay range is (0 to 256) clock cycles. The RxStatus signal is the status signal received by the PHY, and it may contain various status information related to the received data, such as the validity of the received data, whether there are errors, the status of the receive buffer, etc. The upper-layer module can understand the detailed situation of the receiving process based on the RxStatus signal, so as to perform data processing, error handling, and flow control operations to ensure the reliable reception of data and the normal operation of the system.

[0102] The above PHY output interaction signals play an important role in the Pipe interaction signal delay control module. By controlling the delay through a register, the signal timing can be flexibly adjusted to adapt to different system requirements and working scenarios, ensuring that the interaction between the PHY and other modules can be carried out accurately and efficiently, thereby improving the performance and stability of the entire communication system.

[0103] The described Pipe signal EQ process inspection module is used to inspect the equalization (EQ) process of the PIPE interface signal and check the correctness of the EQ process. In high-speed data transmission, due to signal attenuation and distortion on the transmission line, equalization technology is used to compensate for these effects to improve signal quality and transmission reliability. This module will check the parameter settings of the equalizer, signal changes during the equalization process, etc., to ensure that the equalization process can effectively improve signal quality. For example, it checks whether the equalizer can automatically adjust the gain and filtering parameters according to the characteristics of the link to achieve the best equalization effect.

[0104] The rules of the described Pipe signal EQ process inspection module are as follows:

[0105] ① Local Local Preset Coefficients update:

[0106] In high-speed serial communication systems such as PCIe, Preset Coefficients are used for the initialization and adjustment of the Equalizer (EQ). The role of the equalizer is to compensate for the attenuation and distortion of the signal during transmission to improve signal quality and transmission reliability. When it is necessary to update the local Local Preset Coefficients, the following operations are triggered.

[0107] The M2P interface issues a write to the PHYTX Control5 register: The Master to Peripheral (M2P) interface is a communication interface between the master device and the Physical Layer (PHY) in the system. Through this interface, the master device sends instructions to the PHY, specifically writing to the PHYTX Control5 register. This register may contain control information and configuration parameters related to the preset coefficients of the transmitter equalizer. For example, it may include gain coefficients for different frequency bands, filter parameters, etc., for setting the initial state or the updated state of the transmitter equalizer.

[0108] Check the P2M write acknowledge signal: The Peripheral to Master (P2M) write acknowledge signal is the response of the PHY to the master device's write operation. After the master device writes data to the PHYTX Control5 register through the M2P interface, it is necessary to check the P2M write acknowledge signal to confirm whether the PHY has correctly received the write instruction and processed it successfully. If the correct write acknowledge signal is not received, it may mean that the write operation has failed, and further troubleshooting is required, such as interface communication failures, register address errors, PHY module failures, etc.

[0109] ② Local Local FS / LF update:

[0110] Fast Settling (FS) and Long Reach (LF) are settings related to the equalizer operating mode or parameters. When it is necessary to update these local settings, the following operation process is involved:

[0111] The P2M interface issues writes to the PHYTX Control3 and PHYTX Control4 registers: Similar to Rule ①, here data is written to the TX Control3 and TX Control4 registers of the PHY through the P2M interface. These two registers store different parameters or control information related to the FS / LF update. For example, TX Control3 contains content related to the equalizer parameter adjustment in the fast settling mode, while TX Control4 involves some configurations in the long reach transmission mode.

[0112] Check the P2M write acknowledge signal: After a write operation, it is necessary to check the P2M write acknowledge signal to ensure that the write operation is correctly received and processed by the PHY. This is an important step to ensure the accuracy of data transmission and the stability of the system.

[0113] Check that the phystatus signal is pulled low: The phystatus signal is the status signal output by the PHY, which can reflect various status information of the physical layer. Checking that the phystatus signal is pulled low is to confirm that the equalizer parameter update operation has the expected impact on the physical layer status. For example, when updating the parameters related to FS / LF, it is expected that the physical layer enters a specific state, and checking that the phystatus signal is pulled low is used to verify whether this state transition is successful. If the phystatus signal is not pulled low as expected, it means that the equalizer parameter update has not taken effect, or there are other problems with the physical layer, and further analysis and debugging are required.

[0114] The above rules are to ensure the correctness and reliability of the Pipe signal EQ process. Through the write operation of the register and the check of the relevant signals, problems that may occur during the equalizer configuration process can be detected and solved in a timely manner, ensuring the normal operation and performance optimization of the high-speed serial communication system.

[0115] The described Pipe signal low-power process check module is used to verify the operation of the PIPE interface in the low-power mode. With the increasingly strict requirements for power consumption, PCIe devices need to have a low-power mode to reduce energy consumption. This module will check whether the process of the device entering and exiting the low-power mode is correct, whether the signal status in the low-power mode meets the requirements, and whether the response when recovering from the low-power mode to the normal working mode is timely and correct. For example, check whether unnecessary circuit modules can be correctly turned off in the low-power mode to save power, and at the same time be able to wake up quickly and operate normally when it is necessary to resume work.

[0116] The rules of the described Pipe signal low-power process check module are as follows:

[0117] ① When L0 enters the L0s state, in high-speed serial communication protocols such as PCIe, L0 is the normal working state and L0s is a low-power state. When the system needs to enter the L0s state from the L0 state, there will be the following series of signal changes and check steps in sequence:

[0118] TXdata issues EIOS: The transmission data channel (TXdata) issues an Electrical Idle Ordered Set (EIOS). The EIOS is a specific signal sequence used to indicate that the transmitting end is about to enter the idle state, which is a pre-signal for entering the low-power state. For example, the transmitting end notifies the receiving end and other relevant modules by sending the EIOS that it is ready to stop sending valid data and enter the low-power mode.

[0119] Check that TXelec_idle is pulled high: The transmission electrical idle signal (TXelec_idle) is pulled high. This indicates that the transmitting end has entered the electrical idle state, that is, there is no valid data signal being transmitted on the transmission line. The pulled-high TXelec_idle signal is an important sign of entering the L0s state, indicating that the physical layer circuit of the transmitting end has stopped the normal data transmission operation and entered a low-power idle mode.

[0120] Check that power_down equals 2’b01: The power_down signal is related to power consumption control. When it is checked that power_down equals 2’b01, it means that the system has entered the specific power consumption control mode in the L0s state as expected. Here, 2’b01 is a binary code representing a specific power consumption state setting, corresponding to operations such as turning off some unnecessary circuit modules or reducing the working voltage and frequency of some circuits to achieve the purpose of low power consumption.

[0121] Check that phystatus is pulled high: The physical layer status signal (phystatus) is pulled high. The phystatus signal can reflect various status information of the physical layer. The pulled-high phystatus signal indicates that the physical layer has successfully entered the L0s state and the relevant status information has been updated. For example, it indicates that the link status has switched from the normal working state to the low-power L0s state, and various parameters and configurations of the physical layer have been adjusted to the state suitable for the L0s state.

[0122] ② When the system needs to recover from the low-power L0s state to the normal L0 working state, the following steps are taken for signal checking:

[0123] Observe that phystatus is pulled low: First, it is observed that the phystatus signal is pulled low, which indicates that the physical layer is transitioning from a specific state in the L0s state to the normal working state. The pulled-low phystatus signal is a starting sign of the state transition, indicating that the state of the physical layer is changing.

[0124] TXdata sends out FTS: TXdata sends out a Fast Training Sequence (FTS). FTS is a signal sequence used for quickly re - establishing link communication and synchronization. When recovering from a low - power state, sending FTS can help the receiving end quickly lock onto the signal, re - establish the correct data - transmission timing and parameters, so that the system can quickly and stably return to the normal working state.

[0125] Check TXelec_idle pulled low: Finally, check that TXelec_idle is pulled low, which indicates that the transmitter has ended the electrical idle state and started sending valid data signals, that is, the system has successfully switched back from the L0s low - power state to the normal L0 working state, and the physical - layer circuit of the transmitter has restored the normal data - sending function.

[0126] ③ When the system enters the L1 state from L0, and L1 is a state with lower power consumption than L0s. When the system needs to enter the L1 state from L0, the signal changes and the checking process are as follows:

[0127] TXdata sends out EIOS: Similar to entering L0s from L0, the transmitter sends out EIOS through TXdata to notify the system that it is about to enter a lower - power state.

[0128] Check TXelec_idle pulled high: Check that TXelec_idle is pulled high to confirm that the transmitter has entered the electrical idle state, which is an important sign of entering the L1 state.

[0129] Check power_down equal to 2’b10: Here, check that power_down is equal to 2’b10. Different from the power_down value when entering L0s, 2’b10 represents a specific power - consumption control mode in the L1 state. In this mode, the power consumption is lower than that in the L0s state, and more circuit modules will be turned off or the power consumption of the circuit will be further reduced.

[0130] Check phystatus pulled high: Finally, check that phystatus is pulled high, indicating that the physical layer has successfully entered the L1 low - power state and the relevant status information has been updated, and the system is in a standby state with lower power consumption.

[0131] ④ When the system enters the L0 state from L1, when the system needs to recover from the L1 low - power state to the normal L0 working state, the following steps are used for checking:

[0132] phystatus pulled low: First, the phystatus signal is pulled low, which marks that the physical layer starts to convert from the L1 state to the L0 state, and the status information is changing.

[0133] TXdata sends TS1 / TS2: TXdata sends Training Sequence 1 (TS1) or Training Sequence 2 (TS2). TS1 and TS2 are signal sequences used for link training and initialization. When recovering from a low-power state, sending these sequences can help re-establish the electrical parameters of the link, clock synchronization, etc., to ensure that data can be transmitted correctly.

[0134] Check if TXelec_idle is pulled low: Finally, check if TXelec_idle is pulled low, which means that the transmitter has ended the electrical idle state and started sending valid data signals. The system has successfully switched back from the L1 low power state to the normal L0 working state and restored normal data transmission function.

[0135] The above rules specify in detail the signal changes and inspection points when the Pipe signal switches between different low-power states. By monitoring and checking these signals, the correctness and reliability of the system during the low-power mode switching process can be ensured, and effective power consumption management and system performance assurance can be achieved.

[0136] The Pipe signal Lane_margin check module is used to check the lane margin (LaneMargin) of the PIPE interface signal. The lane margin refers to the degree of noise and interference that the signal can tolerate during transmission, which reflects the reliability of signal transmission. This module simulates different degrees of noise and interference to check whether the signal can still be transmitted correctly under various harsh conditions, thereby evaluating the robustness of the system. For example, gradually increase the noise level and observe under what circumstances data transmission errors will occur, so as to determine the size of the lane margin and compare it with the design requirements to ensure that the system meets the reliability indicators.

[0137] The rules of the Pipe signal Lane_margin check module are as follows:

[0138] ① Start Lane Margin command:

[0139] M2P signal interface sends a write to Rx_margin contol register: M2P signal interface is the communication interface between the master device and the physical layer (PHY). When starting Lane Margin check, the master device writes relevant commands or parameters to the Rx_margincontol register through the M2P interface. The Rx_margin contol register contains information such as starting, stopping, and setting check parameters for controlling Lane Margin check. For example, it may be possible to set the channel to be checked, the mode of check (such as voltage margin, timing margin, etc.), the range of check, etc.

[0140] P2M signal write acknowledge signal: After the master device writes data to the Rx_margin contol register, it is necessary to check the write acknowledge signal of the P2M signal. This write acknowledge signal is the response of the PHY to the write operation of the master device and is used to confirm whether the PHY has correctly received the written command and parameters. If the correct write acknowledge signal is not received, it may mean that the write operation has failed, and it is necessary to check whether the M2P interface communication is normal, whether the register address is correct, and whether there is a problem with the PHY module, etc.

[0141] ② Margin signal PHY update check:

[0142] The P2M signal interface issues a write to the Rx_margin status register: During the Lane Margin check, the PHY updates the Rx_margin status register according to the progress and results of the check. At this time, relevant information is written to this register through the P2M signal interface, and this information includes the current check status (such as in progress, completed, error occurred, etc.), the detected margin value, error count, etc.

[0143] M2P signal write acknowledge signal: Similarly, after the PHY writes data to the Rx_margin status register, the master device needs to check the write acknowledge signal of the M2P signal to confirm whether the master device has correctly received the status information updated by the PHY. This step is very important for the master device to understand the situation of the Lane Margin check in real time. The master device can judge whether the check is proceeding normally and whether further measures need to be taken (such as adjusting the check parameters, stopping the check, etc.) based on the received status information.

[0144] Lane Margin check is crucial for ensuring the reliability of high-speed serial communication links. Through the above two rules, the process of Lane Margin check can be effectively controlled and monitored, problems that may occur during the check can be discovered and processed in a timely manner, and the communication link can be ensured to operate stably and reliably under various working conditions. For example, in high-speed buses such as PCIe, good Lane Margin can ensure that data can be correctly transmitted under different circuit board layouts, power fluctuations, temperature changes, etc., and avoid data errors or link failures caused by signal quality problems.

[0145] The present invention is mainly applied to the development and verification of PCIe chips and can be seamlessly embedded into the design code without affecting the synthesis and backend processes of the design code.

[0146] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention.

Claims

1. A physical layer PIPE interface enhanced verification method based on PCIE protocol, characterized in that: Set up a PIPE_WRAPPER architecture and interact with the outside through the phy_mac_pipe interface and the phy_pcs_pipe interface. The PIPE_WRAPPER architecture includes multiple modules, which are responsible for different aspects of PIPE interface verification. The PIPE_WRAPPER architecture includes: Pipe signal initial value check module, Pipe signal data insertion module, Pipe interactive signal delay control module, Pipe signal EQ process check module, Pipe signal low power consumption process check module and Pipe signal Lane_margin check module.

2. The method for enhancing verification of a physical layer PIPE interface based on a PCIE protocol according to claim 1, characterized in that: The Pipe signal initial value check module checks the initial value of the signal of the PIPE interface during the system startup or initialization phase. The signal names checked by the Pipe signal initial value check module include: PhyStatus, TxDetectRx / Loopback, TxElecIdle, TxCompliance, RxPolarity, PowerDown, TxMargin, TxDeemp, and Rate. The corresponding reset initial value check rules are: PhyStatus is pulled high, TxDetectRx / Loopback is pulled low, TxElecIdle is pulled high, TxCompliance is pulled low, RxPolarity is pulled low, PowerDown==4'b0010, TxMargin==3'b000, TxDeemp==1, and Rate==2.5G.

3. The method for enhancing verification of a physical layer PIPE interface based on a PCIE protocol according to claim 1, characterized in that: The Pipe signal data insertion module includes a signal name modification timing module, a data sequence value modification module and a sequence value configuration modification module. The signal name modification timing module is used to determine when to modify the name of the Pipe signal. The data sequence value modification module is responsible for modifying a large number of data sequence values. The sequence value configuration modification module is used to configure the specific modification value of the data sequence value.

4. The method for enhancing verification of a physical layer PIPE interface based on a PCIE protocol according to claim 3, characterized in that: The data modification sequence value module supports modification of 16*33 symbols, and the value range provided by the configuration modification sequence value module is 0 to 16*33.

5. A physical layer PIPE interface enhanced verification method based on PCIE protocol according to claim 3 or 4, characterized in that: The timing and method of modifying the signal name provided by the signal name modification timing module are as follows: When to modify rx_data: mode0: when the rate changes from gen2 to gen3, modify rx_data; mode1: when the rate changes from gen4 to gen5, modify rx_data; mode2: when the rate changes from gen5 to gen6, modify rx_data; tx_data modification time: mode0: when the rate changes from gen2 to gen3, modify tx_data; mode1: when the rate changes from gen4 to gen5, modify tx_data; mode2: When the rate changes from gen5 to gen6, modify tx_data.

6. The method for enhancing verification of a physical layer PIPE interface based on a PCIE protocol according to claim 1, characterized in that: The Pipe interactive signal delay control module is used for MAC and PHY interactive debugging, and the delay control of the pipe interactive signal is realized by setting the MAC output signal control module and the PHY output signal control module.

7. The method for enhancing verification of a physical layer PIPE interface based on a PCIE protocol according to claim 1, characterized in that: The Pipe signal EQ process checking module is used to check the EQ process of the PIPE interface signal. The rules of the Pipe signal EQ process checking module are as follows: ① Local Preset Coefficients update: First, the M2P interface sends a write to the PHYTX Control5 register, and then checks the P2M write acknowledge signal; ②Local FS / LF update: First, the P2M interface sends a write to the PHYTX Control3 and PHYTX Control4 registers, then checks the P2M write acknowledge signal, and finally checks if the phystatus signal is pulled low.

8. The method for enhancing verification of a physical layer PIPE interface based on a PCIE protocol according to claim 1, characterized in that: The Pipe signal low power consumption process checking module is used to verify the working condition of the PIPE interface in the low power consumption mode. The rules of the Pipe signal low power consumption process checking module are as follows: ①L0 enters L0s state, with the following signal changes and inspection steps: TXdata sends EIOS, checks TXelec_idle is pulled high, checks power_down is equal to 2'b01, and checks phystatus is pulled high; ②L0s enters the L0 state, and the following signal changes and inspection steps are performed in sequence: phystatus is pulled low, TXdata sends FTS, and checks TXelec_idle is pulled low; ③L0 enters L1 state, with the following signal changes and inspection steps: TXdata sends EIOS, checks TXelec_idle is pulled high, checks power_down is equal to 2'b10, and checks phystatus is pulled high; ④L1 enters L0 state, and the following signal changes and inspection steps are performed in sequence: phystatus is pulled low, TXdata sends TS1 / TS2, and checks that TXelec_idle is pulled low.

9. The method for enhancing verification of a physical layer PIPE interface based on a PCIE protocol according to claim 1, characterized in that: The Pipe signal Lane_margin checking module is used to check the channel margin of the PIPE interface signal. The rules of the Pipe signal Lane_margin checking module are as follows: ① Start Lane Margin command: First, the M2P signal interface sends a write to the Rx_margin contol register, and then the P2M signal writes the acknowledge signal; ②Margin signal PHY update check: First, the P2M signal interface sends a write to the Rx_margin status register, and then the M2P signal writes the acknowledge signal.

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