Page buffer, method of operating page buffer, memory device, and memory system

Abstract

The embodiment of the invention discloses a page buffer, an operation method of the page buffer, a memory device and a memory system, relates to the field of semiconductors, and can simplify a circuit structure and reduce cost and occupied space. The page buffer includes a plurality of latch circuits. Each latch circuit comprises a reset control circuit, a setting control circuit, a data transmission circuit and a latch transmission circuit. The reset control circuit is coupled to the first data node and is configured to receive a first power supply voltage to determine a potential of the first data node. The setting control circuit is coupled to the second data node and is configured to receive the first power supply voltage to determine a potential of the second data node. The data transmission circuit is coupled to the first data node and the second data node, and is configured to receive a second power supply voltage. The latch transfer circuit is coupled to the first data node, the second data node, and the sensing node. Wherein the first power supply voltage is higher than the second power supply voltage.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and relate to, but are not limited to, a page buffer and its operation method, a memory device, and a memory system. Background Art

[0002] Semiconductor memories can be roughly divided into two categories depending on whether they retain the stored data when power is off; these two categories of semiconductor memories are: volatile memories and non-volatile memories. Volatile memories lose the stored data when power is off, and non-volatile memories retain the stored data when power is off. In non-volatile memories, the memory cells are respectively connected to bit lines and word lines, and thus have good random access time characteristics.

[0003] With the improvement of the integration degree of memories, the area occupied by the page buffer in the peripheral circuit of the memory device is limited and there is a need for its area to tend to decrease. Therefore, the number of components constituting the page buffer also needs to be streamlined. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a page buffer and its operation method, a memory device, and a memory system.

[0005] On the one hand, embodiments of the present application provide a page buffer. The page buffer includes a plurality of latch circuits. Each of the latch circuits includes a reset control circuit, a set control circuit, a data transfer circuit, and a latch transfer circuit. The reset control circuit is coupled to a first data node and is configured to receive a first power supply voltage to determine the potential of the first data node. The set control circuit is coupled to a second data node and is configured to receive the first power supply voltage to determine the potential of the second data node. The data transfer circuit is coupled to the first data node and the second data node and is configured to receive a second power supply voltage. The latch transfer circuit is coupled to the first data node, the second data node, and a sense node. Wherein, the first power supply voltage is higher than the second power supply voltage.

[0006] In some examples, the set control circuit is configured to respond to the set signal being in an enabled state, and the second data node and the first data node are respectively in a first logic level and a second logic level; the first logic level is higher than the second logic level.

[0007] The reset control circuit is configured to respond to the reset signal being in an enabled state, and the first data node and the second data node are respectively in the first logic level and the second logic level;

[0008] The latch transfer circuit is configured to couple the second data node to the sense node, where the sense node is at the second logic level, in response to the transfer signal being in an enabled state and the first data node and the second data node being at the first logic level and the second logic level, respectively.

[0009] In some examples, the latch transfer circuit is further configured to keep the sense node at the first logic level in response to the transfer signal being in an enabled state and the first data node and the second data node being at the second logic level and the first logic level, respectively, when the sense node is at the first logic level.

[0010] In some examples, the data transfer circuit includes a first transistor and a second transistor. The control electrode of the first transistor is coupled to the first data node, the first electrode of the first transistor is coupled to a second power supply voltage node, and the second electrode of the first transistor is coupled to the second data node. The control electrode of the second transistor is coupled to the second data node, the first electrode of the second transistor is coupled to the second power supply voltage node, and the second electrode of the second transistor is coupled to the first data node.

[0011] In some examples, the reset control circuit includes a third transistor. The control electrode of the third transistor receives the reset signal, the first electrode of the third transistor is coupled to a first power supply voltage node, and the second electrode of the third transistor is coupled to the first data node.

[0012] The set control circuit includes a fourth transistor. The control electrode of the fourth transistor receives the set signal, the first electrode of the fourth transistor is coupled to the first power supply voltage node, and the second electrode of the fourth transistor is coupled to the second data node.

[0013] In some examples, the latch transfer circuit includes a fifth transistor and a sixth transistor in a series cascade relationship; the fifth transistor and the sixth transistor are N-type transistors.

[0014] In some examples, the control electrode of the fifth transistor is coupled to the first data node, the first electrode of the fifth transistor is coupled to the second data node, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor. The control electrode of the sixth transistor receives the transfer signal, and the second electrode of the sixth transistor is coupled to the sense node.

[0015] In some examples, the latch circuit further includes a voltage stabilizing circuit. The voltage stabilizing circuit is coupled to the first data node and the second data node and is configured to stabilize the voltage difference between the first data node and the second data node.

[0016] In some examples, the voltage regulation circuit includes a capacitor. A first plate of the capacitor is coupled to the first data node, and a second plate of the capacitor is coupled to the second data node.

[0017] In some examples, the voltage regulation circuit includes a seventh transistor. A control pole of the seventh transistor is coupled to the second data node, and a first pole and a second pole of the seventh transistor are both coupled to the first data node.

[0018] In some examples, the page buffer further includes a bit line control circuit and a bit line discharge circuit. The bit line control circuit is coupled to a first power supply voltage node, a bit line, and the sense node, and is configured to control a potential level of the sense node based on a current level of the bit line during a sensing operation. The bit line discharge circuit is coupled between the bit line and a second power supply voltage node, and is configured to discharge the potential level of the bit line in response to a discharge control signal.

[0019] In this application, the latch transfer circuit in the page buffer is coupled to the first data node and the second data node. Without coupling the latch transfer circuit to a ground voltage node, the connection or disconnection between the latch transfer circuit and the sense node is controlled only based on the logic levels of the first data node Data and the second data node Data_bar obtained by the combined action of the data transfer circuit 6203, the setting circuit 6202, and the reset circuit 6201. This not only reduces the grounding line structure. Moreover, not directly using an inverter also reduces the number of electronic components (such as transistors), reducing the manufacturing cost of the page buffer and the occupied space of the page buffer in the memory device; especially in the case where the memory device includes a page buffer group or a page buffer for driving a multi-level memory cell type, the manufacturing cost and occupied space of the page buffer can be significantly reduced.

[0020] Moreover, through a simplified circuit structure, the complexity of the signal transmission path between the page buffer and the sense node is reduced, and the loss during the transmission of the level signal is reduced, thereby improving the performance of the memory device as a whole.

[0021] On the other hand, this application provides a memory device. The memory device includes a memory cell array and a plurality of page buffers as provided in any of the above examples. The memory cell array is coupled to a plurality of bit lines. Each of the page buffers is coupled to one of the bit lines and is configured to perform a sensing operation based on the current level of the bit line.

[0022] The beneficial effects achieved by the memory device provided in this example are the same as those of the page buffer provided in any of the above examples, and will not be elaborated here.

[0023] In another aspect, the present application provides a memory system. The memory system includes one or more memory devices and a memory controller provided as in the above aspect. The memory controller is coupled to the memory device and is configured to control the memory device.

[0024] The beneficial effects achieved by the memory system provided in this example are the same as those of the memory device provided in the above example, and will not be elaborated here.

[0025] In yet another aspect, the present application provides an operation method for a page buffer. The page buffer includes a plurality of latch circuits, each latch circuit including a reset control circuit coupled to a first data node, a set control circuit coupled to a second data node, and a data transmission circuit coupled to both the first data node and the second data node. And, a latch transmission circuit coupled to the first data node, the second data node, and a sense node.

[0026] The operation method includes:

[0027] In the reset stage, the reset signal is set to an enabled state; the reset control circuit, in response to the enabled state of the reset signal, sets the first data node and the second data node to a first logic level and a second logic level respectively; the first logic level is higher than the second logic level.

[0028] In the read stage after the reset stage, the sense node is at the first logic level; and, the transmission signal is set to an enabled state, and the latch transmission circuit, in response to the transmission signal being in the enabled state, couples the second data node to the sense node, causing the sense node to change from the first logic level to the second logic level.

[0029] In some examples, the operation method further includes:

[0030] In the set stage, the set signal is set to an enabled state; the set control circuit, in response to the enabled state of the set signal, sets the first data node and the second data node to the second logic level and the first logic level respectively.

[0031] In the read stage after the set stage, the sense node is at the first logic level; and, the latch transmission circuit disconnects the second data node from the sense node, and the level of the sense node remains at the first logic level.

[0032] The operation method of the page buffer provided by this application includes two processes. One is based on the level signals stored in the first data node and the second data node during the reset stage. During the read stage, the second data node is coupled to the sensing node through the enabling state of the transmission signal, causing the level of the sensing node to change. The other is based on the level signals stored in the first data node and the second data node during the setting stage. During the read stage, even in response to the enabling state of the transmission signal, the second data node is not connected to the sensing node, and the level of the sensing node is maintained. These two processes are based on different page buffers including multiple latch circuits. Different latch circuits may have different states during the same time period, which is characterized in that the data read during the read stage of the page buffer operation process can be the data stored during the setting stage, or the data stored during the reset stage. In this way, during the read stage, the latch circuits of different page buffers have different effects on the level of the sensing node, so that different data of different page buffers can be obtained through the sensing node. The circuit structure of the page buffer provided by this application can simultaneously realize the reading of data in different states of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the drawings, like reference numerals can describe like components in different views. Like reference numerals with different letter suffixes can represent different examples of like components. The drawings generally illustrate the various embodiments discussed herein by way of example and not limitation.

[0034] Figure 1 Schematic diagram of the structure of an electronic system provided by an embodiment of this application;

[0035] Figure 2 Schematic diagram of the structure of a memory card provided by an embodiment of this application;

[0036] Figure 3 Schematic diagram of the structure of a solid state drive (SSD) provided by an embodiment of this application;

[0037] Figure 4 and Figure 5 Schematic diagram of the structure of a memory including a memory cell array and a peripheral circuit provided by an embodiment of this application;

[0038] Figure 6 Schematic diagram of the structure of a memory including a page buffer group provided by an embodiment of this application;

[0039] Figure 7 Schematic diagram of a page buffer provided by an exemplary embodiment;

[0040] Figure 8 Schematic diagram of a page buffer provided by an embodiment of this application Figure 1 ;

[0041] Figure 9 Schematic diagram of a page buffer provided by an embodiment of the present application Figure 2 ;

[0042] Figure 10 Schematic diagram of a latch circuit of a page buffer provided by an embodiment of the present application;

[0043] Figure 11 Schematic diagram of a partial logic circuit of a latch circuit of a page buffer provided by an embodiment of the present application Figure 1 ;

[0044] Figure 12 Schematic diagram of a partial logic circuit of a latch circuit of a page buffer provided by an embodiment of the present application Figure 2 ;

[0045] Figure 13 Schematic diagram of a partial logic circuit of a latch circuit of a page buffer provided by an embodiment of the present application Figure 3 ;

[0046] Figure 14 Schematic diagram of a partial logic circuit of a latch circuit of a page buffer provided by an embodiment of the present application Figure 4 ;

[0047] Figure 15 Schematic diagram of a logic circuit of a latch circuit of a page buffer provided by an embodiment of the present application;

[0048] Figure 16 Schematic diagram of the structure of a voltage stabilizing circuit of a page buffer provided by an embodiment of the present application Figure 1 ;

[0049] Figure 17 Schematic diagram of a logic circuit of a voltage stabilizing circuit of a page buffer provided by an embodiment of the present application Figure 1 ;

[0050] Figure 18 Schematic diagram of a logic circuit of a voltage stabilizing circuit of a page buffer provided by an embodiment of the present application Figure 2 ;

[0051] Figure 19 Schematic diagram of a logic circuit of a bit line control circuit and a bit line discharge circuit of a page buffer provided by an embodiment of the present application;

[0052] Figure 20 Schematic diagram of a logic circuit of a page buffer provided by an embodiment of the present application;

[0053] Figure 21A Timing of a latch circuit of a page buffer provided by an embodiment of the present application Figure 1 ;

[0054] Figure 21B The timing of a latch circuit of a page buffer provided by an embodiment of the present application Figure 2 ;

[0055] Figure 22 is Figure 21A a flowchart of an operation method of a page buffer provided

[0056] Figure 23 is Figure 21B a flowchart of an operation method of a page buffer provided Detailed implementation manners

[0057] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0059] The "first", "second" and similar terms used in the present application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or objects appearing before the term cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" or "joined" are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

[0060] To thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to explain the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other implementation manners.

[0061] Such as Figure 1As shown, an embodiment of the present application shows an electronic system 10. By way of example, the electronic system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device 32 therein.

[0062] Please continue to refer to Figure 1 , the electronic system 10 may include a host 20 and a memory system 30.

[0063] The host 20 may be a processor of the electronic device (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP))). The host 20 may be configured to send data to the memory system 30 or receive data from the memory system 30.

[0064] The memory system 30 includes a memory controller 31 and one or more memory devices 32, as well as other integrated circuit structures for signal transmission. Among them, the memory controller 31 and one or more memory devices 32 may be integrated and packaged in the same storage device. In this way, it is beneficial to apply the memory system 30 to different types of terminal electronic products.

[0065] By way of example, the types of storage devices integrating the memory controller 31 and one or more memory devices 32 include: universal flash storage (UFS) or embedded multimedia card (eMMC), and other types of storage devices.

[0066] There are various ways of integrating the integrated circuit of the storage device. For example, it may be a memory card 40 formed by integrating a single memory device 32 and a memory controller 31 (as Figure 2 shown), or it may be a solid state drive 50 formed by integrating multiple memory devices 32 and a memory controller 31 (as Figure 3 shown).

[0067] Exemplarily, the memory card 40 may include one or more types of storage devices such as a Personal Computer Memory Card International Association (PC) card, a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multi-Media Card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMC micro), a Secure Digital (SD) card (SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), and a Universal Flash Storage (UFS).

[0068] Wherein, please continue to refer to Figure 2 , the memory card 40 further includes a memory card connector 41. The memory card connector 41 is configured to couple the memory card 40 to a host (e.g., Figure 1 the host 20 in). For example, the memory card connector 41 includes gold fingers.

[0069] Alternatively, please continue to refer to Figure 3 , the solid-state drive (SSD) 50 further includes an SSD connector 51. The SSD connector 51 is configured to couple the SSD 50 to a host (e.g., Figure 1 the host 20 in). For example, the SSD connector 51 includes gold fingers.

[0070] It can be understood that the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0071] The memory controller 31 integrated in the same storage device as described above is coupled to the memory device 32 (and the host 20), and the memory controller 31 is configured to control the memory device 32.

[0072] Exemplarily, the memory controller 31 can be designed to operate in a low-duty-cycle environment. For example, it can be used to operate in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive; or in other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. Additionally, the memory controller 31 can be designed to operate in a high-duty-cycle environment, for example, to operate in a solid-state drive (SSD) or an embedded Multi-Media Card (eMMC). Among them, the SSD or eMMC can be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0073] Furthermore, the memory controller 31 can manage the data in the memory device 32 and communicate with the host 20. The memory controller 31 can be configured to control operations such as reading, erasing, and programming of the memory device 32; it can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 32, including but not limited to bad block management, garbage collection, logical-to-physical address conversion, wear leveling, etc.; it can also be configured to process the error checking and correction (ECC) of the data read from or written to the memory device 32.

[0074] In addition, the memory controller 31 can also perform any other suitable functions, such as formatting the memory device 32, or communicating with external devices according to a specific communication protocol (for example, Figure 1communicate with the host 20. For example, the memory controller 31 can communicate with the host 20 through at least one of various interface protocols. Among them, the interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, and one or more of the other protocols.

[0075] The above memory device 32 can include, but is not limited to, one or more memories such as NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetoresistive Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0076] Based on the above description, in this application, the memory device 32 is a semiconductor memory. For example, a solid-state electronic device (such as a NAND-type memory) that stores data information made by semiconductor integrated circuit technology is used as an example for the subsequent embodiments. The subsequent examples of this application do not limit the specific internal structure of the memory device 32.

[0077] It can be understood that, for the convenience of distinguishing the adaptive adjustments made by the memory device 32 for different scenarios, for example, based on the various structures of the memory device 32 exemplified in the foregoing content, the memory device (e.g., NAND-type memory) provided in the subsequent examples of the present application will be described with the memory device 60.

[0078] As Figure 4 shown, in some embodiments, the memory device 60 may include a memory cell array 61 and a peripheral circuit 62 coupled to the memory cell array 61 and other circuit structures.

[0079] The memory cell array 61 is coupled to a plurality of bit lines BL. Exemplarily, the memory cell array 61 may be a NAND flash memory cell array. For example, the memory cell array 61 is a circuit structure arranged in the form of an array of NAND memory strings 611. Each NAND memory string 611 extends vertically on the substrate. Exemplarily, each NAND memory string 611 may include a plurality of memory cells (cells) coupled in series and vertically stacked. Among them, each memory cell transmits signals in a state of maintaining a continuous analog value (e.g., voltage or charge), and the analog value of the memory cell depends on the number of electrons captured in the memory cell region.

[0080] Exemplarily, each memory cell in the memory cell array 61 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. The present application does not limit this.

[0081] In some examples, the storage type of the above-mentioned memory cells includes any one of single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), etc.

[0082] Exemplarily, each memory cell of the SLC can store one bit of data and has two possible first storage states and second storage states. Among them, the first storage state (e.g., "0") corresponds to a first threshold voltage range, and the second storage state (e.g., "1") corresponds to a second threshold voltage range. In this way, the second storage state (e.g., "1") is used as the erased state, and the first storage state (e.g., "0") is used as the programmed state.

[0083] As another example, each memory cell of the MLC can store two bits of data and has four possible first storage states, second storage states, third storage states, and fourth storage states. Among them, the first storage state (e.g., "11") corresponds to a first threshold voltage range, the second storage state (e.g., "01") corresponds to a second threshold voltage range, the third storage state (e.g., "10") corresponds to a third threshold voltage range, and the fourth storage state (e.g., "00") corresponds to a fourth threshold voltage range. Thus, the fourth storage state (e.g., "00") is used as the erased state, and the first storage state (e.g., "11"), the second storage state (e.g., "01"), and the third storage state (e.g., "10") are used as the programmed states.

[0084] Similarly, each memory cell of the TLC can store three bits of data and has eight possible storage states. The eight storage states respectively correspond to eight threshold voltage ranges, and the specific storage states are not elaborated here. Among them, one of the eight threshold voltage ranges is used as the erased state (e.g., "111"), and the remaining seven threshold voltage ranges are used as the programmed states. Also, each memory cell of the QLC can store four bits of data and has sixteen possible storage states. The sixteen storage states respectively correspond to sixteen threshold voltage ranges, and the specific storage states are not elaborated here. Among them, one of the sixteen threshold voltage ranges is used as the erased state (e.g., "1111"), and the remaining fifteen threshold voltage ranges are used as the programmed states.

[0085] Please continue to refer to Figure 4 , the above-mentioned peripheral circuit 62 can be coupled to the memory cell array 61 through a bit line (Bit Line, BL), a word line (Word Line, WL), a source line, a source select gate (Source Select Gate, SSG), and a drain select gate (Drain Select Gate, DSG). The peripheral circuit 62 is configured to apply voltage signals and / or current signals to each target memory cell and sense voltage signals and / or current signals from each target memory cell via the bit line BL, the word line WL, the source SL, the source select gate SSG, or the drain select gate DSG, etc., to implement the logical operations (e.g., programming, reading, or writing operations) of the memory cell array 61.

[0086] Exemplarily, the peripheral circuit 62 includes various types of circuit structures formed using metal-oxide-semiconductor (Metal-Oxide-Semiconductor, MOS) transistors. For example, as Figure 5As shown in the figure, the peripheral circuit 62 may include various circuit structures such as a row decoder / word line driver 620, a page buffer (PB) / sense amplifier 621, a column decoder / bit line driver 623, a voltage generator 624, a control logic unit 625, a latch circuit 626, an interface 627, and a data bus 628.

[0087] Furthermore, as Figure 6 shown in the figure, the peripheral circuit 62 may include a page buffer group composed of multiple page buffers 621. The page buffer group may be coupled to the memory cell array 61 via multiple bit lines (BL1 to BLk). One page buffer 621 is coupled to the memory cell array 61 via one bit line. For example, as Figure 6 shown in the figure, multiple page buffers 621 may be respectively coupled to the memory cell array 61 via corresponding bit lines BL1 to BLk.

[0088] Based on the above, in some embodiments, the page buffer 621 of the peripheral circuit 62 includes multiple latches 6211. By way of example, as Figure 7 shown in the figure, the page buffer 621 of the peripheral circuit 62 includes at least five latches 6211.

[0089] Among them, the latch 6211 includes two inverters 6212 connected end to end, a data transfer circuit 6213, and other electronic components. The two inverters 6212 include at least four transistors. In this way, when the page buffer 621 includes multiple latches 6211, especially for TLC and QLC type memory cells, the page buffer 621 needs to set a larger number of latches 6211 to implement data reading or programming, and then the number of transistors in each page buffer 621 is larger. Furthermore, when the peripheral circuit 62 implements logical (e.g., programming, reading, or writing) operations through the page buffer group (see Figure 6 ), the number of electronic components of multiple page buffers 621 is superimposed, resulting in a sharp increase in the space occupied by the peripheral circuit 62 in the memory device 60 (e.g., occupying nearly 1 / 3 of the space in the memory device 60), and reducing the energy efficiency ratio of the memory device 60.

[0090] To solve the above problems, as Figures 8 - 20 shown in the figure, the present application provides a structure of a page buffer 622 to simplify the circuit structure and reduce the occupied space and manufacturing cost of the page buffer 622 in the memory device 60.

[0091] In some embodiments, as Figure 8 shown in the figure, the page buffer 622 includes a bit line control circuit 6221, a bit line discharge circuit 6222, and multiple latch circuits 6223.

[0092] The bit line control circuit 6221 is coupled to the first power supply voltage node N1, the bit line BL, and the sense node SO, and is configured to control the potential level of the sense node SO based on the current level of the bit line BL during a sensing operation. For example, it can be determined whether to charge the bit line according to the programmed verification result latched in the latch circuit 6223. For example, when the programmed verification result indicates that the memory cell reaches the target threshold voltage, the bit line BL coupled to the memory cell can be charged to the programming inhibition bit line voltage (e.g., VDD) through the bit line control circuit 6221 to inhibit programming; when the programmed verification result indicates that the memory cell does not reach the target threshold voltage, the bit line BL coupled to the memory cell can be adjusted to the normal programming bit line voltage (e.g., VSS) or the bit line BL forced voltage (greater than VSS and less than VDD) through the bit line control circuit 6221 to continue programming.

[0093] The bit line discharge circuit 6222 is coupled between the bit line BL and the second power supply voltage node N2, and is configured to discharge the potential level of the bit line BL in response to a discharge control signal (e.g., VDD).

[0094] It can be understood that the level of the first power supply voltage node N1 is VDD, and the level of the second power supply voltage node N2 is VSS. The identification symbol of the "node" adopted in the examples of this application only exemplarily characterizes the feature of the node transmitting the level signal, and does not limit the magnitude of the actual level signal transmitted by the node.

[0095] Multiple latch circuits 6223 are all coupled to the sense node SO, and charge and discharge the level of the sense node SO under the drive of the bit line control circuit 6221 and the bit line discharge circuit 6222. For example, as Figure 9 shown in the page buffer 622, the number of the multiple latch circuits 6223 is six. The six latch circuits 6223 can include a sense latch (SLatch), a low voltage latch (LVT Latch), three data latches (DLatch), and a cache latch (C Latch).

[0096] Among them, the sense latch S Latch can be used to store inhibition information and verification information from a verification operation.

[0097] The cache latch C Latch is used for data exchange with the outside. For example, first transfer the external data to the cache latch C Latch, and then transfer it to the sense latch SLatch through the cache latch C Latch. Another example is to transfer the data in the sense latch S Latch to the cache latch C Latch, and then transfer it to the outside through the cache latch C Latch. The outside can be a memory controller 31 or a host 20, etc. Another example is that the cache latch C Latch can also be used for other functions, such as for temporarily storing verification information.

[0098] The data latch D Latch can be used to latch the data of a specified page of a storage unit.

[0099] The low-voltage latch LVT Latch can be used to store inhibition information and the adjusted verification information from a verification operation.

[0100] In some examples, the storage types based on the storage unit include storage types such as SLC, MLC, TLC, and QLC.

[0101] If the storage unit is SLC, the latching circuit 6223 in the page buffer 622 may include a cache latch. The cache latch is used to latch the data of the storage unit.

[0102] If the storage unit is MLC, in addition to the cache latch C Latch, the page buffer 622 may also include a data latch D Latch. Among them, the data latch D Latch can be used to latch the lower-page data of the storage unit, and the cache latch C Latch can be used to latch the upper-page data of the storage unit.

[0103] If the storage unit is TLC, in addition to the cache latch C Latch, the page buffer 622 may also include two data latches D Latch. Among them, one data latch D Latch can be used to latch the lower-page data of the storage unit, another data latch D Latch can be used to latch the middle-page data of the storage unit, and the cache latch C Latch can be used to latch the upper-page data of the storage unit.

[0104] By analogy, if the storage unit is nLC, the number of data latches D Latch in the page buffer 622 can be (n - 1), and the (n - 1) data latches D Latch respectively latch the data of the specified page of the storage unit, where n is a positive integer greater than 0.

[0105] It can be understood that the sense latch S Latch, the low-voltage latch LVT Latch, the data latch DLatch, and the cache latch C Latch include sub-circuits with some identical structures, and these sub-circuits with identical structures can achieve complete data transmission. Among them, the sense latch S Latch and the cache latch C Latch also include additional electronic components to assist in the realization of data transmission, and the present application does not specifically limit the structures of the additional electronic components. In the subsequent examples, some identical circuit structures of different types of latch circuits 6223 are described. Therefore, the latch circuits 6223 mentioned in the subsequent examples do not limit the types of the latch circuits 6223.

[0106] In some embodiments, as Figure 10 shown, each latch circuit 6223 includes a reset control circuit 6201, a set control circuit 6202, a data transmission circuit 6203, and a latch transmission circuit 6204.

[0107] The reset control circuit 6201 is coupled to the first data node Data and is configured to receive the first power supply voltage V1 to determine the potential of the first data node Data.

[0108] The set control circuit 6202 is coupled to the second data node Data_bar and is configured to receive the first power supply voltage V1 to determine the potential of the second data node Data_bar.

[0109] The data transmission circuit 6203 is coupled to the first data node Data and the second data node Data_bar and is configured to receive the second power supply voltage V2.

[0110] The latch transmission circuit 6204 is coupled to the first data node Data, the second data node Data_bar, and the sense node SO.

[0111] Among them, the first power supply voltage V1 is higher than the second power supply voltage V2. For example, the level of the first power supply voltage V1 is VDD, and the level of the second power supply voltage V2 is VSS, and VDD is greater than VSS.

[0112] In the present application, by coupling the latch transmission circuit 6204 in the page buffer 622 to the first data node Data and the second data node Data_bar, the connection or disconnection between the latch transmission circuit 6204 and the sense node SO is controlled only according to the logic levels of the first data node Data and the second data node Data_bar.

[0113] In this way, without coupling the latch transmission circuit 6204 to the second power supply voltage node N2 (such as Figure 7When the inverter 6212 and the data transmission circuit 6213 are grounded, based on the logic levels of the first data node Data and the second data node Data_bar obtained by the combined action of the data transmission circuit 6203, the setting circuit 6202, and the reset circuit 6201, the latching transmission circuit is controlled to be connected or disconnected from the sensing node. This not only reduces the grounding circuit structure; moreover, not using the inverter 6212 also reduces the number of electronic components (such as transistors), reducing the manufacturing cost and the occupied space of the page buffer 622 in the memory device 60; especially when the memory device 60 includes a page buffer group or a page buffer 622 for driving a multi-level memory cell type, it can significantly reduce the manufacturing cost and the occupied space of the page buffer 622.

[0114] Moreover, through the simplified circuit structure, the complexity of the signal transmission path between the page buffer 622 and the sensing node SO is reduced, and the loss during the transmission of the level signal is reduced, thereby improving the performance of the memory device 60 as a whole.

[0115] In addition, when the occupied area of the page buffer 622 remains unchanged, a larger number of latching circuits 6223 can be set (for example, adding a data latching circuit 6223) to meet the requirements of the memory device 60 with higher-bit data, so that more bits of data information can be stored, which is beneficial to improving the bit density of the memory device 60.

[0116] In some examples, the setting control circuit 6202 is configured to respond to the setting signal set being in the enabled state, and the second data node Data_bar and the first data node Data are respectively at the first logic level and the second logic level. The first logic level is higher than the second logic level.

[0117] For example, the first logic level is a high level, and the second logic level is a low level. It can be understood that "high level" and "low level" are two types of signals representing the relative magnitudes of level signals. For example, the first logic level is VDD, and the second logic level is VSS, and VDD is greater than VSS. In this way, the level of the second data node Data_bar is VDD, and the level of the first data node Data is VSS.

[0118] The reset control circuit 6201 is configured to respond to the reset signal rst being in the enabled state, and the first data node Data and the second data node Data_bar are respectively at the first logic level and the second logic level. For example, the level of the second data node Data_bar is VSS, and the level of the first data node Data is VDD.

[0119] The latch transfer circuit 6204 is configured to couple the second data node Data_bar to the sense node SO, where the sense node SO is at the second logic level (e.g., VSS), in response to the transfer signal rd being in the enabled state and the first data node Data and the second data node Data_bar being at the first logic level and the second logic level, respectively.

[0120] The above transfer signal rd is the signal transmitted from the Rd terminal (refer to Figure 10 ). For ease of understanding, in the examples provided in this application, the identification of the signal terminal and the identification symbol of the signal it transmits are distinguished by the case of the first letter. Similarly, in the subsequent examples, the identification of the setting signal set, the reset signal rst, the prech_sel_en signal, the prech_all_en signal, the data setting signal rst_sa_latch, etc. corresponding to the signal terminals shown in Figure 15 and Figure 19 .

[0121] In some examples, the latch transfer circuit 6204 is further configured to keep the sense node SO at the first logic level in response to the transfer signal rd being in the enabled state and the first data node Data and the second data node Data_bar being at the second logic level and the first logic level, respectively, when the sense node SO is at the first logic level.

[0122] Exemplarily, the sense node SO is at the first logic level. When the level of the second data node Data_bar is VDD and the level of the first data node Data is VSS, the latch transfer circuit 6204 disconnects the second data node Data_bar from the sense node SO, and the sense node SO remains at the first logic level.

[0123] In some examples, as shown in Figure 11 , the data transfer circuit 6203 includes a first transistor T1 and a second transistor T2.

[0124] The control electrode of the first transistor T1 is coupled to the first data node Data, the first pole of the first transistor T1 is coupled to the second power supply voltage node N2, and the second pole of the first transistor T1 is coupled to the second data node Data_bar. The control electrode of the second transistor T2 is coupled to the second data node Data_bar, the first pole of the second transistor T2 is coupled to the second power supply voltage node N2, and the second pole of the second transistor T2 is coupled to the first data node Data.

[0125] Exemplarily, please continue to refer to Figure 11 , the first transistor T1 and the second transistor T2 are N-type transistors.

[0126] In some examples, asFigure 12 As shown, the reset control circuit 6201 includes a third transistor T3. The control electrode of the third transistor T3 receives a reset signal rst. The first electrode of the third transistor T3 is coupled to the first power supply voltage node N1, and the second electrode of the third transistor T3 is coupled to the first data node Data.

[0127] Exemplarily, as Figure 12 shown, the third transistor T3 is a P-type transistor.

[0128] In some examples, as Figure 13 shown, the setting control circuit 6202 includes a fourth transistor T4. The control electrode of the fourth transistor T4 receives a setting signal set. The first electrode of the fourth transistor T4 is coupled to the first power supply voltage node N1, and the second electrode of the fourth transistor T4 is coupled to the second data node Data_bar.

[0129] Exemplarily, as Figure 13 shown, the fourth transistor T4 is a P-type transistor.

[0130] In some examples, as Figure 14 shown, the latch transfer circuit 6204 includes a fifth transistor T5 and a sixth transistor T6 in a series cascade relationship.

[0131] The control electrode of the fifth transistor T5 is coupled to the first data node Data. The first electrode of the fifth transistor T5 is coupled to the second data node Data_bar. The second electrode of the fifth transistor T5 is coupled to the first electrode of the sixth transistor T6. The control electrode of the sixth transistor T6 receives a transfer signal rd, and the second electrode of the sixth transistor T6 is coupled to the sense node SO.

[0132] Exemplarily, please continue to refer to Figure 14 , the fifth transistor T5 and the sixth transistor T6 are N-type transistors. Considering that the leakage current of the N-type transistor is small, the latch transfer circuit 6204 using electronic components with N-type transistors can reduce the probability of the level change of the sense node SO being sensitive due to the leakage current and improve the accuracy of the data of the sense latch circuit 6223.

[0133] It can be understood that in the case where the fifth transistor T5 and the sixth transistor T6 are N-type transistors, considering the transmission process of the level signals in the entire circuit structure of the latch circuit 6223 in the reset control circuit 6201 and the setting control circuit 6202, the influence on the actual level magnitudes of the first data node Data and the second data node Data_bar. For example, as Figure 12As shown, the third transistor T3 is a P-type transistor. The P-type transistor conducts under low-level control (i.e., the P-type transistor is more sensitive to the magnitude of the induced level signal at the control electrode), and can transfer as much charge as possible from the first power supply node N1 to the first data node Data. Similarly, as Figure 13 shown, the fourth transistor T4 is set as a P-type transistor, and can transfer as much point charge as possible from the first power supply node N1 to the second data node Data_bar.

[0134] Moreover, in the reading stage of the subsequent page buffer 622, based on the fact that the charge amount of the first data node Data is relatively large, the opening degree of the fifth transistor T5 (i.e., the relationship between the voltage difference between the control electrode and the first electrode and the threshold voltage characterizes the opening degree of the transistor) is ensured to be the target degree (the maximum opening degree based on the threshold voltage of the fifth transistor T5). In this way, when the fifth transistor T5 is turned on in response to the level of the first data node Data, as much of the level of the second data node Data_bar as possible is transferred to the sensing node SO, which is beneficial to improving the sensitivity and accuracy of the sensing node SO to obtain data changes in the latch circuit 6223.

[0135] In some examples, at least two latch circuits 6223 in the page buffer 622 can share a latch transfer circuit 6204. For example, two latch circuits 6223 share a latch transfer circuit 6204. In this way, the area occupied by the structure of the page buffer 622 is smaller, and the area of the memory device 60 can be further reduced, which is beneficial to realizing the high integration and small size of the memory device 60.

[0136] Based on the structure of the latch circuit 6223 provided in the above example, as Figure 15 shown, the latch circuit 6223 includes 6 transistors. Combining Figure 7 with the structure of the latch 6211 shown, the latch circuit 6223 of the present application not only reduces two transistors, but also reduces the cost of the page buffer 622 and the space occupied by the memory device 60. Among them, two transistors of the two inverters 6211 are reduced, and the peak current generated by transmitting signals through multiple transistors through the two inverters is reduced, improving the signal transmission stability of the page buffer 622.

[0137] Moreover, while realizing the charging and discharging operation functions of the sensing node SO, the stability of the line transmission level signal between the latch circuit 6223 and the sensing node SO is improved, the accuracy of the sensing signal of the sensing node SO is improved, and thus the performance of the page buffer 622 is improved.

[0138] In some examples, as Figures 16 - 18 shown, the latch circuit 6223 further includes a voltage stabilizing circuit 6205. As Figure 16As shown, the voltage stabilizing circuit 6205 is coupled to the first data node Data and the second data node Data_bar, and is configured to stabilize the voltage difference between the first data node Data and the second data node Data_bar.

[0139] Exemplarily, as Figure 17 shown, the voltage stabilizing circuit 6205 includes a capacitor C1. The first plate of the capacitor C1 is coupled to the first data node Data, and the second plate of the capacitor C2 is coupled to the second data node Data_bar. In this way, under the action of its self-bootstrapping, the capacitor C1 maintains the voltage difference between the first plate and the second plate stable, and further stabilizes the voltage difference between the first data node Data and the second data node Data_bar, so that the voltage difference between the control electrode and the first electrode of the fifth transistor T5 is stable, that is, the signal flowing through the fifth transistor T5 is ensured to be stable.

[0140] Another exemplarily, as Figure 18 shown, the voltage stabilizing circuit 6206 includes a seventh transistor T7. The control electrode of the seventh transistor T7 is coupled to the second data node Data_bar, and both the first electrode and the second electrode of the seventh transistor T7 are coupled to the first data node Data. In this way, the first electrode and the second electrode of the seventh transistor T7 are coupled to the same node (i.e., the first data node Data). Whether the seventh transistor T7 is turned on or off under the control of the level signal of the second data node Data_bar, the level of the first data node Data can be maintained stable. Furthermore, the turn-on degree of the first transistor T1 controlled by the level of the first data node Data is stable, and the level of the second data node Data_bar is stable. Thus, the voltage difference between the control electrode and the first electrode of the fifth transistor T5 is stable, that is, the signal flowing through the fifth transistor T5 is ensured to be stable.

[0141] For example, the seventh transistor T7 is a P-type transistor. In this way, considering the property that a P-type transistor is turned on under the control of a low-level signal. In order to reduce the problem that the level signal received by the control electrode of the transistor cannot turn on the transistor or the turn-on degree of the transistor is poor due to the loss generated by the transmission of the level signal in the circuit signal line (that is, the relationship between the voltage difference between the control electrode and the first electrode and the threshold voltage characterizes the turn-on degree of the transistor), a P-type transistor is provided between the first data node Data and the second data node Data_bar to improve the sensitivity of sensing the level change of the first data node Data and the second data node Data_bar and improve the voltage stabilizing effect.

[0142] In addition, the voltage regulation circuit 6205 may also be a circuit example including other electronic components with voltage regulation effects. The voltage regulation circuit 6205 includes electronic components such as a voltage regulation diode or a linear voltage regulator (such as a low dropout regulator (LDO)). The embodiments of the present application do not limit this.

[0143] For the sake of easy understanding, based on the page buffer 622 with the latch circuit 6223 provided in the above example, an exemplary description of the process of a latch circuit 6223 implementing data latching and potential regulation of the sensing node SO is given. It should be noted that other latch circuits 6223 in the page buffer 622 can perform similar methods for data setting operations.

[0144] As Figure 20 shown, the page buffer 622 includes a bit line control circuit 6221, a bit line discharge circuit 6222, and five latch circuits 6223. Among them, the five latch circuits 6223 include a sensing latch circuit 6223-1, three data latch circuits 6223-2, 6223-3, and 6223-4, and a cache latch circuit 6223-5.

[0145] The sensing node SO is charged through the bit line control circuit 6221, so that the sensing node SO has a high level (for example, the power supply voltage VDD). At the same time, turn on (the eighth transistor T8 and) Figure 15 the third transistor T3 in, so that the power supply voltage VDD from the power supply voltage terminal can be provided to the first data node Data of the sensing latch circuit 6223-1, that is, the sensing latch circuit 6223-1 latches the data as "1". Alternatively, turn on Figure 15 the fourth transistor T4 in, so that the ground voltage VSS can be transmitted to the first data node Data of the sensing latch circuit 6223-1, that is, the sensing latch circuit 6223-1 latches the data as "0".

[0146] It should be noted that the data "1" can represent a high level or a low level, and the data "0" can represent a low level or a high level. The embodiments of the present application take the data "1" representing a high level and the data "0" representing a low level as an example for description.

[0147] The sense latch circuit 6223-1 receives an enabled transmission signal rd (e.g., the rd signal is a low-level signal), and the latch transmission circuit 6204 in the sense latch circuit 6223-1 is turned on. If the data stored in the sense latch circuit 6223-1 is "1", the high voltage on the sense node SO can be discharged to a low voltage through the latch transmission circuit 6204; if the data stored in the sense latch circuit 6223-1 is "0", the latch transmission circuit 6204 in the sense latch circuit 6223-1 is turned off, and the high voltage on the sense node SO cannot be discharged through the latch transmission circuit 6204, and the voltage on the sense node SO remains high.

[0148] Therefore, by sensing the voltage at the sense node SO at this time, the data information stored in the sense latch circuit 6223-1 can be obtained. Similarly, the data information stored in the corresponding latch circuit 6223 can be sensed using each latch circuit 6223.

[0149] In addition, please continue to refer to Figure 20 , the page buffer 622 further includes a data setting circuit 6224. The data setting circuit 6224 is a forced setting circuit, that is, when the data setting signal rst_sa_latch is enabled (e.g., the rst_sa_latch signal is a low-level signal), regardless of the voltage magnitude of the sense node SO at this time, the specified latch circuit 6223 can be set with data.

[0150] Exemplarily, as Figure 20 shown, the data setting circuit 6224 includes an eighth transistor T8. The control electrode of the eighth transistor T8 is configured to receive the data setting signal rst_sa_latch; the first electrode of the eighth transistor T8 is coupled to the latch circuit 6223; the second electrode of the eighth transistor T8 is coupled to the power supply voltage VDD.

[0151] The eighth transistor T8 includes, but is not limited to, a P-type transistor or an N-type transistor. In the embodiments of the present application, the eighth transistor T8 will be described by taking it as a P-type transistor as an example.

[0152] In the embodiments provided by the present application, before enabling the page buffer 622, the data setting circuit 6224 can be used to perform a set or reset operation on one or more latch circuits 6223 in the page buffer 622. For example, the reset operation can be represented by the binary data "0", and the set operation can be represented by "1".

[0153] In some examples, the peripheral circuit 62 further includes a control logic circuit ( Figure 20 not shown in the figure). The control logic circuit is coupled to the data setting circuit 6224 of the page buffer 622 and is configured to generate the data setting signal rst_sa_latch. For example, Figure 5The control logic unit 625 shown includes the control logic circuit.

[0154] The control logic circuit can also be used to generate various control signals required by the page buffer 100, including but not limited to the data setting signal rst_sa_latch.

[0155] On the other hand, based on the page buffer 622 provided in any of the above examples (see Figures 8 - 20 ), as Figure 22 and Figure 23 shown, the embodiments of the present application also provide an operation method for the page buffer 622. In combination with Figure 19 , Figure 20 , Figure 21A and Figure 21B , an exemplary description of the operation method of the page buffer 622 is given. Among them, the latch circuit 6223 of the page buffer 622 takes the Figure 15 shown circuit structure as an example. The operation method of the page buffer 622 of the present application does not limit that all latch circuits 6223 are the Figure 15 shown circuit structure. For example, the latch circuit 6223 can also include the circuit structure of the voltage stabilizing circuit 6205 as Figures 16 - 18 shown.

[0156] As Figure 19 shown, the page buffer 622 includes a bit line control circuit 6221, a bit line discharge circuit 6222, and a plurality of latch circuits 6223.

[0157] The bit line control circuit 6221 is coupled to the first power supply voltage node N1 (such as the transmission power supply voltage VDD), the bit line BL, and the sense node SO, and is configured to control the potential level of the sense node SO based on the current level of the bit line BL during the sensing operation.

[0158] Exemplarily, the bit line control circuit 6221 can set the voltage at the sense node SO by sensing the latched data in the latch circuit 6223; it can also directly set the voltage at the sense node SO based on the power supply voltage VDD provided by the first power supply voltage node N1 in response to the level signals of the Prech_all_en terminal and the Prech_sel_en terminal. For example, when the signals transmitted at the Prech_all_en terminal and the signals transmitted at the Prech_sel_en terminal are both enabled, the power supply voltage (such as VDD) can be applied to the sense node S through the bit line control circuit 6221.

[0159] During the process of programming the memory cell, the bit line control circuit 6221 can be used to apply a prohibited programming bit line voltage (e.g., VDD) or a normal programming bit line voltage (e.g., VSS) to the bit line BL coupled to the memory cell. Exemplarily, a high level is applied to the bit line through the charging function of the bit line control circuit 6221 to achieve the effect of prohibiting programming, or the bit line is discharged through the discharging function of the bit line control circuit 6221, so that the voltage of the bit line is pulled down to the ground voltage to achieve the effect of allowing programming. Among them, the normal programming bit line voltage < the prohibited programming bit line voltage.

[0160] The bit line discharge circuit 6222 is coupled between the bit line BL and the second power supply voltage node N2 (e.g., transmitting the ground voltage GND), and is configured to discharge the potential level of the bit line BL in response to the discharge control signal prech_all_en.

[0161] Exemplarily, the bit line discharge circuit 6222 can be a combination of multiple N-type transistors and / or P-type transistors. Alternatively, the bit line discharge circuit 6222 includes components that can be used to clamp the voltage or regulate the voltage, such as one or more of a Zener diode, a transient voltage suppressor, a varistor, etc. Exemplarily, the bit line discharge circuit 6222 can generate different bit line forced voltages based on different electronic components. For example, a first bit line forced voltage, a second bit line forced voltage. And the normal programming bit line voltage < the first bit line forced voltage < the second bit line forced voltage < the prohibited programming bit line voltage.

[0162] In this way, the bit line discharge circuit 6222 can be used to apply different bit line forced voltages to the bit line BL to achieve fine-grained programming of the memory cell, making the target threshold voltage distribution narrower, increasing the read window between memory cells in different programming states, and ensuring accurate data reading.

[0163] Multiple latch circuits 6223 are coupled to the sense node SO, and charge and discharge the level of the sense node SO under the drive of the bit line control circuit 6221 and the bit line discharge circuit 6222. As Figure 10 shown, each latch circuit 6223 includes a reset control circuit 6201 coupled to the first data node Data, a set control circuit 6202 coupled to the second data node Data_bar, and a data transmission circuit 6203 coupled to both the first data node Data and the second data node Data_bar. And, a latch transmission circuit 6204 coupled to the first data node Data, the second data node Data_bar, and the sense node SO.

[0164] In some examples, as Figure 19As shown, in the bit line control circuit 6221, when the prech_sel_en signal and the prech_all_en signal are both enabled, the power supply voltage (e.g., VDD) can be directly applied to the sense node SO.

[0165] At this time, as Figure 15 shown, the level of the second data node Data_bar is high, and the level of the first data node Data is low. In this way, under the combined action of the first transistor T1 and the second transistor T2 in the latch circuit 6223 (i.e., the fifth transistor T5 is turned off), the latch circuit 6223 will not discharge the level of the sense node SO. The level of the sense node SO is the power supply voltage VDD applied by the bit line control circuit 6221.

[0166] Furthermore, as Figure 19 shown, when the bit line control circuit 6221 responds to both the vbias signal and the vsoblk signal being enabled to couple the bit line BL and the sense node SO, the bit line BL obtains the data stored in the latch circuit 6223 by reading the level of the sense node SO. For example, if the level of the sense node SO does not change and the data read by the bit line BL is "1", it can be inferred that the latched data in the latch circuit 6223 is "1".

[0167] Or, please continue to refer to Figure 19 , when the prech_sel_en signal is enabled and the prech_all_en signal is not enabled, the bit line control circuit 6221 applies the power supply voltage (VDD) to the sense node SO in response to the signal transmitted by the latch circuit 6223.

[0168] At this time, as Figure 15 shown, the level of the second data node Data_bar is low, and the level of the first data node Data is high. Under the combined action of the first transistor T1 and the second transistor T2 in the latch circuit 6223 (i.e., the fifth transistor T5 is turned on), and in response to the rd signal being enabled, the latch circuit 6223 is coupled to the sense node SO to discharge the level of the sense node SO. That is, the level of the sense node SO starts to discharge from the power supply voltage VDD. In this way, when the vbias signal and the vsoblk signal are both enabled, the level signal of the sense node SO is fed back to the bit line BL. The bit line BL obtains the data stored in the latch circuit 6223 by reading the level of the sense node SO. For example, if the level of the sense node SO changes and the data read by the bit line BL is "0", it can be inferred that the latched data in the latch circuit 6223 is "1".

[0169] To more clearly illustrate the driving process of the latch circuit 6223 of the page buffer 622, the following combines Figure 21A andFigure 21B The timing diagram shown takes Figure 15 the latch circuit 6223 shown as an example to illustrate the above steps in detail.

[0170] As Figure 15 shown, the latch circuit 6223 includes a reset control circuit 6201, a set control circuit 6202, a data transmission circuit 6203, and a latch transmission circuit 6204.

[0171] The reset control circuit 6201 includes a third transistor T3. The third transistor T3 is a P-type transistor.

[0172] The set control circuit 6202 includes a fourth transistor T4. The fourth transistor T4 is a P-type transistor.

[0173] The data transmission circuit 6203 includes a first transistor T1 and a second transistor T2. Both the first transistor T1 and the second transistor T2 are N-type transistors.

[0174] The latch transmission circuit 6204 includes a fifth transistor T5 and a sixth transistor T6 connected in series. Both the fifth transistor T5 and the sixth transistor T6 are N-type transistors.

[0175] Based on this, as Figure 22 and Figure 23 shown, the operation method includes at least S100, S200, S300, and S400. Among them, as Figure 21A and Figure 21B shown, the operation process of the page buffer 622 includes three stages: a set stage P-SET, a reset stage P-RST, and a read stage P-RD. And, Figure 21A and Figure 21B the provided timing diagram only exemplarily shows the signals used in the driving process of the latch circuit 6223. There can be a certain time interval between different stages, or they can be adjacent. This application does not limit this.

[0176] At the same time, in order to reflect the characteristics of the latch circuit 6223, that is, in different stages, the latch circuit 6223 responds to configuration signals with opposite logic levels (for example, the logic levels of the set signal set and the reset signal rst are opposite in the same stage), so that the logic levels of the first data node Data and the second data node Data_bar coupled to the latch transmission circuit 6204 are opposite.

[0177] For example, as Figure 21AAs shown, the previous stage of the read stage P-RD can be the reset stage P-RST, and the logic levels of the first data node Data and the second data node Data_bar obtained in the reset stage P-RST are a set of target levels. Then, based on the characteristics of the latch circuit 6223, there must be a process in which the logic levels of the first data node Data and the second data node Data_bar are opposite to this set of target levels before the reset stage P-RST (for example, the set stage P-SET).

[0178] Alternatively, as Figure 21B shown, the previous stage of the read stage P-RD can also be the set stage P-SET, and the logic levels of the first data node Data and the second data node Data_bar obtained in the set stage P-SET are a set of target levels. Then, based on the characteristics of the latch circuit 6223, there must be a process in which the logic levels of the first data node Data and the second data node Data_bar are opposite to this set of target levels before the set stage P-SET (for example, the reset stage P-RST).

[0179] Moreover, considering that the states of the multiple latch circuits 6223 in different page buffers 622 can be the same or different. For example, some latch circuits 6223 perform write data operations, and some other latch circuits 6223 perform active data transfer operations. That is to say, the read stage P-RD reads the data latched in the previous stage (the set stage P-SET or the reset stage P-RST) of the current state of the latch circuit 6223. In this way, within the same time period, the signals transmitted by different latch circuits 6223 are different, and the data read by the read stage P-RD is different.

[0180] Therefore, as Figure 21A and Figure 21B shown, in the same timing process, two front-back sequences reflecting the set stage P-SET and the reset stage P-RST are presented.

[0181] To clearly distinguish the different operation methods for the read stage P-RD to obtain data of different latch circuits 6223, take Figure 21A and Figure 22 , as well as Figure 21B and Figure 23 these two operation methods as examples for illustration.

[0182] In some examples, as Figure 21A and Figure 22 shown, the operation process of the page buffer 622 includes the set stage P-SET, the reset stage P-RST after the set stage P-SET, and the read stage P-RD after the reset stage P-RST.

[0183] Exemplarily, as Figure 15 , Figure 21A and Figure 22 shown, the operation method includes S300, S100, and S200.

[0184] S300: In the setting stage P-SET, in response to the enabling state of the setting signal set, the setting control circuit 6202 sets the first data node Data and the second data node Data_bar to the second logic level and the first logic level, respectively. The first logic level is higher than the second logic level.

[0185] Exemplarily, please continue to refer to Figure 15 and Figure 21A , a pre-charge operation is performed on the sensing node SO such that the sensing node SO has the first logic level. For example, the first logic level is VDD.

[0186] The fourth transistor T4 of the setting control circuit 6202 is turned on in response to the enabling state of the set signal, coupling the first power supply voltage node N1 to the second data node Data_bar, and transmitting the first logic level to the control electrode of the second transistor T2 in the data transmission circuit 6203. The second transistor T2 is turned on, transmitting the second logic level (e.g., VSS) of the second power supply voltage node N2 to the first data node Data. Among them, the first logic level VDD is higher than the second logic level VSS.

[0187] At this time, the third transistor T3 of the reset control circuit 6201 is turned off in response to the non-enabling state of the reset signal rst, and the level of the first data node Data remains at the second logic level.

[0188] Meanwhile, the first transistor T1 in the data transmission circuit 6203 is turned off in response to the second logic level of the first data node Data, and the level of the second data node Data_bar remains at the first logic level.

[0189] In this way, the fifth transistor T5 of the latch transmission circuit 6204 is turned off in response to the second logic level signal of the first data node Data. The latch circuit 6223 is not connected to the sensing node SO, and the sensing node SO remains at the first logic level.

[0190] S100: In the reset stage P-RST, in response to the enabling state of the reset signal rst, the reset control circuit 6201 initializes the first data node Data and the second data node Data_bar to the first logic level and the second logic level, respectively.

[0191] Exemplarily, please continue to refer to Figure 15 and Figure 21A, in response to the enabling state of the reset signal rst (for example, rst is a low-level signal), the third transistor T3 of the reset control circuit 6201 is turned on, and the level of the first power supply voltage node N1 is transmitted to the first data node Data, and the level of the first data node Data is set to the first logic level.

[0192] The first transistor T1 of the data transmission circuit 6203 is turned on in response to the first logic level (for example, VDD) of the first data node Data, and the level of the second power supply voltage node N2 is transmitted to the second data node Data_bar, and the level of the second data node Data_bar is set to the second logic level (for example, VSS). The first logic level is higher than the second logic level.

[0193] At the same time, the fourth transistor T4 of the setting control circuit 6202 is turned off in response to the setting signal set being in a non-enabled state (set is a high level), and the level of the second data node Data_bar is maintained at the second logic level.

[0194] In this way, the fifth transistor T5 of the latch transmission circuit 6204 is turned on in response to the first logic level of the first data node Data. However, since the sixth transistor T6 is turned off in response to the transmission signal rd being in a non-enabled state (for example, rs is a low level), the latch circuit 6223 is not connected to the sensing node SO, and the sensing node SO remains at the first logic level.

[0195] Based on the above operation process, the level of the sensing node SO is the first logic level. The latch circuit 6223 is programmed through the bit line BL, and the latch circuit 6223 latches the target data. The data set in the reset stage P-RST is read in the subsequent read stage P-RD.

[0196] S200: In the read stage P-RD after the reset stage P-RST, the sensing node SO is at the first logic level; and, in response to the transmission signal rd being in an enabled state, the latch transmission circuit 6204 couples the second data node Data_bar to the sensing node SO, and transmits the second logic level of the second data node Data_bar to the sensing node SO. The sensing node SO changes from the first logic level to the second logic level.

[0197] For example, please continue to refer to Figure 15 and Figure 21A, after S100, the first data node Data has a second logic level, and the second data node Data_bar has a first logic level. The fifth transistor T5 of the latch transfer circuit 6204 is turned on in response to the first logic level of the first data node Data, and the sixth transistor T6 is turned on in response to the transfer signal rd to couple the second data node Data_bar to the sense node SO. Thus, the second logic level of the second data node Data_bar is transferred to the sense node SO.

[0198] In this way, the sense node SO changes from the first logic level to the second logic level. That is to say, the bit line BL reads the data of the latch circuit 6223 through the level change of the sense node SO. Furthermore, the read data can be latched into other latch circuits 6223 through the bit line BL.

[0199] In some other examples, such as Figure 21B and Figure 23 shown, the operation process of the page buffer 622 includes a reset stage P-RST, a setup stage P-SET after the reset stage P-RST, and a read stage P-RD after the setup stage P-SET.

[0200] Exemplarily, such as Figure 15 、 Figure 21B and Figure 23 shown, the operation method includes S100, S300, and S400.

[0201] S100: In the reset stage P-RST, in response to the enabling state of the reset signal rst, the reset control circuit 6201 initializes the first data node Data and the second data node Data_bar to the first logic level and the second logic level respectively.

[0202] Exemplarily, first, a pre-charge operation is performed on the sense node SO so that the sense node SO has a first logic level. For example, the first logic level is VDD.

[0203] Please continue to refer to Figure 15 and Figure 21B , in response to the enabling state of the reset signal rst, the third transistor T3 of the reset setup circuit 6201 is turned on, and the level of the first power supply voltage node N1 is transferred to the first data node Data, and the level of the first data node Data is set to the first logic level.

[0204] The first transistor T1 of the data transmission circuit 6203 is turned on in response to the first logic level of the first data node Data, and transmits the level of the second power supply voltage node N2 to the second data node Data_bar, and the level of the second data node Data_bar is set to the second logic level. The first logic level is higher than the second logic level. For example, the first logic level is VDD and the second logic level is VSS.

[0205] Meanwhile, the fourth transistor T4 of the setting control circuit 6202 is turned off in response to the setting signal set being in a non-enabled state, and the level of the second data node Data_bar is maintained at the second logic level.

[0206] In this way, the fifth transistor T5 of the latch transmission circuit 6204 is turned on in response to the first logic level of the first data node Data. However, since the sixth transistor T6 is turned off in response to the transmission signal rd being in a non-enabled state, the latch circuit 6223 is not connected to the sensing node SO, and does not pull down the level of the sensing node SO, and the sensing node SO remains at the first logic level.

[0207] S300: In the setting phase P-SET, in response to the enabled state of the setting signal set, the setting control circuit 6202 sets the first data node Data and the second data node Data_bar to the second logic level and the first logic level, respectively.

[0208] For example, please continue to refer to Figure 15 and Figure 21B , the fourth transistor T4 of the setting control circuit 6202 is turned on in response to the set signal being in an enabled state, couples the first power supply voltage node N1 to the second data node Data_bar, and transmits the first logic level to the control electrode of the second transistor T2 in the data transmission circuit 6203. The second transistor T2 is turned on, and transmits the second logic level of the second power supply voltage node N2 to the first data node Data. For example, the second logic level is VSS. The first logic level VDD is higher than the second logic level VSS.

[0209] At this time, the third transistor T3 of the reset control circuit 6201 is turned off in response to the reset signal rst being in a non-enabled state, and the level of the first data node Data is maintained at the second logic level. Meanwhile, the first transistor T1 in the data transmission circuit 6203 is turned off in response to the second logic level of the first data node Data, and the level of the second data node Data_bar is maintained at the first logic level.

[0210] In this way, the fifth transistor T5 of the latch transfer circuit 6204 is turned off in response to the second logic level signal of the first data node Data. The latch circuit 6223 is disconnected from the sense node SO, and the sense node SO remains at the first logic level.

[0211] Based on the above operation process, the level of the sense node SO is the first logic level. The latch circuit 6223 is programmed through the bit line BL, and the latch circuit 6223 latches the target data. The data set in the setup phase P-SET is read in the subsequent read phase P-RD.

[0212] S400: In the read phase P-RD after the setup phase P-SET, the sense node SO is at the first logic level; and, the latch transfer circuit 6204 disconnects the second data node Data_bar from the sense node SO, and the level of the sense node SO remains at the first logic level.

[0213] Exemplarily, please continue to refer to Figure 15 and Figure 21B , after S300, the first data node Data has the second logic level, and the second data node Data_bar has the first logic level. The fifth transistor T5 of the latch transfer circuit 6204 is turned off in response to the second logic level of the first data node Data.

[0214] Based on this, regardless of whether the transmission signal rd is in the enabled state (that is, when the rd signal is a high-level signal, the sixth transistor T6 is turned off; or when the rd signal is a low-level signal, the sixth transistor T6 is in the conducting state), the second data node Data_bar is disconnected from the sense node SO, and the level of the sense node SO remains at the first logic level. In this way, the bit line BL continuously reads the data of the latch circuit 6223 through the sense node SO.

[0215] The operation method of the page buffer 622 provided by this application includes as Figure 22 and Figure 23The two processes shown below. One is based on the level signals stored in the first data node Data and the second data node Data_bar during the reset stage P-RST. During the read stage P-RD, the latch transfer circuit 6204 is connected to the sense node SO through the enabling state of the transfer signal rd, causing the level of the sense node SO to change. The other is based on the level signals stored in the first data node Data and the second data node Data_bar during the set stage P-SET. During the read stage P-RD, even in response to the enabling state of the transfer signal rd, the latch transfer circuit 6202 is not connected to the sense node SO, maintaining the level of the sense node SO. These two processes are based on multiple latch circuits of different page buffers. Different latch circuits may have different states during the same time period, which is characterized in that the operation process of the page buffer 622 can be that the data read during the read stage P-RD is the data stored during the set stage P-SET, or the data stored during the reset stage P-RST. In this way, during the read stage P-RD, the latch circuits 6223 of different page buffers 622 have different effects on the level of the sense node SO, so that different data of different page buffers 622 can be obtained through the sense node SO. The circuit structure of the page buffer 622 provided in this application can simultaneously read data in different states of the storage unit.

[0216] It should be understood that "some embodiments" or "some examples" mentioned throughout the specification mean that specific features, structures, or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the appearances of "in some embodiments" or "in some examples" throughout the specification do not necessarily refer to the same embodiments. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the order numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0217] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0218] As described above, it is only the implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A page buffer, characterized in that, it includes: a plurality of latch circuits, each of the latch circuits including: a reset control circuit, coupled to a first data node, configured to receive a first power supply voltage to determine the potential of the first data node; a setting control circuit, coupled to a second data node, configured to receive a first power supply voltage to determine the potential of the second data node; a data transmission circuit, coupled to the first data node and the second data node, configured to receive a second power supply voltage; a latch transmission circuit, coupled to the first data node, the second data node and a sense node; wherein, the first power supply voltage is higher than the second power supply voltage.

2. The page buffer according to claim 1, characterized in that, the setting control circuit is configured to respond to the setting signal being in an enabled state, the second data node and the first data node being at a first logic level and a second logic level respectively; the first logic level is higher than the second logic level; the reset control circuit is configured to respond to the reset signal being in an enabled state, the first data node and the second data node being at the first logic level and the second logic level respectively; the latch transmission circuit is configured to respond to the transmission signal being in an enabled state and the first data node and the second data node being at the first logic level and the second logic level respectively, and couple the second data node to the sense node, the sense node being at the second logic level.

3. The page buffer according to claim 2, characterized in that, the latch transmission circuit is further configured to, when the sense node is at the first logic level, respond to the transmission signal being in an enabled state and the first data node and the second data node being at the second logic level and the first logic level respectively, and the sense node maintains the first logic level.

4. The page buffer according to claim 1, characterized in that, the data transmission circuit includes a first transistor and a second transistor; the control electrode of the first transistor is coupled to the first data node, the first pole of the first transistor is coupled to a second power supply voltage node, and the second pole of the first transistor is coupled to the second data node; the control electrode of the second transistor is coupled to the second data node, the first pole of the second transistor is coupled to a second power supply voltage node, and the second pole of the second transistor is coupled to the first data node.

5. The page buffer according to claim 1, characterized in that, the reset control circuit includes a third transistor, the control electrode of the third transistor receives the reset signal, the first pole of the third transistor is coupled to a first power supply voltage node, and the second pole of the third transistor is coupled to the first data node; the setting control circuit includes a fourth transistor, the control electrode of the fourth transistor receives the setting signal, the first pole of the fourth transistor is coupled to a first power supply voltage node, and the second pole of the fourth transistor is coupled to the second data node.

6. The page buffer according to claim 1, wherein, the latch transfer circuit includes a fifth transistor and a sixth transistor in a series cascade relationship; the fifth transistor and the sixth transistor are N-type transistors.

7. The page buffer according to claim 6, wherein, the control electrode of the fifth transistor is coupled to the first data node, the first electrode of the fifth transistor is coupled to the second data node, and the second electrode of the fifth transistor is coupled to the first electrode of the sixth transistor; the control electrode of the sixth transistor receives the transfer signal, and the second electrode of the sixth transistor is coupled to the sense node.

8. The page buffer according to claim 1, wherein, the latch circuit further includes: a voltage stabilizing circuit, coupled to the first data node and the second data node, and configured to stabilize the voltage difference between the first data node and the second data node.

9. The page buffer according to claim 8, wherein, the voltage stabilizing circuit includes a capacitor; the first plate of the capacitor is coupled to the first data node, and the second plate of the capacitor is coupled to the second data node.

10. The page buffer according to claim 7, wherein, the voltage stabilizing circuit includes a seventh transistor; the control electrode of the seventh transistor is coupled to the second data node, and the first and second electrodes of the seventh transistor are both coupled to the first data node.

11. The page buffer according to claim 1, wherein, the page buffer further includes: a bit line control circuit, coupled to a first power supply voltage node, a bit line, and the sense node, and configured to control the potential level of the sense node based on the current level of the bit line during a sensing operation; a bit line discharge circuit, coupled between the bit line and a second power supply voltage node, and configured to discharge the potential level of the bit line in response to a discharge control signal.

12. A memory device, wherein, comprising: a memory cell array, coupled to a plurality of bit lines; a plurality of page buffers according to any one of claims 1 to 11, each of the page buffers being coupled to one of the bit lines and configured to perform a sensing operation based on the current level of the bit line.

13. A memory system, wherein, the memory system includes: one or more memory devices according to claim 12; a memory controller, coupled to the memory device and configured to control the memory device.

14. A method for operating a page buffer, wherein, the page buffer includes a plurality of latch circuits, each latch circuit including a reset control circuit coupled to a first data node, a set control circuit coupled to a second data node, and a data transfer circuit coupled to both the first data node and the second data node; and a latch transfer circuit coupled to the first data node, the second data node, and the sense node; the operation method includes: In the reset stage, the reset signal is set to an enabled state, and in response to the enabled state of the reset signal, the reset control circuit sets the first data node and the second data node to a first logic level and a second logic level, respectively; the first logic level is higher than the second logic level. In the read stage after the reset stage, the sense node is at the first logic level; and, the transfer signal is set to an enabled state, and in response to the transfer signal being in the enabled state, the latch transfer circuit couples the second data node to the sense node, such that the sense node changes from the first logic level to the second logic level.

15. The method for operating a page buffer according to claim 14, wherein, further comprising: In the setup stage, the setup signal is set to an enabled state, and in response to the enabled state of the setup signal, the setup control circuit sets the first data node and the second data node to the second logic level and the first logic level, respectively. In the read stage after the setup stage, the sense node is at the first logic level; and, the latch transfer circuit disconnects the second data node from the sense node, and the level of the sense node remains at the first logic level.

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