Packaging interconnection structure and packaging process
By using connecting copper sheets instead of traditional bonded wires in chip packages, the load-bearing capacity and heat dissipation problems of bonded wires in high current scenarios are solved, and higher integration and better heat dissipation performance are achieved.
Patent Information
- Application Number
- CN202510219677.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2025-05-27
AI Technical Summary
In the high current demand scenario, the traditional wire bonding process has a small load current and generates severe heat, which limits the integration of the chip and cannot effectively utilize the intermediate area of the chip.
Instead of the traditional solder wire, the chip is fixed on the substrate by adhesive tape, and the connecting copper sheet is covered above the chip, including a first horizontal part, an inclined connecting part and a second horizontal part. The first horizontal part is connected to the substrate, the second horizontal part is connected to the chip by solder, and a plurality of lead-out solder joints are left in the middle part of the chip.
It improves the chip integration, increases the current carrying capacity, reduces the parasitic resistance of the circuit, and improves the product's heat dissipation performance, signal transmission speed and quality.
Smart Images
Figure CN120048811A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip packaging, and in particular to a packaging interconnection structure and a packaging process. Background Art
[0002] In the traditional welding process, the chip is precisely mounted on the substrate and then the chip and the substrate are interconnected using wire bonding (such as Figure 1 As shown in the figure). However, due to its small size, the current that the welding wire can carry is relatively small. In the scenario of high current demand, the welding wire will become the bottleneck of the entire circuit, limiting the performance of the product. In addition, the welding wire also has the phenomenon of serious heating. When high-intensity current passes through, the welding wire will generate a lot of heat due to resistance, which will not only accelerate the aging of the welding wire, but also cause thermal damage to the surrounding electronic components, further affecting the stability and reliability of the product.
[0003] On the other hand, in order to avoid cross-circuiting between bonding wires, bonding wires can only be arranged around the chip, while the middle area of the chip is regarded as a "forbidden zone" where bonding wires cannot be laid, which greatly limits the integration of the chip. In the context of modern electronic products pursuing miniaturization and high performance, the idleness of the middle area of the chip is undoubtedly a waste of precious space, and it also hinders the development of chip packaging technology towards higher density and more complex functions. Therefore, seeking a new packaging interconnection structure that can break through these limitations has become an urgent problem to be solved in the industry. Summary of the invention
[0004] In view of the problems in the prior art of small carrying current, severe heat generation and low chip integration due to wire connection, the present invention provides a packaging interconnection structure and a packaging process.
[0005] The present invention is achieved through the following technical solutions: A packaging interconnection structure includes a substrate, a chip and a connecting copper sheet. The chip is fixedly connected to the substrate by means of adhesive, the connecting copper sheet covers the chip, and the connecting copper sheet includes a first horizontal connecting portion, an inclined connecting portion and a second horizontal connecting portion. The first horizontal portion is connected to the substrate, and the second horizontal portion is connected to the chip by means of solder. A plurality of lead solder joints are reserved in the middle portion of the chip.
[0006] Preferably, the area of the connecting copper sheet is greater than or equal to the area of the chip.
[0007] Preferably, the substrate can be replaced by a lead frame.
[0008] Preferably, the thickness of the connecting copper sheet is greater than or equal to 0.1 mm.
[0009] Preferably, the shape of the connecting copper sheet is consistent with the wiring layout.
[0010] Preferably, the thickness of the adhesive is greater than or equal to 30 μm.
[0011] A packaging process for packaging an interconnect structure, comprising the following steps: S1, thin the wafer to the required thickness, and then cut it into multiple single chips; (the thickness of the wafer after thinning is 40~750μm) S2, mounting the single chip onto the substrate using adhesive tape; S3, printing SMT solder paste on the chip; S4, mounting the connecting copper sheet on the chip and the substrate, the solder paste on the solder joint contacts the connecting copper sheet to form a conducting circuit, and obtaining a rough product; S5, reflow soldering the rough product to obtain a semi-finished packaging structure; S6, plastic-sealing the semi-finished packaging structure to obtain a finished packaging structure.
[0012] Preferably, in S3, the specific process of printing SMT solder paste is: first, prepare a steel mesh, then place the steel mesh on the substrate with the chip mounted, and expose each solder joint on the chip and the substrate, finally apply solder paste, and use vision to detect whether the solder covers all solder joints; wherein the mesh holes of the steel mesh correspond one-to-one to the solder joints on the chip and the solder joints on the substrate.
[0013] Preferably, in S5, main technical parameters of reflow soldering are: vertex temperature of 235-260°C, reflow time of 60-90s, heating slope of less than 2°C / s, and cooling slope of less than 0.5°C / s.
[0014] Preferably, in S6, during the plastic sealing, the temperature is 140-170° C., the pressure is 1.0-1.8t, and the time is 10-20s.
[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a packaging interconnection structure that connects a chip with a substrate or a frame by connecting a copper sheet instead of a traditional wire bonding process, which is a brand-new interconnection structure. The copper sheet has a strong heat dissipation performance and can carry a relatively large current, which can greatly reduce the parasitic resistance of the circuit and improve the heat dissipation performance of the product. And because the copper sheet can cover the entire area of the chip, the middle part of the chip can also lead to a solder joint, thereby greatly improving the integration of the product.
[0016] Furthermore, the area of the connecting copper sheet is limited in order to maximize the wiring and ensure that all lead solder joints on the chip can be effectively connected to the substrate through the copper sheet, thereby maximizing the product integration and improving the reliability and stability of the electrical connection.
[0017] Furthermore, the thickness and shape of the connecting copper sheet are limited. The thickness needs to ensure sufficient supporting force, and the shape is consistent with the routing layout, which can not only optimize the current path, but also reduce resistance and inductance, and improve signal transmission speed and quality.
[0018] Furthermore, the thickness of the die bonding adhesive can ensure that the chip is firmly bonded to the substrate.
[0019] Furthermore, the substrate can be replaced with a lead frame, providing more packaging options to meet the needs of different application scenarios.
[0020] The packaging process of the packaging interconnection structure of the present invention reduces material waste and production costs by optimizing the packaging structure and process flow. Specifically, a complete packaging process is formed through the steps of wafer thinning and cutting, chip mounting, SMT solder paste printing, connection copper sheet mounting, reflow soldering and plastic sealing, which can ensure the stability and consistency of the packaging structure and realize automated and efficient production.
[0021] Furthermore, the parameter settings for SMT solder paste printing and reflow soldering ensure accurate coverage and good wetting of solder joints, improve packaging yield, and help reduce energy consumption and shorten production cycles, thereby reducing production costs.
[0022] Furthermore, the technical parameters during plastic sealing are limited in order to ensure the quality of plastic sealing and product performance. Specifically, the high temperature is to ensure that the plastic sealing material will not solidify too quickly during the plastic sealing process, resulting in incomplete filling. On the one hand, the pressure is to ensure good sealing and ensure that the plastic sealing material will not flow out of the mold during the injection molding process. On the other hand, the plastic sealing material is squeezed into the mold through pressure and time to ensure that the plastic sealing material can be fully filled into the required area. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a schematic diagram of a packaging structure in the prior art; Figure 2 It is a structural schematic diagram of a packaging interconnection structure of the present invention; Figure 3 The present invention is a packaging process flow chart of a packaging interconnection structure. DETAILED DESCRIPTION
[0024] The present invention is further described in detail below in conjunction with specific embodiments, which are intended to explain the present invention rather than to limit it.
[0025] The present invention discloses a packaging interconnection structure, referring to Figure 2 , including a substrate, a chip and a connecting copper sheet, the chip is fixedly connected to the substrate by an adhesive, wherein the thickness of the adhesive is greater than or equal to 30 μm to ensure good bonding strength and thermal conductivity to avoid local overheating.
[0026] The connecting copper sheet covers the chip, where the area of the connecting copper sheet is greater than or equal to the area of the chip to maximize the wiring space. The thickness of the connecting copper sheet is greater than or equal to 0.1mm, which can ensure sufficient support so that the copper sheet can carry the electrical connection between the chip and the substrate during the packaging process. The shape of the connecting copper sheet is consistent with the routing layout, which can optimize the current path and effectively reduce resistance and inductance, thereby significantly improving the speed and quality of signal transmission.
[0027] Specifically, the connecting copper sheet includes a first horizontal portion, an inclined connecting portion, and a second horizontal portion, wherein the first horizontal portion is connected to the substrate, and the second horizontal portion is connected to the chip through solder. The first horizontal portion is used as a connection point between the copper sheet and the substrate (or lead frame), and its shape and size are usually customized according to the layout of the substrate and the design requirements of the copper sheet. The shape and size of the second horizontal portion are usually designed according to the solder joint layout and electrical performance requirements of the chip.
[0028] There is no limitation on the shape of the inclined connection part. On the premise of meeting the mechanical strength requirement, it can be in a variety of forms such as straight line, folded line, and wavy shape, so as to better adapt to different packaging layouts, chip sizes, and thermal expansion coefficient differences. For example, the straight line shape is suitable for packaging scenarios with less space restrictions and a closer distance between the chip and the substrate. The folded line shape can achieve a longer connection path in a limited space, which helps to disperse stress and improve the reliability of the connection. The wavy shape can provide better elastic deformation capacity, which helps to alleviate the stress concentration problem caused by differences in thermal expansion coefficients.
[0029] The middle part of the chip is provided with multiple lead solder joints, which can improve the integration of the product and is suitable for high-density packaging requirements.
[0030] In addition, the substrate can be replaced with a lead frame to meet the needs of different application scenarios, so that the packaging interconnection structure can be more widely used in various electronic devices.
[0031] The present invention discloses a packaging interconnection structure that uses a copper sheet to replace a traditional wire bonding process to achieve interconnection between a chip and a substrate or a frame. This is a brand-new interconnection structure. The copper sheet has a strong heat dissipation performance and can carry a relatively large current, which can greatly reduce the parasitic resistance of the circuit and improve the heat dissipation performance of the product. And because the copper sheet can cover the entire chip area, the middle part of the chip can also lead to a solder joint, thereby greatly improving the integration of the product.
[0032] The present invention also discloses a packaging process for packaging interconnection structures, referring to Figure 3 , including the following steps: S1, thin the wafer to the required thickness (40~750μm) and then cut it into multiple single chips.
[0033] S2, mounting the single chip onto the substrate using adhesive.
[0034] S3, printing SMT solder paste on the chip; the specific process is: first make a steel mesh, then place the steel mesh on the substrate with the chip mounted, and expose every solder joint on the chip and the substrate, finally apply solder paste, and use vision to detect whether the solder covers all the solder joints; the mesh holes of the steel mesh correspond one by one to the solder joints on the chip and the substrate.
[0035] S4, mounting the connecting copper sheet on the chip and the substrate, the solder paste on the solder joint contacts the connecting copper sheet to form a conducting circuit, and obtaining a rough product; S5, reflow soldering the rough product to obtain a semi-finished packaging structure; wherein, the main technical parameters of the reflow soldering are: vertex temperature of 235~260°C, reflow time of 60~90s, heating slope of less than 2°C / s, and cooling slope of less than 0.5°C / s.
[0036] S6, plastic-sealing the semi-finished packaging structure to obtain a finished packaging structure, wherein the temperature during plastic sealing is 140-170° C., the pressure is 1.0-1.8t, and the time is 10-20s.
[0037] The packaging process of a packaging interconnection structure of the present invention significantly reduces resistance and inductance by optimizing the shape and layout of the connecting copper sheet, improves the signal transmission speed and quality, and at the same time, the connecting copper sheet has excellent heat dissipation performance, can effectively transfer the heat generated by the chip, and is suitable for high-power application scenarios. By optimizing the SMT solder paste printing and reflow soldering parameters, the accurate coverage and good wetting of the solder joints are ensured, the packaging yield is improved, and the production cost is reduced. Specifically, the parameter settings of the SMT solder paste printing and reflow soldering are carefully optimized to ensure the accurate coverage and good wetting of the solder joints, which not only improves the packaging yield, but also helps to reduce energy consumption and shorten the production cycle, further reducing the production cost. At the same time, the technical parameters during plastic sealing are also strictly limited to ensure the quality of plastic sealing and product performance. The high temperature setting ensures that the plastic sealing material will not solidify too quickly during the plastic sealing process, thereby avoiding the problem of insufficient filling; and the appropriate pressure setting not only ensures good sealing, prevents the plastic sealing material from flowing outside the mold, but also improves the filling effect of the plastic sealing material and the overall performance of the product through the pressure effect.
[0038] The above description is only a preferred embodiment of the present invention and is not intended to impose any limitation on the technical solution of the present invention. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can also be subjected to several simple modifications and substitutions, and these modifications and substitutions are also within the scope of protection covered by the claims.
Claims
1. A package interconnect structure, characterized in that: It includes a substrate, a chip and a connecting copper sheet. The chip is fixedly connected to the substrate by adhesive. The connecting copper sheet covers the chip. The connecting copper sheet includes a first horizontal connecting part, an inclined connecting part and a second horizontal connecting part. The first horizontal part is connected to the substrate, and the second horizontal part is connected to the chip by soldering. A plurality of lead solder joints are reserved in the middle part of the chip.
2. The package interconnect structure according to claim 1, characterized in that: The area of the connecting copper sheet is greater than or equal to the area of the chip.
3. The package interconnect structure according to claim 1, characterized in that: The substrate can be replaced by a lead frame.
4. The package interconnect structure according to claim 1, characterized in that: The thickness of the connecting copper sheet is greater than or equal to 0.1 mm.
5. The package interconnect structure according to claim 1, characterized in that: The shape of the connecting copper sheet is consistent with the routing layout.
6. The packaging process of the package interconnect structure according to claim 1, characterized in that: The thickness of the adhesive is greater than or equal to 30 μm.
7. A packaging process for the packaging interconnect structure according to claims 1 to 6, characterized in that: The following steps are involved: S1, thinning the wafer to the required thickness and then cutting it into multiple single chips; S2, mounting the single chip onto the substrate using adhesive tape; S3, printing SMT solder paste on the chip; S4, mounting the connecting copper sheet on the chip and the substrate, the solder paste on the solder joint contacts the connecting copper sheet to form a conducting circuit, and obtaining a rough product; S5, reflow soldering the rough product to obtain a semi-finished packaging structure; S6, plastic-sealing the semi-finished packaging structure to obtain a finished packaging structure.
8. The packaging process of the package interconnect structure according to claim 7, characterized in that: In S3, the specific process of printing SMT solder paste is as follows: first, a steel mesh is prepared, and then the steel mesh is placed on the substrate with the chip mounted, exposing each solder joint on the chip and the substrate, and finally solder paste is applied, and vision is used to detect whether the solder covers all solder joints; the mesh holes of the steel mesh correspond one-to-one to the solder joints on the chip and the substrate.
9. The packaging process of the package interconnect structure according to claim 7, characterized in that: In S5, the main technical parameters of reflow soldering are: vertex temperature is 235~260℃, reflow time is 60~90s, heating slope is less than 2℃ / s, and cooling slope is less than 0.5℃ / s.
10. The packaging process of the package interconnect structure according to claim 7, characterized in that: In S6, during plastic sealing, the temperature is 140~170℃, the pressure is 1.0~1.8t, and the time is 10~20s.