A control method and circuit for suppressing the light-off stress of a synchronous rectifier tube

Abstract

The application provides a control method for inhibiting the light load off stress of a synchronous rectifier tube, comprising the following steps: determining the control module setting end level based on a preset high level threshold voltage and a control module setting end voltage; receiving a power failure signal and determining the control module data end level based on the power failure signal; receiving a clock signal and determining the control module driving end level based on the clock signal; determining the control module output end level based on the control module data end level, the control module driving end level and the control module setting end level, generating a PWM off signal based on the control module output end level; and controlling the main control module to turn off the PWM output at a preset safe time based on the PWM off signal, so as to inhibit the off stress of the synchronous rectifier tube. The control method and circuit for inhibiting the light load off stress of the synchronous rectifier tube are combined with the power failure signal and the clock signal to control the main control module to turn off the PWM output at a safe time, thereby avoiding the stress problem of the synchronous rectifier tube.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, in particular to a control method and circuit for suppressing the light-load shutdown stress of a synchronous rectifier. BACKGROUND

[0002] In recent years, switching power supplies are constantly developing towards miniaturization, high efficiency and high power density, and synchronous rectification technology has been very mature. Compared with ordinary diode rectification, synchronous rectification can greatly improve efficiency and is very suitable for low-voltage high-power application scenarios, but also brings certain problems. Due to the unidirectional conduction characteristic of the diode, the output inductor in the converter will not have a negative current, but when synchronous rectification, the output inductor current will have a negative current at no load or light load, which may cause stress problems of the synchronous rectifier during shutdown of the converter. This phenomenon exists in many topologies, and in low-voltage high-power application scenarios, the voltage stress problem caused by the large negative current of the output inductor will be particularly prominent.

[0003] Currently, there are two common methods to solve the shutdown stress problem of the synchronous rectifier converter: (1) using soft shutdown, that is, after detecting the shutdown signal, the converter reference voltage gradually decreases, and the output also gradually decreases under the regulation of the loop, the energy returns to the primary side, until the output decreases to 0V, and the PWM is turned off, at this time there is no energy in the inductor, and no stress problem will occur, but this method does not conform to the actual engineering application, the converter should be immediately turned off PWM when triggering many protections, so as to avoid damage to the subsequent circuit; (2) increasing the absorption capacitor, which can suppress the size of ΔVa, but increases the volume of the converter, and the capacitor will also work in normal operation, which will affect the peak stress in the heavy load condition, the absorption circuit will also heat up, and the cost is high, the efficiency is low, and the effect is not good. SUMMARY

[0004] The present application aims to provide a control method and circuit for suppressing the light-load shutdown stress of a synchronous rectifier, to solve the above technical problems, by controlling the PWM to be turned off at a preset safe time, avoiding the stress problem of the synchronous rectifier caused by the negative current of the output inductor in the no-load and light-load conditions.

[0005] In order to solve the above technical problems, the present application provides a control method for suppressing the light-load shutdown stress of a synchronous rectifier, applied to a control circuit for suppressing the light-load shutdown stress of a synchronous rectifier, comprising the following steps:

[0006] Determine the control module set end level based on the preset high-level threshold voltage and the control module set end voltage;

[0007] Receive the power failure signal, and determine the control module data end level based on the power failure signal;

[0008] receive a clock signal, and determine a control module driving end level based on the clock signal;

[0009] determine a control module output end level based on the control module data end level, the control module driving end level and the control module setting end level, to generate a PWM closing signal based on the control module output end level;

[0010] control the main control module to close the PWM output at a preset safe time based on the PWM closing signal, to realize suppression of the turn-off stress of the synchronous rectifier tube.

[0011] The above scheme receives the power failure signal detected by the fault detection module, and combines the clock signal of the main control module to perform signal integration and transformation, to control the main control module to close the PWM output at a preset safe time, to avoid the stress problem of the synchronous rectifier tube caused by the output inductor negative current in the no-load and light-load conditions.

[0012] Further, the determination of the control module output end level based on the control module data end level, the control module driving end level and the control module setting end level to generate the PWM closing signal based on the control module output end level includes: when the power failure signal exists, the control module driving end level is determined, and when the clock signal is a rising edge, the control module output end level is determined based on the control module data end level, the control module driving end level and the control module setting end level, to generate the PWM closing signal based on the control module output end level.

[0013] In the above scheme, the level change is generated by the control module interface power failure signal and the clock signal, which corresponds to the generation of the output end level change, so that when the power failure signal exists, the output end level signal that appears when the clock signal is a rising edge generates the PWM closing signal, and then the main control module can be controlled to close the PWM output at a preset safe time based on this signal, which simply and effectively solves the stress problem that occurs when closing at a non-pre-set safe time.

[0014] Further, when the power failure signal does not exist, the control module output end level is determined based on the control module data end level, the control module driving end level and the control module setting end level, to generate a release signal based on the control module output end level, to make the main control module continue the original working state based on the release signal.

[0015] The application provides a control method for inhibiting the shutdown stress of a synchronous rectifier tube under light load, which receives a power failure signal detected by a fault detection module, and combines a clock signal of a main control module to realize signal integration transformation through a simple level triggering condition, so that the main control module is controlled to close the PWM output at a preset safe time, thereby avoiding the synchronous rectifier stress problem caused by the negative current of the output inductor under no load and light load conditions; and a release signal is generated when the power failure signal does not exist, so that the control on the main control module is released, and the original working state of the main control module can be continued.

[0016] The application also provides a control circuit for inhibiting the shutdown stress of a synchronous rectifier tube under light load, which is used to realize the control method for inhibiting the shutdown stress of a synchronous rectifier tube under light load, and comprises a fault detection module, a main control module and a PWM closing control module.

[0017] The receiving end of the fault detection module is electrically connected with the output end of the main control module, the output end of the fault detection module is electrically connected with the fault receiving end of the PWM closing control module, the clock receiving end of the PWM closing control module is electrically connected with the clock output end of the main control module, and the output end of the PWM closing control module is electrically connected with the receiving end of the main control module.

[0018] The fault module is used to output a power failure signal.

[0019] The main control module is used to output a clock signal and receive a PWM closing signal, so that the PWM output is closed at a preset safe time based on the PWM closing signal.

[0020] The PWM closing control module is used to determine the level of the setting end based on a preset high-level threshold voltage and a control module setting end voltage, receive a power failure signal and determine the level of the data end of the control module based on the power failure signal, receive a clock signal and determine the level of the driving end of the control module based on the clock signal, and determine the level of the output end of the control module based on the level of the data end of the control module, the level of the driving end of the control module and the level of the setting end of the control module, so as to generate a PWM closing signal based on the level of the output end of the control module, and control the main control module to close the PWM output at a preset safe time based on the PWM closing signal, thereby realizing the inhibition of the shutdown stress of the synchronous rectifier tube.

[0021] The control circuit provided by the above scheme receives a power failure signal detected by a fault detection module through a PWM closing control module, and combines a clock signal of a main control module to realize signal integration transformation, so as to control the main control module to close the PWM output at a preset safe time, thereby avoiding the synchronous rectifier stress problem caused by the negative current of the output inductor under no load and light load conditions.

[0022] Further, the PWM closing control module is further configured to, when the power failure signal is not present, determine the control module output terminal voltage based on the control module data terminal voltage, the control module drive terminal voltage and the control module set terminal voltage, generate a release signal based on the control module output terminal voltage, and make the master control module continue the original working state based on the release signal.

[0023] In the above scheme, the PWM closing control module generates the release signal when the power failure signal is not present to release the control of the master control module, so that the master control module can continue the original working state, and the normal working state of the master control module is ensured.

[0024] Further, the PWM closing control module comprises a flip-flop, a switch tube, an initial capacitor, an initial resistor and an auxiliary power supply, wherein:

[0025] The drive terminal of the flip-flop is used as a PWM closing control module clock receiving terminal and is electrically connected with the output terminal of the master control module; the data terminal of the flip-flop is used as a PWM closing control module failure receiving terminal and is electrically connected with the output terminal of the failure detection module; the data terminal of the flip-flop is electrically connected with the auxiliary power supply; the output terminal of the flip-flop is electrically connected with the receiving terminal of the switch tube; the set terminal of the flip-flop is electrically connected with the output terminal of the initial resistor; and the reset terminal of the flip-flop is electrically connected with the data terminal.

[0026] The input terminal of the initial resistor is electrically connected with the auxiliary power supply.

[0027] The first output terminal of the switch tube is used as a PWM closing control module output terminal and is electrically connected with the receiving terminal of the master control module; and the second output terminal of the switch tube is grounded.

[0028] The output terminal of the initial resistor is electrically connected with the input terminal of the initial capacitor; and the output terminal of the initial capacitor is grounded.

[0029] The auxiliary power supply is used to charge the initial capacitor through the initial resistor to determine the control module set terminal voltage based on a preset high voltage threshold and the control module set terminal voltage.

[0030] The flip-flop is used to receive a clock signal to determine the control module drive terminal voltage based on the clock signal; and receive a power failure signal to determine the control module data terminal voltage based on the power failure signal; so as to determine the control module output terminal voltage based on the control module data terminal voltage, the control module drive terminal voltage and the control module set terminal voltage.

[0031] The switch tube is used to generate a PWM closing signal based on the control module output terminal voltage to control the master control module to close the PWM output at a preset safe time based on the PWM closing signal, so as to realize the suppression of the turn-off stress of the synchronous rectifier tube.

[0032] In the scheme, the circuit composition of the PWM closing control module is designed, and through the cooperation of the flip-flop, the switch tube and some resistance-capacitance devices, the signal integration based on the power failure signal and the clock signal is realized based on the asynchronous clear and set functions of the flip-flop, that is, the level conversion, and finally the PWM closing signal is generated at the level of the output end of the control module, so as to control the main control module to close the PWM output at the preset safe time, and the turn-off stress of the synchronous rectifier tube is suppressed.

[0033] Further, when the power failure signal does not exist: the flip-flop is further used to determine the level of the output end of the control module based on the level of the data end of the control module, the level of the driving end of the control module and the level of the set end of the control module; and the switch tube is further used to generate a release signal based on the level of the output end of the control module, so as to make the main control module continue the original working state based on the release signal.

[0034] In the scheme, when the power failure signal does not exist, the release signal is generated through the level change of the flip-flop, so as to release the control of the main control module, so that it can continue the original working state, and the normal working state of the main control module is ensured not to be affected.

[0035] Further, the PWM closing control module further comprises a pull-up resistor, an input end of the pull-up resistor is electrically connected with the input end of the initial resistor, and an output end of the pull-up resistor is electrically connected with the data end of the flip-flop.

[0036] In the scheme, the pull-up resistor is added to prevent the set end of the flip-flop from being in an indefinite state, and the stability of the working state of the circuit is maintained.

[0037] Further, the PWM closing control module further comprises a protection resistor, a first end of the protection resistor is electrically connected with the output end of the flip-flop, and a second end of the protection resistor is electrically connected with the receiving end of the switch tube.

[0038] In the scheme, the protection resistor is arranged to maintain the stability of the current and voltage of the circuit, and the damage of the device is avoided.

[0039] Further, the PWM closing control module further comprises a NOT gate, wherein: an output end of the NOT gate is electrically connected with the driving end of the flip-flop, and a receiving end of the NOT gate is electrically connected with the clock output end of the main control module as the receiving end of the PWM closing control module; and the NOT gate is used to receive the clock signal and perform inversion to generate a driving signal, so as to determine the level of the driving end of the control module based on the driving signal.

[0040] In the scheme, the NOT gate is additionally arranged to provide another processing mode, and the flip-flop is triggered by the falling edge to generate the PWM closing signal at the preset safe time.

[0041] The application provides a control circuit for inhibiting light-load shutdown stress of a synchronous rectifier tube, wherein a power failure signal detected by a failure detection module is transmitted to a PWM closing control module first, and then, signal integration and transformation are performed through simple level triggering conditions in combination with a clock signal of a main control module, so that the main control module outputs a PWM closing signal at a preset safe time, and the main control module is closed at the preset safe time, thereby avoiding the stress problem of the synchronous rectifier tube caused by output inductance negative current under no-load and light-load conditions; meanwhile, a release signal is generated when the power failure signal does not exist, so as to release the control of the main control module, and the main control module can continue the original working state. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A control method for inhibiting light-load shutdown stress of a synchronous rectifier tube is provided for an embodiment of the application.

[0043] Figure 2 A control circuit for inhibiting light-load shutdown stress of a synchronous rectifier tube is provided for an embodiment of the application.

[0044] Figure 3 A full-bridge topology converter circuit is provided for an embodiment of the application.

[0045] Figure 4 A working mode waveform of the full-bridge topology converter circuit under no-load steady state is provided for an embodiment of the application.

[0046] Figure 5 A circuit schematic diagram of a non-isolated Buck converter with a single-end topology of a synchronous rectifier converter is provided for an embodiment of the application.

[0047] Figure 6 A working mode waveform of a non-isolated Buck converter with a single-end topology of a synchronous rectifier converter is provided for an embodiment of the application.

[0048] Figure 7 A schematic diagram of inductor front-end voltage waveform and VDS waveforms of MOS tubes SR1 and SR2 when the PWM is closed at t0-t1 stage is provided for an embodiment of the application.

[0049] Figure 8 A schematic diagram of inductor front-end voltage waveform and VDS waveforms of MOS tubes SR1 and SR2 when the PWM is closed at t1-t2 stage is provided for an embodiment of the application.

[0050] Figure 9 A schematic diagram of inductor front-end voltage waveform and VDS waveforms of MOS tubes SR1 and SR2 when the PWM is closed at t2-t3 stage is provided for an embodiment of the application.

[0051] Figure 10 A schematic diagram of the inductor front-end voltage waveform and the VDS waveforms of MOS transistors SR1 and SR2 when the PWM is closed in the t3-t4 stage is provided for an embodiment of the present application.

[0052] Figure 11 A schematic diagram of a control system for suppressing the light-load turn-off stress of a synchronous rectifier is provided for an embodiment of the present application.

[0053] Figure 12 A schematic diagram of a PWM closing control circuit for suppressing the light-load turn-off stress of a synchronous rectifier is provided for an embodiment of the present application.

[0054] Figure 13 A timing sequence diagram of the working process of a control circuit for suppressing the light-load turn-off stress of a synchronous rectifier is provided for an embodiment of the present application.

[0055] Figure 14 A schematic diagram of a control circuit for suppressing the light-load turn-off stress of a synchronous rectifier using a NAND gate is provided for an embodiment of the present application.

[0056] Figure 15 A timing sequence diagram of the working process of a control circuit for suppressing the light-load turn-off stress of a synchronous rectifier using a NAND gate is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0058] Embodiment One:

[0059] The present embodiment provides a control method for suppressing the light-load turn-off stress of a synchronous rectifier, which is applied to a control circuit for suppressing the light-load turn-off stress of a synchronous rectifier, as shown in Figure 1 The method comprises the following steps:

[0060] S1: determining the control module set end level based on a preset high-level threshold voltage and a control module set end voltage;

[0061] S2: receiving a power failure signal and determining the control module data end level based on the power failure signal;

[0062] S3: receiving a clock signal and determining the control module drive end level based on the clock signal;

[0063] S4: determining the control module output end level based on the control module data end level, the control module drive end level and the control module setting end level, to generate the PWM closing signal based on the control module output end level;

[0064] S5: controlling the main control module to close the PWM output at the preset safe time based on the PWM closing signal, to realize the turn-off stress inhibition of the synchronous rectifier tube.

[0065] The above scheme receives the power failure signal detected from the fault detection module, and combines the clock signal of the main control module to perform signal integration transformation, to control the main control module to close the PWM output at the preset safe time, to avoid the stress problem of the synchronous rectifier tube caused by the negative current of the output inductor under no-load and light-load conditions.

[0066] Optionally, step S4 includes: when the power failure signal exists, determining the control module output end level based on the control module data end level, the control module drive end level and the control module setting end level when the clock signal is a rising edge, to generate the PWM closing signal based on the control module output end level.

[0067] In the specific implementation process, the level change is generated by the control module interface power failure signal and the clock signal, which corresponds to the change of the output end level, so that the output end level signal that appears when the clock signal is a rising edge generates the PWM closing signal when the power failure signal exists, and then the main control module can be controlled to close the PWM output at the preset safe time based on this signal, which simply and effectively solves the stress problem that occurs when closing at a non-pre-set safe time.

[0068] Optionally, when the power failure signal does not exist, the control module output end level is determined based on the control module data end level, the control module drive end level and the control module setting end level, to generate the release signal based on the control module output end level, to make the main control module continue the original working state based on the release signal.

[0069] The control method for inhibiting the light-load turn-off stress of the synchronous rectifier tube provided in the embodiment receives the power failure signal detected from the fault detection module, and combines the clock signal of the main control module to perform signal integration transformation through simple level triggering, to control the main control module to close the PWM output at the preset safe time, to avoid the stress problem of the synchronous rectifier tube caused by the negative current of the output inductor under no-load and light-load conditions; and when the power failure signal does not exist, a release signal is generated to release the control of the main control module, so that it can continue the original working state.

[0070] Embodiment two:

[0071] The embodiment provides a control circuit for inhibiting turn-off stress of a synchronous rectifier tube under light load, and the control circuit is used for realizing a control method for inhibiting turn-off stress of a synchronous rectifier tube under light load, as shown in the method. Figure 2 As shown in the method, the control circuit comprises a fault detection module, a main control module and a PWM closing control module, wherein:

[0072] The output end of the fault detection module is electrically connected with the input end of the main control module, and the output end of the fault detection module is electrically connected with the fault receiving end of the PWM closing control module; the clock receiving end of the PWM closing control module is electrically connected with the clock output end of the main control module; and the output end of the PWM closing control module is electrically connected with the receiving end of the main control module.

[0073] The fault module is used for outputting a power failure signal.

[0074] The main control module is used for outputting a clock signal and receiving a PWM closing signal to close PWM output at a preset safe time based on the PWM closing signal.

[0075] The PWM closing control module is used for determining a set end level based on a preset high-level threshold voltage and a control module set end voltage; receiving the power failure signal and determining a control module data end level based on the power failure signal; receiving the clock signal and determining a control module driving end level based on the clock signal; and determining a control module output end level based on the control module data end level, the control module driving end level and the control module set end level to generate the PWM closing signal based on the control module output end level; so as to control the main control module to close the PWM output at the preset safe time based on the PWM closing signal, and realize inhibition of turn-off stress of the synchronous rectifier tube.

[0076] The control circuit provided by the above scheme receives the power failure signal detected by the fault detection module through the PWM closing control module, and combines the clock signal of the main control module to perform signal integration and transformation, so as to control the main control module to close the PWM output at the preset safe time, thereby avoiding the problem of stress of the synchronous rectifier tube caused by negative inductive current under no-load and light load.

[0077] In the specific implementation process, as Figure 3As shown, the full-bridge topology converter is taken as an example, the secondary side adopts the full-bridge synchronous rectification mode, the input voltage is Vin, the output voltage is Vo, and the working mode of half a cycle in the no-load steady state is as follows: (1) in the t0-t1 stage, the primary side switch tubes S1 and S4 are turned on, the secondary side synchronous rectification tubes SR1 and SR4 are turned on, SR2 and SR3 are turned off, and the energy is transmitted from the input end to the output end, at this time, it is rectification stage 1, and the output inductor current (iL) is gradually reduced in the negative direction; (2) in the t1-t2 stage, the state of the switch tube is unchanged, at this time, it is rectification stage 2, and the output inductor current is turned to be positive and gradually increases; (3) in the t2-t3 stage, all the switch tubes of the primary side are turned off, and all the switch tubes of the secondary side are turned on, at this time, it is freewheeling stage 1, and the output inductor current is reduced to zero in the positive direction; (4) in the t3-t4 stage, the state of the switch tube is unchanged, at this time, it is freewheeling stage 2, and the output inductor current is turned to be negative and gradually increases; the lower half cycle is consistent with the above (1)-(4), and the inductor front end (VFF point) waveform is as shown in Figure 4 As shown in Figure 5 As shown, when the synchronous rectification converter is a single-ended topology non-isolated Buck converter (including the primary side switch tube S1 and the synchronous rectification tube SR1), the output inductor current waveform is as shown in Figure 6 As shown, like the full-bridge converter, it is divided into four stages, and the inductor current is positive in the t1-t3 interval, and closing the PWM in this interval will not cause stress problems, and the difference is that the Buck converter completes the current circulation once in a cycle, and the full-bridge converter is in half a cycle; the synchronous rectification topology can be a single-ended topology, for example, a forward converter, a BUCK converter, or a double-ended topology, for example, a full-bridge converter, a half-bridge converter, a push-pull converter, etc., which can be controlled by the PWM of the scheme.

[0078] When the power converter trigger protection needs to turn off the PWM, the PWM off point is random, which can appear at any time in the four stages in a cycle, Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 The inductor front end (VFF point) voltage waveform and the MOS tube SR1_VDS / V, SR2_VDS / V and iL / A and time / mSecs waveform when the PWM is turned off in different stages, wherein the horizontal coordinate value interval is selected to be 5, and the vertical coordinate value interval is selected to be 10; (1) as shown in Figure 7As shown, PWM is turned off in the t0-t1 stage. Before PWM is turned off, the VDS voltage of SR2 is Vin / N (N is the transformer turns ratio), the VDS voltage of SR1 is 0, and the inductor current is negative. When PWM is turned off at this time, the negative current will charge the parasitic capacitance and absorption capacitance of the MOS transistor. The voltage at VFF point rises from Vin / N until the negative current of the inductor is completely discharged. The increased voltage is called ΔVa. Since the initial VDS voltage of SR2 is Vin / N, its stress is Vin / N+ΔVa / 2, while the VDS of SR1 rises from 0 to ΔVa / 2. Next is the resonance process of the magnetizing inductor, the output inductor and the parasitic capacitance of the MOS. Turning off in this interval will lead to excessive stress problems, especially when PWM is turned off in the initial stage close to t0, the negative current is large and the stress is the greatest. (2) Figure 8 As shown, PWM is turned off in the t1-t2 stage. Before PWM is turned off, the VDS voltage of SR2 is Vin / N (N is the transformer turns ratio), the VDS voltage of SR1 is 0, and the output inductor current is positive. When PWM is turned off, due to the presence of magnetizing inductance and magnetizing current, and iL>im*N at this time, the output inductor enters the freewheeling stage, and the VDS of SR1 and SR2 are both 0. When iL=im*N, the VDS voltage of SR1 rises and is clamped at Vin / N, the VDS voltage of SR2 is still 0, and then the inductor current and magnetizing current both slowly decrease to 0. During this period, the output inductor and the MOS parasitic capacitance are in resonance. Then the output inductor, the parasitic capacitance of each MOS tube, and the magnetizing inductor resonate together. The stress of the synchronous rectifier tube is low and there is no risk when PWM is turned off in this interval. (3) Figure 9 As shown, PWM is turned off in the t2-t3 stage. Before PWM is turned off, the VDS voltage of SR2 is 0, the VDS voltage of SR1 is 0, and the inductor current is decreasing in the positive direction. When PWM is turned off, due to the presence of magnetizing inductor and magnetizing current, the VDS voltage of SR1 is clamped at Vin / N, the VDS voltage of SR2 is 0, the voltage across the inductor is still positive, and the current rises again. When iL = im*N, the inductor current and magnetizing current both slowly decrease to 0. During this period, the output inductor and the MOS parasitic capacitance are in resonance. Then the output inductor, the parasitic capacitance of each MOS transistor, and the magnetizing inductor resonate together. The stress of the synchronous rectifier is low and there is no risk when PWM is turned off in this interval. (4) Figure 10As shown, in the t3-t4 stage, the PWM is turned off, before the PWM is turned off, the VDS voltage of SR2 is 0, the VDS voltage of SR1 is 0, and the inductor current is negative and rises upward; at this time, the PWM is turned off, the negative current charges the parasitic capacitance and the absorption capacitance of the MOS tube, and the voltage at the VFF point rises from 0 to the full discharge of the negative inductor current; the part of the voltage that is increased is referred to as ΔVa; in an ideal state, the stress of SR1 and SR2 is ΔVa / 2; however, in actuality, due to the existence of the transformer excitation current, in the case that all MOS are turned off, the excitation current still needs to establish a flow path, resulting in that the stress of SR1 is Vin / N+ΔVa / 2, and the stress of SR2 is ΔVa / 2; turning off in this interval will cause a problem of excessively high stress, especially when the PWM is turned off close to the t4 moment, the negative current is large, and the stress is maximum. In summary, it can be known that when the converter is in an idle or light load state, in the t0-t1 and t3-t4 time periods, the output inductor has a negative current, at this time, the PWM output is turned off, a high stress is formed in the DS of one of the synchronous rectification MOS tubes, and the synchronous rectification MOS tube is easily damaged due to over-stress, that is, the preset safe moment can be selected as the t2 moment, and the key to solving the problem is to control the PWM to be turned off at a suitable controllable point, rather than randomly.

[0079] In the specific implementation process, the fault detection module can be built by an analog circuit or realized by a single-chip microcomputer, and is mainly used for detecting overvoltage, undervoltage, over-temperature, over-current and other protections of the power supply module, so as to send a power supply fault signal based on the detection result, make the main control module turn off the PWM output, and the traditional way is that the fault detection signal directly gives the main control chip, resulting in that the moment of turning off the PWM is random and stress problems are easily caused; the embodiment first processes the power supply fault signal and then transmits it to the main control module, so that the PWM is turned off at the preset safe moment.

[0080] In the specific implementation process, the control circuit for suppressing the light load turn-off stress of the synchronous rectification tube is built into the control system for suppressing the light load turn-off stress of the synchronous rectification tube, and the power supply is turned off at a safe moment, such as Figure 11 As shown, the system includes an auxiliary power supply circuit, a fault detection circuit, a PWM turn-off control circuit, a main control IC, a driving circuit and an auxiliary power supply circuit; the auxiliary power supply circuit is used for supplying power to each module, the fault detection circuit is used for detecting and obtaining a power supply fault signal (Fault_signal) based on the main control IC and transmitting it to the PWM turn-off control circuit, the PWM turn-off control circuit is also used for receiving a clock signal (the clock signal is a driving signal PWM_SR1 or PWM_SR2 sent by the main control IC to the synchronous rectification tube SR1 or SR2) from the main control IC, obtaining a PWM turn-off signal (Shutdown) based on the clock signal and the power supply fault signal, and thereby controlling the main control IC to turn off the PWM output (PWM_S1 or PWM_S2) to the driving circuit.

[0081] Optionally, the PWM closing control module is further configured to, when the power failure signal is not present, determine the control module output terminal voltage level based on the control module data terminal voltage level, the control module drive terminal voltage level and the control module set terminal voltage level, generate a release signal based on the control module output terminal voltage level, and cause the master control module to continue the original working state based on the release signal when the power failure signal is not present.

[0082] In the specific implementation process, the PWM closing control module releases the control of the master control module by generating the release signal when the power failure signal is not present, so that the master control module can continue the original working state, thereby ensuring that the normal working state of the master control module is not affected.

[0083] Optionally, the PWM closing control module comprises a flip-flop, a switch tube, an initial capacitor, an initial resistor and an auxiliary power supply, wherein:

[0084] The drive terminal of the flip-flop is used as a PWM closing control module clock receiving terminal and is electrically connected to the output terminal of the master control module; the data terminal of the flip-flop is used as a PWM closing control module failure receiving terminal and is electrically connected to the output terminal of the failure detection module; the data terminal of the flip-flop is electrically connected to the auxiliary power supply; the output terminal of the flip-flop is electrically connected to the receiving terminal of the switch tube; the set terminal of the flip-flop is electrically connected to the output terminal of the initial resistor; and the reset terminal of the flip-flop is electrically connected to the data terminal.

[0085] The input terminal of the initial resistor is electrically connected to the auxiliary power supply.

[0086] The first output terminal of the switch tube is used as a PWM closing control module output terminal and is electrically connected to the receiving terminal of the master control module; and the second output terminal of the switch tube is grounded.

[0087] The output terminal of the initial resistor is electrically connected to the input terminal of the initial capacitor; and the output terminal of the initial capacitor is grounded.

[0088] The auxiliary power supply is used to charge the initial capacitor through the initial resistor, so as to determine the control module set terminal voltage level based on a preset high voltage level threshold and the control module set terminal voltage.

[0089] The flip-flop is used to receive a clock signal to determine the control module drive terminal voltage level based on the clock signal; and receive a power failure signal to determine the control module data terminal voltage level based on the power failure signal; thereby determining the control module output terminal voltage level based on the control module data terminal voltage level, the control module drive terminal voltage level and the control module set terminal voltage level.

[0090] The switch tube is used to generate a PWM closing signal based on the control module output terminal voltage level, and control the master control module to close the PWM output at a preset safe time based on the PWM closing signal, so as to realize the suppression of the turn-off stress of the synchronous rectifier tube.

[0091] In the implementation process, the flip-flop can be a rising edge triggered D-type flip-flop, and the switch tube can be a triode or a MOS tube; the PWM closing control module has two input signals, one power supply and one output signal, the auxiliary power supply is the power supply Vcc of the flip-flop, generally 3.3V, which is determined according to the specific selected chip model; the output signal is the output signal of the collector of the triode or the drain of the MOS tube, which is generally connected to the UVLO pin or the SS pin of the main control module, i.e. the receiving end of the main control module, and these pins being pulled low can close the PWM output, that is, based on the PWM closing signal to control the main control module to close the PWM output at the preset safe time, so as to realize the suppression of the turn-off stress of the synchronous rectifier tube.

[0092] Optionally, when the power failure signal does not exist: the flip-flop is further used to determine the control module output end level based on the control module data end level, the control module drive end level and the control module set end level; and the switch tube is further used to generate a release signal based on the control module output end level, so as to make the main control module continue the original working state based on the release signal.

[0093] In the implementation process, when the power failure signal does not exist, the release signal is generated by the level change of the flip-flop to release the control of the main control module, so that it can continue the original working state, and the normal working state of the main control module is ensured not to be affected.

[0094] Optionally, the PWM closing control module further comprises a pull-up resistor, the pull-up resistor input end and the initial resistor input end are electrically connected, and the pull-up resistor output end and the flip-flop data end are electrically connected.

[0095] In the implementation process, the pull-up resistor is added to prevent the flip-flop set end from being in an indefinite state, and the stability of the circuit working state is maintained.

[0096] Optionally, the PWM closing control module further comprises a protection resistor, the protection resistor first end and the flip-flop output end are electrically connected, and the protection resistor second end and the switch tube receiving end are electrically connected.

[0097] In the implementation process, the protection resistor is set to maintain the stability of the circuit current and voltage, and to avoid device damage.

[0098] In the implementation process, the circuit diagram of the PWM closing control module is as follows Figure 12As shown, the D-type flip-flop IC1 is adopted, after power-on, the D pin (data end) and RST\ pin are high level, Vcc (auxiliary power supply) charges C1 (initial capacitor) through R1 (initial resistor), PRE\ (set end) is low level before the voltage reaches the preset high level threshold voltage, Fault_signal is high during the power-on initialization process, the power module detects that all voltages, temperatures and other things are normal, and then sets low (L), the main control IC starts. According to the function table shown in Table 1 below (X represents any state), the input end (INPUTS) controls the level change of the output end (OUTPUTS): the Q pin (output end) outputs high level (H), the role of R1 and C1 is to initialize the output of the flip-flop to high level, Q1 is pulled low, the main control module does not start and waits for the initialization of the fault detection module and the detection of the power fault signal; when PRE\ is higher than the threshold voltage and is maintained, PWM_SR1 and PWM_SR2 have no signal because the machine has not started, when the fault detection module detects no fault, Fault_signal becomes low level, because RST\ is low level, Q is low level, Q1 is disconnected, the main control IC can start, PWM_SR1 and PWM_SR2 start to have signals; during the normal operation of the module, if a fault occurs, the fault detection module sets Fault_signal signal to high level, in the case that RST\ and PRE\ are high level, the output Q is determined by D, and is updated when the rising edge (↑) of CLK comes, the rising edge of PWM_SR1 or PWM_SR2 comes, Q is set to high level, Q1 is pulled low, and the PWM output of the main control IC is turned off. The rising edge of PWM_SR1 or PWM_SR2 corresponds to t2, at this time, turning off the PWM synchronous rectifier tube will not cause high stress. When the fault is eliminated, Fault_signal becomes low level, Q is cleared again, Q1 is turned off, a release signal is generated, and the main control IC is released and can start next time. The timing diagram of this working process is shown in Figure 13 .

[0099] Table 1: Flip-flop function table

[0100]

[0101] Optionally, the PWM shutdown control module further comprises a NOT gate, wherein: the NOT gate output end is electrically connected with the flip-flop driving end, the NOT gate receiving end is used as the PWM shutdown control module receiving end and is electrically connected with the main control module clock output end; the NOT gate is used for receiving a clock signal and inverting the clock signal to generate a driving signal, so as to determine the control module driving end level based on the driving signal.

[0102] In the implementation process, if the trigger is a falling edge triggered D-type flip-flop, since the falling edge of PWM_S1 or PWM_S2 is also the corresponding t2 moment, the primary side MOS driving signal PWM_S1 or PWM_S2 can be used as the clock signal of the D flip-flop; similarly, when PWM_S1 or PWM_S2 triggers a D flip-flop at the same time and is an up edge triggered D flip-flop, PWM_S1 or PWM_S2 can be connected to the CLK pin after being inverted by a NOT gate (IC2) or a resistance in combination with a MOS, and the circuit schematic diagram is as shown in Figure 14 .

[0103] In the implementation process, when the power failure signal comes, the up edge triggered D flip-flop waits for the next up edge to trigger the PWM to be closed, so that the maximum delay time is one period, although the time is very short, after the improvement of the embodiment, the delay time can be further reduced. The input of the PWM closing control module is three signals, the fault signal Fault_signal output by the fault detection module, the driving PWM_SR1 sent by the main control IC to the synchronous rectifier SR1, and the driving PWM_SR2 sent by the main control IC to the synchronous rectifier SR2. After the PWM_SR1 and PWM_SR2 pass through an AND gate, the signal generated is connected to the CLK pin. This signal can fuse the up edges of the two signals, so that the delay time is reduced to half a period. The timing diagram of the specific working process is as shown in Figure 15 . There are many ways to generate the signal of the CLK pin, for example, using PWM_S1 and PWM_S2 after passing through a NOT gate, as long as the PWM can be closed at t2.

[0104] The control circuit for suppressing the light load shutdown stress of the synchronous rectifier provided by the embodiment can transmit the power failure signal detected by the fault detection module to the PWM closing control module first, combine the clock signal of the main control module, and perform signal integration and transformation through a simple level trigger condition, so as to control the main control module to output the PWM closing signal at the preset safe moment, so that the main control module closes the PWM output at the preset safe moment, avoiding the problem of the stress of the synchronous rectifier caused by the output inductive negative current in the no-load and light load conditions. At the same time, when the power failure signal does not exist, a release signal is generated to release the control of the main control module, so that the main control module can continue the original working state.

[0105] The above is the preferred embodiment of the present application, and it should be pointed out that for ordinary skilled persons in the technical field, without departing from the principle of the present application, a number of improvements and refinements can be made, which are also considered to be within the protection scope of the present application.

Claims

1. A control circuit for suppressing the light-off stress of a synchronous rectifier tube, characterized by comprising: The PWM closing control module comprises a flip-flop, a switch tube, an initial capacitor, an initial resistor and an auxiliary power supply. The fault detection module is electrically connected with the output end of the main control module. The fault detection module is configured to output a power failure signal. The main control module is configured to output a clock signal and receive a PWM closing signal to close the PWM output at a preset safe time based on the PWM closing signal. The PWM closing control module comprises a flip-flop, a switch tube, an initial capacitor, an initial resistor and an auxiliary power supply. The driving end of the flip-flop is electrically connected with the output end of the main control module as the clock receiving end of the PWM closing control module. The data end of the flip-flop is electrically connected with the output end of the fault detection module as the fault receiving end of the PWM closing control module. The data end of the flip-flop is electrically connected with the auxiliary power supply. The output end of the flip-flop is electrically connected with the receiving end of the switch tube. The setting end of the flip-flop is electrically connected with the output end of the initial resistor. The input end of the initial resistor is electrically connected with the auxiliary power supply. The first output end of the switch tube is electrically connected with the receiving end of the main control module as the output end of the PWM closing control module. The second output end of the switch tube is grounded.

2. The control circuit for suppressing the stress of the turn-off of the synchronous rectifier tube in light load according to claim 1, wherein The output end of the initial resistor is electrically connected with the input end of the initial capacitor.

3. The control circuit for suppressing the stress of the turn-off of the synchronous rectifier tube in light load according to claim 1, wherein The output end of the initial capacitor is grounded. The auxiliary power supply is configured to charge the initial capacitor through the initial resistor to determine the voltage level of the setting end of the control module based on a preset high voltage threshold and the voltage of the setting end of the control module. The flip-flop is configured to receive the clock signal to determine the voltage level of the driving end of the control module based on the clock signal, receive the power failure signal to determine the voltage level of the data end of the control module based on the power failure signal, and determine the voltage level of the output end of the control module based on the voltage level of the data end of the control module, the voltage level of the driving end of the control module and the voltage level of the setting end of the control module.

4. The control circuit for suppressing the stress of the turn-off of the synchronous rectifier tube in light load according to claim 1, characterized in that, The switch tube is configured to generate the PWM closing signal based on the voltage level of the output end of the control module to control the main control module to close the PWM output at the preset safe time based on the PWM closing signal, thereby suppressing the turn-off stress of the synchronous rectifier tube.

5. The control circuit for suppressing the stress of the turn-off of the synchronous rectifier tube in light load according to claim 1, wherein The PWM closing control module is further configured to, when the power failure signal is absent, determine the voltage level of the output end of the control module based on the voltage level of the data end of the control module, the voltage level of the driving end of the control module and the voltage level of the setting end of the control module, generate a release signal based on the voltage level of the output end of the control module, and control the main control module to continue the original working state based on the release signal. When the power failure signal is absent: The flip-flop is further configured to determine the voltage level of the output end of the control module based on the voltage level of the data end of the control module, the voltage level of the driving end of the control module and the voltage level of the setting end of the control module. The switch tube is further configured to generate the release signal based on the voltage level of the output end of the control module to control the main control module to continue the original working state based on the release signal. The PWM closing control module further comprises a pull-up resistor, the input end of the pull-up resistor is electrically connected with the input end of the initial resistor, and the output end of the pull-up resistor is electrically connected with the data end of the flip-flop. The PWM closing control module further comprises a protection resistor, the first end of the protection resistor is electrically connected with the output end of the flip-flop, and the second end of the protection resistor is electrically connected with the receiving end of the switch tube.

6. The control circuit for suppressing the stress of the turn-off of the synchronous rectifier tube in light load according to claim 1, wherein The PWM closing control module further comprises a NOT gate, wherein: The output end of the NOT gate is electrically connected with the driving end of the flip-flop, and the receiving end of the NOT gate serves as the receiving end of the PWM closing control module and is electrically connected with the clock output end of the master control module; The NOT gate is used for receiving a clock signal and performing inversion to generate a driving signal, so as to determine the level of the driving end of the control module based on the driving signal.

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