High-speed brushless direct current motor hardware commutation circuit with fault self-detection function

Abstract

The invention relates to the field of brushless direct current motor hardware commutation circuits, in particular to a high-speed brushless direct current motor hardware commutation circuit with a fault self-detection function. The high-speed brushless direct current motor hardware commutation circuit with the fault self-detection function has remarkable technical advantages and practical value, hardware commutation replaces traditional software commutation, resource occupation of a single-chip microcomputer is greatly reduced, the response speed and the operation efficiency of a system are improved, and the high-speed brushless direct current motor hardware commutation circuit with the fault self-detection function is suitable for popularization and application. The brushless direct current motor is enabled to stably realize high-speed operation, meanwhile, the design integrates a complete fault self-detection function, each module in a hardware commutation circuit can be monitored in real time, and the hardware commutation circuit comprises key parts such as a PWM speed regulation circuit, a Hall signal decoding circuit, a commutation selection circuit and a fault display circuit; the problem that a hardware commutation circuit in the prior art lacks real-time monitoring capability on the running state of the motor is solved.

Description

Technical Field

[0001] The present invention relates to the field of brushless DC motor hardware commutation circuits, and specifically to a high-speed brushless DC motor hardware commutation circuit with fault self-detection. Background Art

[0002] Due to its high efficiency, reliability, and low maintenance characteristics, brushless DC motors are widely used in industrial control, automotive, and household electrical appliance fields. Currently, most brushless DC motor control systems use a single-chip microcomputer for software commutation. However, when the motor runs at high speed, due to frequent commutation, the resource occupancy of the single-chip microcomputer increases significantly, which easily leads to commutation lag problems. Therefore, high-speed motors usually use hardware logic circuits to achieve commutation. Although the hardware commutation circuit is more suitable for high-speed applications in terms of performance, most existing designs are relatively simple and lack the ability to monitor the operating state of the motor in real time. When faults such as abnormal Hall sensor signals or decoder circuit failures occur, it usually relies on external devices or manual detection. This method not only increases the difficulty of fault location but also prolongs the repair cycle and reduces the system operation efficiency. In addition, if the fault is not detected in time and the motor enable is not cut off, it may have a serious impact on the safety of system operation. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the present invention provides a high-speed brushless DC motor hardware commutation circuit with fault self-detection, which solves the problem that the existing hardware commutation circuit lacks the ability to monitor the operating state of the motor in real time.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A high-speed brushless DC motor hardware commutation circuit with fault self-detection, including a brushless DC motor, further including:

[0006] A single-chip microcomputer module, which is used to output corresponding control signals to control a PWM speed regulation circuit, a Hall signal decoding circuit, and a steering selection circuit respectively;

[0007] A commutation selection circuit, which is used to select a commutation signal according to the state after Hall decoding output by the steering selection circuit to control the three-phase connection state of a three-phase inverter bridge;

[0008] A PWM speed regulation circuit, which is used to perform chopper speed regulation on the brushless DC motor according to the PWM speed regulation signal output by the single-chip microcomputer module;

[0009] A three-phase inverter bridge, which is used to invert direct current into three-phase alternating current to drive the brushless DC motor;

[0010] Hall signal decoding circuit, which is used to read the three-phase Hall signals output by the brushless DC motor according to the decoder enable signal output by the single-chip microcomputer module, and convert them into corresponding Hall states through the decoder and output them to the steering selection circuit for logical judgment;

[0011] Steering selection circuit, which is used to screen the Hall decoded states according to the steering selection signal output by the single-chip microcomputer module and output them to the commutation selection circuit for commutation signal selection;

[0012] Fault detection module, which includes a speed regulation fault detection circuit, a decoding fault detection circuit, a commutation fault detection circuit and a fault signal display circuit, and is used to detect whether faults occur in the PWM speed regulation circuit, the Hall signal decoding circuit and the commutation selection circuit respectively, and display them.

[0013] Preferably, the commutation selection circuit includes eighteen first OR gates. Every three first OR gates form a group. The output terminals of each group of first OR gates correspond to the input terminals of one MOS transistor in the three-phase inverter bridge. One of the first OR gates in each group of first OR gates has its two input terminals connected to the output terminals of the other two first OR gates.

[0014] Preferably, the PWM speed regulation circuit includes six first AND gates, where three first AND gates are used for the upper half-bridge control of the three-phase inverter bridge, and the other three first AND gates are used for the lower half-bridge control of the three-phase inverter bridge.

[0015] Preferably, the three-phase inverter bridge includes MOS transistors Q1, Q2, Q3, Q4, Q5 and Q6. The gates of MOS transistors Q1, Q2, Q3, Q4, Q5 and Q6 are respectively connected to the six output terminals of the PWM speed regulation circuit. The drains of MOS transistors Q1, Q3 and Q5 are connected to each other and then connected to the power supply. The sources of MOS transistors Q2, Q4 and Q6 are connected to each other and then grounded. Three-phase currents are respectively output between the source of MOS transistor Q1 and the drain of MOS transistor Q2, between the source of MOS transistor Q3 and the drain of MOS transistor Q4, and between the source of MOS transistor Q5 and the drain of MOS transistor Q6.

[0016] Preferably, the Hall signal decoding circuit includes a decoding chip U1. The 1st, 2nd and 3rd pins of the decoding chip U1 are respectively connected to the U, V, and W of the Hall signal. The 4th and 5th pins are connected to the enable signal of the fault output module. The 6th pin is connected to the DC voltage. The 9th, 10th, 11th, 12th, 13th and 14th pins are respectively connected with first NOT gates.

[0017] Preferably, the steering selection circuit includes twelve second AND gates. The input ends of six of the second AND gates are used to connect to the six output ends of the Hall signal decoding circuit, the forward rotation signal output by the single-chip microcomputer module, and the NOT gate U9 for converting the forward rotation signal into a reverse rotation signal. The input ends of the other six second AND gates are respectively connected to the six output ends of the Hall signal decoding circuit and the output end of the NOT gate U9.

[0018] Preferably, the speed regulation fault detection circuit includes a digital comparator chip U54, and an AND gate U55 is connected to the 19th pin of the digital comparator chip U54.

[0019] Preferably, the decoding fault detection circuit includes an encoder chip U33 and a four-bit comparator chip U35. NOT gates U34A, U34B, and U34C are respectively connected between the 6th, 7th, and 9th pins of the encoder chip U33 and the 9th, 11th, and 14th pins of the corresponding four-bit comparator chip U35. A comparator U53 is connected to the 6th pin of the four-bit comparator chip U35.

[0020] Preferably, the commutation fault detection circuit includes two groups of logic gate circuits respectively connected to the forward rotation signal and the reverse rotation signal. Each group of logic gate circuits includes seven third AND gates, six exclusive-OR gates, two NOR gates, and one NAND gate. The two input ends of one of the third AND gates are respectively connected to the output end of the NAND gate and the forward rotation signal. NOR gates are respectively connected to the input ends of the NAND gate. Three exclusive-OR gates are respectively connected to the input ends of each NOR gate. One third AND gate is connected to the input end of each exclusive-OR gate.

[0021] Preferably, the fault display circuit includes three second OR gates. Two of the second OR gates are connected to the two input ends of the other second OR gate, and LEDs are connected to the input ends of these two second OR gates.

[0022] Compared with the prior art, the present invention provides a hardware commutation circuit for a high-speed brushless DC motor with fault self-detection, having the following beneficial effects:

[0023] 1. The hardware commutation circuit for a high-speed brushless DC motor with fault self-detection function provided by the present invention has significant technical advantages and practical value. By replacing traditional software commutation with hardware commutation, it not only greatly reduces the resource occupation of the single-chip microcomputer, but also improves the response speed and operation efficiency of the system, enabling the brushless DC motor to stably achieve high-speed operation. At the same time, this design integrates a complete fault self-detection function, which can monitor each module in the hardware commutation circuit in real time, including key parts such as the PWM speed regulation circuit, Hall signal decoding circuit, commutation selection circuit, and fault display circuit.

[0024] 2. When the system failure is detected in the present invention, the circuit can quickly and accurately locate the position where the failure occurs, and report the specific failure information to the single-chip microcomputer through logical judgment. After receiving the failure signal, the single-chip microcomputer will immediately cut off the enable signal of the Hall signal decoding circuit, thus stopping the operation of the entire system, ensuring that the system can quickly shut down in the failure state, and avoiding equipment damage or safety hazards that may be caused by continuous operation. In addition, the failure display circuit intuitively indicates the specific failure type through the LED lamp, facilitating the maintenance personnel to quickly identify the problem, reducing the complexity and cost of manual detection.

[0025] 3. This design can not only provide stable control performance under high-speed operation conditions, but also significantly improve the safety and reliability of the system. Compared with the traditional design, this scheme has obvious advantages in terms of failure detection efficiency and troubleshooting speed, providing an efficient and reliable hardware solution for the industrial application of brushless DC motors. Through this design, not only the potential risks during system operation are reduced, but also the stability of equipment operation and the convenience of maintenance are improved, saving time and resource costs for users, and at the same time promoting the development and application of high-speed brushless DC motor control technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments and descriptions thereof of the present application are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0027] Figure 1 is the system structure diagram of the present invention;

[0028] Figure 2 is the circuit diagram of the single-chip microcomputer module of the present invention;

[0029] Figure 3 is the corresponding diagram of the Hall state and the on-off of the MOS transistors in the three-phase inverter bridge of the present invention;

[0030] Figure 4 is the commutation selection circuit diagram of the present invention;

[0031] Figure 5 is the PWM speed regulation circuit diagram of the present invention;

[0032] Figure 6 is the three-phase inverter bridge circuit diagram of the present invention;

[0033] Figure 7 is the Hall signal decoding circuit diagram of the present invention;

[0034] Figure 8 is the steering selection circuit diagram of the present invention;

[0035] Figure 9It is the speed regulation fault detection circuit diagram of the present invention;

[0036] Figure 10 It is the decoding fault detection circuit diagram of the present invention;

[0037] Figure 11 It is the first circuit diagram for commutation fault detection of the present invention;

[0038] Figure 12 It is the second circuit diagram for commutation fault detection of the present invention;

[0039] Figure 13 It is the fault signal display circuit diagram of the present invention. Detailed implementation manners

[0040] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. Thus, the implementation process of how the present application uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0041] Those of ordinary skill in the art can understand that all or part of the steps in the following embodiment methods can be completed by instructing relevant hardware through a program. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0042] A hardware commutation circuit for a high-speed brushless DC motor with fault self-detection, as Figure 1 shown, includes a brushless DC motor, and further includes:

[0043] A single-chip microcomputer module for outputting corresponding control signals to control a PWM speed regulation circuit, a Hall signal decoding circuit, and a steering selection circuit respectively, as Figure 2As shown, the single-chip microcomputer model can be STM32F103C8T6 of STMicroelectronics. The PB3 pin of the single-chip microcomputer outputs a PWM debugging signal and connects it to the AND gates U10, U11, and U12 responsible for outputting the on-off signals of the upper half-bridge MOS transistors of the three-phase inverter bridge. When the duty cycle of the PWM modulation signal is larger, the motor speed is faster. The PB0 pin of the single-chip microcomputer outputs a level signal and connects it to the AND gates U3, U4, U5, U6, U7, and U8 responsible for outputting the forward rotation signal of the phase change selection circuit. At the same time, this level signal is connected to the AND gates U13, U14, U15, U16, U17, and U18 responsible for reverse rotation through the NOT gate U9. When the PB0 pin outputs a high level, the motor rotates forward; when it outputs a low level, the motor rotates in reverse. The PB1 pin of the single-chip microcomputer is the fault signal input pin, and this pin is connected to the output of U52C in the fault display circuit. The single-chip microcomputer can detect whether the circuit has a fault by scanning the level of this pin. The PB2 pin of the single-chip microcomputer is the enable pin of the Hall signal decoding circuit, and this pin is connected to the enable signal pins 4 and 5 of the 74LS138 decoder chip in the Hall signal decoding circuit, used to provide an enable signal to the decoder chip.

[0044] The circuit is a phase change selection circuit used to select the phase change signal according to the state after Hall decoding output by the steering selection circuit to control the three-phase connection state of the three-phase inverter bridge. There are a total of three phases of Hall signals, which can output eight states: 000, 111, 001, 010, 011, 100, 101, and 110. Among them, 000 and 111 belong to the fault states, and the remaining valid states have the corresponding relationships as Figure 3 shown during forward or reverse rotation with the conduction states of the MOS transistors of the three-phase inverter bridge. Therefore, the function of this circuit is to select the MOS transistors conducting the three-phase inverter bridge according to the Hall state output by the steering selection circuit. The composition of the phase change selection circuit is as Figure 4 shown. The circuit structure of the phase change selection circuit will be further described below. The phase change selection circuit includes eighteen first OR gates. Every three first OR gates form a group. The output terminals of each group of first OR gates correspond to the input terminals of one MOS transistor in the three-phase inverter bridge. One of the first OR gates in each group of first OR gates has its two input terminals connected to the output terminals of the other two first OR gates. The composition of each group of first OR gates is as Figure 4As shown, the outputs of the first OR gates U22A and U22B are connected to the inputs of the first OR gate U25, the outputs of the first OR gates U22C and U22D are connected to the inputs of the first OR gate U26, the outputs of the first OR gates U23A and U23B are connected to the inputs of the first OR gate U27, the outputs of the first OR gates U23C and U23D are connected to the inputs of the first OR gate U28, the outputs of the first OR gates U24A and U24B are connected to the inputs of the first OR gate U29, and the outputs of the first OR gates U24C and U24D are connected to the inputs of the first OR gate U30. The output of the first OR gate U25 is the control signal responsible for selecting whether to turn on the upper half-bridge of the U-phase of the three-phase inverter bridge. This signal is fed to the AND gate U10 in the PWM speed control circuit for PWM chopper modulation and then output to the upper half-bridge of the U-phase of the three-phase inverter bridge. The output of the first OR gate U26 is the control signal responsible for selecting whether to turn on the lower half-bridge of the U-phase of the three-phase inverter bridge. This signal is fed to the AND gate U19 in the PWM speed control circuit for PWM chopper modulation and then output to the lower half-bridge of the U-phase of the three-phase inverter bridge. The output of the first OR gate U27 is the control signal responsible for selecting whether to turn on the upper half-bridge of the V-phase of the three-phase inverter bridge. This signal is fed to the AND gate U11 in the PWM speed control circuit for PWM chopper modulation and then output to the upper half-bridge of the V-phase of the three-phase inverter bridge. The output of the first OR gate U28 is the control signal responsible for selecting whether to turn on the lower half-bridge of the V-phase of the three-phase inverter bridge. This signal is fed to the AND gate U20 in the PWM speed control circuit for PWM chopper modulation and then output to the lower half-bridge of the V-phase of the three-phase inverter bridge. The output of the first OR gate U29 is the control signal responsible for selecting whether to turn on the upper half-bridge of the W-phase of the three-phase inverter bridge. This signal is fed to the AND gate U12 in the PWM speed control circuit for PWM chopper modulation and then output to the upper half-bridge of the W-phase of the three-phase inverter bridge. The output of the first OR gate U30 is the control signal responsible for selecting whether to turn on the lower half-bridge of the W-phase of the three-phase inverter bridge. This signal is fed to the AND gate U21 in the PWM speed control circuit for PWM chopper modulation and then output to the lower half-bridge of the W-phase of the three-phase inverter bridge. The inputs of the first OR gate U22A are the outputs of the steering selection circuits U3 and U7, the input of U22B is the output of the steering selection circuits U14 and U18, the inputs of the first OR gate U22C are the outputs of the steering selection circuits U4 and U8, the input of U22D is the output of the steering selection circuits U13 and U17, the inputs of the first OR gate U23A are the outputs of the steering selection circuits U4 and U5, the input of U23B is the output of the steering selection circuits U16 and U17, the inputs of the first OR gate U23C are the outputs of the steering selection circuits U6 and U7, the input of U23D is the output of the steering selection circuits U14 and U15, the inputs of the first OR gate U24A are the outputs of the steering selection circuits U6 and U8, the input of U24B is the output of the steering selection circuits U13 and U15, the inputs of the first OR gate U24C are the outputs of the steering selection circuits U3 and U5, and the input of U24D is the output of the steering selection circuits U16 and U18.

[0045] A PWM speed control circuit for chopping speed control of a brushless DC motor according to the PWM speed control signal output by the single-chip microcomputer module, as Figure 5 shown. The specific structure of the PWM speed control circuit will be further described below, including six first AND gates U10, U11, U12, U19, U20, and U21, where three first AND gates are used for the upper half-bridge control of the three-phase inverter bridge, and the other three first AND gates are used for the lower half-bridge control of the three-phase inverter bridge.

[0046] A three-phase inverter bridge for converting direct current into three-phase alternating current to drive a brushless DC motor. The circuit structure of the three-phase inverter bridge circuit will be further described below. The three-phase inverter bridge includes MOS transistors Q1, Q2, Q3, Q4, Q5, and Q6. The gates of MOS transistors Q1, Q2, Q3, Q4, Q5, and Q6 are respectively connected to the six output terminals of the PWM speed control circuit. The drains of MOS transistors Q1, Q3, and Q5 are connected to each other and then connected to the power supply. The sources of MOS transistors Q2, Q4, and Q6 are connected to each other and then grounded. Three-phase currents are respectively output between the source of MOS transistor Q1 and the drain of MOS transistor Q2, between the source of MOS transistor Q3 and the drain of MOS transistor Q4, and between the source of MOS transistor Q5 and the drain of MOS transistor Q6.

[0047] A Hall signal decoding circuit for decoding the Hall signal according to the decoder enable signal output by the single-chip microcomputer module. The Hall signal decoding circuit reads the three-phase Hall signals output by the brushless DC motor and converts them into corresponding Hall states through the decoder and outputs them to the steering selection circuit for logical judgment. The specific structure of the Hall signal decoding circuit will be further described below, as Figure 7 shown. The Hall signal decoding circuit includes a decoding chip U1. The 1st, 2nd, and 3rd pins of the decoding chip U1 are respectively connected to the U, V, and W of the Hall signal. The 4th and 5th pins are connected to the enable signal of the fault output module. The 6th pin is connected to the DC voltage. The 9th, 10th, 11th, 12th, 13th, and 14th pins are respectively connected with first NOT gates.

[0048] A steering selection circuit for screening the Hall-decoded states according to the steering selection signal output by the single-chip microcomputer module and outputting them to the commutation selection circuit for commutation signal selection. The circuit structure of the steering selection circuit will be further described below, as Figure 8As shown in the figure, the steering selection circuit includes twelve second AND gates. The input terminals of six second AND gates U3, U4, U5, U6, U7, and U8 are used to connect the outputs of six output terminals of the Hall signal decoding circuit, namely U2A, U2B, U2C, U2D, U2E, and U2F, the forward rotation signal output by the single-chip microcomputer module, and the NOT gate U9 for converting the forward rotation signal into a reverse rotation signal. The input terminals of the other six second AND gates U13, U14, U15, U16, U17, and U18 are also respectively connected to the six output terminals of the Hall signal decoding circuit and the output terminal of the NOT gate U9.

[0049] The fault detection module including a speed regulation fault detection circuit, a decoding fault detection circuit, a commutation fault detection circuit, and a fault signal display circuit is used to respectively detect whether faults occur in the PWM speed regulation circuit, the Hall signal decoding circuit, and the commutation selection circuit, and display them.

[0050] The following further explains each circuit in the fault detection module:

[0051] As Figure 9 shown, the speed regulation fault detection circuit includes a digital comparator chip U54, such as a digital comparator chip with the signal 74LS688. The 2nd, 4th, 6th, 8th, 11th, and 13th pins of this chip are respectively connected to the output signals of the OR gates of the commutation selection circuit U25, U26, U27, U28, U29, and U30. The 3rd, 5th, 7th, 9th, 12th, and 14th pins are respectively connected to the output of the AND gates of the PWM speed regulation circuit U10, U11, U12, U19, U20, and U21. The 1st, 15th, 17th, 16th, and 18th pins are grounded. An AND gate U55 is connected to the 19th pin of the digital comparator chip U54. At the same time, the remaining two pins of the 55th AND gate are connected to the PWM speed regulation signal of the single-chip microcomputer and a high level. When the output of the commutation selection circuit is inconsistent with the output of the PWM speed regulation circuit, it indicates that the PWM speed regulation circuit is abnormal. At this time, the 55th AND gate outputs a high-level fault alarm signal, and at the same time, the LED lamp D3 of the fault display circuit will go out, indicating that this part is abnormal.

[0052] As Figure 10As shown, the decoding fault detection circuit includes an encoder chip U33 and a four-bit comparator chip U35. The model of the four-bit comparator chip U35 can be 74LS85, and the model of the encoder chip U33 can be 74LS148 encoder chip. Pins 0 and 7 of the encoder chip U33 are connected to +3.3V. There are NOT gates U34A, U34B, and U34C connected between pins 6, 7, and 9 of the encoder chip U33 and pins 9, 11, and 14 of the corresponding four-bit comparator chip U35 respectively. A comparator U53 is connected to pin 6 of the four-bit comparator chip U35. Pins 1, 2, 3, 4, 5, and 6 of the encoder chip U33 are respectively connected to the outputs of the 74LS138 chip in the Hall signal decoding circuit, which can inverse-encode the 6 Hall states decoded by the 74LS138 chip into the original three-phase Hall signals. Pins 6, 7, and 9 are respectively connected to the inputs of NOT gates U34A, U34B, and U34C. The output three-phase Hall signals of the NOT gates are connected to pins 9, 11, and 14 of the 74LS85 four-bit comparator chip U35. Pins 10, 12, and 13 of the 74LS85 four-bit comparator chip U35 are connected to the three-phase Hall signals output by the motor. Subsequently, the 74LS85 four-bit comparator chip U35 will compare the differences between the two groups of signals. If the two groups of signals are not equal, a high level will be output at pin 6 of the 74LS85 four-bit comparator chip U35. At this time, the Hall decoding fault indicator light in the fault display circuit goes out, indicating a fault in the Hall signal decoding circuit, and the decoded value does not correspond to the three-phase Hall value.

[0053] As Figure 11 and Figure 12As shown in the figure, the commutation fault detection circuit includes two sets of logic gate circuits respectively connected to the forward rotation signal and the reverse rotation signal. Each set of logic gate circuits includes seven third AND gates, six exclusive-OR gates, two NOR gates, and one NAND gate. The two input terminals of one of the third AND gates are respectively connected to the output terminal of the NAND gate and the forward rotation signal. NOR gates are respectively connected to the input terminals of the NAND gate. Three exclusive-OR gates are respectively connected to the input terminals of each NOR gate. One third AND gate is connected to the input terminal of each exclusive-OR gate. The logic gate circuit connected to the forward rotation signal is composed of 7 two-input single-output AND gates U36A, U36C, U38A, U38C, U39A, U39C, U50, 6 two-input single-output exclusive-OR gates U32B, U37A, U37B, U37C, U37D, U40A, 2 three-input single-output NOR gates U41A, U41B, and one NAND gate U42A. The logic gate circuit connected to the reverse rotation signal is composed of 7 two-input single-output AND gates U43A, U43C, U45A, U45C, U46A, U46C, U51, 6 two-input single-output exclusive-OR gates U44B, U44A, U44C, U44D, U47B, U47A, 2 three-input single-output NOR gates U48A, U48B, and one NAND gate U49A. AND gates U36A, U36C, U38A, U38C, U39A, U39C, U43A, U43C, U45A, U45C, U46A, U46C are connected to the commutation selection signal output by the commutation selection circuit. The exclusive-OR gates U32B, U37A, U37B, U37C, U37D, U40A, U44B, U44A, U44C, U44D, U47B, U47A respectively input and connect the outputs of the AND gates U36A, U36C, U38A, U38C, U39A, U39C, U43A, U43C, U45A, U45C, U46A, U46C and the corresponding Hall states output by the Hall signal decoding circuit. After logical judgment, the outputs of the exclusive-OR gates U32B, U37A, U37B are connected to the input of the NOR gate U41A. The outputs of the exclusive-OR gates U37C, U37D, U40A are connected to the input of the NOR gate U41B. The outputs of the exclusive-OR gates U44B, U44A, U44C are connected to the input of the NOR gate U48A. The outputs of the exclusive-OR gates U44D, U47B, U47A are connected to the input of the NOR gate U48B. After logical judgment, the NOR gates output and are connected to the NAND gate. Among them, the outputs of the NOR gates U41A, U41B are connected to the input of the NAND gate U42A. The outputs of the NOR gates U48A, U48B are connected to the input of the NAND gate U49A. After logical judgment, the output of the NAND gate U42A is connected to the input of the AND gate U50 and makes a logical judgment with the forward rotation signal. If a high level is output to the fault display circuit, the forward commutation fault indicator light goes out, indicating abnormal commutation during forward rotation.After the NAND gate U49A performs a logical judgment, its output is connected to the input of the AND gate U51. Together with the reverse signal, a logical judgment is made. If a high level is output to the fault display circuit, the reverse conversion fault indicator light goes out, indicating an abnormal commutation during the reverse process, thereby achieving the purpose of fault detection.

[0054] The fault display circuit includes three second OR gates. Two of the second OR gates are connected to the two input ends of the other second OR gate. LEDs are connected to the input ends of these two second OR gates. Specifically, as Figure 13 shown, the circuit consists of 4 LED lights D1, D2, D3, D4 and three OR gates U52A, U52B, U52C. D1 is the decoder fault indicator light, D2 is the PWM speed regulation fault indicator light, D3 is the forward rotation fault indicator light, and D4 is the reverse rotation fault indicator light. All the LED lights adopt the common anode connection method, with the anodes of the LED lights commonly connected to the +3.3V power supply, and the cathodes respectively connected to their corresponding fault signals. When there is no fault normally, the fault detection signals output by each fault detection circuit are at a low level, and the LED indicator lights are always on. When a fault occurs, the fault detection signals output by each fault detection circuit are at a high level, and the LED indicator lights go out, indicating that a fault has occurred. The four fault signals are respectively connected to the inputs of two OR gates U52A and U52B for logical judgment. The outputs of the two OR gates U52A and U52B are connected to the OR gate U52C for logical judgment. The signal output by U52C is connected to the PB1 pin of the single-chip microcomputer. When there is no fault, U52C outputs a low level, and the single-chip microcomputer determines that there is no fault. The PB2 pin of the single-chip microcomputer outputs a low level, and the 74LS138 decoder works normally. When any fault occurs, U52C outputs a high level, the single-chip microcomputer reads the abnormal state, the PB2 pin of the single-chip microcomputer outputs a high level, and the 74LS138 decoder stops working. At this time, the motor stops commutation and will not continue to run, thus ensuring the safe shutdown of the system.

[0055] The above embodiments have introduced the present invention in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A high-speed brushless DC motor hardware commutation circuit with fault self-detection, comprising a brushless DC motor, characterized in that: Also includes: A single-chip microcomputer module, wherein the single-chip microcomputer module is used to output corresponding control signals to respectively control a PWM speed regulation circuit, a Hall signal decoding circuit and a steering selection circuit; A commutation selection circuit, the commutation selection circuit is used to select a commutation signal to control the three-phase connection state of the three-phase inverter bridge according to the Hall decoded state output by the steering selection circuit; A PWM speed regulation circuit, wherein the PWM speed regulation circuit is used to perform chopping speed regulation on the brushless DC motor according to the PWM speed regulation signal output by the single-chip microcomputer module; A three-phase inverter bridge, which is used to invert direct current into three-phase alternating current to drive a brushless direct current motor; A Hall signal decoding circuit, which is used to read the three-phase Hall signal output by the brushless DC motor according to the decoder enable signal output by the single-chip microcomputer module, and convert it into a corresponding Hall state through the decoder and output it to the steering selection circuit for logic judgment; A steering selection circuit, the steering selection circuit is used to screen the state after Hall decoding according to the steering selection signal output by the single-chip module and output it to the phase switching selection circuit for phase switching signal selection; The fault detection module includes a speed regulation fault detection circuit, a decoding fault detection circuit, a phase change fault detection circuit and a fault signal display circuit, which are used to detect whether the PWM speed regulation circuit, the Hall signal decoding circuit and the phase change selection circuit have faults and display them.

2. The commutation circuit according to claim 1, characterized in that: The phase-changing selection circuit includes eighteen first OR gates, each three first OR gates form a group, the output end of each group of first OR gates corresponds to the input end of a MOS tube in the three-phase inverter bridge, and the two input ends of a first OR gate in each group of first OR gates are connected to the output ends of the other two first OR gates.

3. The commutation circuit according to claim 1, characterized in that: The PWM speed regulation circuit includes six first AND gates, three of which are used for controlling the upper half bridge of the three-phase inverter bridge, and the other three are used for controlling the lower half bridge of the three-phase inverter bridge.

4. The commutation circuit according to claim 1, characterized in that: The three-phase inverter bridge comprises MOS tubes Q1, Q2, Q3, Q4, Q5 and Q6, the gates of the MOS tubes Q1, Q2, Q3, Q4, Q5 and Q6 are respectively connected to the six output ends of the PWM speed regulation circuit, the drains of the MOS tubes Q1, Q3 and Q5 are connected to each other and then to the power supply, the sources of the MOS tubes Q2, Q4 and Q6 are connected to each other and then to the ground, and three-phase currents are respectively output between the source of the MOS tube Q1 and the drain of the MOS tube Q2, between the source of the MOS tube Q3 and the drain of the MOS tube Q4, and between the source of the MOS tube Q5 and the drain of the MOS tube Q6.

5. The commutation circuit according to claim 1, characterized in that: The Hall signal decoding circuit includes a decoding chip U1, wherein pins 1, 2 and 3 of the decoding chip U1 are respectively connected to U, V and W of the Hall signals, pins 4 and 5 are connected to the enable signal of the fault output module, pin 6 is connected to a DC voltage, and pins 9, 10, 11, 12, 13 and 14 are respectively connected to a first NOT gate.

6. The commutation circuit according to claim 1, characterized in that: The steering selection circuit includes twelve second AND gates, six of which have input ends connected to the six output ends of the Hall signal decoding circuit and the forward signal output by the single-chip microcomputer module, and a NOT gate U9 used to convert the forward signal into a reverse signal, and the input ends of the other six second AND gates are connected to the six output ends of the Hall signal decoding circuit and the output end of the NOT gate U9.

7. The commutation circuit according to claim 1, characterized in that: The speed regulation fault detection circuit includes a digital comparison chip U54, and the pin 19 of the digital comparison chip U54 is connected to an AND gate U55.

8. The commutation circuit according to claim 1, characterized in that: The decoding fault detection circuit includes an encoder chip U33 and a four-bit comparator chip U35. Pins 6, 7, and 9 of the encoder chip U33 and pins 9, 11, and 14 of the corresponding four-bit comparator chip U35 are respectively connected to NOT gates U34A, U34B, and U34C. Pin 6 of the four-bit comparator chip U35 is connected to a comparator U53.

9. The commutation circuit according to claim 1, characterized in that: The phase-changing fault detection circuit includes two groups of logic gate circuits respectively connected to the forward signal and the reverse signal, each group of logic gate circuits includes seven third AND gates, six XOR gates, two NOR gates and one NAND gate, two input ends of one third AND gate are respectively connected to the output end of the NAND gate and the forward signal, the input ends of the NAND gate are respectively connected to the NOR gate, the input ends of each NOR gate are respectively connected to three XOR gates, and the input end of each XOR gate is connected to a third AND gate.

10. The commutation circuit according to claim 1, characterized in that: The fault display circuit comprises three second OR gates, wherein two second OR gates are connected to two input ends of another second OR gate, and the input ends of the two second OR gates are both connected to LEDs.

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