A dynamic bias circuit and method for radio frequency power amplifier

Abstract

The present invention relates to the technical field of wireless digital communications and specifically provides a dynamic bias circuit and method for a radio frequency power amplifier. The circuit includes an LDO module and a dynamic control module. The LDO module uses an operational amplifier (AMP) and a transistor (MP). The dynamic control module uses an OSC, a trigger group consisting of a plurality of first D flip-flops connected in series, a second D flip-flop, and a third D flip-flop. The method divides the output process of the radio frequency power amplifier into nodes T0, T1, T2, and T3 according to a time relationship, where T0-T1 is a preheat stage, T1-T2 is a preheat stabilization stage, and T2-T3 is a postheat stage. The present invention optimizes the design of a dynamic bias circuit, introduces preheat to enable dynamic control of the preheat and postheat stages, and dynamically adjusts the Vreg voltage achieved by the dynamic bias circuit, thereby greatly improving the flatness of the output power of the radio frequency power amplifier over time, improving the error vector amplitude performance of the PA under dynamic conditions, and enhancing the linearity index of the PA.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless digital communications, and in particular to a dynamic bias circuit and method for a radio frequency power amplifier. Background Art

[0002] RF power amplifiers are essential key components in various wireless communication applications. They are used to amplify the modulated RF signal output by the transceiver to meet the power requirements of the RF signal required for wireless communication.

[0003] To reduce power consumption, RF power amplifiers (PAs) in Wi-Fi applications typically operate in a time-sharing mode, with periods of operation followed by periods of inactivity. They are not constantly transmitting RF power. This results in differences between the PA's initial startup state and its stable operating state. Due to heat dissipation, device temperatures differ significantly between the initial startup state and the thermally stable state. This manifests as significant differences in power gain and digital dynamic error vector magnitude (DEVM) performance between the initial startup state and the thermally stable state.

[0004] The transmission time of the PA varies depending on the length of the data packet. The transmission time of a long packet is about 6mS, and it is even longer for the seventh generation Wi-Fi wireless network technology, wifi7. The transmission time of a short packet is about 200uS. The thermal state of the PA is different for different transmission times. Due to the memory effect, the output power curve of the PA is not flat over time. When a constant bias voltage or current is used as the PA bias, the relationship between the PA output power, bias voltage Vreg and time is as follows: Figure 1a 、 1b As shown, Vreg enables the PA at t0 and disables it at t3. The PA's output power rises and then falls over time. From t0 to t1, Vreg biases the PA, causing the PA's power transistor's ICC to slowly increase, leading to a rise in output power. From t1 to t2, the output power is approximately stable. From t2 to t3, the PA's power transistor generates heat over a prolonged period of operation, causing its current gain factor (gm) to decrease somewhat. This causes the output power to slowly decline over time, impacting the RF power amplifier's output power and signal transmission reliability. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a dynamic bias circuit and method for a radio frequency power amplifier, so as to solve the problem in the prior art that the output power of the radio frequency power amplifier and the reliability of signal transmission are affected by the existence of heat loss in the radio frequency power amplifier.

[0006] To achieve the above objectives and other related objectives, the present invention provides a dynamic bias circuit for a radio frequency power amplifier, the circuit comprising an LDO module and a dynamic control module;

[0007] The LDO module uses an operational amplifier AMP and a transistor MP. The inverting input terminal of the operational amplifier AMP is connected to the vref voltage, the non-inverting input terminal is connected to the collector of the transistor MP, and the output terminal is connected to the base of the transistor MP. The emitter of the transistor MP is connected to a high level and the collector is grounded. The LDO module also includes a preheating unit and a post-heating unit. The preheating unit uses a transistor M1_pre. The collector of the transistor M1_pre is connected to the reference current Iref_pre, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP. The post-heating unit uses a transistor M1_pos. The collector of the transistor M1_pos is connected to the reference current Iref_pos, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP.

[0008] generating a vreg voltage of PA at the collector of the transistor MP;

[0009] The dynamic control module uses an OSC, a trigger group consisting of several first D triggers connected in series, a second D trigger, and a third D trigger. The OSC is used to generate a periodic square wave signal, and the trigger group is used to extend the OSC clock period to 2 n T, where T is time and n is the number of first D flip-flops connected in series; the D terminal of the second D flip-flop is connected to a high level and the Q terminal outputs a preheat_off signal, the D terminal of the third D flip-flop is connected to a high level and the Q terminal outputs a postheat_on signal, the second D flip-flop is connected in parallel to the first D flip-flop located at n / 2 of the trigger group, and the third D flip-flop is connected in parallel to the first D flip-flop located at the end of the trigger group.

[0010] In one embodiment of the present invention, a resistor R1 and a resistor R2 are connected to the collector of the transistor MP, and a non-inverting input terminal of the operational amplifier AMP is connected between the resistor R1 and the resistor R2.

[0011] In one embodiment of the present invention, the LDO module generates the PA vreg voltage, which is expressed as follows:

[0012] Vreg=Vref(R1+R2) / R1+(is_pre+is_post)*R2

[0013] In one embodiment of the present invention, there are V1, V2, V3, V4, V5, and V6 signals in sequence in the trigger group. The V1, V2, and V3 signals are respectively controlled by NOR gates to extract current is_pre from the preheat unit; the V4, V5, and V6 signals are respectively controlled by NOR gates to extract current is_pos from the postheat unit.

[0014] In one embodiment of the present invention, in an initial state, the preheat_off signal and the postheat_on signal are both 0.

[0015] In one embodiment of the present invention, a three-phase six-arm drive structure is adopted in both the preheating unit and the post-heating unit. Each phase of the three-phase six-arm drive structure adopts two MOS tubes. In the same phase, the emitter of the MOS tube located in the upper arm is connected to the collector of the MOS tube located in the lower arm.

[0016] In one embodiment of the present invention, the duty cycle of the periodic square wave signal generated by the OSC is set to 50%.

[0017] A dynamic bias method for a radio frequency power amplifier, comprising the dynamic bias circuit for a radio frequency power amplifier, comprises the following steps:

[0018] S1. Divide the output process of the RF power amplifier into nodes T0, T1, T2, and T3 according to the time relationship, where T0-T1 is the preheat stage, T1-T2 is the preheat stabilization stage, and T2-T3 is the postheat stage;

[0019] S2. Use an OSC to generate a periodic square wave signal, set the duty cycle of the signal to 50% and the period to T;

[0020] S3, connect the first D flip-flops of the flip-flop group into a two-way frequency division form, so that the clock period of the square wave signal is 2 n times are stretched; that is, in the trigger group, the period of V1 is 2T, the period of V2 is 4T, the period of V3 is 8T, the period of V4 is 32T, the period of V5 is 64T, and the period of V6 is 128T, where V6 is the transmission time covering the entire long data packet;

[0021] At S4 and T0, both the preheat_off signal and the postheat_on signal are 0;

[0022] S5. In the T0-T1 stage, V1, V2, and V3 in the trigger group control the three extracted currents is_pre in the preheat stage through the NOR gate; in the T1-T2 stage, as the clock signal repeats periodically, V1, V2, and V3 in the trigger group form a long clock cycle, and the three extracted currents is_pre gradually decrease. At the end of the preheat stage, preheat_off is set high, so that en1_pre, en2_pre, and en3_pre are all set to 0, thereby closing the preheat stage; in the T2-T3 stage, V4, V5, and V6 in the trigger group control the three extracted currents is_post in the postheat stage through the NOR gate; when the V6 signal does not jump, postheat_on is still set to 0, the postheat stage is still in operation, and is_post increases gradually; and when the V6 signal jumps, postheat is set high, so that the postheat stage is closed, thereby completing the transmission of the entire data packet.

[0023] In one embodiment of the present invention, in step S5, since the input D terminal of the second D flip-flop associated with preheat_off is connected to VDD, the entire preheat stage is in a closed state when the reset signal does not appear. The preheat stage will not be restarted until the next reset signal arrives, that is, the preheat stage will not be restarted until the next data packet is sent.

[0024] As described above, the dynamic bias circuit and method for a radio frequency power amplifier of the present invention have the following beneficial effects:

[0025] The present invention designs a dynamic vreg voltage bias scheme, which divides the output process of the RF power amplifier into nodes T0, T1, T2, and T3 according to the time relationship. In the t0-t1 stage, called the preheat stage, the vreg voltage has a certain overshoot and gradually decays. This period generally lasts about 100uS, which is used to compensate for the slow power rise at the initial startup of the PA, thereby improving the flatness of the output power over time at the initial startup; in the t1-t2 stage, the preheat overshoot disappears, and the vreg bias voltage is consistent with the thermal stability state; in the t2-t3 stage, called the postheat stage, the vreg voltage slowly increases in this stage, po The stheat stage mainly compensates for the decrease in current gain beta or transconductance gm caused by the thermal effect after the PA has been working for a certain period of time, thereby improving the flatness of the output power over time during this period, preventing the power curve from declining, and enabling the RF power amplifier to provide high-power output, ensuring the reliability and stability of signal transmission; the present invention optimizes the design of the dynamic bias circuit, introduces preheat to achieve dynamic control of the preheating and postheating stages, and realizes dynamic adjustment of the vreg voltage through the dynamic bias circuit, which greatly improves the flatness of the RF power amplifier output power over time, improves the error vector amplitude performance of the PA under dynamic conditions, and improves the PA linearity index. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a Displayed is a graph showing the relationship between the PA's output power and time.

[0027] Figure 1b The graph shows the relationship between the PA bias voltage Vreg and time.

[0028] Figure 2a Shown is a circuit schematic diagram of an LDO module for a dynamic bias circuit of a radio frequency power amplifier disclosed in the present invention.

[0029] Figure 21a Display as Figure 2a An enlarged diagram of the operational amplifier AMP and transistor MP.

[0030] Figure 22a Display as Figure 2a Enlarged view of the preheating unit.

[0031] Figure 23a Display as Figure 2a A magnified view of the middle and rear thermal units.

[0032] Figure 2b Shown is a circuit schematic diagram of a dynamic control module of a dynamic bias circuit for a radio frequency power amplifier disclosed in the present invention.

[0033] Figure 21b Display as Figure 2b A partial enlarged view of the .

[0034] Figure 22b Display as Figure 2b Another enlarged view of the part.

[0035] Figure 3a The graph shows the relationship between output power and time after the improvement of the dynamic bias method for a radio frequency power amplifier disclosed in the present invention.

[0036] Figure 3b A curve diagram showing the relationship between the bias voltage Vreg and time after the improvement using the dynamic bias method for a radio frequency power amplifier disclosed in the present invention is shown.

[0037] Description of labels:

[0038] Preheating unit 1; post-heating unit 2; trigger group 3; first D trigger 31; second D trigger 4; third D trigger 5. DETAILED DESCRIPTION

[0039] The following describes the implementation of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0040] See also Figure 1a 、 1b , 2a, 21a-23a, 2b, 21b-22b, 3a, 3b. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in this specification for those familiar with this technology to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in sizes should still fall within the scope of the technical contents disclosed in this invention without affecting the efficacy and purpose of the present invention.

[0041] Example 1, please refer to Figure 2a 、 21a -23a, 2b, 21b-22b, this embodiment provides a dynamic bias circuit for a radio frequency power amplifier, the circuit including an LDO module and a dynamic control module.

[0042] The LDO module uses an operational amplifier AMP and a transistor MP. The inverting input terminal of the operational amplifier AMP is connected to the vref voltage, the non-inverting input terminal is connected to the collector of the transistor MP, and the output terminal is connected to the base of the transistor MP. The emitter of the transistor MP is connected to a high level and the collector is grounded. The collector of the transistor MP is connected to a resistor R1 and a resistor R2. The non-inverting input terminal of the operational amplifier AMP is specifically connected between the resistor R1 and the resistor R2. The LDO module also includes a preheating unit 1 and a post-heating unit 2. The preheating unit 1 uses a transistor M1_pre and a transistor M2_pre. The collector of is_pre is connected to the reference current Iref_pre, the emitter is grounded, and the base is connected to the non-inverting input of the operational amplifier AMP. The post-heat unit 2 uses a transistor M1_pos, whose collector is connected to the reference current Iref_pos, the emitter is grounded, and the base is connected to the non-inverting input of the operational amplifier AMP. Both pre-heat units 1 and 2 use a three-phase six-arm drive structure, with two MOS transistors in each phase. The emitter of the MOS transistor in the upper arm of the same phase is connected to the collector of the MOS transistor in the lower arm. The collector of transistor MP generates the PA's vreg voltage, i.e., the output voltage expression of the vreg voltage is Vreg = Vref(R1+R2) / R1+(is_pre+is_post)*R2.

[0043] The dynamic control module uses an OSC, a trigger group 3 consisting of several first D triggers connected in series, a second D trigger 4, and a third D trigger 5. The OSC is used to generate a periodic square wave signal. The duty cycle of the periodic square wave signal generated by the OSC is set to 50%, and the period is T. The trigger group 3 is used to extend the clock period generated by the OSC to 2 n T, where T is time and n is the number of first D flip-flops 31 connected in series. In flip-flop group 3, signals V1, V2, V3, V4, V5, and V6 are sequentially present. The V1, V2, and V3 signals are controlled by NOR gates to extract current is_pre from the preheat unit. The V4, V5, and V6 signals are controlled by NOR gates to extract current is_pos from the postheat unit. Initially, the preheat_off and postheat_on signals are both 0. The D terminal of the second D flip-flop 4 is connected to a high level, and the Q terminal outputs the preheat_off signal. The D terminal of the third D flip-flop 5 is connected to a high level, and the Q terminal outputs the postheat_on signal. The second D flip-flop 4 is connected in parallel to the first D flip-flop 31 at position n / 2 of the flip-flop group 3, and the third D flip-flop 5 is connected in parallel to the first D flip-flop 31 at the end of the flip-flop group 3.

[0044] This embodiment designs a dynamic bias circuit consisting of an LDO module and a dynamic control module. The LDO module generates the PA's vreg voltage. The output voltage expression of the vreg voltage is Vreg = Vref(R1+R2) / R1+(is_pre+is_post)*R2. It can be seen that the vreg voltage is controlled by the dynamic control module and is divided into a preheat stage and a postheat stage. Dynamic current extraction is provided in each stage to increase the vreg voltage output.

[0045] Example 2, please refer to Figure 2a 、 2b 3a, 3b Based on Example 1, this embodiment provides a dynamic bias method for a radio frequency power amplifier, comprising the following steps:

[0046] S1. Divide the output process of the RF power amplifier into nodes T0, T1, T2, and T3 according to the time relationship, where T0-T1 is the preheat stage, T1-T2 is the preheat stabilization stage, and T2-T3 is the postheat stage;

[0047] S2. Use an OSC to generate a periodic square wave signal, set the duty cycle of the signal to 50% and the period to T;

[0048] S3, connect the first D flip-flops 31 constituting the flip-flop group 3 into a two-way frequency division form, so that the clock period of the square wave signal is 2 n times are stretched; that is, in trigger group 3, the period of V1 is 2T, the period of V2 is 4T, the period of V3 is 8T, the period of V4 is 32T, the period of V5 is 64T, and the period of V6 is 128T, where V6 is the transmission time covering the entire long data packet;

[0049] At S4 and T0, under the action of the reset signal or the PA working signal, the preheat_off signal and the postheat_on signal are both 0;

[0050] S5. In the T0-T1 phase, V1, V2, and V3 in the trigger group 3 control the three extracted currents is_pre in the preheat phase through the NOR gate; in the T1-T2 phase, as the clock signal repeats periodically, V1, V2, and V3 in the trigger group 3 form a long clock cycle, and the three extracted currents is_pre gradually decrease. At the end of the preheat phase, preheat_off is set high, so that en1_pre, en2_pre, and en3_pre are all set to 0, thereby closing the preheat phase; since the input D terminal of the second D trigger 4 related to preheat_off is connected to VDD, the entire preheat phase is in a closed state when the reset signal does not appear, and the preheat phase will not be restarted until the next reset signal arrives, that is, the preheat phase will not be restarted until the next data packet is sent. In the T2-T3 phase, V4, V5, and V6 in trigger group 3 control the three extracted currents is_post in the postheat phase through the NOR gate; when the V6 signal does not jump, postheat_on is still set to 0, the postheat phase is still in operation, and is_post increases gradually; and when the V6 signal jumps, postheat is set high, so that the postheat phase is turned off, thereby completing the transmission of the entire data packet.

[0051] The present invention designs a dynamic vreg voltage bias scheme, which divides the output process of the RF power amplifier into nodes T0, T1, T2, and T3 according to the time relationship. In the t0-t1 stage, called the preheat stage, the vreg voltage has a certain overshoot and gradually decays. In practical applications, the overshoot and gradual decay of the vreg voltage generally last for about 100uS, which is used to compensate for the slow power rise state in the initial stage of PA startup, thereby improving the flatness of the output power over time in the initial stage of startup; in the t1-t2 stage, the preheat overshoot disappears, and the vreg bias voltage is consistent with the thermal stability state; in the t2-t3 stage, called the postheat stage, the vreg voltage slowly increases in this stage. The postheat stage mainly compensates for the decrease in current gain beta or transconductance gm caused by the thermal effect after the PA has worked for a certain period of time, thereby also improving the flatness of the output power over time during this period, preventing the power curve from declining, and enabling the RF power amplifier to provide high power output, ensuring the reliability and stability of signal transmission.

[0052] In summary, the present invention optimizes the design of a dynamic bias circuit and introduces a preheating mechanism to dynamically control both the preheating and postheating stages. This dynamic bias circuit enables dynamic adjustment of the vreg voltage, significantly improving the temporal flatness of the RF power amplifier's output power, enhancing the PA's error vector magnitude (EVM) performance under dynamic conditions, and improving the PA's linearity. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial value.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A dynamic bias circuit for a radio frequency power amplifier, characterized in that: The circuit includes an LDO module and a dynamic control module; The LDO module uses an operational amplifier AMP and a transistor MP. The inverting input terminal of the operational amplifier AMP is connected to the vref voltage, the non-inverting input terminal is connected to the collector of the transistor MP, and the output terminal is connected to the base of the transistor MP. The emitter of the transistor MP is connected to a high level and the collector is grounded. The LDO module also includes a preheating unit and a post-heating unit. The preheating unit uses a transistor M1_pre. The collector of the transistor M1_pre is connected to the reference current Iref_pre, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP. The post-heating unit uses a transistor M1_pos. The collector of the transistor M1_pos is connected to the reference current Iref_pos, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP. generating a vreg voltage of PA at the collector of the transistor MP; The dynamic control module uses an OSC, a trigger group consisting of several first D triggers connected in series, a second D trigger, and a third D trigger. The OSC is used to generate a periodic square wave signal, and the trigger group is used to extend the OSC clock period to 2 n T, where T is time and n is the number of first D flip-flops connected in series; the D terminal of the second D flip-flop is connected to a high level and the Q terminal outputs a preheat_off signal, the D terminal of the third D flip-flop is connected to a high level and the Q terminal outputs a postheat_on signal, the second D flip-flop is connected in parallel to the first D flip-flop located at n / 2 of the trigger group, and the third D flip-flop is connected in parallel to the first D flip-flop located at the end of the trigger group.

2. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, wherein: The collector of the transistor MP is connected to a resistor R1 and a resistor R2 , and the non-inverting input terminal of the operational amplifier AMP is connected between the resistor R1 and the resistor R2 .

3. The dynamic bias circuit for a radio frequency power amplifier according to claim 2, wherein: The output voltage expression of the PA vreg voltage generated by the LDO module is as follows: Vreg=Vref(R1+R2) / R1+(is_pre+is_post)*R2.

4. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, wherein: In the trigger group, there are V1, V2, V3, V4, V5, and V6 signals in sequence. The V1, V2, and V3 signals are respectively controlled by NOR gates to extract current is_pre in the preheat unit; the V4, V5, and V6 signals are respectively controlled by NOR gates to extract current is_pos in the postheat unit.

5. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, wherein: In an initial state, the preheat_off signal and the postheat_on signal are both 0.

6. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, wherein: A three-phase six-arm drive structure is adopted in both the preheating unit and the post-heating unit. Each phase of the three-phase six-arm drive structure adopts two MOS tubes. The emitter of the MOS tube located in the upper arm in the same phase is connected to the collector of the MOS tube located in the lower arm.

7. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, wherein: The duty cycle of the periodic square wave signal generated by the OSC is set to 50%.

8. A dynamic bias method for a radio frequency power amplifier, comprising the dynamic bias circuit for a radio frequency power amplifier according to any one of claims 1 to 7, characterized in that: The steps include: S1. Divide the output process of the RF power amplifier into nodes T0, T1, T2, and T3 according to the time relationship, where T0-T1 is the preheat stage, T1-T2 is the preheat stabilization stage, and T2-T3 is the postheat stage; S2. Use an OSC to generate a periodic square wave signal, set the duty cycle of the signal to 50% and the period to T; S3, connect the first D flip-flops of the flip-flop group into a two-way frequency division form, so that the clock period of the square wave signal is 2 n times are stretched; that is, in the trigger group, the period of V1 is 2T, the period of V2 is 4T, the period of V3 is 8T, the period of V4 is 32T, the period of V5 is 64T, and the period of V6 is 128T, where V6 is the transmission time covering the entire long data packet; At S4 and T0, both the preheat_off signal and the postheat_on signal are 0; S5. In the T0-T1 phase, V1, V2, and V3 in the trigger group control the three extracted currents is_pre in the preheat phase through the NOR gate; In the T1-T2 stage, as the clock signal repeats periodically, V1, V2, and V3 in the trigger group form a long clock cycle loop, and the three extracted currents is_pre gradually decrease. At the end of the preheat stage, preheat_off is set high, so that en1_pre, en2_pre, and en3_pre are all set to 0, thereby closing the preheat stage; in the T2-T3 stage, V4, V5, and V6 in the trigger group control the three extracted currents is_post in the postheat stage through the NOR gate; when the V6 signal does not jump, postheat_on is still set to 0, the postheat stage is still in operation, and is_post increases gradually; and when the V6 signal jumps, postheat is set high, so that the postheat stage is closed, thereby completing the transmission of the entire data packet.

9. The dynamic bias method for a radio frequency power amplifier according to claim 8, wherein: In step S5, since the input D terminal of the second D flip-flop related to preheat_off is connected to VDD, the entire preheat stage is in a closed state when the reset signal does not appear. The preheat stage will not be restarted until the next reset signal comes, that is, the preheat stage will not be restarted until the next data packet is sent.

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