Successive approximation analog-to-digital converter and method, touch chip and electronic equipment

Abstract

The invention provides a successive approximation analog-to-digital converter, a successive approximation analog-to-digital converter method, a touch chip and electronic equipment, and the successive approximation analog-to-digital converter comprises a logic module which is configured to receive a sampling clock signal, and generate a comparison clock signal according to the sampling clock signal; a comparison module configured to: receive an input voltage and the comparison clock signal; comparing the input voltage with the current analog voltage in each comparison period of the comparison clock signal, and outputting a comparison result and a comparison completion signal; the logic module is further configured to receive the comparison result and the comparison completion signal, and instruct the comparison module to update the analog voltage according to the comparison result; outputting a comparison state signal; and an adaptive controller configured to receive the comparison state signal and the sampling clock signal, and adjust at least one of the sampling clock signal and the comparison clock signal according to the comparison state signal and the sampling clock signal.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and in particular, to a successive approximation analog-to-digital converter and method, a touch control chip, and an electronic device. Background Art

[0002] A successive approximation register (SAR) analog-to-digital converter (ADC) has characteristics such as low power consumption and small size, and is widely used in medium to high-resolution analog-to-digital conversion scenarios. In order to further meet the requirements of the development of chip miniaturization, it is necessary to further reduce the area of the SAR ADC. However, the reduction of the area will amplify the influence of process corners, operating temperature, and operating voltage on device performance, resulting in difficulty for the SAR ADC to maintain optimal performance. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a successive approximation analog-to-digital converter and method, a touch control chip, and an electronic device.

[0004] On the one hand, embodiments of the present application provide a successive approximation analog-to-digital converter, including:

[0005] A logic module, configured to: receive a sampling clock signal and generate a comparison clock signal according to the sampling clock signal;

[0006] A comparison module, configured to: receive an input voltage and the comparison clock signal; within each comparison period of the comparison clock signal, compare the input voltage with the current analog voltage, and output a comparison result and a comparison completion signal;

[0007] The logic module is further configured to: receive the comparison result and the comparison completion signal, and instruct the comparison module to update the analog voltage according to the comparison result; output a comparison status signal;

[0008] An adaptive controller, configured to: receive the comparison status signal and the sampling clock signal, and adjust at least one of the sampling clock signal and the comparison clock signal according to the comparison status signal and the sampling clock signal.

[0009] In some embodiments, the adaptive controller is further configured to:

[0010] Receive setting information before adjusting at least one of the sampling clock signal and the comparison clock signal;

[0011] Adjusting at least one of the sampling clock signal and the comparison clock signal according to the comparison status signal and the sampling clock signal includes:

[0012] Determining remaining time information according to the comparison status signal and the sampling clock signal;

[0013] Adjusting the sampling clock signal and the comparison clock signal according to the setting information and the remaining time information.

[0014] In some embodiments, the successive approximation analog-to-digital converter further includes:

[0015] A ring oscillator configured to generate an internal clock signal; wherein the oscillation frequency of the internal clock signal varies based on environmental conditions;

[0016] A calibration module configured to: receive an initial sampling clock signal and the internal clock signal, and measure the speed of the internal clock signal based on the initial sampling clock signal; determine the setting information according to the internal clock signal; transmit the setting information to the adaptive controller.

[0017] In some embodiments, the outputting the comparison status signal specifically includes:

[0018] Generating a first comparison status signal and a second comparison status signal according to the comparison completion signal and the sampling clock signal, and generating the rising edge of the first comparison status signal before the rising edge of the second comparison status signal.

[0019] In some embodiments, the determining the remaining time information according to the comparison status signal and the sampling clock signal specifically includes:

[0020] If, at the rising edge of the first time period of the sampling clock signal, both the first comparison status signal and the second comparison status signal are at the first level, the remaining time information indicates insufficient remaining time;

[0021] If, at the rising edge of the first time period of the sampling clock signal, both the first comparison status signal and the second comparison status signal are at the second level, the remaining time information indicates sufficient remaining time.

[0022] In some embodiments, the comparison module includes a capacitor array module, and the capacitor array module includes a plurality of capacitors;

[0023] The logic module is further configured to: generate a control signal according to the comparison result, and transmit the control signal to the capacitor array module;

[0024] The capacitance array module is configured to: in response to the control signal, charge at least one of the capacitors to generate the updated analog voltage;

[0025] The adaptive controller is further configured to: adjust the charging speed of the capacitors in the capacitance array module according to the remaining time information.

[0026] In some embodiments, the successive approximation analog-to-digital converter further includes:

[0027] An adaptive recording module, coupled to the adaptive controller and configured to: receive and record adjustment information; the adjustment information indicates adjusting at least one of the sampling clock signal and the comparison clock signal.

[0028] On the other hand, an embodiment of the present application further provides a successive approximation analog-to-digital conversion method, including:

[0029] Receiving a sampling clock signal and generating a comparison clock signal according to the sampling clock signal;

[0030] Receiving an input voltage and the comparison clock signal, and within each comparison period of the comparison clock signal, comparing the input voltage with the current analog voltage to generate a comparison result and a comparison completion signal;

[0031] Updating the analog voltage according to the comparison result;

[0032] Generating a comparison status signal;

[0033] Adjusting at least one of the sampling clock signal and the comparison clock signal according to the comparison status signal and the sampling clock signal.

[0034] In some embodiments, the method further includes:

[0035] Receiving setting information before adjusting at least one of the sampling clock signal and the comparison clock signal;

[0036] The adjusting at least one of the sampling clock signal and the comparison clock signal according to the comparison status signal and the sampling clock signal includes:

[0037] Determining remaining time information according to the comparison status signal and the sampling clock signal;

[0038] Adjusting the sampling clock signal and the comparison clock signal according to the setting information and the remaining time information.

[0039] In some embodiments, the generating the comparison status signal specifically includes:

[0040] Generate a first comparison status signal and a second comparison status signal based on the comparison completion signal and the sampling clock signal, and generate the rising edge of the first comparison status signal before the rising edge of the second comparison status signal.

[0041] In some embodiments, determining the remaining time information according to the comparison status signal and the sampling clock signal specifically includes:

[0042] If, at the rising edge of the first level period of the sampling clock signal, both the first comparison status signal and the second comparison status signal are at the first level, the remaining time information indicates that the remaining time is insufficient;

[0043] If, at the rising edge of the first level period of the sampling clock signal, both the first comparison status signal and the second comparison status signal are at the second level, the remaining time information indicates that the remaining time is sufficient.

[0044] In some embodiments, the method further includes:

[0045] Generate a control signal according to the comparison result;

[0046] In response to the control signal, charge at least one capacitor in the capacitor array module to generate the updated analog voltage;

[0047] Adjust the charging speed of the capacitor in the capacitor array module according to the remaining time information.

[0048] In some embodiments, the method further includes:

[0049] Record adjustment information; the adjustment information indicates adjusting at least one of the sampling clock signal and the comparison clock signal.

[0050] In another aspect, an embodiment of the present application further provides a touch chip, including the successive approximation analog-to-digital converter described in any of the foregoing embodiments.

[0051] In another aspect, an embodiment of the present application further provides an electronic device, including: a processor and a memory for storing a computer program that can run on the processor;

[0052] Wherein, when the processor is used to run the computer program, it executes the successive approximation analog-to-digital conversion method described in any of the foregoing embodiments.

[0053] In the technical solution provided by this application, the successive approximation analog-to-digital converter includes an adaptive controller. The logic module can generate a comparison status signal, and the adaptive controller can adjust at least one of the sampling clock signal and the comparison clock signal according to the comparison status signal and the sampling clock signal. That is, the successive approximation analog-to-digital converter provided by this application can adjust the sampling clock signal and the comparison clock signal through an adaptive adjustment mechanism to optimize the internal time allocation of the successive approximation analog-to-digital converter, so that the successive approximation analog-to-digital converter can exert its best performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 Schematic diagram of an asynchronous clock SAR ADC provided by the related art;

[0055] Figure 2 Timing diagram of the asynchronous clock SAR ADC provided by the related art;

[0056] Figure 3 Schematic diagram of a successive approximation analog-to-digital converter provided by an embodiment of this application Figure 1 ;

[0057] Figure 4 Schematic diagram of a successive approximation analog-to-digital converter provided by an embodiment of this application Figure 2 ;

[0058] Figure 5 Timing diagram of the successive approximation analog-to-digital converter provided by an embodiment of this application;

[0059] Figure 6 Timing diagram for the successive approximation analog-to-digital converter provided by an embodiment of this application to generate a comparison status signal Figure 1 ;

[0060] Figure 7 Timing diagram for the successive approximation analog-to-digital converter provided by an embodiment of this application to generate a comparison status signal Figure 2 ;

[0061] Figure 8 Timing diagram for the successive approximation analog-to-digital converter provided by an embodiment of this application to generate a comparison status signal Figure 3 ;

[0062] Figure 9 Schematic diagram for the successive approximation analog-to-digital converter provided by an embodiment of this application to adjust the clock signal based on the remaining time information;

[0063] Figure 10 Schematic diagram of the look-up table algorithm in the successive approximation analog-to-digital converter provided by an embodiment of this application;

[0064] Figure 11Schematic flowchart of the successive approximation analog-to-digital conversion method provided by the embodiments of the present application;

[0065] Figure 12 Schematic diagram of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0066] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0067] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some well-known technical features are not described to avoid confusion with the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0068] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0069] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application can also have other embodiments.

[0070] The successive approximation register (SAR) analog-to-digital converter (ADC) has characteristics such as low power consumption and small size, and is widely used in medium to high-resolution analog-to-digital conversion scenarios. The analog-to-digital conversion process of the SAR ADC includes comparing the input voltage with the analog voltage in each comparison cycle of the comparison clock signal, and successively changing the magnitude of the analog voltage based on the comparison result to make the analog voltage gradually approach the input voltage. After N comparisons are completed, the input voltage can be converted into an N-bit digital signal, thus realizing the conversion from an analog signal to a digital signal. The SAR ADC includes a synchronous clock SAR ADC and an asynchronous clock SAR ADC. The main difference is that the comparison clock signal of the synchronous clock SAR ADC needs to be provided externally, while the comparison clock signal of the asynchronous clock SAR ADC is generated by an internal logic module, which has better flexibility.

[0071] Figure 1 FIG. is a schematic diagram of an asynchronous clock SAR ADC provided by the related art. Figure 2 FIG. is a timing diagram of the asynchronous clock SAR ADC provided by the related art, as Figure 1 and Figure 2 shown. The SAR ADC includes a logic module 100 and a comparison module 101. Among them, the logic module 100 can generate a comparison clock signal CLKC based on the sampling clock signal CLKS, and send the comparison clock signal CLKC and a control signal to the comparison module 101. The comparison module 101 can generate an analog voltage in response to the control signal, and in each comparison cycle of the comparison clock signal CLKC, compare the input voltage with the current analog voltage to generate a comparison completion signal READY and a comparison result COMP_OUT. The logic module 100 can change the control signal based on the comparison result COMP_OUT, so that the comparison module 101 generates an analog voltage that is closer to the input voltage in response to the control signal, and compares the input voltage with the current analog voltage again until N comparisons are completed. The logic module 100 will generate an identification signal EOC indicating the completion of N comparisons and N-bit comparison result data DOUT.

[0072] Here, the comparison clock signal CLKC includes N comparison cycles, and the identification signal EOC indicating the completion of N comparisons is generated based on the falling edge of the pulse of the last comparison completion signal READY. The pulse of the last comparison completion signal READY is the pulse of the comparison completion signal READY generated in the last comparison cycle of the comparison clock signal CLKC. During the actual operation of the successive approximation analog-to-digital converter, the sampling clock signal CLKS comes from the outside, and the duration of its low-level period is often fixed. Within the low-level period of the sampling clock signal CLKS, the comparison module 101 must complete N comparisons, otherwise it may cause the failure to generate EOC, resulting in the inability to output the final output data.

[0073] To meet the requirements of chip miniaturization development, it is necessary to further reduce the area of the SAR ADC. However, the reduction of the area will amplify the influence of process corners, operating temperature, and operating voltage on the performance of the SAR ADC, which may cause the SAR ADC to be unable to complete N comparisons within the low-level period of the sampling clock signal CLKS. Therefore, it is necessary to further optimize the design of the SAR ADC to improve its reliability.

[0074] In response to this, the present application proposes the following implementation manners.

[0075] The present application provides a successive approximation analog-to-digital converter. Figure 3 Schematic diagram of a successive approximation analog-to-digital converter provided by an embodiment of the present application Figure 1 The successive approximation analog-to-digital converter includes a logic module 200, a comparison module 210, and an adaptive controller 220. The logic module 200 is configured to: receive the sampling clock signal CLKS_D and generate a comparison clock signal CLKC according to the sampling clock signal CLKS_D; the comparison module 210 is configured to: receive an input voltage and the comparison clock signal CLKC; within each comparison cycle of the comparison clock signal CLKC, compare the input voltage with the current analog voltage and output a comparison result COMP_OUT and a comparison completion signal READY; the logic module 200 is further configured to: receive the comparison result COMP_OUT and the comparison completion signal READY, and update the analog voltage of the comparison module 210 according to the comparison result COMP_OUT; output a comparison status signal; the adaptive controller 220 is configured to: receive the comparison status signal and the sampling clock signal CLKS_D, and adjust at least one of the sampling clock signal CLKS_D and the comparison clock signal CLKC according to the comparison status signal and the sampling clock signal CLKS_D.

[0076] In an embodiment of the present application, a successive approximation analog-to-digital converter includes an adaptive controller 220. The logic module 200 can generate a comparison status signal. The adaptive controller 220 can generate adjustment information according to the comparison status signal and the sampling clock signal CLKS_D. The adjustment information can be used to indicate an adjustment of at least one of the sampling clock signal CLKS_D and the comparison clock signal CLKC. That is, the successive approximation analog-to-digital converter provided in the present application can adjust the sampling clock signal CLKS_D and the comparison clock signal CLKC through an adaptive adjustment mechanism to optimize the internal time allocation of the successive approximation analog-to-digital converter, so that the successive approximation analog-to-digital converter can exert its best performance.

[0077] Figure 4 Schematic diagram of a successive approximation analog-to-digital converter provided in an embodiment of the present application Figure 2 , such as Figure 3 and Figure 4 shown, the comparison module 210 may include a capacitor array module 211, a comparator 212, and a sampling module 213. Among them, the sampling module 213 can sample the input voltage during the high-level period of the sampling clock signal CLKS_D. Here, the input voltage can be a differential input voltage (VINN and VINP). During the low-level period of the sampling clock signal CLKS_D, the sampling module 213 can output the differential input voltage to the capacitor array module 211. The capacitor array module 211 can first convert the differential input voltage into a single-ended input voltage, and the magnitude of the single-ended input voltage can be equal to the difference between VINP and VINN. Then, the capacitor array module 211 can charge a certain number of capacitors by using the reference voltage provided by the reference voltage generation module 250 in response to the control signal provided by the logic module 200, so as to generate an analog voltage, and output the analog voltage and the single-ended input voltage to the comparator 212. The comparator 212 can start comparing the analog voltage and the single-ended input voltage at the rising edge of the comparison clock signal CLKC, and output a pulse of the comparison result COMP_OUT and the comparison completion signal READY after the comparison is completed.

[0078] In some embodiments, the logic module 200 is further configured to: generate a control signal based on the comparison result COMP_OUT, and transmit the control signal to the capacitor array module 211. The capacitor array module 211 is configured to: in response to the control signal, charge at least one capacitor to generate an updated analog voltage. Here, the updated analog voltage will be closer to the single-ended input voltage than the analog voltage generated in the previous comparison. At the rising edge of the next comparison clock signal CLKC, the comparator 212 will compare the updated analog voltage with the single-ended input voltage, and output a pulse of the comparison completion signal READY and the comparison result COMP_OUT. In addition, the logic module 200 will also generate comparison result data DOUT based on the comparison result COMP_OUT, and output it to the output buffer module 280 for buffering. This process repeats, and the analog voltage generated by the capacitor array module 211 will gradually approach the single-ended input voltage.

[0079] Figure 5 is the timing diagram of the successive approximation analog-to-digital converter provided by the embodiments of the present application. As Figure 4 and Figure 5 shown, within the low-level period of the sampling clock signal CLKS_D, T1 is the time interval from the falling edge of the sampling clock signal CLKS_D to the first rising edge of the comparison clock signal CLKC, that is, the delay time of the comparison clock signal CLKC; T2 is the time interval from the start of a comparison to the completion of the comparison, which depends on the comparison speed of the comparator 212; T3 is the time interval from the completion of a comparison to the reset of the comparator 212, which depends on the duration of the high-level period of the comparison clock signal CLKC; T4 is the time interval from the completion of a comparison to the start of the next comparison, which depends on the duration of the high-level period and the low-level period of the comparison clock signal CLKC; T5 is the time interval from the reset of the last comparator 212 to the rising edge of EOC. Among them, the duration of the low-level period of the sampling clock signal CLKS_D, T1, T2, T3, and T4 together determine whether the successive approximation analog-to-digital converter can complete N comparisons within the low-level period of the sampling clock signal CLKS_D. In the successive approximation analog-to-digital converter provided by the present application, the adaptive controller 220 can set and adjust the sampling clock signal CLKS_D and the comparison clock signal CLKC to achieve a reasonable allocation of the duration of the low-level period of the sampling clock signal CLKS_D, T1, T3, and T4, so that N comparisons can be completed within the low-level period of the sampling clock signal CLKS_D, and an identification signal EOC indicating the completion of N comparisons can be generated. Next, the setting process and adjustment process of the adaptive controller 220 for the sampling clock signal CLKS_D and the comparison clock signal CLKC will be specifically introduced.

[0080] In some embodiments, the adaptive controller 220 is further configured to: receive the setting information Result_cal before adjusting at least one of the sampling clock signal CLKS_D and the comparison clock signal CLKC; adjust at least one of the sampling clock signal CLKS_D and the comparison clock signal CLKC according to the comparison status signal and the sampling clock signal CLKS_D, including: determining the remaining time information according to the comparison status signal and the sampling clock signal CLKS_D; adjusting the sampling clock signal CLKS_D and the comparison clock signal CLKC according to the setting information Result_cal and the remaining time information.

[0081] In some embodiments, as Figure 4 shown, the successive approximation analog-to-digital converter further includes: a ring oscillator 240 configured to generate an internal clock signal CLK_cal; wherein the oscillation frequency of the internal clock signal CLK_cal varies based on environmental conditions; a calibration module 241 configured to receive an initial sampling clock signal CLKS and the internal clock signal CLK_cal, and measure the speed of the internal clock signal CLK_cal based on the initial sampling clock signal CLKS; determine the setting information Result_cal according to the internal clock signal CLK_cal; transmit the setting information Result_cal to the adaptive controller 220. Here, the initial sampling clock signal CLKS is an unadjusted clock signal received from the outside.

[0082] In the embodiments of the present application, the transistors in the ring oscillator 240 can be synchronously formed with other transistors in the successive approximation analog-to-digital converter under the same process conditions, that is, the process corners of the transistors in the ring oscillator 240 are the same as those of other transistors in the successive approximation analog-to-digital converter, and the environmental conditions of the ring oscillator 240 are the same as those of other devices in the successive approximation analog-to-digital converter. Then, the oscillation frequency of the internal clock signal CLK_cal generated by the ring oscillator 240 is related to the process corner of the successive approximation analog-to-digital converter and the current environmental conditions. Here, the environmental conditions include but are not limited to temperature and power supply voltage. Further, the calibration module 241 can measure the speed of the internal clock signal CLK_cal based on the initial sampling clock signal CLKS received from the outside. For example, the number of cycles of the initial sampling clock signal CLKS within one cycle of the internal clock signal CLK_cal can be calculated, so that the setting information Result_cal can be obtained, and the setting information can reflect the process corner of the successive approximation analog-to-digital converter and the current environmental conditions.

[0083] In some embodiments, adjusting the sampling clock signal CLKS_D and the comparison clock signal CLKC according to the setting information Result_cal and the remaining time information includes: preliminarily setting the sampling clock signal CLKS_D and the comparison clock signal CLKC based on the setting information Result_cal to set the sampling clock signal CLKS_D and the comparison clock signal CLKC to a mode adapted to the process corner and environmental conditions of the successive approximation analog-to-digital converter.

[0084] In some embodiments, as Figure 4 shown, the successive approximation analog-to-digital converter further includes a sampling clock generation module 230 and a reference voltage generation module 250. The logic module 200 further includes a comparison clock delay module 202 and a comparison clock timing adjustment module 203. The adaptive controller 220 can be configured to: instruct the sampling clock generation module 230 to set the duty cycle of the sampling clock signal CLKS_D; instruct the reference voltage generation module 250 to set the charging speed of the capacitors in the capacitor array module 211; instruct the comparison clock delay module 202 to set the delay time of the comparison clock signal CLKC; instruct the comparison clock timing adjustment module 203 to set the duration of the high-level period and the low-level period of the comparison clock signal CLKC.

[0085] Here, as Figure 5 shown, the smaller the duty cycle of the sampling clock signal CLKS_D, the longer the duration of the low-level period and the shorter the duration of the high-level period of the sampling clock signal CLKS_D, that is, the longer the comparison time and the shorter the sampling time; the shorter the delay time of the comparison clock signal CLKC, the shorter the time interval (T1) between the falling edge of the sampling clock signal CLKS_D and the first rising edge of the comparison clock signal CLKC; the shorter the duration of the high-level period and the low-level period of the comparison clock signal CLKC, the shorter T3 and T4, and the faster the speed of each comparison; the faster the charging speed of the capacitors in the capacitor array module 211, the higher the degree of compression of the duration of the low-level period of the comparison clock signal CLKC can be.

[0086] In some embodiments, the sampling clock generation module 230 can reduce the duty cycle of the initial sampling clock signal CLKS to generate a sampling clock signal CLKS_D with a smaller duty cycle. For example, the duty cycle of the initial sampling clock signal CLKS can be 50%, and the range of the duty cycle of the sampling clock signal CLKS_D can be 40% to 50%.

[0087] In some embodiments, the capacitor array module 211 includes a plurality of capacitors with different capacitance values. The comparison clock signal CLKC includes N comparison cycles. In the initial plurality of comparison cycles, it is usually necessary to charge the capacitors with larger capacitance values in the capacitor array module 211 to generate an analog voltage. Then, the comparison clock timing adjustment module 203 can separately set the high-level period and the low-level period of the initial plurality of comparison cycles. For example, the high-level period and the low-level period of the initial plurality of comparison cycles can be set to be longer, so that sufficient charging time can be reserved for the capacitors with larger capacitance values. The high-level period and the low-level period of other comparison cycles are set to be shorter, which is beneficial to shortening the total duration of the N comparison cycles.

[0088] In some embodiments, the reference voltage generation module 250 can preset a plurality of drive enhancement options. The stronger the driving ability of the generated reference voltage, the faster the charging speed of charging the capacitors in the capacitor array module 211 using the reference voltage, and the greater the power consumption required.

[0089] In some embodiments, adjusting the sampling clock signal CLKS_D and the comparison clock signal CLKC according to the setting information Result_cal and the remaining time information further includes: adjusting at least one of the sampling clock signal CLKS_D and the comparison clock signal CLKC according to the remaining time information.

[0090] In the embodiments of the present application, the remaining time information is used to reflect whether the remaining time during the successive approximation analog-to-digital conversion performed by the successive approximation analog-to-digital converter is sufficient. If the remaining time is sufficient, within the low-level period of the sampling clock signal CLKS_D, the comparison module 210 can complete N comparisons, and the logic module 200 can output an identification signal EOC indicating that N comparisons are completed, that is, the successive approximation analog-to-digital converter can complete the successive approximation analog-to-digital conversion; if the remaining time is insufficient, within the low-level period of the sampling clock signal CLKS_D, the comparison module 210 cannot complete N comparisons, and the logic module 200 cannot output an identification signal EOC indicating that N comparisons are completed, that is, the successive approximation analog-to-digital converter cannot complete the analog-to-digital conversion.

[0091] In some embodiments, as Figure 4 shown, the logic module 200 further includes a comparison status signal generation module 204. The comparison status signal generation module 204 can be configured to: generate a first comparison status signal EOC_0 and a second comparison status signal EOC_1 according to the comparison completion signal READY and the sampling clock signal CLKS_D, and generate the rising edge of the first comparison status signal EOC_0 before the rising edge of the second comparison status signal EOC_1.

[0092] Figure 6 、Figure 7 And Figure 8 They are three timing diagrams for generating comparison status signals for the successive approximation analog-to-digital converter provided by the embodiments of the present application respectively.

[0093] As Figure 6 And Figure 7 As shown, when N comparisons can be completed within the low-level period of the sampling clock signal CLKS_D, then within the low-level period of the sampling clock signal CLKS_D, N pulses of the comparison completion signal READY will be generated. Generating the first comparison status signal EOC_0 and the second comparison status signal EOC_1 includes: generating the rising edge of the first comparison status signal EOC_0 and the rising edge of the second comparison status signal EOC_1 based on the falling edge of the pulse of the last comparison completion signal READY, and generating the rising edge of the first comparison status signal EOC_0 before generating the rising edge of the second comparison status signal EOC_1, that is, the time interval T5a between the falling edge of the pulse of the last comparison completion signal READY and the rising edge of the first comparison status signal EOC_0 is less than the time interval T5b between the falling edge of the pulse of the last comparison completion signal READY and the rising edge of the second comparison status signal EOC_1, and generating the falling edge of the first comparison status signal EOC_0 and the falling edge of the second comparison status signal EOC_1 based on the rising edge of the low-level period of the sampling clock signal CLKS_D, and the time interval between the rising edge of the sampling clock signal CLKS_D and the falling edge of the first comparison status signal EOC_0 is equal to the time interval between the rising edge of the sampling clock signal CLKS_D and the falling edge of the second comparison status signal EOC_1.

[0094] As Figure 8 As shown, when N comparisons cannot be completed within the low-level period of the sampling clock signal CLKS_D, the pulse of the last comparison completion signal READY cannot be generated, then the first comparison status signal EOC_0 and the second comparison status signal EOC_1 remain low-level signals and no pulses will be generated.

[0095] In some embodiments, the remaining time information is determined based on a comparison status signal and a sampling clock signal, specifically including: if, at the rising edge of the first level period of the sampling clock signal CLKS_D, both the first comparison status signal EOC_0 and the second comparison status signal EOC_1 are at the first level, the remaining time information indicates that the remaining time is insufficient; if, at the rising edge of the first level period of the sampling clock signal CLKS_D, both the first comparison status signal EOC_0 and the second comparison status signal EOC_1 are at the second level, the remaining time information indicates that the remaining time is sufficient; if, at the rising edge of the first level period of the sampling clock signal CLKS_D, the first comparison status signal EOC_0 is at the second level and the second comparison status signal EOC_1 is at the first level, the remaining time information indicates that the remaining time is appropriate. Here, the first level may be a low level, and the second level may be a high level.

[0096] As Figure 6 shown, if, at the rising edge of the low level period of the sampling clock signal CLKS_D, both the first comparison status signal EOC_0 and the second comparison status signal EOC_1 are at a high level, the remaining time information may be "11", indicating that the remaining time is sufficient. As Figure 7 shown, if, at the rising edge of the low level period of the sampling clock signal CLKS_D, the first comparison status signal EOC_0 is at a high level and the second comparison status signal EOC_1 is at a low level, the remaining time information may be "01", indicating that the remaining time is appropriate. As Figure 8 shown, if, at the rising edge of the low level period of the sampling clock signal CLKS_D, both the first comparison status signal EOC_0 and the second comparison status signal EOC_1 are at a low level, the remaining time information may be "00", indicating that the remaining time is insufficient.

[0097] Figure 9 FIG. is a schematic diagram of adjusting a clock signal based on remaining time information in the successive approximation analog-to-digital converter provided by the embodiments of the present application. As Figure 4 、 Figure 5 and Figure 9As shown, in response to the remaining time information indicating that the remaining time is insufficient, the adaptive controller 220 may be configured to generate adjustment information to perform at least one of the following: instruct the sampling clock generation module 230 to reduce the duty cycle of the sampling clock signal CLKS_D to extend the duration of the low-level period of the sampling clock signal CLKS_D; instruct the comparison clock delay module 202 in the logic module 200 to shorten the delay time of the comparison clock signal CLKC to shorten the time interval (T1) between the falling edge of the sampling clock signal CLKS_D and the first rising edge of the comparison clock signal CLKC; instruct the comparison clock timing adjustment module 203 in the logic module 200 to shorten the duration of the high-level period and the low-level period of the comparison clock signal CLKC to shorten the comparison period of the comparison clock signal CLKC and improve the speed of each comparison; instruct the reference voltage generation module 250 to increase the charging speed of the capacitors in the capacitor array module 211 so that after shortening the comparison period of the comparison clock signal CLKC, the capacitor array module 211 can complete the charging of the capacitors within the shortened low-level period.

[0098] In some embodiments, in response to the remaining time information indicating that the remaining time is sufficient, the adaptive controller 220 may be configured to generate adjustment information to perform at least one of the following: instruct the sampling clock generation module 230 to increase the duty cycle of the sampling clock signal CLKS_D; instruct the comparison clock delay module 202 in the logic module 200 to extend the delay time of the comparison clock signal CLKC; instruct the comparison clock timing adjustment module 203 in the logic module 200 to extend the duration of the high-level period and the low-level period of the comparison clock signal CLKC; instruct the reference voltage generation module 250 to slow down the charging speed of the capacitors in the capacitor array module 211.

[0099] In the embodiments of the present application, in the case of insufficient remaining time, in order to enable the successive approximation analog-to-digital converter to complete the analog-to-digital conversion operation, the remaining time can be increased by compressing part of the time or increasing the power consumption. And in the case of sufficient remaining time, in order to improve the reliability of each device in the successive approximation analog-to-digital converter and save power consumption, the remaining time can be appropriately compressed by extending part of the time and reducing the power consumption.

[0100] In some embodiments, the setting and adjustment of the sampling clock signal CLKS_D and the comparison clock signal CLKC can be implemented by a look-up table algorithm. As Figure 4 and Figure 10As shown, the successive approximation analog-to-digital converter further includes a memory 270, and the memory 270 can be configured to store a preset set of settings. Specifically, the adaptive controller 220 can look up the set of settings corresponding to the setting information Result_cal from Table 1 stored in the memory 270 according to the setting information Result_cal, and based on this set of settings, preliminarily set the duty cycle of the sampling clock signal CLKS_D, the delay time of the comparison clock signal CLKC, the duration of the high-level period and the low-level period of the comparison clock signal CLKC, and the charging speed of the capacitor. Then, the successive approximation analog-to-digital converter can start to acquire the input voltage and perform the analog-to-digital conversion operation. The comparison status signal generation module 204 in the logic module 200 can generate a first comparison status signal EOC_0 and a second comparison status signal EOC_1 during each analog-to-digital conversion operation. The adaptive controller 220 can determine the remaining time information according to the first comparison status signal EOC_0 and the second comparison status signal EOC_1, and select the set of settings in Table 2 according to the remaining time information and the adaptive algorithm, and based on this set of settings, adjust the duty cycle of the sampling clock signal CLKS_D, the delay time of the comparison clock signal CLKC, the duration of the high-level period and the low-level period of the comparison clock signal CLKC, and the charging speed of the capacitor.

[0101] Here, the adaptive algorithm may include: when the remaining time information is "00", that is, when the remaining time information indicates insufficient remaining time, adjusting to the next faster setting group to accelerate N comparisons and appropriately increase the remaining time; when the remaining time information is "01", that is, when the remaining time information indicates appropriate remaining time, keeping the current setting group unchanged; when the remaining time information is "11", that is, when the remaining time information indicates sufficient remaining time, adjusting to the next slower setting group to slow down N comparisons and appropriately compress the remaining time. The adaptive controller 220 may perform at least one of the following based on the next faster setting group: instructing the sampling clock generation module 230 to reduce the duty cycle of the sampling clock signal CLKS_D; instructing the comparison clock delay module 202 in the logic module 200 to shorten the delay time of the comparison clock signal CLKC; instructing the comparison clock timing adjustment module 203 in the logic module 200 to shorten the high-level duration and the low-level duration of the comparison clock signal CLKC; instructing the reference voltage generation module 250 to accelerate the charging speed of the capacitors in the capacitor array module 211. The adaptive controller 220 may perform at least one of the following based on the next slower setting group: instructing the sampling clock generation module 230 to increase the duty cycle of the sampling clock signal CLKS_D; instructing the comparison clock delay module 202 in the logic module 200 to extend the delay time of the comparison clock signal CLKC; instructing the comparison clock timing adjustment module 203 in the logic module 200 to extend the high-level duration and the low-level duration of the comparison clock signal CLKC; instructing the reference voltage generation module 250 to slow down the charging speed of the capacitors in the capacitor array module 211.

[0102] In some other embodiments, the settings and adjustments of the sampling clock signal CLKS_D and the comparison clock signal CLKC can also be implemented through other algorithms. For example, when the remaining time information indicates that the remaining time is insufficient, the adaptive controller 220 can determine the current settings of the sampling clock generation module 230, the comparison clock delay module 202, the comparison clock timing adjustment module 203, and the reference voltage generation module 250, and then preferentially adjust the settings of the comparison clock timing adjustment module 203 to shorten the high-level duration and the low-level duration of the comparison clock signal CLKC. When the high-level duration and the low-level duration of the comparison clock signal CLKC have been adjusted to the minimum values, the settings of the comparison clock delay module 202 are adjusted to shorten the delay time of the comparison clock signal CLKC. When the delay time of the comparison clock signal CLKC has been adjusted to the minimum value, the settings of the sampling clock generation module 230 are adjusted to reduce the duty cycle of the sampling clock signal CLKS_D, shorten the sampling time, and extend the comparison time. When the duty cycle of the sampling clock signal CLKS_D has been adjusted to the minimum value, the settings of the reference voltage generation module 250 are adjusted to increase the driving ability of the reference voltage to accelerate the charging speed of the capacitor. After adjusting the settings of the reference voltage generation module 250, the settings of the comparison clock timing adjustment module 203 can be adjusted again to further compress the low-level duration of the comparison clock signal CLKC. In addition, the setting adjustment processes of the above-mentioned modules can also be executed in parallel to improve the efficiency of adaptive adjustment.

[0103] In some embodiments, as Figure 4 shown, the successive approximation analog-to-digital converter further includes an adaptive recording module 260, which is coupled to the adaptive controller 220 and is configured to: receive and record adjustment information; the adjustment information indicates to adjust at least one of the sampling clock signal CLKS_D and the comparison clock signal CLKC. Here, the adjustment information can be the instruction information sent by the adaptive controller 220 to the sampling clock generation module 230, the comparison clock delay module 202, the comparison clock timing adjustment module 203, and the reference voltage generation module 250, and is used to indicate the adjustment of the settings of the relevant modules. The adaptive recording module 260 can provide an interface for feedback adjustment information during the test process of the successive approximation analog-to-digital converter. In addition, the successive approximation analog-to-digital converter can also include an interface for feedback process information, which can be used to provide the setting information Result_cal reflecting the process corner and environmental conditions of the successive approximation analog-to-digital converter, so as to provide reference information for the performance debugging, algorithm optimization, and circuit design optimization of the successive approximation analog-to-digital converter.

[0104] In an embodiment of the present application, the successive approximation analog-to-digital converter includes an adaptive controller. The adaptive controller can preliminarily set the sampling clock signal and the comparison clock signal according to the setting information reflecting the process corner and environmental conditions of the successive approximation analog-to-digital converter, so as to set the sampling clock signal and the comparison clock signal to a mode adapted to the process corner and environmental conditions of the successive approximation analog-to-digital converter. Further, during the process of the successive approximation analog-to-digital converter performing analog-to-digital conversion, the adaptive controller can determine the remaining time information reflecting the remaining time, and adjust at least one of the sampling clock signal and the comparison clock signal according to the remaining time information and the adaptive adjustment algorithm, so as to further optimize the time allocation of the successive approximation analog-to-digital converter, keep the successive approximation analog-to-digital converter at the optimal performance, and thus enable the successive approximation analog-to-digital converter to exert its best performance.

[0105] Based on the same inventive concept, the present application also provides a successive approximation analog-to-digital conversion method. Figure 11 As shown in the flowchart of a successive approximation analog-to-digital conversion method provided by an embodiment of the present application, Figure 11 The successive approximation analog-to-digital conversion method includes the following steps:

[0106] Step S101: Receive the sampling clock signal and generate a comparison clock signal according to the sampling clock signal;

[0107] Step S102: Receive the input voltage and the comparison clock signal, and within each comparison period of the comparison clock signal, compare the input voltage with the current analog voltage to generate a comparison result and a comparison completion signal;

[0108] Step S103: Update the analog voltage according to the comparison result;

[0109] Step S104: Generate a comparison status signal;

[0110] Step S105: Adjust at least one of the sampling clock signal and the comparison clock signal according to the comparison status signal and the sampling clock signal.

[0111] In some embodiments, the successive approximation analog-to-digital conversion method further includes: receiving setting information before adjusting at least one of the sampling clock signal and the comparison clock signal; the specific process of performing step S105 may include: determining remaining time information according to the comparison status signal and the sampling clock signal; adjusting the sampling clock signal and the comparison clock signal according to the setting information and the remaining time information.

[0112] In some embodiments, the specific process of performing step S104 may include: generating a first comparison status signal and a second comparison status signal according to the comparison completion signal and the sampling clock signal, and generating the rising edge of the first comparison status signal before the rising edge of the second comparison status signal.

[0113] In some embodiments, the remaining time information is determined based on a comparison status signal and a sampling clock signal, specifically including: if the first comparison status signal and the second comparison status signal are both at a first level at the rising edge of the first electrical level period of the sampling clock signal, the remaining time information indicates that the remaining time is insufficient; if the first comparison status signal and the second comparison status signal are both at a second level at the rising edge of the first electrical level period of the sampling clock signal, the remaining time information indicates that the remaining time is sufficient.

[0114] In some embodiments, the successive approximation analog-to-digital conversion method further includes: generating a control signal according to a comparison result; in response to the control signal, charging at least one capacitor in the capacitor array module to generate an updated analog voltage; adjusting the charging speed of the capacitors in the capacitor array module according to the remaining time information.

[0115] In some embodiments, the successive approximation analog-to-digital conversion method further includes: recording adjustment information; the adjustment information indicates adjusting at least one of the sampling clock signal and the comparison clock signal.

[0116] In the embodiments of the present application, the successive approximation analog-to-digital conversion method includes adjusting at least one of the sampling clock signal and the comparison clock signal according to the setting information and the remaining time information to optimize the time allocation, thereby improving the reliability of the successive approximation analog-to-digital conversion.

[0117] Based on the same inventive concept, the embodiments of the present application further provide a touch chip, including the successive approximation analog-to-digital converter in any of the above embodiments.

[0118] In some embodiments, the touch chip may include multiple successive approximation analog-to-digital converters, and the input voltage of the successive approximation analog-to-digital converter may be the output voltage of a pressure sensor or other sensors. To improve the touch accuracy, it is necessary to increase the number of sensors and successive approximation analog-to-digital converters as much as possible. In this case, the area of the successive approximation analog-to-digital converter needs to be small, so that as many successive approximation analog-to-digital converters as possible can be arranged in the limited area of the touch chip.

[0119] The successive approximation analog-to-digital converter provided by the present application has an adaptive adjustment mechanism, which can adjust the sampling clock signal and the comparison clock signal based on the process corner, the current environmental conditions, and the execution situation of the analog-to-digital conversion to adaptively optimize the internal time allocation, so as to adapt to the application scenario where the negative impacts of the process corner and environmental conditions on the device performance caused by area compression are amplified, and improve the reliability of the touch chip.

[0120] Based on the same inventive concept, the embodiments of the present application further provide an electronic device Figure 12Schematic diagram of an electronic device provided by an embodiment of the present application, as shown in Figure 12 As shown, the electronic device 300 includes: a processor 301 and a memory 302 for storing a computer program 3021 that can run on the processor 301; wherein, when the processor 301 is used to run the computer program 3021, it executes the successive approximation analog-to-digital conversion method described in any of the above embodiments.

[0121] In some embodiments, the above-mentioned processor 301 may be at least one of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor.

[0122] In some embodiments, the above-mentioned memory 302 may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a ferromagnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it may also be various terminals including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc.

[0123] The various embodiments / implementations provided by the present application can be combined with each other without conflict.

[0124] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A successive approximation analog-to-digital converter, characterized in that: include: A logic module is configured to: receive a sampling clock signal, and generate a comparison clock signal according to the sampling clock signal; A comparison module is configured to: receive an input voltage and the comparison clock signal; compare the input voltage with a current analog voltage in each comparison cycle of the comparison clock signal, and output a comparison result and a comparison completion signal; The logic module is further configured to: receive the comparison result and the comparison completion signal, and instruct the comparison module to update the analog voltage according to the comparison result; Output comparison status signal; The adaptive controller is configured to receive the comparison state signal and the sampling clock signal, and adjust at least one of the sampling clock signal and the comparison clock signal according to the comparison state signal and the sampling clock signal.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that: The adaptive controller is further configured to: receiving setting information before adjusting at least one of the sampling clock signal and the comparison clock signal; The step of adjusting at least one of the sampling clock signal and the comparison clock signal according to the comparison state signal and the sampling clock signal comprises: determining remaining time information according to the comparison state signal and the sampling clock signal; The sampling clock signal and the comparison clock signal are adjusted according to the setting information and the remaining time information.

3. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The successive approximation analog-to-digital converter also includes: A ring oscillator configured to: generate an internal clock signal; wherein an oscillation frequency of the internal clock signal varies based on environmental conditions; The calibration module is configured to: receive an initial sampling clock signal and the internal clock signal, and measure the speed of the internal clock signal based on the initial sampling clock signal; determine the setting information according to the internal clock signal; and transmit the setting information to the adaptive controller.

4. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The output comparison state signal specifically includes: A first comparison state signal and a second comparison state signal are generated according to the comparison completion signal and the sampling clock signal, and a rising edge of the first comparison state signal is generated before a rising edge of the second comparison state signal is generated.

5. The successive approximation analog-to-digital converter according to claim 4, characterized in that: The determining the remaining time information according to the comparison state signal and the sampling clock signal specifically includes: If, at the rising edge of the first level period of the sampling clock signal, the first comparison state signal and the second comparison state signal are both at the first level, then the remaining time information indicates that the remaining time is insufficient; If the first comparison status signal and the second comparison status signal are both at the second level during the rising edge of the first level period of the sampling clock signal, the remaining time information indicates that the remaining time is sufficient.

6. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The comparison module includes a capacitor array module, and the capacitor array module includes a plurality of capacitors; The logic module is further configured to: generate a control signal according to the comparison result, and transmit the control signal to the capacitor array module; The capacitor array module is configured to: charge at least one of the capacitors in response to the control signal to generate the updated analog voltage; The adaptive controller is further configured to adjust the speed of charging the capacitor in the capacitor array module according to the remaining time information.

7. The successive approximation analog-to-digital converter according to any one of claims 1 to 6, characterized in that: The successive approximation analog-to-digital converter also includes: The adaptive recording module is coupled to the adaptive controller and is configured to: receive and record adjustment information; the adjustment information indicates adjusting at least one of the sampling clock signal and the comparison clock signal.

8. A successive approximation analog-to-digital conversion method, characterized in that: include: receiving a sampling clock signal, and generating a comparison clock signal according to the sampling clock signal; Receiving an input voltage and the comparison clock signal, and comparing the input voltage with a current analog voltage in each comparison cycle of the comparison clock signal, and generating a comparison result and a comparison completion signal; updating the analog voltage according to the comparison result; generating a comparison status signal; At least one of the sampling clock signal and the comparison clock signal is adjusted according to the comparison status signal and the sampling clock signal.

9. The successive approximation analog-to-digital conversion method according to claim 8, characterized in that: The method further comprises: receiving setting information before adjusting at least one of the sampling clock signal and the comparison clock signal; The step of adjusting at least one of the sampling clock signal and the comparison clock signal according to the comparison state signal and the sampling clock signal comprises: determining remaining time information according to the comparison state signal and the sampling clock signal; The sampling clock signal and the comparison clock signal are adjusted according to the setting information and the remaining time information.

10. The successive approximation analog-to-digital conversion method according to claim 9, characterized in that: The generating of the comparison status signal specifically includes: A first comparison state signal and a second comparison state signal are generated according to the comparison completion signal and the sampling clock signal, and a rising edge of the first comparison state signal is generated before a rising edge of the second comparison state signal is generated.

11. The successive approximation analog-to-digital conversion method according to claim 10, characterized in that: The determining the remaining time information according to the comparison state signal and the sampling clock signal specifically includes: If, at the rising edge of the first level period of the sampling clock signal, the first comparison state signal and the second comparison state signal are both at the first level, then the remaining time information indicates that the remaining time is insufficient; If the first comparison status signal and the second comparison status signal are both at the second level during the rising edge of the first level period of the sampling clock signal, the remaining time information indicates that the remaining time is sufficient.

12. The successive approximation analog-to-digital conversion method according to claim 9, characterized in that: The method further comprises: generating a control signal according to the comparison result; In response to the control signal, charging at least one capacitor in the capacitor array module to generate the updated analog voltage; The speed of charging the capacitor in the capacitor array module is adjusted according to the remaining time information.

13. The successive approximation analog-to-digital conversion method according to any one of claims 8 to 12, characterized in that: The method further comprises: Record adjustment information; the adjustment information indicates adjusting at least one of the sampling clock signal and the comparison clock signal.

14. A touch chip, characterized in that: The method comprises a successive approximation analog-to-digital converter as claimed in any one of claims 1 to 7.

15. An electronic device, characterized in that: include: a processor and a memory for storing a computer program capable of running on said processor; Wherein, when the processor is used to run the computer program, it executes the successive approximation analog-to-digital conversion method described in any one of claims 8 to 12.

Images