Data processing method, chip, communication system, storage medium and electronic equipment

Abstract

The invention provides a data processing method, a chip, a communication system, a storage medium and electronic equipment. The data processing method comprises the following steps: receiving a first part of a data frame on a CAN FD bus at a first bit rate; sampling a value of a BRS bit of the data frame at at least one advanced sampling point as an advanced sampling value, wherein the at least one advanced sampling point is arranged before a fixed sampling point of the BRS bit of the data frame; monitoring a jump edge from a BRS bit to an ESI bit of the data frame according to the advanced sampling value; and if the jump edge appears before the fixed sampling point, switching from the first bit rate to a second bit rate different from the first bit rate at the jump edge so as to continue to receive a second part of the data frame at the second bit rate. According to the data processing method, the accuracy of CANFD bus variable-speed position sampling can be improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of data communication technology, and in particular, relates to a data processing method, a chip, a communication system, a storage medium and an electronic device. Background Art

[0002] In CAN FD (Controller Area Network Flexible Data Rate) communication, the sampling accuracy of the BRS (BitRate Switch) bit is critical to the stability and correctness of data transmission. If the bit rate sampling points of the sending node and the receiving node do not match, inconsistent and incorrect data transmission may occur. The CAN FD bus is often used in the automotive electronics field for communication between electronic control units (ECUs) and other devices. Summary of the invention

[0003] The embodiments of the present disclosure provide a data processing method, a chip, a communication system, a storage medium and an electronic device for improving the accuracy of CANFD bus speed shift sampling.

[0004] In a first aspect, an embodiment of the present disclosure provides a data processing method. The data processing method comprises: receiving a first part of a data frame on a CAN FD bus at a first bit rate; sampling a value of a BRS bit of the data frame at at least one advance sampling point as an advance sampling value, wherein the at least one advance sampling point is set before a fixed sampling point for the BRS bit of the data frame; monitoring a transition edge from the BRS bit of the data frame to the ESI bit according to the advance sampling value; and if the transition edge occurs before the fixed sampling point, switching from the first bit rate to a second bit rate different from the first bit rate at the transition edge, so as to continue receiving the second part of the data frame at the second bit rate.

[0005] In an implementation of the first aspect, the data processing method further includes: if the transition edge does not appear before the fixed sampling point, switching from the first bit rate to the second bit rate at the fixed sampling point, so as to continue to receive the second part of the data frame at the second bit rate.

[0006] In an implementation of the first aspect, the data processing method further includes: if the transition edge occurs before the fixed sampling point, using the advance sampling value as the true value of the BRS bit of the data frame; and if the transition edge does not occur before the fixed sampling point, using the fixed sampling value at the fixed sampling point as the true value of the BRS bit of the data frame.

[0007] In an implementation of the first aspect, monitoring the transition edge from the BRS bit to the ESI bit of the data frame according to the advance sampling value includes: if the advance sampling value is a preset level, monitoring the transition edge from the BRS bit to the ESI bit of the data frame.

[0008] In an implementation manner of the first aspect, the at least one early sampling point is set at a position corresponding to a range of 45% to 55% of a bit time of a BRS bit of the data frame.

[0009] In an implementation of the first aspect, the data processing method also includes: calculating the time period between the transition edge from the r0 bit to the BRS bit of the data frame and the transition edge from the BRS bit to the ESI bit of the data frame as the bit time value of the BRS bit of the data frame; and automatically adjusting the position of the at least one early sampling point based on the bit time value, so that the at least one early sampling point is between the transition edge from the r0 bit to the BRS bit and the transition edge from the BRS bit to the ESI bit.

[0010] In an implementation of the first aspect, sampling the value of the BRS bit of the data frame at at least one advance sampling point as the advance sampling value includes: sampling the signal value of the BRS bit on the CAN FD bus at the at least one sampling point respectively; if the sampling results at the at least one sampling point are substantially consistent, using the sampling results as the advance sampling value; and if the sampling results at the at least one sampling point are inconsistent, determining the advance sampling value from the sampling results through a majority voting mechanism.

[0011] In an implementation of the first aspect, the data processing method also includes: configuring the starting point of the BRS bit of the current node to be aligned with the transition edge from the r0 bit to the BRS bit of the arbitration segment of the data frame to achieve resynchronization, the r0 bit is a dominant bit, and the BRS bit is a recessive bit; and starting the bit timing of the BRS bit at the transition edge from the r0 bit to the BRS bit.

[0012] In an implementation of the first aspect, the data processing method also includes: if a transition edge from the BRS bit to the ESI bit is detected before the fixed sampling point, the bit timing of the BRS bit is ended at the transition edge, and the bit timing of the ESI bit is started at the same time, and the transition edge is used as the speed change point from the first bit rate to the second bit rate; if the transition edge from the BRS bit to the ESI bit is not detected before the fixed sampling point, the fixed sampling point is used as the speed change point, and the bit timing of the BRS bit is ended at the transition edge, and the bit timing of the ESI bit is started at the same time.

[0013] In an implementation of the first aspect, the first part includes an arbitration segment of the data frame, the second part includes a data segment of the data frame, and the second bit rate is higher than the first bit rate.

[0014] In a second aspect, an embodiment of the present disclosure provides a chip. The chip includes: a control module, which is electrically coupled to a CAN FD bus and is configured to: receive a first portion of a data frame on the CAN FD bus at a first bit rate; sample a value of a BRS bit of the data frame at at least one advance sampling point as an advance sampling value, wherein the at least one advance sampling point is set before a fixed sampling point for the BRS bit of the data frame; monitor a transition edge from the BRS bit of the data frame to the ESI bit according to the advance sampling value; and if the transition edge occurs before the fixed sampling point, switch from the first bit rate to a second bit rate different from the first bit rate at the transition edge, so as to continue receiving the second portion of the data frame at the second bit rate.

[0015] In an implementation of the second aspect, the control module is further configured to: if the transition edge does not appear before the fixed sampling point, switch from the first bit rate to the second bit rate at the fixed sampling point, so as to continue to receive the second part of the data frame at the second bit rate.

[0016] In a third aspect, an embodiment of the present disclosure provides a communication system. The communication system includes: a CAN FD bus; at least one communication node electrically coupled to the CAN FD bus; and a controller electrically coupled to the CAN FD bus and configured to: receive a first portion of a data frame from at least one communication node via the CAN FD bus at a first bit rate; sample a value of a BRS bit of the data frame at at least one advance sampling point as an advance sampling value, the at least one advance sampling point being set before a fixed sampling point for the BRS bit of the data frame; monitor a transition edge from the BRS bit to the ESI bit of the data frame according to the advance sampling value; if the transition edge occurs before the fixed sampling point, then at the transition edge, switch from the first bit rate to a second bit rate different from the first bit rate, so as to continue receiving the second portion of the data frame at the second bit rate; if the transition edge does not occur before the fixed sampling point, then at the fixed sampling point, switch from the first bit rate to the second bit rate, so as to continue receiving the second portion of the data frame at the second bit rate.

[0017] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements the data processing method described in any one of the first aspects of the present disclosure.

[0018] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory configured to store a processor-executable program; and a processor configured to call the program to execute the data processing method according to any one of the first aspects of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a schematic diagram of the structure of the communication system described in an embodiment of the present disclosure.

[0020] Figure 2 Shown is a schematic diagram of the structure of a CAN FD frame in CAN FD bus communication.

[0021] Figure 3 The figure shows a schematic diagram of the receiving configuration of CAN FD frames in CAN FD bus communication.

[0022] Figure 4A Shown is a flow chart of the data processing method described in an embodiment of the present disclosure.

[0023] Figure 4B Another flowchart of the data processing method described in the embodiment of the present disclosure is shown.

[0024] Figure 4C Shown is a third flow chart of the data processing method described in an embodiment of the present disclosure.

[0025] Figure 4D Shown is a fourth flow chart of the data processing method described in an embodiment of the present disclosure.

[0026] Figure 5 Shown is a schematic diagram of an exemplary configuration of fixed sampling points in the data processing method described in an embodiment of the present disclosure.

[0027] Fig. 6A Shown is a schematic diagram of an exemplary configuration of an advance sampling point in the data processing method according to an embodiment of the present disclosure.

[0028] Figure 6B An exemplary flow chart of automatically adjusting the position of the advance sampling point according to an embodiment of the present disclosure is shown.

[0029] Figure 6C A schematic diagram showing an exemplary configuration of an advance sampling point in the data processing method according to an embodiment of the present disclosure is shown.

[0030] Figure 7 Shown is an exemplary flowchart of the data processing method described in an embodiment of the present disclosure.

[0031] Figure 8Shown is a schematic diagram of an exemplary configuration of resynchronization in the data processing method according to an embodiment of the present disclosure.

[0032] Fig. 9 Shown is a schematic diagram of the structure of an electronic device described in an embodiment of the present disclosure.

[0033] Fig.10 Shown is a schematic diagram of the structure of the chip described in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following describes the implementation of the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the embodiments of the present disclosure from the contents disclosed in this specification. The embodiments of the present disclosure can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the embodiments of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0035] It should be noted that the illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the embodiments of the present disclosure. Therefore, the drawings only show components related to the embodiments of the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.

[0036] Figure 1 Schematic diagram of an application scenario of the present disclosure embodiment. Figure 1 As shown, this embodiment provides a communication system of a CAN FD bus, and the communication system 100 includes a CAN FD bus 110 and at least two communication nodes 120a to 120c (collectively referred to as communication nodes 120 in this article). Each of the communication nodes 120 sends data to the CAN FD bus 110, or receives data transmitted on the CAN FD bus 110, and the communication node 120 is both a sending node and a receiving node. The communication node 120 includes a controller 121, and the controller 121 can implement the data processing method described in the present disclosure, but the implementation device of the data processing method described in the present disclosure includes but is not limited to the structure of the controller listed in the embodiment of the present disclosure. All structural deformations and replacements of the prior art made according to the principles of the present disclosure are included in the protection scope of the present disclosure.

[0037] Figure 2 : is a schematic diagram showing the structure of a CAN FD frame in CAN FD bus communication. Figure 2As shown in the figure, the CAN FD frame includes an arbitration segment and a data segment. The receiving node receives the data in the arbitration segment based on the standard bit rate and receives the data in the data segment based on the selectable high bit rate. The arbitration segment includes the segments such as SOF, Identifier, r1, IDE, FDF, r0, and BRS, and the data segment includes the segments such as ESI, DLC, Data, and CRC.

[0038] In CAN FD communication, the communication node 120 uses sampling points to determine when to read the data segment on the CAN FD bus. When a sending node sends a data frame, it sends the frame header and arbitration segment at the standard bit rate during its transmission. Then, when the BRS bit is set, the sending node switches to a higher data bit rate to send the data segment and CRC segment immediately after the sampling point of the BRS bit. The receiving node also switches to the data bit rate according to the same sampling point to correctly receive the data.

[0039] If the sampling points of the transmitting and receiving nodes do not match, the transmitting node will switch to the data bit rate while the receiving node is waiting for the slower standard bit rate to sample. This will cause the receiving node to read an undefined value or erroneous data transmission during data bit overlap.

[0040] Figure 3 2 is a schematic diagram showing the receiving configuration of a CAN FD frame in CAN FD bus communication. Figure 3 As shown, for example, the sampling point of the receiving node is set to 80%, and the sampling point of the sending node is set to 60%. When the sending node sends the BRS bit, the receiving node is still waiting for the standard bit nTseg1 segment to be completed. When the receiving node arrives at the sampling point of the BRS bit, it samples the dominant level of the ESI bit, causing a reception error at the receiving node.

[0041] In actual applications, due to differences in parameter configurations between communication nodes, hardware differences, clock inaccuracies and other factors, it is easy to cause sampling point mismatch problems. When a general CANFD controller encounters a sampling point mismatch, the BRS bit is prone to sampling errors.

[0042] Currently, the existing technology can only solve this problem by manually configuring the sampling points of each node on the bus to be at the same position. When there are many nodes on the bus, the bus configuration will be more complicated, and some nodes cannot even be configured with the sampling point position.

[0043] In order to solve at least the above problems, the present disclosure provides a solution for improving the sampling accuracy of the CAN FD bus speed change bit, which solves the problem that the sampling points between nodes in the CAN FD bus system are too different and cannot communicate. In some embodiments, a set of independent advance sampling points is added corresponding to the BRS bit, and its position is set before the fixed sampling point, and before the transition edge of the bus BRS bit to the ESI bit, so as to sample the value of the BRS bit in advance, and the sampling value is determined by multiple sampling and majority voting, and the fixed sampling point of the BRS bit is retained. In addition, if the transition edge from the BRS bit to the ESI bit is detected before the fixed sampling point, the transition edge position from the BRS bit to the ESI bit is used as the speed change point, and the bit rate is switched at the transition edge. If the transition edge from the BRS bit to the ESI bit is not detected before the fixed sampling point, the fixed sampling point is used as the speed change point, and the bit rate is switched at the fixed sampling point.

[0044] Figure 4A is a flow chart showing a data processing method according to an embodiment of the present disclosure. The hardware device for implementing the data processing method may be, for example, Figure 1 The communication node (referred to as node) shown in FIG. 1 can receive data (i.e., CAN FD frames) from the CAN FD bus using the data processing method described in the embodiment of the present disclosure. Figure 4A As shown, the data processing method provided by the embodiment of the present disclosure may include the following steps S410 to S440.

[0045] In step S410 , a first portion of a data frame on the CAN FD bus is received at a first bit rate.

[0046] In step S420, the value of the BRS bit of the data frame is sampled at at least one advance sampling point as an advance sampling value, and the at least one advance sampling point is set before a fixed sampling point for the BRS bit of the data frame.

[0047] In step S430, a transition edge from the BRS bit to the ESI bit of the data frame is monitored according to the advance sampling value.

[0048] In step S440, if the transition edge occurs before the fixed sampling point, the first bit rate is switched to a second bit rate different from the first bit rate at the transition edge to continue receiving the second part of the data frame at the second bit rate.

[0049] According to an embodiment of the present disclosure, the first part includes the arbitration segment of the data frame, the second part includes the data segment of the data frame, and the second bit rate is higher than the first bit rate.

[0050] According to one embodiment of the present disclosure, Figure 4B 4 is another flow chart showing the data processing method according to the embodiment of the present disclosure. In addition to the steps S410 to S440 described above, the data processing method provided by the present embodiment may further include the following step S450.

[0051] In step S450, if the transition edge does not appear before the fixed sampling point, switching from the first bit rate to the second bit rate is performed at the fixed sampling point to continue receiving the second part of the data frame at the second bit rate.

[0052] According to an embodiment of the present disclosure, in step S440, if the transition edge occurs before the fixed sampling point, the advance sampling value is used as the true value of the BRS bit of the data frame. In addition, in step S450, if the transition edge does not occur before the fixed sampling point, the fixed sampling value at the fixed sampling point is used as the true value of the BRS bit of the data frame.

[0053] According to one embodiment of the present disclosure, in step S420, sampling the value of the BRS bit of the data frame at at least one advance sampling point as the advance sampling value includes: sampling the signal value of the BRS bit on the CAN FD bus at the at least one sampling point respectively; if the sampling results at the at least one sampling point are substantially consistent, taking the sampling results as the advance sampling value; and if the sampling results at the at least one sampling point are inconsistent, determining the advance sampling value from the sampling results by a majority voting mechanism.

[0054] According to an embodiment of the present disclosure, in step S420, the at least one advanced sampling point is set at a position corresponding to a range of 45% to 55% of the bit time of the BRS bit of the data frame.

[0055] According to one embodiment of the present disclosure, in step S430, monitoring the transition edge from the BRS bit to the ESI bit of the data frame according to the advance sampling value includes: if the advance sampling value is a preset level, monitoring the transition edge from the BRS bit to the ESI bit of the data frame.

[0056] According to one embodiment of the present disclosure, Figure 4C 4 is a third flow chart showing the data processing method according to the embodiment of the present disclosure. In addition to the above-described steps S410 to S450, the data processing method provided by the present embodiment may further include step S460. The step S460 specifically includes the following steps S461 to S462.

[0057] In step S461, the time period between the transition edge from the r0 bit to the BRS bit of the data frame and the transition edge from the BRS bit to the ESI bit of the data frame is calculated as the bit time value of the BRS bit of the data frame.

[0058] In step S462, the position of the at least one early sampling point is automatically adjusted and configured based on the bit time value, so that the at least one early sampling point is between the transition edge from the r0 bit to the BRS bit and the transition edge from the BRS bit to the ESI bit.

[0059] In the embodiments of the present disclosure, Figure 5 As shown, the bit time of the BRS bit sent by the sending node A is Tbrs_A = (nTseg1_A + dTseg2_A), and the position of the receiving node B at the fixed sampling point SP of BRS can be expressed as nTseg1_B. If Tbrs_A < nTseg1_B, then the receiving node B will sample the BRS bit incorrectly. The method of sampling the BRS bit in advance is to use the advance sampling point ESP to collect the bus signal value in advance. The position of ESP is set before the fixed sampling point SP. At the same time, if ESP is set before the transition edge from the bus BRS bit to the ESI bit, the value of the BRS bit can be correctly collected.

[0060] According to the above description, in the embodiment of the present disclosure, the sampling method for receiving the BRS bit of the CANFD frame from the bus as a receiving node does not need to know the position of the fixed sampling point of other communication nodes. It only needs to configure the advance sampling point before the fixed sampling point of the communication node to improve the accuracy and adaptability of the sampling of the communication node itself.

[0061] In the embodiments of the present disclosure, the node itself can improve the tolerance of the sampling point error by sampling in advance and automatically adjusting the BRS bit sampling point, eliminating the need for manual unified configuration. In particular, the BRS bit width that may be sent by some nodes has nothing to do with the sampling point configuration. Even with unified configuration, it cannot be guaranteed that the BRS bit width meets the bus requirements. In some bus systems, it is impossible to uniformly configure the sampling point positions of each node. In these cases, the method of the embodiments of the present disclosure can greatly improve the accuracy and tolerance of BRS bit sampling.

[0062] According to an embodiment of the present disclosure, the position of the advance sampling point is pre-arbitrarily configured.

[0063] Fig. 6A is a schematic diagram showing an exemplary configuration of an advance sampling point in the data processing method described in an embodiment of the present disclosure. In some implementations, such as Fig. 6AAs shown in the figure, a set of independent early sampling points ESP (Early Sampling Point) is added to the BRS bit, and early sampling is performed at the BRS bit. At the same time, three samplings (ESP1, ESP2, ESP3 three early sampling points) and majority voting are used to determine the early sampling value. At the same time, the fixed sampling point SP of the BRS bit will be retained. The positions of the three early sampling points ESP1, ESP2 and ESP3 can be arbitrarily configured. Fig. 6A The 45%, 50% and 55% are just given as an example.

[0064] According to an embodiment of the present disclosure, the position of the advance sampling point is automatically adjusted and configured based on the Tbrs value obtained by measurement; the Tbrs value is the time between the start point and the end point of the BRS bit configured by the current node.

[0065] In some implementations, the positions of the early sampling points ESP1, ESP2, and ESP3 may also be automatically adjusted according to the measured Tbrs value.

[0066] In addition, if Fig. 6A As shown, when the r0 bit and the ESI bit are dominant bits and the BRS bit is recessive, the communication node can automatically measure the bit width of the BRS bit and automatically adjust the position of the early sampling point on the BRS bit. The receiving node B will measure the time Tbrs between the starting point of the BRS bit and the end point of the BRS bit. If Tesp2<Tbrs<Tesp3, the sampling values ​​of the early sampling points ESP1 and ESP2 will be different from the sampling value of the early sampling point ESP3. Then the receiving node B can adjust the values ​​of the early sampling points ESP1, ESP2, and ESP3 to the appropriate position according to the value of Tbrs to increase the sampling accuracy of subsequent data frames. Among them, Tesp2 is the time between the starting point of the BRS bit and the early sampling point ESP2 of the receiving node B, and Tesp3 is the time between the starting point of the BRS bit and the early sampling point ESP3 of the receiving node B.

[0067] Figure 6B FIG. 1 is a schematic diagram showing an exemplary process of automatically adjusting the position of the advance sampling point according to an embodiment of the present disclosure. Figure 6B As shown, the position of the advance sampling point is automatically adjusted and configured based on the Tbrs value obtained by measurement, including the following steps: starting to measure the time of the BRS bit at the transition edge from the r0 bit to the BRS bit, and ending the measurement of the BRS bit at the transition edge from the BRS bit to the ESI bit, and obtaining the BRS bit time as Tbrs; when Tesp2<Tbrs<Tesp3, setting Tesp3 to Tbrs to realize automatic adjustment of the position of the advance sampling point; otherwise ending.

[0068] According to an embodiment of the present disclosure, the advance sampling points include a group of advance sampling preset points. The number of the advance sampling preset points is an odd number equal to or greater than 3. The advance sampling preset points are all located on the BRS bit and are located before the fixed sampling point.

[0069] In the embodiment of the present disclosure, the sampling points of the communication nodes of the CANFD bus are usually set between 60% and 90%. Fig. 6A As shown in the figure, the position of the advance sampling point is set at about 50%, so that the signal can be collected before the transition edge from the BRS bit to the ESI bit. Moreover, for a typical square wave signal, the bus signal is stable at about 50%, and the accuracy of the collection is also guaranteed. The three-time sampling method is to collect the signal value of the bus at the positions of ESP1, ESP2 and ESP3 respectively, and determine the advance sampling value through the voting mechanism of minority obeys majority.

[0070] According to the above description, in the embodiment of the present disclosure, three advance sampling preset points are set mainly to resist noise and error. The three-time sampling method runs at different time points to capture the value of the signal, thereby increasing redundant information and improving the reliability of high-speed data processing. At the same time, based on the results of the three samplings, a signal decision is made to determine the true value of the data bit. If the results of the three samplings are mostly consistent, then this value is used. If the results of the three samplings are inconsistent, a majority vote is used to determine the true value. For example, if the sampling values ​​of ESP1 and ESP2 are both 1, and the sampling value of ESP3 is 0, the true value of the BRS bit will be determined to be 1.

[0071] It can be seen from the above description that in the embodiments of the present disclosure, by setting a group of advance sampling preset points, multiple advance sampling can be achieved, thereby further improving the accuracy of sampling.

[0072] According to one embodiment of the present disclosure, Figure 4D 4 is a fourth flow chart showing the data processing method according to the embodiment of the present disclosure. In addition to the above-described steps S410 to S460, the data processing method provided by the present embodiment may further include the following step S470.

[0073] In step S470, the starting point of the BRS bit of this node is configured to be aligned with the transition edge from the r0 bit to the BRS bit of the arbitration segment of the data frame to achieve resynchronization, the r0 bit is a dominant bit, and the BRS bit is a recessive bit; and the bit timing of the BRS bit is started at the transition edge from the r0 bit to the BRS bit.

[0074] Figure 7The present invention is a flow chart showing an exemplary data processing method according to an embodiment of the present invention, comprising the following steps: synchronizing at the table edge from r0 to BRS; collecting the value of BRS at the advance sampling point ESP1, collecting the value of BRS at the advance sampling point ESP2, collecting the value of BRS at the advance sampling point ESP3, and determining the advance sampling value of BRS according to the voting mechanism; judging whether the advance sampling value is a recessive level, if so, waiting for the transition edge from BRS to ESI, otherwise, no speed change is required and the process ends; judging whether the transition edge from BRS to ESI occurs before the fixed sampling point, if so, taking the advance sampling value as the true value of BRS, and performing bit rate switching at the transition edge from BRS to ESI; otherwise, taking the fixed sampling value as the true value of BRS, and performing bit rate switching at the fixed sampling point.

[0075] In the embodiments of the present disclosure, Figure 8 FIG. 2 shows an exemplary configuration diagram of resynchronization in the data processing method according to an embodiment of the present disclosure. Figure 8 As shown, the r0 bit is a dominant bit, and the BRS bit is a recessive bit. When the r0 bit jumps to the BRS bit, a resynchronization (BRS_Sync) is performed to align the starting point of the BRS bit of the receiving node B with the transition edge from r0 to the BRS bit on the bus, further improving the sampling accuracy of the BRS bit. In other words, in order to further enhance the position accuracy of the BRS bit early sampling point, the embodiment of the present disclosure also performs a resynchronization at the dominant bit to recessive bit transition edge from r0 bit to BRS bit, that is, the receiving node B immediately starts the BRS bit bit timing at the dominant bit to recessive bit transition edge from r0 bit to BRS bit. Figure 8 As shown in FIG. 1 , at the transition edge position from the r0 bit to the BRS bit, the receiving node B performs a synchronization operation (BRS_Sync) and starts the BRS bit timing. Synchronization can improve the accuracy of the receiving node B at the early sampling point position of the BRS bit.

[0076] According to one embodiment of the present disclosure, if the transition edge from the BRS bit to the ESI bit is detected before the fixed sampling point, the bit timing of the BRS bit is terminated in advance, and the data bit rate (i.e., high-speed bit rate) is switched to at the transition edge from the BRS bit to the ESI bit; that is, the bit timing of the BRS bit is terminated at the transition edge from the BRS bit to the ESI bit, and the bit timing of the ESI bit is started at the same time.

[0077] In the embodiments of the present disclosure, Figure 6CAs shown, after the receiving node B determines that the value of the BRS bit is a recessive level through the method of advance sampling, it confirms that the CANFD frame being received is a variable speed frame, and the receiving node B will continue to monitor the bus signal. If the transition edge from the BRS bit to the ESI bit is detected before the fixed sampling point SP, the receiving node B will end the bit timing of the BRS bit in advance and switch to the high-speed bit rate to start the bit timing of the ESI bit. The transition edge position of the bus BRS bit to the ESI bit is the end point of the BRS bit of the receiving node B.

[0078] According to one embodiment of the present disclosure, if the transition edge from the BRS bit to the ESI bit is not detected before the fixed sampling point, the data bit rate (i.e., high-speed bit rate) is switched to the fixed sampling point, and the bit timing of the BRS bit is ended at the transition edge from the BRS bit to the ESI bit, and the bit timing of the ESI bit is started at the same time.

[0079] In the embodiments of the present disclosure, Figure 6C As shown, if the transition from the BRS bit to the ESI bit is not detected before the fixed sampling point SP, the high-speed bit rate is switched to at the fixed sampling point SP. At this time, the fixed sampling point SP is the speed change point. At the same time, the BRS bit timing is ended and the ESI bit timing is started at the transition edge from the BRS bit to the ESI bit.

[0080] The protection scope of the data processing method described in the embodiments of the present disclosure is not limited to the execution order of the steps listed in the embodiments of the present disclosure. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present disclosure are included in the protection scope of the present disclosure.

[0081] According to the above description, the innovation of the present disclosure lies in receiving signals from the CANFD bus and sampling the received signals, sampling the BRS bit of the CANFD bus by the advance sampling method, performing BRS by three sampling methods to determine the value of the advance sampling, adding a resynchronization at the transition edge from the r0 bit to the BRS bit, measuring the BRS bit time by the circuit and automatically adjusting the advance sampling point position, thereby improving the accuracy of CANFD speed change bit sampling on the complex CANFD bus system, improving the robustness of the CANFD node, and reducing bus error frames. In the FPGA test, the data processing method described in the present disclosure has no problems with CANFD speed change bit sampling under various baud rate combinations, and has a good application effect.

[0082] The embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. The computer program is executed to implement the data processing method according to any embodiment of the present disclosure.

[0083] A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above-mentioned embodiment can be completed by instructing a processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above-mentioned storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid-state disk (SSD)), etc.

[0084] Fig. 9 1 is a schematic diagram showing the structure of an electronic device 900 provided according to an embodiment of the present disclosure. Fig. 9 As shown, the chip 900 in the embodiment of the present disclosure includes a memory 910 and a processor 920 .

[0085] The memory 910 is used to store computer programs. In some possible implementations, the memory may include a computer system readable medium in the form of a volatile memory, such as a RAM and / or a cache memory. The electronic device may further include other removable / non-removable, volatile / non-volatile computer system storage media. The memory may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0086] The processor 920 is communicatively connected to the memory 910, and is used to execute the computer program stored in the storage module, so that the electronic device 900 executes the data processing method provided by any embodiment of the present disclosure. In some possible implementations, the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc. In other implementations, the processor can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0087] In some possible implementations, the electronic device 900 provided by the embodiment of the present disclosure may further include a display 930. The display is communicatively connected to the memory and the processor, and is used to display a graphical user interface (GUI) related to the data processing method provided by any embodiment of the present disclosure.

[0088] In the disclosed embodiments, the display may include a display screen (display panel). In some implementations, the display panel may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like. In addition, the display may also be a touch panel (touch screen, touch screen), and the touch panel may include a display screen and a touch-sensitive surface. When the touch-sensitive surface detects a touch operation on or near it, it is transmitted to the processor to determine the type of touch event, and then the processor provides a corresponding visual output on the display device according to the type of touch event.

[0089] The electronic device provided in the embodiments of the present disclosure can implement the data processing method described in the present disclosure, but the implementation device of the data processing method described in the present disclosure includes but is not limited to the structure of the electronic device listed in the embodiments of the present disclosure. All structural deformations and replacements of the prior art made according to the principles of the present disclosure are included in the protection scope of the present disclosure.

[0090] Fig.10: is a schematic diagram showing the structure of a chip provided according to an embodiment of the present disclosure. The chip (SoC) includes a control module (RKCAN). The control module (RKCAN) is connected to the CANFD bus for communication, and receives the header and arbitration segment of the data frame on the CANFD bus based on the standard bit rate sampling, and sets an advance sampling point based on the fixed sampling point of the BRS bit configured by this node. The advance sampling point is located on the BRS bit and before the fixed sampling point. At the advance sampling point, switch from the standard bit rate to the data bit rate, and continue to sample and receive the data frame based on the data bit rate.

[0091] According to an embodiment of the present disclosure, the position of the advance sampling point is pre-arbitrarily configured.

[0092] According to an embodiment of the present disclosure, the position of the advance sampling point is automatically adjusted and configured based on a Tbrs value obtained by measurement. The Tbrs value is the time between the start point and the end point of the BRS bit configured by the current node.

[0093] According to an embodiment of the present disclosure, the advance sampling points include a group of advance sampling preset points. The number of the advance sampling preset points is an odd number equal to or greater than 3. The advance sampling preset points are all located on the BRS bit and are located before the fixed sampling point.

[0094] According to one embodiment of the present disclosure, the control module (RKCAN) switches from the standard bit rate to the data bit rate at each of the advance sampling preset points, continues to receive the data frame based on the data bit rate, and obtains corresponding reception results. If the reception results are substantially consistent, each of the advance sampling preset points is used as the advance sampling point, or one of the advance sampling preset points is selected as the advance sampling point. If the reception results are inconsistent, the true advance sampling preset point is determined by majority voting, and the true advance sampling preset point is used as the advance sampling point, or one of the true advance sampling preset points is selected as the advance sampling point.

[0095] According to one embodiment of the present disclosure, the control module (RKCAN) configures the starting point of the BRS bit of the node to be aligned with the transition edge from the r0 bit to the BRS bit of the arbitration segment of the data frame on the CANFD bus to achieve resynchronization. The r0 bit is a dominant bit and the BRS bit is a recessive bit. The bit timing of the BRS bit starts at the transition edge from the r0 bit to the BRS bit.

[0096] According to an embodiment of the present disclosure, if the control module (RKCAN) detects the transition edge from the BRS bit to the ESI bit before the fixed sampling point, the bit timing of the BRS bit is terminated in advance, and the bit timing is switched to the data bit rate (i.e., high-speed bit rate) at the transition edge from the BRS bit to the ESI bit. That is, the bit timing of the BRS bit is terminated at the transition edge from the BRS bit to the ESI bit, and the bit timing of the ESI bit is started at the same time.

[0097] According to one embodiment of the present disclosure, if the control module (RKCAN) does not detect the transition edge from the BRS bit to the ESI bit before the fixed sampling point, it switches to the data bit rate (i.e., high-speed bit rate) at the early sampling point position, and ends the bit timing of the BRS bit at the transition edge from the BRS bit to the ESI bit, and starts the bit timing of the ESI bit at the same time.

[0098] In some possible implementations, the control module (RKCAN) provided in the embodiment of the present disclosure may be connected to the CANFD bus through a transceiver. The chip (SoC) may also include modules such as a CPU and a memory, and the control module (RKCAN) may also be connected to the CPU, the memory and other modules.

[0099] The chip provided in the embodiments of the present disclosure can implement the data processing method described in the present disclosure, but the implementation device of the data processing method described in the present disclosure includes but is not limited to the structure of the chip listed in the embodiments of the present disclosure. All structural deformations and replacements of the prior art made according to the principles of the present disclosure are included in the protection scope of the present disclosure.

[0100] In the several embodiments provided in the embodiments of the present disclosure, it should be understood that the disclosed system, device or method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules or units, which can be electrical, mechanical or other forms.

[0101] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure. For example, the functional modules / units in the various embodiments of the present disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0102] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiments of the present disclosure.

[0103] The embodiments of the present disclosure may also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiments of the present disclosure is generated in whole or in part. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer or data center to another website site, computer or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0104] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product may be a software installation package, and when the above method is required, the computer program product may be downloaded and executed on a computer.

[0105] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0106] The above embodiments are merely illustrative of the principles and effects of the embodiments of the present disclosure, and are not intended to limit the embodiments of the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the embodiments of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the embodiments of the present disclosure shall still be covered by the claims of the embodiments of the present disclosure.

Claims

1. A data processing method, characterized in that, comprising: receiving a first part of a data frame on a CAN FD bus at a first bit rate; sampling a value of a BRS bit of the data frame at at least one early sampling point as an early sampling value, the at least one early sampling point being set before a fixed sampling point for the BRS bit of the data frame; monitoring a transition edge from the BRS bit to an ESI bit of the data frame according to the early sampling value; and if the transition edge occurs before the fixed sampling point, then at the transition edge, switching from the first bit rate to a second bit rate different from the first bit rate so as to continue receiving a second part of the data frame at the second bit rate.

2. The data processing method according to claim 1, characterized in that, further comprising: if the transition edge does not occur before the fixed sampling point, then at the fixed sampling point, switching from the first bit rate to the second bit rate so as to continue receiving a second part of the data frame at the second bit rate.

3. The data processing method according to claim 2, characterized in that, further comprising: if the transition edge occurs before the fixed sampling point, then taking the early sampling value as a true value of the BRS bit of the data frame; and if the transition edge does not occur before the fixed sampling point, then taking a fixed sampling value at the fixed sampling point as a true value of the BRS bit of the data frame.

4. The data processing method according to claim 1, characterized in that, monitoring a transition edge from the BRS bit to an ESI bit of the data frame according to the early sampling value comprises: if the early sampling value is a preset level, then monitoring a transition edge from the BRS bit to an ESI bit of the data frame.

5. The data processing method according to claim 1, characterized in that, the at least one early sampling point is set at a position corresponding to a range of 45% to 55% of a bit time of the BRS bit of the data frame.

6. The data processing method according to claim 1, characterized in that, further comprising: calculating a time period between a transition edge from an r0 bit to a BRS bit of the data frame and a transition edge from the BRS bit to an ESI bit of the data frame as a bit time value of the BRS bit of the data frame; and automatically adjusting and configuring a position of the at least one early sampling point based on the bit time value such that the at least one early sampling point is between the transition edge from the r0 bit to the BRS bit and the transition edge from the BRS bit to the ESI bit.

7. The data processing method according to claim 1, characterized in that, sampling a value of a BRS bit of the data frame at at least one early sampling point as an early sampling value comprises: respectively sampling signal values of the BRS bit on the CAN FD bus at the at least one sampling point; if sampling results at the at least one sampling point are substantially the same, then taking the sampling results as the early sampling value; and if sampling results at the at least one sampling point are inconsistent, then determining the early sampling value from the sampling results through a voting mechanism of the minority obeying the majority.

8. The data processing method according to claim 1, wherein, it further comprises: configuring the starting point of the BRS bit of the present node to be aligned with the transition edge from the r0 bit to the BRS bit of the arbitration segment of the data frame to achieve resynchronization, the r0 bit being a dominant bit and the BRS bit being a recessive bit; and starting the bit timing of the BRS bit at the transition edge from the r0 bit to the BRS bit.

9. The data processing method according to claim 2, wherein, it further comprises: if a transition edge from the BRS bit to the ESI bit is detected before the fixed sampling point, ending the bit timing of the BRS bit at the transition edge, simultaneously starting the bit timing of the ESI bit, and taking the transition edge as the speed change point from the first bit rate to the second bit rate; if a transition edge from the BRS bit to the ESI bit is not detected before the fixed sampling point, taking the fixed sampling point as the speed change point, and ending the bit timing of the BRS bit at the transition edge, simultaneously starting the bit timing of the ESI bit.

10. The data processing method according to claim 1, wherein, the first part includes the arbitration segment of the data frame, the second part includes the data segment of the data frame, and the second bit rate is higher than the first bit rate.

11. A chip, wherein, it includes: a control module, electrically coupled to the CAN FD bus and configured to: receive the first part of the data frame on the CAN FD bus at a first bit rate; sample the value of the BRS bit of the data frame at at least one early sampling point as an early sampling value, the at least one early sampling point being set before the fixed sampling point for the BRS bit of the data frame; monitor the transition edge from the BRS bit to the ESI bit of the data frame according to the early sampling value; and if the transition edge occurs before the fixed sampling point, switching from the first bit rate to a second bit rate different from the first bit rate at the transition edge so as to continue receiving the second part of the data frame at the second bit rate.

12. The chip according to claim 11, wherein, the control module is further configured to: if the transition edge does not occur before the fixed sampling point, switching from the first bit rate to the second bit rate at the fixed sampling point so as to continue receiving the second part of the data frame at the second bit rate.

13. A communication system, wherein, it includes: a CAN FD bus; at least one communication node, electrically coupled to the CAN FD bus; and a controller, electrically coupled to the CAN FD bus and configured to: receive the first part of the data frame from at least one communication node via the CAN FD bus at a first bit rate; sample the value of the BRS bit of the data frame at at least one early sampling point as an early sampling value, the at least one early sampling point being set before the fixed sampling point for the BRS bit of the data frame; Monitor the rising edge of the BRS bit to the ESI bit of the data frame according to the pre-sampled value; If the rising edge occurs before the fixed sampling point, at the rising edge, switch from the first bit rate to a second bit rate different from the first bit rate, so as to continue receiving the second part of the data frame at the second bit rate; If the rising edge does not occur before the fixed sampling point, at the fixed sampling point, switch from the first bit rate to the second bit rate, so as to continue receiving the second part of the data frame at the second bit rate.

14. A computer-readable storage medium, on which a computer program is stored, characterized in that, when the program is executed, it implements the data processing method according to any one of claims 1 to 10.

15. An electronic device, characterized in that, comprising: a memory configured to store a program executable by a processor; and a processor configured to call the program to execute the data processing method according to any one of claims 1 to 10.

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