Full super junction power semiconductor device and manufacturing method thereof
By adopting a multi-layer epitaxial structure and alternately arranged doped regions in semiconductor devices, the problems of complex manufacturing processes and high on-resistance of high-voltage fully superjunction devices are solved, and a higher density superjunction and lower on-resistance are achieved.
Patent Information
- Application Number
- CN202510105213.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-27
AI Technical Summary
At this stage, the manufacturing process of high-voltage fully super junction semiconductor devices is complicated, and it is difficult to stabilize mass production and etch trenches above 50um, resulting in high device on-resistance.
Using a multi-layer epitaxial structure, a structure with smaller key sizes is achieved by forming alternately arranged P-type and N-type doped regions in the bottom and upper epitaxial layers, and a doped region with smaller width and higher density is formed on the upper epitaxial layer.
The density of the device superjunction is increased, allowing the second N-type doping region to increase the doping concentration, thereby reducing the on-resistance of the device.
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Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a full super junction power semiconductor device and a manufacturing method thereof. Background Art
[0002] The current mainstream application voltage of superjunction semiconductor devices is 600-800V. However, with the continuous development of new energy power transmission in recent years, the demand for high-voltage semiconductor devices has become more and more urgent, especially in the field of fast charging piles. However, the current high-voltage devices are basically semi-superjunction structures, and their on-resistance is much higher than that of full superjunction structures. Usually, the full superjunction structure in the relevant technology includes an epitaxial layer with a thickness of 60um, which can achieve a withstand voltage of more than about 800V, and the superjunction trench depth is about 50um. The semi-superjunction structure includes an epitaxial layer with a thickness of 100um, which is composed of an upper layer with a higher concentration epitaxial layer and a lower concentration epitaxial layer at the bottom. The withstand voltage is about 1000V and the superjunction trench depth is 50um.
[0003] However, due to the limitation of dry etching process, it is currently impossible to stably mass-produce trenches larger than 50um. Therefore, the high-voltage full super junction structure generally undergoes two epitaxy processes and two trenches. The width of the upper super junction trench needs to be consistent with the width of the lower super junction trench. This places high demands on the process and limits the reduction of the on-resistance of the device. Summary of the invention
[0004] The present application provides a full super junction power semiconductor device and a method for manufacturing the same, which can solve the problem that related technical processes are difficult and limit the reduction of device on-resistance.
[0005] In order to solve the technical problem in the background technology, the first aspect of the present application provides a full super junction power semiconductor device, the full super junction power semiconductor device comprising:
[0006] substrate layer;
[0007] A bottom epitaxial layer, wherein the bottom epitaxial layer is formed on the substrate layer, and a first P-type doping region and a first N-type doping region are formed in the bottom epitaxial layer and are alternately arranged along a first direction;
[0008] An upper epitaxial layer, wherein the upper epitaxial layer is formed on the bottom epitaxial layer, and wherein a second P-type doping region and a second N-type doping region are formed in the upper epitaxial layer and are alternately arranged along a second direction; wherein the first direction and the second direction are perpendicular; wherein the lower surface of the second P-type doping region sequentially contacts with the upper surface of the alternately arranged first P-type doping region and the first N-type doping region in the first direction; and wherein the lower surface of the second N-type doping region sequentially contacts with the upper surface of the alternately arranged first P-type doping region and the first N-type doping region in the first direction.
[0009] Optionally, a width of the second P-type doping region in the second direction is smaller than a width of the first P-type doping region in the first direction.
[0010] Optionally, a density of the second P-type doping region in the second direction is greater than a density of the first P-type doping region in the first direction.
[0011] Optionally, a concentration of N-type impurities in the second N-type doping region is greater than a concentration of N-type impurities in the first N-type doping region.
[0012] Optionally, the upper portion of the upper epitaxial layer forms a P-type body region and a trench gate alternately arranged along the second direction;
[0013] The trench gate contacts the second N-type doping region downward;
[0014] The P-type body region contacts downwardly with the second P-type doping region and a portion of the second N-type doping region on both sides of the second P-type doping region;
[0015] A contact hole structure is formed on the P-type body region, and N-type heavily doped regions are formed on both sides of the contact hole structure;
[0016] The upper epitaxial layer is covered with a source metal layer, an oxide layer is separated from the source metal layer and the upper epitaxial layer, and the contact hole structure is connected to the source metal layer upward.
[0017] In order to solve the technical problem in the background technology, the second aspect of the present application provides a method for manufacturing a full super junction power semiconductor device, the method for manufacturing a full super junction power semiconductor device comprising the following steps:
[0018] providing a substrate layer;
[0019] forming an N-type doped bottom epitaxial layer on the substrate layer;
[0020] A plurality of first P-type doping regions spaced apart from each other along a first direction are formed in the N-type doped bottom epitaxial layer, and a first N-type doping region is formed between two adjacent first P-type doping regions;
[0021] forming an N-type doped upper epitaxial layer on the bottom epitaxial layer;
[0022] A plurality of second P-type doping regions spaced apart from each other along a second direction are formed in the N-type doped upper epitaxial layer, and a second N-type doping region is formed between two adjacent second P-type doping regions; the first direction is perpendicular to the second direction;
[0023] The lower surface of the second P-type doping region contacts the upper surfaces of the alternately arranged first P-type doping regions and the first N-type doping regions in sequence in the first direction; the lower surface of the second N-type doping region contacts the upper surfaces of the alternately arranged first P-type doping regions and the first N-type doping regions in sequence in the first direction.
[0024] Optionally, the step of forming a plurality of first P-type doping regions spaced apart from each other along a first direction in the N-type doped bottom epitaxial layer, and forming a first N-type doping region spaced apart between two adjacent first P-type doping regions, comprises:
[0025] A plurality of first deep trenches spaced apart from each other along a first direction are formed in the N-type doped bottom epitaxial layer, wherein the length of the first deep trenches extends along the second direction;
[0026] Filling the first deep trench with a first P-type doping region through an epitaxial filling process, and forming a first N-type doping region between two adjacent first P-type doping regions;
[0027] The upper surface of the bottom epitaxial layer is planarized by chemical mechanical polishing.
[0028] Optionally, the step of forming a plurality of second P-type doping regions spaced apart from each other along a second direction in the N-type doped upper epitaxial layer, and forming a second N-type doping region spaced apart between two adjacent second P-type doping regions, comprises:
[0029] A plurality of second deep trenches spaced apart from each other along a second direction are formed in the N-type doped upper epitaxial layer, wherein the length of the second deep trenches extends along the first direction;
[0030] Filling the second deep trench with a second P-type doping region through an epitaxial filling process, and forming a second N-type doping region between two adjacent second P-type doping regions;
[0031] The upper surface of the epitaxial layer is planarized by chemical mechanical polishing.
[0032] Optionally, the method further comprises the following steps:
[0033] Forming P-type body regions and trench gates alternately arranged along a second direction on the upper portion of the upper epitaxial layer;
[0034] The trench gate contacts the second N-type doping region downward;
[0035] The P-type body region contacts downwardly with the second P-type doping region and a portion of the second N-type doping region on both sides of the second P-type doping region;
[0036] A contact hole structure is formed on the P-type body region, and N-type heavily doped regions are formed on both sides of the contact hole structure;
[0037] The upper epitaxial layer is covered with a source metal layer, an oxide layer is separated from the source metal layer and the upper epitaxial layer, and the contact hole structure is connected to the source metal layer upward.
[0038] Optionally, a width of the second P-type doping region in the second direction is smaller than a width of the first P-type doping region in the first direction.
[0039] Optionally, a density of the second P-type doping region in the second direction is greater than a density of the first P-type doping region in the first direction.
[0040] Optionally, a concentration of N-type impurities in the second N-type doping region is greater than a concentration of N-type impurities in the first N-type doping region.
[0041] The technical solution of the present application includes at least the following advantages: In the present application, the second P-type doping region and the second N-type doping region in the upper epitaxial layer are respectively orthogonal to the first P-type doping region and the first N-type doping region in the underlying epitaxial layer, so that the widths of the second P-type doping region and the second N-type doping region in the upper epitaxial layer in the second direction are not affected by the widths of the first P-type doping region and the first N-type doping region in the first direction, so that the widths of the second P-type doping region and the second N-type doping region in the upper epitaxial layer can be smaller, that is, a structure with a smaller critical dimension is adopted, which can improve the density of the device super junction on the one hand, and allow the second N-type doping region to increase the doping concentration on the other hand, thereby reducing the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0043] Figure 1 A schematic cross-sectional structure diagram of a full super junction power semiconductor device provided by an embodiment of the present application is shown;
[0044] Figure 2 A flow chart of a method for manufacturing a full super junction power semiconductor device provided by an embodiment of the present application is shown;
[0045] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0046] Figure 4A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0047] Figure 5 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S5 is completed. DETAILED DESCRIPTION
[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0049] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0050] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0051] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0052] Figure 1 FIG. 1 shows a schematic cross-sectional structure diagram of a full super junction power semiconductor device provided by an embodiment of the present application. Figure 1 As can be seen in FIG. 1 , the full superjunction power semiconductor device includes a substrate layer 100, a bottom epitaxial layer 200 and an upper epitaxial layer 300 stacked sequentially from bottom to top. Exemplarily, the thickness h1 of the bottom epitaxial layer 200 is 60 um, and the thickness h2 of the upper epitaxial layer 300 is 20 um.
[0053] The bottom epitaxial layer 200 is formed on the substrate layer 100 , and a first P-type doping region 210 and a first N-type doping region 220 alternately arranged along a first direction X are formed in the bottom epitaxial layer 200 .
[0054] An upper epitaxial layer 300 is formed on the underlying epitaxial layer 200, and a second P-type doping region 310 and a second N-type doping region 320 are formed in the upper epitaxial layer 300 and are arranged alternately along a second direction Y; the first direction X and the second direction Y are perpendicular; the lower surface of the second P-type doping region 310 is in contact with the upper surface of the alternately arranged first P-type doping region 210 and the first N-type doping region 220 in the first direction X; the lower surface of the second N-type doping region 320 is in contact with the upper surface of the alternately arranged first P-type doping region 210 and the first N-type doping region 220 in the first direction X.
[0055] In the present application, the second P-type doping region and the second N-type doping region in the upper epitaxial layer are respectively orthogonal to the first P-type doping region and the first N-type doping region in the underlying epitaxial layer, so that the widths of the second P-type doping region and the second N-type doping region in the upper epitaxial layer in the second direction are not affected by the widths of the first P-type doping region and the first N-type doping region in the first direction, so that the widths of the second P-type doping region and the second N-type doping region in the upper epitaxial layer can be smaller, that is, a structure with a smaller critical dimension is adopted, which can improve the density of the device super junction on the one hand, and allow the second N-type doping region to increase the doping concentration on the other hand, thereby reducing the on-resistance of the device.
[0056] Exemplarily, the width of the second P-type doping region 310 in the second direction Y is smaller than the width of the first P-type doping region 210 in the first direction X. The width of the first P-type doping region 210 in the bottom epitaxial layer 200 in the present application may be inconsistent with the width of the second P-type doping region 310 in the upper epitaxial layer 300, that is, the second P-type doping region 310 may have a smaller width to increase the P-type doping region density of the device, that is, to increase the density of the super junction and reduce the on-resistance.
[0057] Exemplarily, the density of the second P-type doping regions 310 in the second direction Y is greater than the density of the first P-type doping regions 210 in the first direction X.
[0058] Exemplarily, the N-type impurity concentration of the second N-type doping region 320 is greater than the N-type impurity concentration of the first N-type doping region 220. Optionally, the N-type impurity concentration of the second N-type doping region 320 is 6E15 atoms / cm 3 To 1E16atoms / cm 3 The concentration of N-type impurities in the first N-type doping region 220 is 3E15 atoms / cm 3To 6E15 atoms / cm 3 .
[0059] Continue to refer to Figure 1 The upper portion of the upper epitaxial layer 300 forms a P-type body region 330 and a trench gate 340 that are alternately arranged along the second direction Y.
[0060] The trench gate 340 contacts the second N-type doping region 320 downward.
[0061] The P-type body region 330 contacts downwardly the second P-type doping region 310 and portions of the second N-type doping regions 320 on both sides of the second P-type doping region 310 .
[0062] A contact hole structure 350 is formed on the P-type body region 330 , and N-type heavily doped regions 360 are formed on both sides of the contact hole structure 350 .
[0063] The upper epitaxial layer 300 is covered with a source metal layer 400 , an oxide layer 500 is separated from the source metal layer 400 and the upper epitaxial layer 300 , and the contact hole structure 350 is in contact with and connected to the source metal layer 400 upwards.
[0064] Figure 2 A flow chart of a method for manufacturing a full super junction power semiconductor device according to an embodiment of the present application is shown. Figure 2 It can be seen that the manufacturing method of the full super junction power semiconductor device includes the following steps:
[0065] Step S1: providing a substrate layer.
[0066] Step S2: forming an N-type doped bottom epitaxial layer on the substrate layer.
[0067] Figure 3 The schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown. Figure 3 It can be seen from the figure that an N-type doped bottom epitaxial layer is formed on the substrate layer.
[0068] Step S3: forming a plurality of first P-type doping regions spaced apart from each other along a first direction in the N-type doped bottom epitaxial layer, and forming a first N-type doping region between two adjacent first P-type doping regions.
[0069] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S3 is completed, from Figure 4 In the bottom epitaxial layer, a first P-type doping region and a first N-type doping region are formed which are alternately arranged along a first direction.
[0070] Exemplarily, step S3 can be implemented by following steps S31 to S33:
[0071] Step S31: forming a plurality of first deep trenches spaced apart from each other along a first direction in the N-type doped bottom epitaxial layer, wherein the length of the first deep trenches extends along the second direction.
[0072] Step S32: filling the first deep trench with a first P-type doping region through an epitaxial filling process, and forming a first N-type doping region between two adjacent first P-type doping regions.
[0073] Step S33: performing chemical mechanical polishing to planarize the upper surface of the bottom epitaxial layer.
[0074] Step S4: forming an N-type doped upper epitaxial layer on the bottom epitaxial layer.
[0075] Step S5: forming a plurality of second P-type doping regions spaced apart from each other along a second direction in the N-type doped upper epitaxial layer, and forming a second N-type doping region between two adjacent second P-type doping regions; the first direction is perpendicular to the second direction.
[0076] The lower surface of the second P-type doping region contacts the upper surfaces of the alternately arranged first P-type doping regions and the first N-type doping regions in sequence in the first direction; the lower surface of the second N-type doping region contacts the upper surfaces of the alternately arranged first P-type doping regions and the first N-type doping regions in sequence in the first direction.
[0077] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed, from Figure 5 It can be seen that second P-type doping regions and second N-type doping regions arranged alternately along the second direction are formed in the upper epitaxial layer; the first direction and the second direction are perpendicular; the lower surface of the second P-type doping region is in contact with the upper surface of the first P-type doping region and the first N-type doping region arranged alternately in the first direction in sequence; the lower surface of the second N-type doping region is in contact with the upper surface of the first P-type doping region and the first N-type doping region arranged alternately in the first direction in sequence.
[0078] Exemplarily, step S5 can be implemented by following steps S51 to S53:
[0079] Step S51: forming a plurality of second deep trenches spaced apart from each other along a second direction in the N-type doped upper epitaxial layer, wherein the length of the second deep trenches extends along the first direction.
[0080] Step S52: filling the second deep trench with a second P-type doping region through an epitaxial filling process, and forming a second N-type doping region between two adjacent second P-type doping regions.
[0081] Step S53: performing chemical mechanical polishing to planarize the upper surface of the epitaxial layer.
[0082] After completing step S5, the following step S6 is also performed:
[0083] Step S6: forming a P-type body region and a trench gate alternately arranged along a second direction on the upper part of the upper epitaxial layer. The trench gate contacts the second N-type doped region downward; the P-type body region contacts the second P-type doped region and part of the second N-type doped region on both sides of the second P-type doped region downward; a contact hole structure is formed on the P-type body region, and N-type heavily doped regions are formed on both sides of the contact hole structure; the upper epitaxial layer is covered with a source metal layer, the source metal layer and the upper epitaxial layer are separated by an oxide layer, and the contact hole structure contacts and connects with the source metal layer upward.
[0084] In the present application, the second P-type doping region and the second N-type doping region in the upper epitaxial layer are respectively orthogonal to the first P-type doping region and the first N-type doping region in the underlying epitaxial layer, so that the widths of the second P-type doping region and the second N-type doping region in the upper epitaxial layer in the second direction are not affected by the widths of the first P-type doping region and the first N-type doping region in the first direction, so that the widths of the second P-type doping region and the second N-type doping region in the upper epitaxial layer can be smaller, that is, a structure with a smaller critical dimension is adopted, which can improve the density of the device super junction on the one hand, and allow the second N-type doping region to increase the doping concentration on the other hand, thereby reducing the on-resistance of the device.
[0085] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A full super junction power semiconductor device, characterized in that: The full super junction power semiconductor device comprises: substrate layer; A bottom epitaxial layer, wherein the bottom epitaxial layer is formed on the substrate layer, and a first P-type doping region and a first N-type doping region are formed in the bottom epitaxial layer and are alternately arranged along a first direction; An upper epitaxial layer, wherein the upper epitaxial layer is formed on the bottom epitaxial layer, and wherein a second P-type doping region and a second N-type doping region are formed in the upper epitaxial layer and are alternately arranged along a second direction; wherein the first direction and the second direction are perpendicular; wherein the lower surface of the second P-type doping region sequentially contacts with the upper surface of the alternately arranged first P-type doping region and the first N-type doping region in the first direction; and wherein the lower surface of the second N-type doping region sequentially contacts with the upper surface of the alternately arranged first P-type doping region and the first N-type doping region in the first direction.
2. The full super junction power semiconductor device according to claim 1, characterized in that: A width of the second P-type doping region in the second direction is smaller than a width of the first P-type doping region in the first direction.
3. The full super junction power semiconductor device according to claim 1, characterized in that: The density of the second P-type doping region in the second direction is greater than the density of the first P-type doping region in the first direction.
4. The full super junction power semiconductor device according to claim 1, characterized in that: The N-type impurity concentration of the second N-type doping region is greater than the N-type impurity concentration of the first N-type doping region.
5. The full super junction power semiconductor device according to claim 1, characterized in that: The upper portion of the upper epitaxial layer forms a P-type body region and a trench gate alternately arranged along a second direction; The trench gate contacts the second N-type doping region downward; The P-type body region contacts downwardly with the second P-type doping region and a portion of the second N-type doping region on both sides of the second P-type doping region; A contact hole structure is formed on the P-type body region, and N-type heavily doped regions are formed on both sides of the contact hole structure; The upper epitaxial layer is covered with a source metal layer, an oxide layer is separated from the source metal layer and the upper epitaxial layer, and the contact hole structure is connected to the source metal layer upward.
6. A method for manufacturing a full super junction power semiconductor device, characterized in that: The method for manufacturing the full super junction power semiconductor device comprises the following steps: providing a substrate layer; forming an N-type doped bottom epitaxial layer on the substrate layer; A plurality of first P-type doping regions spaced apart from each other along a first direction are formed in the N-type doped bottom epitaxial layer, and a first N-type doping region is formed between two adjacent first P-type doping regions; forming an N-type doped upper epitaxial layer on the bottom epitaxial layer; A plurality of second P-type doping regions spaced from each other along a second direction are formed in the N-type doped upper epitaxial layer, and a second N-type doping region is formed between two adjacent second P-type doping regions; the first direction is perpendicular to the second direction; The lower surface of the second P-type doping region contacts the upper surfaces of the alternately arranged first P-type doping regions and the first N-type doping regions in sequence in the first direction; the lower surface of the second N-type doping region contacts the upper surfaces of the alternately arranged first P-type doping regions and the first N-type doping regions in sequence in the first direction.
7. The method for manufacturing a full super junction power semiconductor device according to claim 6, characterized in that: The step of forming a plurality of first P-type doping regions spaced apart from each other along a first direction in the N-type doped bottom epitaxial layer, and forming a first N-type doping region spaced apart between two adjacent first P-type doping regions, comprises: A plurality of first deep trenches spaced apart from each other along a first direction are formed in the N-type doped bottom epitaxial layer, wherein the length of the first deep trenches extends along the second direction; Filling the first deep trench with a first P-type doping region through an epitaxial filling process, and forming a first N-type doping region between two adjacent first P-type doping regions; The upper surface of the bottom epitaxial layer is planarized by chemical mechanical polishing.
8. The method for manufacturing a full super junction power semiconductor device according to claim 6, characterized in that: The step of forming a plurality of second P-type doping regions spaced apart from each other along a second direction on the N-type doped upper epitaxial layer, and forming a second N-type doping region spaced apart between two adjacent second P-type doping regions, comprises: A plurality of second deep trenches spaced apart from each other along a second direction are formed in the N-type doped upper epitaxial layer, wherein the length of the second deep trenches extends along the first direction; Filling the second deep trench with a second P-type doping region through an epitaxial filling process, and forming a second N-type doping region between two adjacent second P-type doping regions; The upper surface of the epitaxial layer is planarized by chemical mechanical polishing.
9. The method for manufacturing a full super junction power semiconductor device according to claim 6, characterized in that: The following steps are also included: Forming P-type body regions and trench gates alternately arranged along a second direction on the upper portion of the upper epitaxial layer; The trench gate contacts the second N-type doping region downward; The P-type body region contacts downwardly with the second P-type doping region and a portion of the second N-type doping region on both sides of the second P-type doping region; A contact hole structure is formed on the P-type body region, and N-type heavily doped regions are formed on both sides of the contact hole structure; The upper epitaxial layer is covered with a source metal layer, an oxide layer is separated from the source metal layer and the upper epitaxial layer, and the contact hole structure is connected to the source metal layer upward.
10. The method for manufacturing a full super junction power semiconductor device according to claim 6, characterized in that: A width of the second P-type doping region in the second direction is smaller than a width of the first P-type doping region in the first direction.
11. The method for manufacturing a full super junction power semiconductor device according to claim 6, characterized in that: The density of the second P-type doping region in the second direction is greater than the density of the first P-type doping region in the first direction.
12. The method for manufacturing a full super junction power semiconductor device according to claim 6, characterized in that: The N-type impurity concentration of the second N-type doping region is greater than the N-type impurity concentration of the first N-type doping region.