Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, which adjusts the step of opening the second hard mask layer of the NMOS region after forming the germanium-silicon source-drain of the PMOS region in the prior art to before the photolithography process for forming the germanium-silicon source-drain of the PMOS region, and removes the second hard mask layer on the top of the gate of the NMOS region and the PMOS region by adopting the chemical mechanical polishing (CMP) method, so that the photomask and the wet etching process required when the second hard mask layer of the NMOS region is opened in the prior art can be omitted, the process flow is simplified, the cost of the photomask is saved, the problem of the recessed substrate surface of the NMOS region caused by the wet etching process is avoided, and the device performance is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing, and particularly relates to a manufacturing method of semiconductor device. BACKGROUND

[0002] In the technical field of semiconductor, with the rapid development of nanometer processing technology, the process node of transistor has been promoted to 28 nanometer level or below, and SiGe (called germanium silicon or germanium silicon) is introduced into the source-drain of PMOS transistor due to its excellent performance, so as to improve the mobility of hole carriers of PMOS transistor.

[0003] However, the existing CMOS process of introducing SiGe source-drain into PMOS transistor has the problems of high mask cost and easy to cause substrate surface damage or surface depression. SUMMARY

[0004] The present application aims to provide a manufacturing method of semiconductor device, which can introduce SiGe source-drain into PMOS transistor, save masks, and improve the problem of substrate surface damage or surface depression.

[0005] To achieve the above-mentioned purpose, the present application provides a manufacturing method of semiconductor device, which comprises the following steps:

[0006] A substrate with PMOS region and NMOS region is provided, and an oxide layer, a gate layer and a first hard mask layer are formed on the surface of the substrate, and the first hard mask layer and the gate layer are etched to form a gate on the PMOS region and the NMOS region;

[0007] A gate sidewall is formed on the sidewall of each gate, and a contact etching stop layer and a second hard mask layer are deposited on the oxide layer, the gate sidewall and the first hard mask layer in turn in a conformal manner;

[0008] A sacrificial dielectric layer is deposited on the second hard mask layer, and the sacrificial dielectric layer is subjected to chemical mechanical polishing to remove the second hard mask layer on the top of the first hard mask layer;

[0009] The first wet process is used to remove the sacrificial dielectric layer;

[0010] A patterned photoresist layer is formed to protect the NMOS region, and the second hard mask layer, the contact etching stop layer and the substrate on the PMOS region are etched with the patterned photoresist layer as a mask to form a source-drain trench in the substrate on both sides of the gate of the PMOS region;

[0011] The patterned photoresist layer is removed, and a germanium silicon epitaxial growth process is used to form a germanium silicon source-drain in the source-drain trench;

[0012] The first hard mask layer and the second hard mask layer are removed by a second wet process.

[0013] Optionally, the contact etch stop layer and the sacrificial dielectric layer are both oxides, and the etchant of the first wet process includes hydrofluoric acid.

[0014] Optionally, the contact etch stop layer on top of the first hard mask layer is removed simultaneously by the chemical mechanical polishing or the first wet process.

[0015] Optionally, the etchant of the second wet process includes phosphoric acid.

[0016] Optionally, the first hard mask layer and the second hard mask layer are made of the same material.

[0017] Optionally, the contact etch stop layer and the second hard mask layer are both formed by an atomic layer deposition process.

[0018] Optionally, the manufacturing method further comprises, before removing the first hard mask layer and the second hard mask layer, forming a protective layer on top of the germanium-silicon source-drain; and / or, after removing the first hard mask layer and the second hard mask layer, depositing a metal and performing a rapid thermal process to form a metal silicide on top of the germanium-silicon source-drain and the gate.

[0019] Optionally, the manufacturing method further comprises, after removing the first hard mask layer and the second hard mask layer and before depositing the metal, or after forming the gate and before depositing the contact etch stop layer, performing N-type ion implantation to the substrate on both sides of the gate of the NMOS region to form an N-type ion-doped source-drain region.

[0020] Optionally, before depositing the metal, the oxide layer on the N-type ion-doped source-drain region is removed by a wet process to expose the surface of the N-type ion-doped source-drain region.

[0021] Optionally, during the process of forming the germanium-silicon source-drain in the source-drain trench by a germanium-silicon epitaxial growth process, P-type ions are doped in situ into the germanium-silicon source-drain to form a P-type ion-doped source-drain region; or, after removing the first hard mask layer and the second hard mask layer, the NMOS region is masked, and P-type ion implantation is performed to the germanium-silicon source-drain on both sides of the gate of the PMOS region to form a P-type ion-doped source-drain region.

[0022] Compared with the prior art, the technical scheme of the present application removes the second hard mask layer on the top of the gate by deposition and chemical mechanical polishing (CMP) of the sacrificial medium layer before forming the patterned photoresist layer to mask the NMOS region and defining the area of the PMOS region where the source-drain trench is to be formed. On the one hand, when the first wet process is used to remove the sacrificial medium layer, the second hard mask layer, the contact etching stop layer and the oxide layer are still covered on the substrate surface outside the gate of the PMOS region and the NMOS region, so the etching liquid of the first wet process will not cause damage to the substrate surface or even produce recess and other problems, thereby improving the device performance. On the other hand, the second hard mask layer on the top of the gate of the PMOS region and the NMOS region is opened by chemical mechanical polishing before the epitaxial growth of the germanium-silicon source-drain, so a mask used to remove the second hard mask layer on the top of the gate of the NMOS region alone can be saved, thereby saving the cost. BRIEF DESCRIPTION OF DRAWINGS

[0023] Those skilled in the art will understand that the provided drawings are for the purpose of better illustrating the present application and do not constitute any limitation on the scope of the present application. Among them:

[0024] Figure 1 is a device cross-sectional structure schematic diagram in the prior semiconductor device manufacturing method.

[0025] Figure 2 is a flow chart of the semiconductor device manufacturing method of the specific embodiment of the present application.

[0026] Figure 3 is a device cross-sectional structure schematic diagram in the semiconductor device manufacturing method of the specific embodiment of the present application. DETAILED DESCRIPTION

[0027] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon reading this disclosure that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application. It should be understood that the present application can be practiced with departure from these specific details, and that specific details can be implemented only in some embodiments. There are many

[0028] The technical solutions of the present application are further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0029] The process of introducing SiGe source and drain to the PMOS transistor in the existing CMOS process includes the following steps:

[0030] Please refer to (A) in Figure 1 After the oxide layer 102, the gate 103, the first hard mask layer 104 and the double-layer gate side wall (not labeled) of the PMOS region and the NMOS region are formed, the contact etching stop layer 105, the second hard mask layer 106 and the bottom anti-reflective layer 107 are deposited, and the photoresist layer 108 is coated.

[0031] Please refer to (A) in Figure 1(B) of FIG. 6, the photoresist layer 108 is exposed to light through a corresponding mask, and the photoresist layer 108 in the PMOS region is removed, while the NMOS region is masked by the remaining photoresist layer 108. The photoresist layer 108 after exposure is used as a mask to etch the bottom anti-reflective layer 107, and then to etch the second hard mask layer 106 and the contact etching stop layer 105 in the PMOS region to expose the substrate 100 region for manufacturing the SiGe source and drain.

[0032] Referring to Figure 1 (C) of FIG. 6, SiGe is epitaxially grown in the source and drain trench 109 to form the SiGe source and drain 110.

[0033] Referring to Figure 1 (D) of FIG. 6, in order to remove the first hard mask layer 104 on the top of the gate 103 in both the NMOS and PMOS regions to expose the gate 103 for growing metal silicide, after the SiGe source and drain 110 in the PMOS region is formed, the second hard mask layer 106 on the top of the gate 103 in the NMOS region needs to be further removed. The process generally includes depositing a bottom anti-reflective layer 111, coating a photoresist layer 112, and exposing the photoresist layer 112 to light through another mask to remove the photoresist layer 112 in the NMOS region, while the PMOS region is masked by the remaining photoresist layer 112. The photoresist layer 112 after exposure is used as a mask to etch the bottom anti-reflective layer 111 in the NMOS region, and then to dry-etch the second hard mask layer 106 on the top of the gate 103 in the NMOS region and on the substrate 100. At this time, a part of the second hard mask layer 106 remains on the sidewall of the gate sidewall in the NMOS region.

[0034] Referring to Figure 1 (E) of FIG. 6, the photoresist layer 112 and the bottom anti-reflective layer 111 are removed, the contact etching stop layer 105 on the top of the gate 103 is opened by hydrofluoric acid, and then the first hard mask layer 104 on the top of the gate 103 and the second hard mask layer 106 on the sidewall of the gate sidewall are removed by phosphoric acid.

[0035] The above process needs to use two masks, and the cost is high. Before the first hard mask layer 104 on the top of the gate 103 and the second hard mask layer 106 on the sidewall of the gate sidewall are removed by phosphoric acid, hydrofluoric acid is needed to open the contact etching stop layer 105 on the top of the gate. Because the gap between the gate sidewall and the line width of the top of the gate are different, the thickness of the contact etching stop layer 105 on the substrate and the top of the gate may be different. In order to completely remove the contact etching stop layer 105 on the top of the gate, an excessive amount of hydrofluoric acid must be used to etch the contact etching stop layer 105 on the top of the gate (i.e., over-etching). This process easily consumes the oxide layer 102 on the exposed substrate surface of the NMOS region, and even causes the substrate surface to be exposed, so that the hydrofluoric acid directly contacts the substrate to cause damage to the substrate surface or form a substrate surface depression 113 (the depth can reach ) When the first hard mask layer 104 and the second hard mask layer 106 are removed by phosphoric acid, the oxide layer 102 on the exposed substrate surface of the NMOS region is further consumed, and the damage to the substrate surface or the formation of the substrate surface depression 113 is aggravated, which affects the distance between the source and the drain of the NMOS region and causes loss of the previously injected ions, thereby affecting the performance of the CMOS device.

[0036] In addition, even if the thickness of the contact etching stop layer 105 on the substrate and the top of the gate is the same, the oxide layer 102 on the exposed substrate surface of the NMOS region can still be consumed to expose the substrate surface after the above-mentioned multiple wet etching (i.e., acid treatment), so that the acid directly contacts the substrate to cause damage to the substrate surface or form a substrate surface depression 113.

[0037] If the pattern of the other mask is changed, the bottom anti-reflective layer 111 and the second hard mask layer 106 in the NMOS region can be etched, and the active region of the NMOS region can be reserved. However, when the second hard mask layer 106 on the top of the gate 103 of the NMOS region is removed by dry etching, a serious loading effect is caused, and the modified mask pattern has strict requirements, so it is difficult to be widely implemented.

[0038] Based on this, please refer to Figure 2 , an embodiment of the present application provides a manufacturing method of a semiconductor device, which comprises the following steps:

[0039] S1, providing a substrate with a PMOS region and an NMOS region, forming an oxide layer, a gate layer and a first hard mask layer on the surface of the substrate, and etching the first hard mask layer and the gate layer to form a gate on the PMOS region and the NMOS region;

[0040] S2, forming a gate sidewall on sidewalls of each of the gates, and conformally depositing a contact etching stop layer and a second hard mask layer on the oxide layer, the gate sidewall and the first hard mask layer in sequence;

[0041] S3, depositing a sacrificial dielectric layer on the second hard mask layer, and performing chemical mechanical polishing on the sacrificial dielectric layer to remove the second hard mask layer on top of the first hard mask layer;

[0042] S4, removing the sacrificial dielectric layer by a first wet process;

[0043] S5, forming a patterned photoresist layer to protect the NMOS region, and etching the second hard mask layer, the contact etching stop layer and the substrate on the PMOS region to form source-drain trenches in the substrate on both sides of the gate of the PMOS region by taking the patterned photoresist layer as a mask;

[0044] S6, removing the patterned photoresist layer and forming a germanium-silicon source-drain in the source-drain trenches by a germanium-silicon epitaxial growth process;

[0045] S7, removing the first hard mask layer and the second hard mask layer by a second wet process.

[0046] In the embodiment, the process of providing the substrate 200 and forming the gate in step S1 includes:

[0047] First, refer to (A) in Figure 3 , a substrate 200 is provided by reasonably selecting a substrate material according to the device application requirement, for example, single-crystal silicon (Si), silicon-on-insulator (SOI), single-crystal germanium (Ge), germanium-on-insulator (GeOI), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP) and the like. Further, a shallow trench isolation structure 201 is formed in the substrate 200 by a shallow trench isolation process (including shallow trench lithography, etching and filling), and the material of the shallow trench isolation structure 201 can be conventional insulating materials such as oxide, nitride and oxynitride. The shallow trench isolation structure 201 is used to define a PMOS region and an NMOS region in the substrate 200, wherein Figure 3 the left region in corresponds to the PMOS region, and the right region corresponds to the NMOS region. Figure 3 Although only one NMOS region and one PMOS region are shown in , actually, according to the layout design requirement, multiple PMOS regions and multiple NMOS regions can be formed in the substrate. An N-type well region (not shown) can also be formed in the substrate 200 of the PMOS region, and a P-type well region (not shown) can also be formed in the substrate 200 of the NMOS region.

[0048] Next, refer to Figure 3In step (A), an oxide layer 202 is sequentially deposited on the entire surface of the substrate 200, including the shallow trench isolation structure 201, followed by the deposition of a gate layer and a first hard mask layer 204. The oxide layer 202 can be formed by thermal oxidation or vapor deposition, and can be silicon dioxide, silicon oxynitride, silicon nitride, or a high-k material with a dielectric constant K higher than silicon dioxide (e.g., hafnium-based oxides), or combinations thereof. The gate layer can be made of polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous germanium, or combinations thereof. The first hard mask layer 204 can be silicon nitride or silicon oxynitride, or combinations thereof. The oxide layer 202 can be a gate oxide layer of uniform thickness, or it can consist of a gate oxide layer of uniform thickness and a natural oxide layer located between the bottom of the gate oxide layer and the substrate 200.

[0049] Then, please refer to Figure 3 In step (A), photolithography is performed using a photomask (not shown) for fabricating the gate. This photolithography process may include depositing an amorphous carbon layer (not shown) and a bottom anti-reflective layer (BARC) (not shown), coating photoresist (PR) (not shown), and performing exposure, development, etching of the bottom anti-reflective layer (BARC) and the amorphous carbon layer, etc. Using the remaining photoresist film after photolithography as a mask, a first hard mask layer 204 is further etched. Then, after removing the remaining photoresist film after photolithography, the gate layer is etched using the remaining first hard mask layer 204 as a mask to form gates 203 on both the PMOS and NMOS regions of the substrate. At this time, the remaining first hard mask layer 204 remains on top of the gates 203. In this embodiment, the gates 203 on the PMOS and NMOS regions are formed simultaneously, but in other embodiments, the gates 203 on the PMOS and NMOS regions may be formed separately and sequentially. The oxide layer sandwiched between the bottom of the gate 203 and the substrate 200 is the gate oxide layer.

[0050] In this embodiment, the process of forming the gate sidewall, the contact etch stop layer 205, and the second hard mask layer 206 in step S2 includes:

[0051] First, please refer to Figure 3 In step (A), any suitable deposition process, such as atomic layer deposition or chemical vapor deposition, can be used to conformally deposit sidewall material on the oxide layer 202, the sidewalls of each of the gates 203, and the top and sidewalls of the first hard mask layer 204. Gate sidewalls are then formed on the sidewalls of each gate 203 through sidewall etching processes. The gate sidewalls can be a single-layer film structure or a multi-layer film structure formed from different sidewall materials. For example, the gate sidewalls may include an inner sidewall 203a and an outer sidewall 203b formed from two different sidewall materials. The inner sidewall 203a can be a material such as silicon oxide, and the outer sidewall 203b can be a material such as silicon nitride.

[0052] Next, please refer to Figure 3 In step (A), any suitable deposition process, such as atomic layer deposition, can be used to conformally deposit a contact etch stop layer 205 and a second hard mask layer 206 on the sidewalls of the oxide layer 202 and the gate sidewall, as well as on the top and sidewalls of the first hard mask layer 204. The material of the contact etch stop layer 205 differs from the materials of the second hard mask layer 206 and the outer surface of the gate sidewall. The contact etch stop layer 205 serves two purposes: firstly, it acts as an etch stop layer during subsequent etching or removal of the first hard mask layer 204 and the second hard mask layer 206; secondly, it acts as a barrier layer, protecting the gate 203 and other film layers from subsequent etching losses. As an example, the contact etch stop layer 205 is silicon oxide, and the second hard mask layer 206 is silicon nitride.

[0053] Optionally, after forming the gate 203 and before depositing the contact etch stop layer 205, or after forming the gate sidewall and before depositing the contact etch stop layer 205, N-type ions such as phosphorus P, arsenic As, and antimony Sb can be used to ion implant the substrates on both sides of the gate of the PMOS and NMOS regions simultaneously without the aid of an additional mask layer to mask the PMOS region. Alternatively, a corresponding patterned mask layer can be formed first to mask the PMOS region and expose the NMOS region, and N-type ions can be used to ion implant the substrates on both sides of the gate of the NMOS region to form N-type ion-doped source / drain regions (not shown) of the NMOS region.

[0054] In other embodiments of the present invention, a patterned mask layer may be formed to mask the PMOS region and expose the NMOS region after step S7 is performed, and N-type ions may be used to implant ions into the substrate on both sides of the gate of the NMOS region to form N-type ion-doped source and drain regions (not shown) of the NMOS region.

[0055] In step S3 of this embodiment, please refer to Figure 3 In step (A), a process such as chemical vapor deposition can be used to deposit materials such as oxides to form a sacrificial dielectric layer 207 on the second hard mask layer 206. The deposited sacrificial dielectric layer 207 can fill the gaps between the gate sidewalls. Then, please refer to... Figure 3 In step (B), the sacrificial dielectric layer is chemically mechanically polished (CMP) and the polishing terminates on the surface of the first hard mask layer 204 above the top of the gate 203 (this CMP process can allow for either non-negligible or negligible high wear on the first hard mask layer 204), thereby removing the second hard mask layer 206 and the contact etch stop layer 205 on top of the first hard mask layer 204.

[0056] In other embodiments of the present application, in step S3, the CMP process can also stop on the surface of the contact etching stop layer 205 above the gate 203, which can be removed together with the sacrificial dielectric layer 207 in the subsequent wet etching process to expose the top surface of the first hard mask layer 204. Thus, before the SiGe source and drain needed for the PMOS region is generated, one wet etching process to remove the contact etching stop layer 205 on the top of the gate can be reduced, so that the consumption of the oxide layer 202 on the substrate in the wet etching process in the prior art can be avoided, and the unnecessary consumption of the substrate silicon before the metal silicide process can be avoided.

[0057] In this step S3, the removal of the second hard mask layer 206 and the contact etching stop layer 205 on the top of the gate 203 can reduce the load effect of the NMOS region and the PMOS region in the subsequent process, and avoid the problem of surface depression of the substrate of the NMOS region in the corresponding subsequent process.

[0058] In step S4 of the present embodiment, please refer to (C) in Figure 3 According to the material properties of the sacrificial dielectric layer 207, any suitable first wet process can be selected to remove the sacrificial dielectric layer 207. For example, if the sacrificial dielectric layer 207 is an oxide, a hydrofluoric acid etching solution can be used for wet etching to remove the sacrificial dielectric layer 207. Since the etching selectivity ratio of the sacrificial dielectric layer 207 and the contact etching stop layer 205 is not high, the contact etching stop layer 205 on the top of the gate 203 can also be removed at the same time. Since the second mask layer 206 and the contact etching stop layer 205 are still retained on the oxide layer 202 outside the gate 203 of the PMOS region and the NMOS region in this process, the etching solution will not penetrate the second mask layer 206, the contact etching stop layer 205 and the oxide layer 202 to consume the silicon in the substrate 200.

[0059] In step S5 of the present embodiment, please refer to Figure 3(D) of FIG. 8, first, at least one of amorphous carbon, organic material, anti-reflective material is deposited to form a filling layer 208 filling the gap between the gate sidewall and having a flat top surface, and further coating photoresist on the top surface of the filling layer 208, then photoresist is photoetched (including exposure, development and other processes) using a corresponding mask to form a patterned photoresist layer 209, which masks the surface of the filling layer 208 in the NMOS region and exposes the surface of the filling layer 208 in the PMOS region; then, using the patterned photoresist layer 209 as a mask, a corresponding dry etching process is used to etch the filling layer 208, the second hard mask layer 206, the contact etching stop layer 205 and the oxide layer 202 in sequence, thereby exposing the substrate surface in the region on both sides of the gate 203 in the PMOS region, and continuing to etch the exposed substrate in the PMOS region to form a source-drain trench 210 in the substrate 200 on both sides of the gate 203 in the PMOS region.

[0060] It should be understood that since the dry etching process is anisotropic, the vertical etching rate is greater than the lateral etching rate, so after the source-drain trench 210 is formed, there is still a redundant sidewall formed by the second hard mask layer 206 and the contact etching stop layer 205 on the outer sidewall of the gate sidewall, which needs to be removed subsequently.

[0061] In addition, Figure 3 The patterned photoresist layer 209 shown in (D) of FIG. 8 exposes the global surface of the PMOS region, but the technical solution of the present application is not limited thereto, in other embodiments of the present application, under the condition that the mask precision and photoetching precision allow, the patterned photoresist layer 209 can only expose the surface of the region to be formed with the source-drain trench 210 in the PMOS region, after etching the filling layer 208, the second hard mask layer 206, the contact etching stop layer 205 and the oxide layer 202 using the patterned photoresist layer 209 as a mask, the substrate surface to be formed with the source-drain trench 210 in the PMOS region is exposed, and the global surface of the NMOS region and the surface of other regions of the PMOS region except the source-drain trench 210 are all protected by the patterned photoresist layer 209 and the filling layer 208, the second hard mask layer 206, the contact etching stop layer 205 and the oxide layer 202 thereunder.

[0062] In step S6 of the present embodiment, please refer to Figure 3In (E) of FIG. 9, first, the patterned photoresist layer 209 and the filling layer 208 are removed by any suitable process such as a wet stripping process. Then, a germanium-silicon is grown in the source-drain trench 210 by any suitable germanium-silicon epitaxial growth process to form the germanium-silicon source-drain 211 required for the PMOS region. In this process, the substrate surface of the NMOS region and the substrate surface of other regions of the PMOS region are all masked by the remaining second hard mask layer 206 and other film layers, the top of each gate 203 is masked by the first hard mask layer 204, and the sidewall of each gate 203 is masked by the gate sidewall, so none of them will grow germanium-silicon.

[0063] Optionally, the top of the germanium-silicon source-drain 211 grown in the source-drain trench 210 is higher than the top of the surrounding substrate 200.

[0064] Optionally, in-situ doping of P-type ions such as boron B, aluminum Al, gallium Ga, and indium In is performed at the same time as the epitaxial growth of germanium-silicon in the source-drain trench 210 in step S5, so that the formed germanium-silicon source-drain 211 serves as a P-type ion doped source-drain region required for the PMOS region. In other embodiments of the present application, P-type ion implantation can also be performed on the germanium-silicon source-drain 211 after the epitaxial growth of the germanium-silicon source-drain 211 or after step S7 is performed, to form a P-type ion doped source-drain region (not shown) required for the PMOS region, which can effectively reduce the source-drain contact resistance of the PMOS region, while also applying stress to the channel of the PMOS region to increase the hole carrier mobility.

[0065] In step S7 of the present embodiment, please refer to ​ (F) of FIG. 9, after the formation of the germanium-silicon source-drain 211, a thermal oxidation process or the like can be performed on the top surface of the germanium-silicon source-drain 211 in an ozone environment to form a protective layer (not shown) to prevent the germanium-silicon source-drain 211 from being damaged in subsequent processes of removing the first hard mask layer 204 and the second hard mask layer 206. Then, a second wet process is performed using any suitable etching liquid such as phosphoric acid to remove the first hard mask layer 204 on the top of the gate 203 and the second hard mask layer 206 on the outer wall of the gate sidewall by wet etching. In this process, since the substrate surface of the NMOS region has a relatively thick oxide layer 202, there is no problem of substrate surface depression.

[0066] After the step S7 is performed and the P-type ion-doped source-drain region (not shown) of the PMOS region and the N-type ion-doped source-drain region (not shown) of the NMOS region are formed, the corresponding oxide layer 202 on the top surface of the contact area of the N-type ion-doped source-drain region and the protective layer on the top surface of the contact area of the P-type ion-doped source-drain region are removed, so as to expose the top surface of the contact area of the N-type ion-doped source-drain region and the P-type ion-doped source-drain region. Then, a metal or alloy such as Co, Ni, Ti, etc. is deposited, and a first rapid thermal annealing process with a relatively low temperature is performed. After the unreacted metal is removed, a second rapid thermal annealing process with a relatively high temperature is performed, so as to form the required metal silicide. In this embodiment, the metal silicide (not shown) is formed on the top of the P-type ion-doped source-drain region of the PMOS region, the N-type ion-doped source-drain region of the NMOS region, and each gate 203.

[0067] Optionally, before the corresponding oxide layer 202 on the top surface of the contact area of the N-type ion-doped source-drain region and the protective layer on the top surface of the contact area of the P-type ion-doped source-drain region are removed, a contact etching stop layer (not shown) is deposited conformally again, and a low-k material with a dielectric constant lower than that of silicon dioxide is further deposited, so as to form an interlayer dielectric layer (ILD, not shown) with a flat top surface. Then, the interlayer dielectric layer, the contact etching stop layer, the corresponding oxide layer 202 on the top surface of the contact area of the N-type ion-doped source-drain region, and the protective layer on the top surface of the contact area of the P-type ion-doped source-drain region are etched, so as to form a source-drain contact hole exposing the top surface of the contact area of the P-type ion-doped source-drain region in the PMOS region and a source-drain contact hole exposing the top surface of the contact area of the N-type ion-doped source-drain region in the NMOS region. After the metal deposition, the first rapid thermal annealing, the removal of the unreacted metal, and the second rapid thermal annealing, the metal silicide can be formed in each source-drain contact hole.

[0068] In summary, the manufacturing method of the semiconductor device of the present application adjusts the step of opening the second hard mask layer of the NMOS region after forming the germanium-silicon source-drain of the PMOS region in the prior art to before the photolithography process for forming the germanium-silicon source-drain of the PMOS region, and removes the second hard mask layer on the top of the gate of the NMOS region and the PMOS region by using the chemical mechanical polishing (CMP) method, so as to eliminate the photomask and wet etching process required when the second hard mask layer of the NMOS region is opened in the prior art, simplify the process flow, save the cost of the photomask, avoid the problem of the surface of the substrate of the NMOS region being recessed caused by the wet etching process, and further improve the performance of the device. The manufacturing method of the semiconductor device of the present application can be applied to the device manufacturing of the process nodes of 28 nm and smaller.

[0069] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by those skilled in the art according to the above disclosure is within the protection scope of the technical scheme of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A substrate having a PMOS region and an NMOS region is provided, an oxide layer, a gate layer and a first hard mask layer are formed on the surface of the substrate, and the first hard mask layer and the gate layer are etched to form a gate on the PMOS region and the NMOS region. Gate sidewalls are formed on the sidewalls of each of the gates, and a contact etch stop layer and a second hard mask layer are deposited conformally on the oxide layer, the gate sidewalls and the first hard mask layer in sequence. A sacrificial medium layer is deposited on the second hard mask layer, and the sacrificial medium layer is chemically and mechanically polished to remove the second hard mask layer on top of the first hard mask layer; The sacrificial medium layer is removed using a first wet process; A patterned photoresist layer is formed to protect the NMOS region, and the patterned photoresist layer is used as a mask to etch a second hard mask layer, a contact etch stop layer and a substrate on the PMOS region to form source and drain trenches in the substrate on both sides of the gate of the PMOS region. Remove the patterned photoresist layer and form germanium-silicon source / drain in the source / drain trench using a germanium-silicon epitaxial growth process; The first hard mask layer and the second hard mask layer are removed using a second wet process.

2. The manufacturing method as described in claim 1, characterized in that, Both the contact etching stop layer and the sacrificial dielectric layer are oxides, and the etching solution for the first wet process includes hydrofluoric acid.

3. The manufacturing method as described in claim 1, characterized in that, The contact etch stop layer on top of the first hard mask layer is simultaneously removed by the chemical mechanical polishing or the first wet process.

4. The manufacturing method as described in claim 1, characterized in that, The etching solution used in the second wet process includes phosphoric acid.

5. The manufacturing method as described in claim 1, characterized in that, The first hard mask layer and the second hard mask layer are made of the same material.

6. The manufacturing method as described in claim 1, characterized in that, Both the contact etch stop layer and the second hard mask layer are formed using atomic layer deposition (ALD) technology.

7. The manufacturing method as described in claim 1, characterized in that, Before removing the first hard mask layer and the second hard mask layer, a protective layer is first formed on the top surface of the germanium-silicon source / drain; and / or, after removing the first hard mask layer and the second hard mask layer, metal is also deposited and subjected to rapid thermal processing to form metal silicide on the top surface of the germanium-silicon source / drain and the gate.

8. The manufacturing method as described in claim 7, characterized in that, After removing the first hard mask layer and the second hard mask layer and before depositing metal, or after forming the gate and before depositing the contact etch stop layer, the method further includes: performing N-type ion implantation on the substrate on both sides of the gate of the NMOS region to form N-type ion-doped source / drain regions.

9. The manufacturing method as described in claim 8, characterized in that, Before depositing the metal, the oxide layer on the N-type ion-doped source / drain regions is removed by wet process to expose the surface of the N-type ion-doped source / drain regions.

10. The manufacturing method according to any one of claims 1-9, characterized in that, During the process of forming germanium-silicon source drains in the source drain trench using germanium-silicon epitaxial growth technology, P-type ions are in-situ doped into the germanium-silicon source drains to form P-type ion-doped source drain regions; or, after removing the first hard mask layer and the second hard mask layer, the NMOS region is masked, and P-type ion implantation is performed on the germanium-silicon source drains on both sides of the gate of the PMOS region to form P-type ion-doped source drain regions.

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