Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a manufacturing method of a semiconductor structure and the semiconductor structure, and relates to the field of integrated circuits. According to the manufacturing method of the semiconductor structure, after the first hard mask pattern is formed on the first region and the second region, the sacrificial layer is adopted to cover the side wall of the first hard mask pattern of the first region, and the sacrificial layer is used for protecting the first hard mask pattern of the first region; the first hard mask pattern in the first area is etched to form the second hard mask pattern with the smaller line width, the first hard mask pattern in the first area is not influenced by etching, multiple times of exposure transfer are not needed to form the pattern with the smaller line width, the photoetching exposure frequency can be reduced, the process window of exposure transfer is increased, the manufacturing difficulty is reduced, and the manufacturing efficiency is improved. The yield and reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices has been continuously reduced, and the manufacturing process of semiconductor devices faces greater challenges.

[0003] Currently, Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) are used to manufacture finer semiconductor devices to increase the pattern density to meet the requirements of integrated circuits for smaller feature sizes. However, the implementation process of the self-aligned double patterning technology is complex. As the feature size of semiconductor devices is continuously reduced, the process window of multiple exposures becomes narrower, and the difficulty and uncertainty of self-aligned double patterning are large, which affects the yield and reliability of the devices. Summary of the Invention

[0004] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure to address the problems of large difficulty and uncertainty in the existing self-aligned double patterning, which affect the yield and reliability of the devices.

[0005] To achieve the above object, in a first aspect, the present disclosure provides a method for manufacturing a semiconductor structure, including:

[0006] Providing a substrate, the substrate including a first region and a second region;

[0007] Forming a first hard mask pattern, the first hard mask pattern being located in the first region and the second region;

[0008] Forming a sacrificial layer in the first region, the sacrificial layer covering the sidewalls of the first hard mask pattern in the first region;

[0009] Etching the first hard mask pattern in the second region to form a second hard mask pattern, the line width of the second hard mask pattern being smaller than the line width of the first hard mask pattern.

[0010] In one embodiment, forming a sacrificial layer in the first region includes:

[0011] Forming a sacrificial material layer, the sacrificial material layer being located in the first region and the second region, the sacrificial material layer covering and filling between adjacent first hard mask patterns and covering the first hard mask pattern;

[0012] Pattern the sacrificial material layer located in the second region, exposing the sidewalls of the first hard mask pattern in the second region;

[0013] Remove the sacrificial material layer on the top surface of the first hard mask pattern. The sacrificial material layer in the first region forms the sacrificial layer.

[0014] In one embodiment, patterning the sacrificial material layer located in the second region includes:

[0015] Form a patterned photoresist layer on the sacrificial material layer;

[0016] Etch the sacrificial material layer according to the patterned photoresist layer, removing the sacrificial material layer between the first hard mask patterns in the second region.

[0017] In one embodiment, forming a patterned photoresist layer on the sacrificial material layer includes:

[0018] Form a photoresist layer on the sacrificial material layer;

[0019] Process the photoresist layer using a lithography process to define a first photoresist pattern in the first region and a second photoresist pattern in the second region, obtaining the patterned photoresist layer.

[0020] In one embodiment, the projection of the first photoresist pattern on the substrate covers the first hard mask pattern in the first region; the projection of the second photoresist pattern on the substrate coincides with the projection of the first hard mask pattern in the second region on the substrate.

[0021] In one embodiment, after etching the sacrificial material layer according to the patterned photoresist layer: the sacrificial material layer in the first region covers the first hard mask pattern in the first region and fills between the adjacent first hard mask patterns in the first region; the sacrificial material layer in the first region covers the top surface of the first hard mask pattern in the second region, exposing the substrate between the adjacent first hard mask patterns in the second region.

[0022] In one embodiment, etching the first hard mask pattern in the second region includes:

[0023] Use an anisotropic etching process to etch the first hard mask pattern in the second region along the horizontal direction.

[0024] In one embodiment, after forming the second hard mask pattern, remove the sacrificial layer.

[0025] In one embodiment, the manufacturing method further includes:

[0026] Etch the substrate according to the first hard mask pattern in the first region and the second hard mask pattern in the second region, form a first fin in the first region, and form a second fin in the second region; the line width of the second fin is smaller than that of the first fin.

[0027] In a second aspect, the present disclosure provides a semiconductor structure manufactured by using the manufacturing method of the semiconductor structure as described in the first aspect.

[0028] In the manufacturing method of the semiconductor structure and the semiconductor structure of the present disclosure, after forming the first hard mask pattern on the first region and the second region, a sacrificial layer is used to cover the sidewalls of the first hard mask pattern in the first region. The sacrificial layer is used to protect the first hard mask pattern in the first region, and then the first hard mask pattern in the second region is etched to form a second hard mask pattern with a smaller line width. The first hard mask pattern in the first region is not affected by the etching, and there is no need to perform multiple exposure transfers to form a pattern with a smaller line width, which can save the number of photolithography exposures, increase the process window of the exposure transfer, reduce the manufacturing difficulty, and improve the yield and reliability of the semiconductor structure. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0030] Figure 1 It is a process flow chart of the manufacturing method of the semiconductor structure provided in an embodiment;

[0031] Figure 2 It is a schematic structural diagram after forming the first hard mask pattern provided in an embodiment;

[0032] Figure 3 It is a schematic structural diagram after forming the sacrificial material layer provided in an embodiment;

[0033] Figure 4 It is a schematic structural diagram after forming a patterned photoresist layer on the sacrificial material layer provided in an embodiment;

[0034] Figure 5 It is a schematic structural diagram after etching the sacrificial material layer according to the patterned photoresist layer provided in an embodiment;

[0035] Figure 6 It is a schematic structural diagram after forming a sacrificial layer in the first region provided in an embodiment;

[0036] Figure 7 Schematic diagram of the structure after forming the second hard mask pattern in an embodiment;

[0037] Figure 8 Schematic diagram of the structure after removing the sacrificial layer provided in an embodiment;

[0038] Figure 9 Schematic diagram of the semiconductor structure provided in an embodiment;

[0039] Figure 10 Schematic diagram of the electronic device provided in an embodiment.

[0040] Description of reference numerals:

[0041] 10. Substrate; 11. First fin; 12. Second fin; 21. First hard mask pattern; 22. Second hard mask pattern; 30. Sacrificial layer; 31. Sacrificial material layer; 400. Electronic device; 401. Circuit board; 402. Integrated circuit;

[0042] A1. First region; A2. Second region; d1. First line width; d2. Second line width. Detailed implementation manners

[0043] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0045] With the development of semiconductor technology, the size of transistors (Metal-Oxide-Semiconductor, MOS) has been continuously reduced, and the channel length of transistors has decreased accordingly, affecting the performance and stability of transistors. In related technologies, complementary metal-oxide-semiconductor transistor fin field-effect transistors (Fin Field-Effect Transistor, FINFET) are used. The gate of the FINFET adopts a fork-like architecture similar to a fin, increasing the channel length of the transistor, which can effectively control the on and off of the circuit on both sides of the circuit, thus significantly improving the control ability of the circuit and effectively reducing the leakage current. In addition, this design also helps to shorten the gate length of the transistor, further improving the integration and performance of the transistor.

[0046] In the manufacturing process of FINFETs, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) are usually used to fabricate the fins of FINFETs. However, self-aligned double patterning requires strict control of the height and width of each fin to ensure the performance and stability of the device. In the actual process, the process window of multiple exposures in self-aligned double patterning is getting narrower, increasing the manufacturing difficulty and uncertainty, and affecting the yield and reliability of the device.

[0047] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor structure, as Figure 1 shown, the method for manufacturing a semiconductor structure includes the following steps:

[0048] Step S10: Provide a substrate, the substrate includes a first region and a second region.

[0049] Step S20: Form a first hard mask pattern, the first hard mask pattern is located in the first region and the second region.

[0050] Step S30: Form a sacrificial layer in the first region, the sacrificial layer covers the sidewalls of the first hard mask pattern in the first region.

[0051] Step S40: Etch the first hard mask pattern in the second region to form a second hard mask pattern, and the line width of the second hard mask pattern is smaller than the line width of the first hard mask pattern.

[0052] In the method for fabricating a semiconductor structure according to this embodiment, after forming a first hard mask pattern on the first region and the second region, a sacrificial layer is used to cover the sidewalls of the first hard mask pattern in the first region. The sacrificial layer is used to protect the first hard mask pattern in the first region. Then, the first hard mask pattern in the second region is etched to form a second hard mask pattern with a smaller line width. The first hard mask pattern in the first region is not affected by the etching, and there is no need to perform multiple exposure transfers to form a pattern with a smaller line width, which can save the number of photolithography exposures, increase the process window of the exposure transfer, reduce the manufacturing difficulty, and improve the yield and reliability of the semiconductor structure.

[0053] The following will Figures 2 - 9 describe each step of the method for fabricating a semiconductor structure in detail. Figures 2 - 9 FIG. is a schematic structural diagram of a semiconductor structure in the process of its fabrication according to an exemplary embodiment of the present disclosure.

[0054] In step S10, as Figure 2 shown, the substrate 10 may be a semiconductor substrate. The material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including, such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. The substrate 10 may be a single-layer structure or a multi-layer structure. The substrate 10 is doped with conductive ions, and the substrate 10 may have a P-type conductivity type or an N-type conductivity type.

[0055] As Figure 2 shown, the substrate 10 includes a first region A1 and a second region A2.

[0056] In step S20, a first hard mask pattern 21 is formed on the substrate 10, and the first hard mask pattern 21 is located in the first region A1 and the second region A2.

[0057] In this embodiment, to form the first hard mask pattern 21 on the substrate 10, the following implementation manner may be adopted:

[0058] First, a hard mask material layer (not shown in the figure) is formed on the substrate 10, and the hard mask material layer covers the first region A1 and the second region A2. The hard mask material layer may be a single-layer structure or a multi-layer structure.

[0059] Exemplarily, the material of the hard mask material layer may include silicon nitride, silicon oxynitride, silicon carbonitride, or nitrogen-doped silicon nitride, etc. In this embodiment, the material of the hard mask material layer includes silicon nitride.

[0060] Then, a first photoresist mask (not shown in the figure) is formed on the hard mask material layer. The first photoresist mask performs a photolithography process to define a first photolithography pattern (not shown in the figure) in the first photoresist mask.

[0061] Next, the hard mask material layer is etched according to the first photolithography pattern to transfer the pattern of the first photolithography pattern to the hard mask material layer. As Figure 2 shown, a first hard mask pattern 21 is formed on the first region A1 and the second region 21. The line width and pattern density of the first hard mask pattern 21 on the first region A1 are the same as those of the first hard mask pattern 21 on the second region A2.

[0062] As Figure 2 shown, the first hard mask pattern 21 has a first line width d1. In this embodiment, when forming the first photolithography pattern by photolithographic exposure, this step forms a first photolithography pattern with a relatively large first line width d1. The etching window for transferring the pattern by etching the hard mask material layer according to the first photolithography pattern is relatively large, which can reduce the manufacturing difficulty and improve the transfer accuracy of the first photolithography pattern, so as to fabricate a first hard mask pattern 21 with a first line width d1, which is beneficial to improving the product yield.

[0063] In step S30, referring to Figures 3 - 6 , a sacrificial layer 30 is formed to cover the first hard mask pattern 21 in the first region A1. The sacrificial layer 30 covers at least the sidewalls of the first hard mask pattern 21 in the first region A1 to protect the first hard mask pattern 21 in the first region A1 and prevent the first hard mask pattern 21 from being damaged during the subsequent etching of the second region A2.

[0064] Exemplarily, the sacrificial layer 30 may only cover the sidewalls of the first hard mask pattern 21 in the first region A1, or the sacrificial layer 30 may cover the sidewalls and the top surface of the first hard mask pattern 21 in the first region A1. Or, the sacrificial layer 30 may cover the sidewalls of the first hard mask pattern 21 in the first region A1 and be filled between adjacent first hard mask patterns 21 in the first region A1.

[0065] Exemplarily, the sacrificial layer 30 may be formed by deposition and etching, or the sacrificial layer 30 may be formed by spin-coating a material on the first region A1.

[0066] In this embodiment, there is no limitation on the material of the sacrificial layer 30, as long as the material of the sacrificial layer 30 has a high etching ratio relative to the material of the first hard mask pattern 21.

[0067] Exemplarily, the material of the first hard mask pattern 21 includes silicon nitride, and the material of the sacrificial layer 30 may include silicon oxide.

[0068] In step S40, referring to Figure 6 、 Figure 7As shown, the first hard mask pattern 21 in the second region A2 is etched, including: etching the first hard mask pattern 21 in the second region A2 in the horizontal direction by using an anisotropic etching process.

[0069] In this embodiment, the first hard mask pattern 21 in the second region A2 is dry-etched, and dry etching has high etching accuracy and good directionality control.

[0070] Exemplarily, referring to Figure 6 、 Figure 7 As shown, the first hard mask pattern 21 in the second region A2 can be etched by using an etching gas or plasma. Among them, the etching rate of the etching gas or plasma in the horizontal direction (parallel to the substrate 10) for etching the first hard mask pattern 21 is much greater than the etching rate of the etching gas or plasma in the vertical direction (parallel to the substrate 10) for etching the first hard mask pattern 21, so as to achieve anisotropic etching, etch the first hard mask pattern 21 in the second region A2 in the horizontal direction, reduce the line width of the first hard mask pattern 21 in the second region A2, form a second hard mask pattern 22 with a second line width d2 in the second region A2, and the second line width d2 of the second hard mask pattern 22 in the second region A2 is smaller than the first line width d1 of the first hard mask pattern 21 in the first region A1.

[0071] Compared with the traditional multiple exposure techniques (SADP or SAQP), the manufacturing method of the semiconductor structure in this embodiment only needs to perform one transfer of the exposure pattern, and then mask patterns with different line widths can be formed in the first region A1 and the second region A2 of the substrate 10, reducing the process steps, shortening the process cycle and the manufacturing time, thereby improving the production efficiency; reducing the number of exposures can improve problems such as pattern misalignment and overlapping defects, improve the line width accuracy of the first hard mask pattern 21 and the second hard mask pattern 22, and can meet the higher requirements for pattern accuracy in semiconductor processes with smaller nodes; at the same time, in this embodiment, the first photolithography pattern with the first line width d1 is formed, reducing the requirement for the fineness of the mask master for forming the first photolithography pattern. The first hard mask pattern 21 is etched with the first photolithography pattern with the first line width d1, and the process window for pattern transfer is larger, which can reduce the manufacturing difficulty, is beneficial to improving the stability and reliability of the semiconductor structure, and improving the product yield.

[0072] In some embodiments, step S30 of forming a sacrificial layer in the first region includes steps S31 - S33:

[0073] Step S31: Form a sacrificial material layer. The sacrificial material layer is located in the first region and the second region, and the sacrificial material layer covers and fills between adjacent first hard mask patterns and covers the first hard mask patterns.

[0074] Referring to Figure 3As shown, any one of the deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering can be used to deposit and form the sacrificial material layer 31. The sacrificial material layer 31 covers the first hard mask pattern 21 in the first region A1 and the second region A2 and is between the filled first hard mask patterns 21.

[0075] In this embodiment, by controlling the thickness of the sacrificial material layer 31, the top surface of the sacrificial material layer 31 is made higher than the top surface of the first hard mask pattern 21.

[0076] Step S32: Pattern the sacrificial material layer in the second region to expose the sidewalls of the first hard mask pattern in the second region.

[0077] Refer to Figure 4 、 Figure 5 As shown, pattern the sacrificial material layer 31 in the second region A2, at least etch away a part of the sacrificial material layer 31 in the second region A2 to expose the sidewalls of the first hard mask pattern 21 in the second region A2, so as to facilitate subsequent horizontal etching of the first hard mask pattern 21 and reduce the line width of the first hard mask pattern 21.

[0078] Step S33: Remove the sacrificial material layer on the top surface of the first hard mask pattern, and the sacrificial material layer in the first region forms a sacrificial layer.

[0079] Refer to Figure 6 As shown, using the top surface of the first hard mask pattern 21 as the polishing end point, polish the sacrificial material layer 31 by chemical mechanical polishing (CMP) to remove the first hard mask pattern 21 on the first hard mask pattern 21. The sacrificial material layer 31 retained by grinding in the first region A1 forms a sacrificial layer 30. The sacrificial layer 30 covers the sidewalls of the first hard mask pattern 21 in the first region A1 to protect the line width of the first hard mask pattern 21 in the first region A1 and prevent the line width of the first hard mask pattern 21 in the first region A1 from changing due to etching damage.

[0080] In some embodiments, step S32: Pattern the sacrificial material layer in the second region, including steps S321 - S322:

[0081] Step S321: Form a patterned photoresist layer on the sacrificial material layer.

[0082] In this embodiment, forming a patterned photoresist layer on the sacrificial material layer includes:

[0083] Step S321-1: Form a photoresist layer on the sacrificial material layer.

[0084] Coat a photoresist solution on the top surface of the sacrificial material layer 31, and after drying, form a photoresist layer (not shown in the figure).

[0085] Step S321-2: Process the photoresist layer using a photolithography process, define a first photoresist pattern in the first region and a second photoresist pattern in the second region to obtain a patterned photoresist layer.

[0086] Refer to Figure 4 As shown, perform photolithography processes such as exposure and development on the photoresist layer, define a first photoresist pattern 411 in the first region A1 and a second photoresist pattern 412 in the second region A2 to obtain a patterned photoresist layer 41.

[0087] Refer to Figure 4 As shown, in this embodiment, the projection of the first photoresist pattern 411 on the substrate 10 covers the first hard mask pattern 21 in the first region A1; the projection of the second photoresist pattern on the substrate 10 coincides with the projection of the first hard mask pattern 21 in the second region A2 on the substrate 10. Thus, during the process of processing the photoresist layer 41 by the photolithography process, the feature size of the defined second photoresist pattern 412 is the first line width d1, and the first photoresist pattern 411 has a larger line width. Making the patterned photoresist layer 41 requires a lower fineness requirement for the mask master, the process difficulty of making the patterned photoresist layer 41 is lower, the controllability is high, and the yield can be improved.

[0088] Step S322: Etch the sacrificial material layer according to the patterned photoresist layer, and remove the sacrificial material layer between the first hard mask patterns in the second region.

[0089] Refer to Figure 5 As shown, etch the sacrificial material layer 31 according to the patterned photoresist layer 41, remove the sacrificial material layer 31 exposed by the first photoresist pattern 411 and the second photoresist pattern 412, and stop etching until the top surface of the substrate 10 in the second region A2 is exposed.

[0090] In this embodiment, refer to Figure 5 As shown, after etching the sacrificial material layer 31 according to the patterned photoresist layer 41: the sacrificial material layer 31 in the first region A1 covers the first hard mask pattern 21 in the first region A1 and fills between the first hard mask patterns 21 adjacent to the first region A1; the sacrificial material layer 31 in the first region A1 covers the top surface of the first hard mask pattern 21 in the second region A2, and exposes the substrate 10 between the first hard mask patterns 21 adjacent to the second region A2.

[0091] Thus, in this embodiment, etching the sacrificial material layer 31 has a low difficulty in transferring the patterns of the first photoresist pattern 411 and the second photoresist pattern 412 to the sacrificial material layer 31, and the process controllability is high. At the same time, when the pattern of this step is transferred to the sacrificial material layer 31 and the sacrificial material layer 31 is etched instead of directly etching the first hard mask pattern 21, problems such as pattern misalignment and overlap defects in this step can be repaired, and the process has a high fault tolerance and large tolerance, which is beneficial to improving the product yield.

[0092] In some embodiments, after forming the second hard mask pattern in step S40, it further includes:

[0093] Step S50: Remove the sacrificial layer.

[0094] Referring to Figure 7 、 Figure 8 As shown, a wet process can be used to etch and remove the sacrificial layer 30, exposing the first hard mask pattern 21 in the first region A1 and the substrate 10 between the adjacent first hard mask patterns 21 in the first region A1, facilitating subsequent processes.

[0095] Exemplarily, a buffered hydrofluoric acid (BHF) solution can be used to etch and remove the sacrificial layer 30.

[0096] Step S60: Etch the substrate according to the first hard mask pattern in the first region and the second hard mask pattern in the second region, forming a first fin in the first region and a second fin in the second region; the line width of the second fin is smaller than the line width of the first fin.

[0097] Referring to Figure 8 、 Figure 9 As shown, using the first hard mask pattern 21 in the first region A1 and the second hard mask pattern 22 in the second region A2 as masks to etch the substrate 10, transferring the pattern of the first hard mask pattern 21 to the first region A1, forming a first fin 11 with a first line width d1 in the first region A1, and forming a second fin 12 with a second line width d2 in the second region A2, where the line width of the second fin 12 is smaller than the line width of the first fin 11.

[0098] Exemplarily, a dry process can be used to etch the substrate 10 to form the first fin 11 and the second fin 12.

[0099] Exemplarily, referring to Figure 8 、 Figure 9 As shown, the etching ratio of the substrate 10 to the first hard mask pattern 21 and the second hard mask pattern 22 can be controlled during the etching process to simultaneously etch the first hard mask pattern 21 and the second hard mask pattern 22 during the pattern transfer process, so that after the first fin 11 and the second fin 12 are formed, the first hard mask pattern 21 and the second hard mask pattern 22 are all etched and removed, saving the process of removing the first hard mask pattern 21 and the second hard mask pattern 22.

[0100] After forming the first fin portion 11 and the second fin portion 12, the first fin portion 11 and the second fin portion 12 are cleaned with a cleaning solution to remove the etching residues on the surfaces of the first fin portion 11 and the second fin portion 12.

[0101] In the manufacturing method of the semiconductor structure of this embodiment, by forming the first hard mask pattern 21 and the second hard mask pattern 22 with different line widths in different regions, and performing one etching on the substrate 10, the patterns of the first hard mask pattern 21 and the second hard mask pattern 22 are transferred into the substrate 10. Thus, the first fin portion 11 with the first line width d1 can be formed in the first region A1, and at the same time, the second fin portion 12 with the second line width d2 can be formed in the second region A2. There is no need to perform multiple pattern transfers on the substrate 10, reducing the etching steps for the substrate 10, capable of reducing the damage to the substrate 10, and being beneficial to improving the performance and reliability of the semiconductor structure; meanwhile, the line widths and layouts of the hard mask patterns on different regions of the substrate 10 can be adjusted to form fins with different line widths and layouts in different regions of the substrate 10, meeting the requirements for the line widths and positions of the fins in different regions for forming semiconductor devices.

[0102] In summary, in the manufacturing method of the semiconductor structure in this embodiment, by forming mask patterns with different line widths in different regions of the substrate 10 and only requiring one transfer of the exposed pattern, fins with different line widths are formed in different regions of the semiconductor substrate 10, meeting the requirements of the continuously shrinking process nodes of semiconductor devices for the manufacturing process, capable of reducing the number of exposures, improving productivity, reducing energy consumption, improving product quality and continuity, enhancing safety, and meeting the development needs of the sustainable development and competitiveness improvement of the semiconductor manufacturing industry.

[0103] In some embodiments, during the process of forming the first hard mask pattern 21 in step S20 and forming the second hard mask pattern 22 in step S40, advanced process control (APC) and the method of loading different temperature units are used to correct and compensate the feature sizes of the first hard mask pattern 21 and the second hard mask pattern 22, so as to improve the dimensional accuracy and uniformity of the first hard mask pattern 21 in the first region A1, improve the dimensional accuracy and uniformity of the second hard mask pattern 22 in the second region A2, thereby improving the dimensional accuracy of the formed first fin portion 11 and second fin portion 12, enabling the sizes of the first fin portion 11 and the second fin portion 12 to reach the preset feature sizes, and enhancing the production yield and reliability of the semiconductor structure.

[0104] Among them, the APC technology is a method for monitoring and controlling key parameters in the semiconductor manufacturing process to ensure the stability and repeatability of the process. The APC technology precisely adjusts the feature sizes of the first hard mask pattern 21 and the second hard mask pattern 22 by real-time monitoring and analyzing key parameters (such as etching rate, uniformity, selectivity, etc.) during the dry etching process. Through the feedback control system, APC can automatically adjust the process parameters to compensate for the mask size deviation caused by factors such as equipment aging and material changes.

[0105] It should be understood that although Figure 1 each step in the process steps described above is shown in sequence according to the indication of the arrow or the sequence of steps, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise clearly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 at least some of the steps in the process steps described above may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0106] The order of fabrication of the various devices in the foregoing embodiments can be arbitrarily adjusted or combined with each other. Therefore, those skilled in the art should fall within the protection scope of the embodiments of the present disclosure when combining and / or swapping any number of fabrication processes without creative efforts.

[0107] According to an exemplary embodiment, this embodiment provides a semiconductor structure, which is fabricated by using the fabrication method of the semiconductor structure in the above embodiment. The semiconductor structure can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), or other types of memories.

[0108] Referring to Figure 9As shown, the semiconductor structure of this embodiment includes a substrate 10, which includes a first region A1 and a second region A2. A first fin 11 is disposed on the first region A1, and a second fin 12 is disposed on the second region A2. The first fin 11 has a first line width d1, and the second fin 12 has a second line width d2, and the second line width d2 is smaller than the first line width d1.

[0109] For the semiconductor structure of this embodiment, by performing one etching on the substrate 10, the patterns of the first hard mask pattern 21 and the second hard mask pattern 22 are transferred into the substrate 10, a first fin 11 with a first line width d1 is formed in the first region A1, and at the same time, a second fin 12 with a second line width d2 is formed in the second region A2. There is no need to perform multiple pattern transfers on the substrate 10, reducing the etching steps for the substrate 10, which can reduce the damage to the substrate 10 and is beneficial to improving the performance and reliability of the semiconductor structure. At the same time, the line widths and layouts of the hard mask patterns on different regions of the substrate 10 can be adjusted, and fins with different line widths and layouts can be formed in different regions of the substrate 10 to meet the requirements for the line widths and positions of the fins in forming semiconductor devices in different regions.

[0110] According to an exemplary embodiment, this embodiment provides an electronic device 400, which includes the semiconductor structure as described in any one of the embodiments of the present disclosure. Figure 10 The structural schematic diagram of the electronic device 400 according to the embodiment of the present application is shown. As Figure 10 shown, the electronic device 400 may include a circuit board 401 and an integrated circuit 402 coupled to the circuit board 401. The semiconductor structure as described above may be formed in the integrated circuit 402. For example, the integrated circuit 402 may be disposed on the circuit board 401. The integrated circuit 402 may exist in the form of a memory, a processor, etc.

[0111] It can be understood that the structure schematically shown in the embodiment of the present application does not constitute a specific limitation on the electronic device 400. In other embodiments of the present application, the electronic device 400 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or have different component arrangements. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0112] The electronic device 400 is, for example but not limited to, consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products and other suitable types of electronic products. Consumer electronic products such as mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products such as smart door locks, TVs, refrigerators, wearable devices, etc. Vehicle-mounted electronic products such as vehicle-mounted navigators, vehicle-mounted DVDs, etc. Financial terminal products such as ATMs, terminals for self-service business handling, etc.

[0113] It should be noted that the term "pattern" appears in multiple places in the foregoing text, and this term has different meanings for different objects. For a semiconductor substrate, a pattern refers to a pattern formed by various structures (such as trenches, protrusions, etc.) located on the semiconductor substrate; for a mask, a pattern refers to a pattern formed by various design patterns (such as lines, gaps between lines, etc.) on the mask. Those skilled in the art should understand that the pattern of the mask can be converted into a physical pattern on the semiconductor substrate through appropriate semiconductor processes (such as lithography, etching, etc.).

[0114] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0115] The above-described embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the scope of the present disclosure. Therefore, the scope of the present disclosure patent should be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a first hard mask pattern, wherein the first hard mask pattern is located in the first region and the second region; forming a sacrificial layer in the first region, wherein the sacrificial layer covers a sidewall of the first hard mask pattern in the first region; The first hard mask pattern in the second region is etched to form a second hard mask pattern, wherein a line width of the second hard mask pattern is smaller than a line width of the first hard mask pattern.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a sacrificial layer in the first region comprises: forming a sacrificial material layer, the sacrificial material layer being located in the first region and the second region, the sacrificial material layer covering and filling between adjacent first hard mask patterns and covering the first hard mask pattern; patterning the sacrificial material layer located in the second region to expose the sidewall of the first hard mask pattern in the second region; The sacrificial material layer on the top surface of the first hard mask pattern is removed, and the sacrificial material layer in the first region forms the sacrificial layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: Patterning the sacrificial material layer located in the second region comprises: forming a patterned photoresist layer on the sacrificial material layer; The sacrificial material layer is etched according to the patterned photoresist layer to remove the sacrificial material layer located between the first hard mask patterns in the second region.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: Forming a patterned photoresist layer on the sacrificial material layer, comprising: forming a photoresist layer on the sacrificial material layer; The photoresist layer is processed by a photolithography process, a first photoresist pattern is defined in the first area, and a second photoresist pattern is defined in the second area, so as to obtain the patterned photoresist layer.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The projection of the first photoresist pattern on the substrate covers the first hard mask pattern in the first region; A projection of the second photoresist pattern on the substrate coincides with a projection of the first hard mask pattern in the second region on the substrate.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: After etching the sacrificial material layer according to the patterned photoresist layer: the sacrificial material layer in the first area covers the first hard mask pattern in the first area and fills between the adjacent first hard mask patterns in the first area; the sacrificial material layer in the first area covers the top surface of the first hard mask pattern in the second area, exposing the substrate between the adjacent first hard mask patterns in the second area.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: Etching the first hard mask pattern in the second region includes: The first hard mask pattern in the second region is etched along a horizontal direction using an anisotropic etching process.

8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: After forming the second hard mask pattern, the sacrificial layer is removed.

9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: The production method further comprises: The substrate is etched according to the first hard mask pattern in the first area and the second hard mask pattern in the second area to form a first fin in the first area and a second fin in the second area; the line width of the second fin is smaller than the line width of the first fin.

10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the manufacturing method of any one of claims 1 to 9.

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