Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: injecting insulating ions into a CMOS (Complementary Metal Oxide Semiconductor) device region and a BJT (Bipolar Junction Transistor) device region, so as to form an embedded insulating layer in a substrate, and enabling the substrate to cover the surface of the embedded insulating layer; an epitaxial layer is formed on the surface of the substrate, the conductive type of the epitaxial layer is the same as that of the substrate, the epitaxial layer has a second doping ion concentration, and the second doping ion concentration is smaller than the first doping ion concentration; an isolation structure is formed in the substrate and the epitaxial layer, the isolation structure penetrates through the epitaxial layer in the direction perpendicular to the surface of the substrate and is located between the adjacent device areas, and the bottom of the isolation structure is connected with the embedded insulating layer; forming a plurality of VDMOS gate structures in the epitaxial layer on the VDMOS device region or on the surface of the epitaxial layer; forming a body region in the epitaxial layer on the VDMOS device region on one side or two sides of the VDMOS gate structure; and the VDMOS source doping region is formed in the body region, so that the compatibility of the VDMOS device and the BCD process is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic integration process technology, which fabricates bipolar junction transistor (BJT) devices, complementary metal-oxide semiconductor (CMOS) devices, and double-diffused metal-oxide semiconductor (DMOS) devices on the same chip. Devices manufactured using the BCD process are widely used in fields such as power management, display driving, automotive electronics, and industrial control.

[0003] However, the existing BCD process needs to be further improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a plurality of device regions, the plurality of device regions include a VDMOS device region, a CMOS device region, and a BJT device region, the CMOS device region includes a first device region, the substrate has a first conduction type and a first doping ion concentration; a buried insulating layer located within the substrate, the substrate covers the surface of the buried insulating layer; an epitaxial layer located on the surface of the substrate, the epitaxial layer has the same conduction type as the substrate, and the epitaxial layer has a second doping ion concentration, the second doping ion concentration is less than the first doping ion concentration; an isolation structure located within the substrate and the epitaxial layer, the isolation structure penetrates the epitaxial layer in a direction perpendicular to the surface of the substrate, and is located between adjacent device regions, the bottom of the isolation structure is in contact with the buried insulating layer; a plurality of VDMOS gate structures located within the epitaxial layer or on the surface of the epitaxial layer above the VDMOS device region; a plurality of CMOS gate structures located on the surface of the epitaxial layer above the CMOS device region, the plurality of CMOS gate structures include a plurality of first gate structures located on the first device region; a body region located within the epitaxial layer above the VDMOS device region on one side or both sides of the VDMOS gate structure, the body region has a second conduction type, the second conduction type is different from the first conduction type; a first source region located within the epitaxial layer above the first device region on one side of the first gate structure, and a first drain region located within the epitaxial layer above the first device region on the other side of the first gate structure, the first source region and the first drain region have the second conduction type; a VDMOS source doping region located within the body region, the VDMOS source doping region has the first conduction type; a plurality of BJT devices located within the epitaxial layer above the BJT device region, the BJT devices include a base region, an emitter region, and a collector region.

[0006] Optionally, the CMOS device region further includes a second device region; the plurality of CMOS gate structures further include a plurality of second gate structures located on the second device region; the isolation structure is also located between the first device region and the second device region; a second substrate layer is further provided within the substrate, the second substrate layer is located on the buried insulating layer within the second device region, an epitaxial inversion layer located on the second device region is further provided within the epitaxial layer, the second substrate layer and the epitaxial inversion layer have the second conduction type, and the second substrate layer has a third doping ion concentration, the epitaxial inversion layer has a fourth doping ion concentration, the third doping ion concentration is greater than the fourth doping ion concentration.

[0007] Optionally, it further includes: a second source region in the epitaxial inversion layer on one side of the second gate structure, and a second drain region in the epitaxial inversion layer on the other side of the second gate structure, and the second source region and the second drain region have the first conduction type.

[0008] Optionally, the second device region includes a first region and a second region arranged parallel to the substrate surface direction, the first region and the second region are discrete from each other, and the second source region and the second drain region are located on the first region; it further includes: a first substrate electrode region in the epitaxial inversion layer on the second region, and the first substrate electrode region has the second conduction type.

[0009] Optionally, the first device region includes a third region and a fourth region arranged parallel to the substrate surface direction, the third region and the fourth region are discrete from each other, and the first source region and the first drain region are located on the third region; it further includes: a second substrate electrode region in the epitaxial layer on the fourth region, and the second substrate electrode region has the first conduction type.

[0010] Optionally, it further includes: a doped region in the epitaxial layer on the VDMOS device region, the doped region is in contact with the substrate, and the conduction type of the doped region is different from that of the epitaxial layer; the doped region has a fifth doping ion concentration, and the fifth doping ion concentration is equal to the second doping ion concentration; the body region is located above the doped region and is in contact with the doped region.

[0011] Optionally, the VDMOS gate structure is located in the epitaxial layer, and the depth of the VDMOS gate structure is greater than the depth of the body region, and the doped region is discrete from the VDMOS gate structure.

[0012] Optionally, the VDMOS gate structure is located on the surface of the epitaxial layer; the edge of the body region is flush with the edge of the doped region, or the edge of the body region is closer to the bottom of the VDMOS gate structure relative to the edge of the doped region.

[0013] Optionally, the body region further extends under part of the VDMOS gate structure.

[0014] Optionally, the BJT device region further includes a fifth region, a sixth region, and a seventh region arranged parallel to the substrate surface direction, the fifth region and the sixth region are adjacent, and the fifth region and the seventh region are respectively located on both sides of the sixth region; the base region is located on the sixth region, the emitter region is located on the fifth region, and the collector region is located on the seventh region.

[0015] Optionally, the base region is also located in the fifth region, and the depth of the base region is greater than the depth of the emitter region.

[0016] Optionally, the substrate has opposite first and second surfaces, and the epitaxial layer is located on the first surface; further comprising: a conductive structure, the conductive structure includes a VDMOS gate conductive layer located on the surface of the VDMOS gate structure, a source conductive layer located on the surface of the VDMOS source doping region, a first gate conductive layer located on the surface of the first gate structure, a first source conductive layer located on the surface of the first source region, a first drain conductive layer located on the surface of the first drain region, a base conductive layer located on the surface of the base region, an emitter conductive layer located on the surface of the emitter region, and a collector conductive layer located in the collector region; a drain conductive layer located on the second surface of the substrate.

[0017] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a plurality of device regions, the plurality of device regions include a VDMOS device region, a CMOS device region, and a BJT device region, the CMOS device region includes a first device region, the substrate has a first conduction type and a first doping ion concentration; injecting insulating ions into the CMOS device region and the BJT device region to form a buried insulating layer in the substrate, the substrate covers the surface of the buried insulating layer; forming an epitaxial layer on the surface of the substrate, the conduction type of the epitaxial layer is the same as that of the substrate, and the epitaxial layer has a second doping ion concentration, the second doping ion concentration is less than the first doping ion concentration; forming an isolation structure in the substrate and the epitaxial layer, the isolation structure penetrates the epitaxial layer in a direction perpendicular to the surface of the substrate and is located between adjacent device regions, and the bottom of the isolation structure is in contact with the buried insulating layer; forming a plurality of VDMOS gate structures in the epitaxial layer or on the surface of the epitaxial layer on the VDMOS device region; forming a plurality of CMOS gate structures on the surface of the epitaxial layer on the CMOS device region, the plurality of CMOS gate structures include a plurality of first gate structures located on the first device region; forming a body region in the epitaxial layer on one side or both sides of the VDMOS gate structure on the VDMOS device region, the body region has a second conduction type, the second conduction type is different from the first conduction type; forming a first source region in the epitaxial layer on the first device region on one side of the first gate structure, forming a first drain region in the epitaxial layer on the first device region on the other side of the first gate structure, the first source region and the first drain region have a second conduction type; forming a VDMOS source doping region in the body region, the VDMOS source doping region has the first conduction type; forming a plurality of BJT devices in the epitaxial layer on the BJT device region, the BJT devices include a base region, an emitter region, and a collector region.

[0018] Optionally, the CMOS device region further includes a second device region; a plurality of the CMOS gate structures further include a plurality of second gate structures located on the second device region; the isolation structure is further formed between the first device region and the second device region; the method further includes: after forming the isolation structure and before forming a plurality of the VDMOS gate structures and a plurality of the CMOS gate structures, injecting first conductive ions into the epitaxial layer on the second device region and its bottom, using the second device region on the buried insulating layer as a second substrate layer, using the epitaxial layer on the second device region as an epitaxial inversion layer, the second substrate layer and the epitaxial inversion layer having the second conductivity type, and the second substrate layer having a third doping ion concentration and the epitaxial inversion layer having a fourth doping ion concentration, the third doping ion concentration being greater than the fourth doping ion concentration; forming a second source region in the epitaxial inversion layer on one side of the second gate structure and forming a second drain region in the epitaxial inversion layer on the other side of the second gate structure, the second source region and the second drain region having the first conductivity type.

[0019] Optionally, the second device region includes a first region and a second region arranged in a direction parallel to the substrate surface, the first region and the second region being separated from each other, and the second source region and the second drain region are formed on the first region; the method further includes: forming a first substrate electrode region in the epitaxial inversion layer on the second region, the first substrate electrode region having the second conductivity type.

[0020] Optionally, the method of injecting the first conductive ions into the epitaxial layer and the substrate includes: injecting the first conductive ions into the substrate using a first ion implantation process, injecting the first conductive ions into the epitaxial layer using a second ion implantation process, the energy of the first conductive ions in the first ion implantation process being greater than the energy of the first conductive ions in the second ion implantation process, and the dose of the first conductive ions in the first ion implantation process being greater than the dose of the first conductive ions in the second ion implantation process.

[0021] Optionally, the method of forming the isolation structure includes: forming trenches in the substrate and the epitaxial layer, the trenches penetrating through the epitaxial layer in a direction perpendicular to the substrate surface and being located between adjacent device regions, and the bottom of the trenches exposing the buried insulating layer; filling the trenches with an insulating material to form the isolation structure.

[0022] Optionally, the first device region includes a third region and a fourth region arranged parallel to the substrate surface, the third region and the fourth region are discrete from each other, and the first source region and the first drain region are formed on the third region; the method further includes: forming a second substrate electrode region in the epitaxial layer on the fourth region, and the second substrate electrode region has the first conductivity type.

[0023] Optionally, after forming the epitaxial layer and before forming a plurality of the VDMOS gate structures, it further includes: forming a doped region in the epitaxial layer on the VDMOS device region, the doped region is in contact with the substrate, and the doped region and the epitaxial layer have different conductivity types; the doped region has a fifth doping ion concentration, and the fifth doping ion concentration is equal to the second doping ion concentration; the body region is formed above the doped region and is in contact with the doped region.

[0024] Optionally, the VDMOS gate structure is formed in the epitaxial layer, and the depth of the VDMOS gate structure is greater than the depth of the body region, and the doped region and the VDMOS gate structure are discrete from each other.

[0025] Optionally, the VDMOS gate structure is formed on the surface of the epitaxial layer; the edge of the body region is flush with the edge of the doped region, or the edge of the body region is closer to the bottom of the VDMOS gate structure relative to the edge of the doped region.

[0026] Optionally, the body region also extends under part of the VDMOS gate structure.

[0027] Optionally, the BJT device region further includes a fifth region, a sixth region, and a seventh region arranged parallel to the substrate surface, the fifth region and the sixth region are adjacent, and the fifth region and the seventh region are respectively located on both sides of the sixth region; the method for forming the BJT device includes: injecting second conductive ions into the epitaxial layer on the sixth region to form the base region; injecting third conductive ions into the epitaxial layer on the fifth region to form the emitter region; injecting fourth conductive ions into the epitaxial layer on the seventh region to form the collector region.

[0028] Optionally, the second conductive ions are also injected into the fifth region, the base region is also located in the fifth region, and the depth of the base region is greater than the depth of the emitter region.

[0029] Optionally, the substrate has opposite first and second surfaces, and the epitaxial layer is formed on the first surface; further comprising: forming a conductive structure, the conductive structure including a VDMOS gate conductive layer on the surface of the VDMOS gate structure, a source conductive layer on the surface of the VDMOS source doping region, a first gate conductive layer on the surface of the first gate structure, a first source conductive layer on the surface of the first source region, a first drain conductive layer on the surface of the first drain region, a base conductive layer on the surface of the base region, an emitter conductive layer on the surface of the emitter region, and a collector conductive layer in the collector region; forming a drain conductive layer on the second surface of the substrate.

[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0031] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the VDMOS device and the BCD structure are integrated into one body, effectively improving the compatibility between the VDMOS device and the BCD process; furthermore, an isolation structure is provided between different devices, and the VDMOS device and the CMOS device and the BJT device in the BCD process are physically isolated through the buried insulating layer and the isolation structure, which is beneficial to reducing the influence of system parasitic parameters and improving the process stability of the overall structure.

[0032] Further, a doping region is formed in the epitaxial layer on the VDMOS device region, and the doping region and the epitaxial layer have different conduction types. The doping region is used to form a superjunction VDMOS device to improve the breakdown voltage of the device.

[0033] In the semiconductor structure provided by the technical solution of the present invention, the VDMOS device and the BCD structure are integrated into one body, effectively improving the compatibility between the VDMOS device and the BCD process; furthermore, an isolation structure is provided between different devices, and the VDMOS device and the CMOS device and the BJT device in the BCD process are physically isolated through the buried insulating layer and the isolation structure, which is beneficial to reducing the influence of system parasitic parameters and improving the process stability of the overall structure.

[0034] Further, a doping region is present in the epitaxial layer on the VDMOS device region, and the doping region and the epitaxial layer have different conduction types. The doping region is used to form a superjunction VDMOS device to improve the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 9 is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0036] Figures 10 to 12 is a schematic structural diagram of each step of the method for forming a semiconductor structure according to another embodiment of the present invention;

[0037] Figures 13 to 14 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to another embodiment of the present invention. Detailed implementation manners

[0038] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0039] As described in the background art, the existing BCD process needs to be further improved.

[0040] Specifically, the existing mature BCD process is a planar structure. The laterally diffused metal oxide semiconductor (LDMOS) is more easily compatible with the CMOS process and is widely used. However, due to its lateral structure, restricted by the on-resistance, it cannot provide a large current and can only meet the applications with low power. To meet the high-power requirements, it is necessary to integrate a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS) device in the BCD process. The VDMOS has a higher breakdown voltage than the planar LDMOS, and has the advantages of small on-resistance and small layout area. However, due to its vertical structure, its compatibility with low-voltage CMOS circuits is poor.

[0041] To solve the above problems, in a semiconductor structure and a method for forming the same provided by the present invention, the VDMOS device is integrated with the BCD structure, effectively improving the compatibility between the VDMOS device and the BCD process. Furthermore, an isolation structure is provided between different devices, and the VDMOS device is physically isolated from the CMOS device and the BJT device in the BCD process through the buried insulating layer and the isolation structure, which is beneficial to reducing the influence of system parasitic parameters and improving the process stability of the overall structure.

[0042] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0043] Figures 1 to 9 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 1, a substrate 100 is provided. The substrate 100 includes a plurality of device regions. The plurality of device regions include a VDMOS device region V, a CMOS device region C, and a BJT device region B. The CMOS device region C includes a first device region I. The substrate 100 has a first conductivity type and a first doping ion concentration.

[0045] In this embodiment, the CMOS device region C further includes a second device region II.

[0046] Here, the VDMOS device region V is used to define the position of a Vertical Double-diffused Metal Oxide Semiconductor Field-Effect Transistor (abbreviated as VDMOS) device. The BJT device region B is used to define the position of a bipolar junction transistor (abbreviated as BJT) device. The CMOS device region C is used to define the position of a Complementary Metal Oxide Semiconductor (abbreviated as CMOS) device. Among them, the first device region I is used to define the position of a first MOS device, and the second device region II is used to define the position of a second MOS device. The first MOS device and the second MOS device have different conductivity types.

[0047] In this embodiment, the second device region II includes a first region (not shown in the figure) and a second region (not shown in the figure) arranged in a direction parallel to the surface of the substrate 100. The first region and the second region are separated from each other. Here, the first region is used to define the positions of the second source region and the second drain region of the second MOS device. The subsequently formed second source region and second drain region are located on the first region. The second region is used to define the position of the first substrate electrode region of the second MOS device. The first substrate electrode region is used for the substrate lead-out of the second MOS device.

[0048] In this embodiment, the first device region I includes a third region (not shown in the figure) and a fourth region (not shown in the figure) arranged in a direction parallel to the surface of the substrate. The third region and the fourth region are separated from each other. Here, the third region is used to define the positions of the first source region and the first drain region of the first MOS device. The subsequently formed first source region and first drain region are located on the third region. The fourth region is used to define the position of the second substrate electrode region of the first MOS device. The second substrate electrode region is used for the substrate lead-out of the first MOS device.

[0049] In this embodiment, the BJT device region further includes a fifth region (not shown in the figure), a sixth region (not shown in the figure), and a seventh region (not shown in the figure) arranged parallel to the surface of the substrate 100. The fifth region and the sixth region are adjacent, and the fifth region and the seventh region are respectively located on both sides of the sixth region. Here, the fifth region is used to define the position of the emitter region of the BJT device, the sixth region is used to define the position of the base region of the BJT device, and the sixth region is used to define the position of the collector region of the BJT device.

[0050] In this embodiment, the first conduction type is N-type, that is, the VDMOS device is N-type, the first MOS device is a PMOS device, and the second MOS device is an NMOS device.

[0051] In other embodiments, the first conduction type may be P-type, that is, the VDMOS device is P-type, the first MOS device is an NMOS device, and the second MOS device is a PMOS device.

[0052] In this embodiment, the material of the substrate 100 is silicon.

[0053] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0054] In this embodiment, in addition to serving as the substrate for the CMOS device and the BJT device, the substrate 100 also serves as the drain doping region of the VDMOS device.

[0055] In this embodiment, the substrate 100 has opposite first surface 10a and second surface 10b. An epitaxial layer will be formed on the first surface 10a later, and a drain conductive layer will be formed on the second surface 10b. The drain conductive layer is used for electrical lead-out of the drain doping region.

[0056] Please refer to Figure 2 , inject insulating ions into the CMOS device region C and the BJT device region B to form a buried insulating layer 101 in the substrate 100, and the substrate 100 covers the surface of the buried insulating layer 101.

[0057] In this embodiment, the insulating ions are oxygen ions, and the material of the formed buried insulating layer 101 is silicon oxide.

[0058] The method for forming the embedded insulating layer 101 further includes: forming a first mask layer 102 on the surface of the substrate 100, and the first mask layer 102 exposes the surfaces of the CMOS device region C and the BJT device region B; using the first mask layer 102 as a mask, injecting insulating ions into the CMOS device region C and the BJT device region B.

[0059] In this embodiment, the first mask layer 102 covers the surface of the VDMOS device region V, and also exposes the surface of the substrate 100 between the CMOS device region C and the VDMOS device region V.

[0060] In this embodiment, the material of the first mask layer 102 includes photoresist; after forming the embedded insulating layer 101, the first mask layer 102 is further removed.

[0061] Please refer to Figure 3 , an epitaxial layer 103 is formed on the surface of the substrate 100. The epitaxial layer 103 has the same conductivity type as the substrate 100, and the epitaxial layer 103 has a second doping ion concentration, and the second doping ion concentration is less than the first doping ion concentration.

[0062] Please refer to Figure 4 , an isolation structure 104 is formed in the substrate 100 and the epitaxial layer 103. The isolation structure 104 penetrates the epitaxial layer 103 along a direction perpendicular to the surface of the substrate 100, and is located between adjacent device regions. The bottom of the isolation structure 104 is in contact with the embedded insulating layer 101.

[0063] In this embodiment, the method for forming the isolation structure 104 includes: forming a trench (not shown in the figure) in the substrate 100 and the epitaxial layer 103. The trench penetrates the epitaxial layer 103 along a direction perpendicular to the surface of the substrate 100, and is located between adjacent device regions. The bottom of the trench exposes the embedded insulating layer 101; filling an insulating material in the trench to form the isolation structure 104. The isolation structure 104 is used for electrical isolation between different device regions.

[0064] In this embodiment, the method for forming the trench includes: etching the epitaxial layer 103 and the substrate 100 from the first surface 10a to the second surface 10b until the embedded insulating layer 101 is exposed.

[0065] In this embodiment, the isolation structure 104 is also formed between the first device region I and the second device region II.

[0066] Subsequently, a plurality of VDMOS gate structures are formed in or on the VDMOS device region; a plurality of CMOS gate structures are formed on the CMOS device region.

[0067] In another embodiment, after forming the epitaxial layer and before forming a plurality of VDMOS gate structures, a doped region is further formed in the epitaxial layer on the VDMOS device region, and the doped region has a different conductivity type from that of the epitaxial layer; the doped region has a fifth doping ion concentration, and the fifth doping ion concentration is equal to the second doping ion concentration; subsequently, a body region in contact with the doped region is formed above the doped region. The doped region is used to form a superjunction VDMOS device to improve the breakdown voltage of the device.

[0068] In this embodiment, after forming the isolation structure 104 and before forming a plurality of VDMOS gate structures and a plurality of CMOS gate structures, please refer to Figure 5 .

[0069] Please refer to Figure 5 , and inject first conductive ions into the epitaxial layer 103 on the second device region II and its bottom. Taking the second device region II on the buried insulating layer 101 as the second substrate layer 105 and the epitaxial layer 103 on the second device region II as the epitaxial inversion layer 106, the second substrate layer 105 and the epitaxial inversion layer 106 have the second conductivity type, and the second substrate layer 105 has a third doping ion concentration, and the epitaxial inversion layer 106 has a fourth doping ion concentration, and the third doping ion concentration is greater than the fourth doping ion concentration.

[0070] In this embodiment, the method of injecting the first conductive ions into the epitaxial layer 103 and the substrate 100 includes: injecting the first conductive ions into the substrate 100 by using a first ion implantation process, and injecting the first conductive ions into the epitaxial layer 103 by using a second ion implantation process. The energy of the first conductive ions in the first ion implantation process is greater than the energy of the first conductive ions in the second ion implantation process, and the dose of the first conductive ions in the first ion implantation process is greater than the dose of the first conductive ions in the second ion implantation process.

[0071] Here, by injecting the first conductive ions, the conductivity type of the second device region II and the epitaxial layer 103 above it is changed, so that the second substrate layer 105 is used as the substrate of the second MOS device, and the epitaxial inversion layer 106 is used as the well region of the second MOS device.

[0072] In this embodiment, the first conductive ions include P-type doping ions.

[0073] In another embodiment, the first conductive ions include N-type doped ions.

[0074] Please refer to Figure 6 , in the epitaxial layer 103 within or on the surface of the epitaxial layer 103 on the VDMOS device region V, a plurality of VDMOS gate structures 107 are formed; on the surface of the epitaxial layer 103 on the CMOS device region C, a plurality of CMOS gate structures are formed, and the plurality of CMOS gate structures include a plurality of first gate structures 108 located on the first device region I.

[0075] In this embodiment, the plurality of CMOS gate structures further include a plurality of second gate structures 109 located on the second device region II.

[0076] In this embodiment, the plurality of VDMOS gate structures 107 are formed on the surface of the epitaxial layer 103, and the plurality of VDMOS gate structures 107 and the plurality of CMOS gate structures are formed simultaneously.

[0077] Specifically, the method for forming the plurality of VDMOS gate structures 107 and the plurality of CMOS gate structures includes: forming a gate oxide material layer (not shown in the figure) on the surface of the epitaxial layer 103; forming a gate material layer (not shown in the figure) on the surface of the gate oxide material layer; patterning the gate material layer and the gate oxide material layer to form a plurality of VDMOS gate structures 107 on the VDMOS device region V, a plurality of the first gate structures 108 on the first device region I, and a plurality of the second gate structures 109 on the second device region II.

[0078] In other embodiments, the plurality of VDMOS gate structures and the plurality of CMOS gate structures may not be formed simultaneously.

[0079] In this embodiment, the material of the gate oxide material layer includes silicon oxide, and the material of the gate material layer includes polysilicon.

[0080] In another embodiment, a plurality of VDMOS gate structures are formed within the epitaxial layer.

[0081] Please refer to Figure 7, a body region 110 is formed in the epitaxial layer 103 on the VDMOS device region V on one or both sides of the VDMOS gate structure 107. The body region 110 has a second conductivity type, which is different from the first conductivity type. A first source region 111 is formed in the epitaxial layer 103 on the first device region I on one side of the first gate structure 108, and a first drain region 112 is formed in the epitaxial layer 103 on the first device region I on the other side of the first gate structure 108. The first source region 111 and the first drain region 112 have the second conductivity type. A base region 113 of the BJT device is formed in the epitaxial layer 103 on the BJT device region B.

[0082] Specifically, the first source region 111 and the first drain region 112 are formed on the third region, and the base region 113 is formed on the sixth region.

[0083] In this embodiment, the method for forming the body region 110 includes: using the VDMOS gate structure 107 as a mask, injecting fifth conductive ions into the epitaxial layer 103 on the VDMOS device region V.

[0084] In this embodiment, after forming the VDMOS gate structure 107, the body region 110 is formed. In another embodiment, the VDMOS gate structure may also be formed after forming the body region.

[0085] In this embodiment, after injecting the fifth conductive ions, the epitaxial layer 103 is further annealed to make the fifth conductive ions diffuse under the VDMOS gate structure 107, that is, the body region 110 also extends under a part of the VDMOS gate structure 107.

[0086] In this embodiment, the method for forming the first source region 111 and the first drain region 112 includes: using the first gate structure 108 as a mask, injecting sixth conductive ions into the epitaxial layer 103 on the first device region I.

[0087] In this embodiment, the method for forming the BJT device includes: injecting second conductive ions into the epitaxial layer 103 on the sixth region to form the base region 113.

[0088] In this embodiment, the base region 113 is also formed in the fifth region, that is, the second conductive ions are also injected into the fifth region.

[0089] In another embodiment, the base region 113 may be formed only in the sixth region.

[0090] The emitter region and the collector region of the BJT device have the same conductivity type, which is different from that of the base region 113.

[0091] In this embodiment, the conductivity type of the base region 113 is different from that of the epitaxial layer 103, and the base region 113 has the second conductivity type.

[0092] In another embodiment, the conductivity type of the base region and the epitaxial layer may be the same.

[0093] In this embodiment, the BJT device is an NPN device.

[0094] In another embodiment, the BJT device may also be a PNP device.

[0095] In this embodiment, a first substrate electrode region 114 is further formed in the epitaxial inversion layer 106 on the second region, and the first substrate electrode region 114 has the second conductivity type.

[0096] In this embodiment, the method for forming the first substrate electrode region 114 includes: injecting seventh conductive ions into the epitaxial inversion layer 106 on the second region to form the first substrate electrode region 114.

[0097] In this embodiment, the second conductivity type is P-type.

[0098] In another embodiment, the second conductivity type is N-type.

[0099] It should be noted here that the second conductive ions, the fifth conductive ions, the sixth conductive ions, and the seventh conductive ions are doping ions of the same conductivity type. To simplify the process, the body region 110, the first source region 111, the first drain region 112, the base region 113, and the first substrate electrode region 114 can be formed together, and there is no need to limit their sequence.

[0100] In this embodiment, the second conductive ions, the fifth conductive ions, the sixth conductive ions, and the seventh conductive ions are all P-type doping ions, and the P-type doping ions may be boron, indium, gallium, etc.

[0101] In another embodiment, the second conductive ions, the fifth conductive ions, the sixth conductive ions, and the seventh conductive ions are all N-type doping ions, and the N-type doping ions may be phosphorus, arsenic, etc.

[0102] Please refer to Figure 8, a VDMOS source doping region 115 is formed within the body region 110, and the VDMOS source doping region 115 has the first conduction type; an emitter region 116 and a collector region 117 of the BJT device are formed within the epitaxial layer 103 on the BJT device region B.

[0103] So far, the VDMOS device and the BCD structure are integrated into one body, effectively improving the compatibility between the VDMOS device and the BCD process; furthermore, an isolation structure is provided between different devices, and the VDMOS device and the CMOS device and the BJT device in the BCD process are physically isolated through the buried insulating layer 101 and the isolation structure 104, which is beneficial to reducing the influence of system parasitic parameters and improving the process stability of the overall structure.

[0104] In this embodiment, the method for forming the VDMOS source doping region 115 includes: using the VDMOS gate structure 107 as a mask, injecting an eighth conductive ion into the epitaxial layer 103 on the VDMOS device region V, and the injection depth of the eighth conductive ion is less than the injection depth of the fifth conductive ion.

[0105] In this embodiment, the method for forming the emitter region 116 and the collector region 117 further includes: injecting a third conductive ion into the epitaxial layer 103 on the fifth region to form the emitter region 116; injecting a fourth conductive ion into the epitaxial layer 103 on the seventh region to form the collector region 117.

[0106] In this embodiment, the collector region 117 is not in contact with the base region 113, and the formed BJT device has a relatively high breakdown voltage.

[0107] In another embodiment, the collector region 117 may be in contact with the base region 113.

[0108] In this embodiment, the depth of the base region 113 is greater than the depth of the emitter region 116.

[0109] In this embodiment, the emitter region 116 and the collector region 117 have the first conduction type.

[0110] Only one BJT device is shown here, and the number of BJT devices can be set according to actual needs.

[0111] In this embodiment, a second source region 118 is further formed within the epitaxial inversion layer 106 on one side of the second gate structure 109, and a second drain region 119 is formed within the epitaxial inversion layer 106 on the other side of the second gate structure 109, and the second source region 118 and the second drain region 119 have the first conduction type.

[0112] In this embodiment, the method for forming the second source region 118 and the second drain region 119 includes: using the second gate structure 109 as a mask, injecting ninth conductive ions into the epitaxial inversion layers 106 on both sides of the second gate structure 109.

[0113] In this embodiment, a second substrate electrode region 120 is further formed in the epitaxial layer 103 on the fourth region, and the second substrate electrode region 120 has the first conductivity type.

[0114] In this embodiment, the method for forming the second substrate electrode 120 includes: injecting ninth conductive ions into the epitaxial layer 103 on the fourth region.

[0115] It should be noted here that the third conductive ions, the fourth conductive ions, the eighth conductive ions, the ninth conductive ions, and the tenth conductive ions are doping ions of the same conductivity type. For the sake of simplifying the process, the emitter region 116, the collector region 117, the VDMOS source doping region 115, the second source region 118, the second drain region 119, and the second substrate electrode 120 can be formed together, and there is no need to limit their sequence.

[0116] In this embodiment, the third conductive ions, the fourth conductive ions, the eighth conductive ions, the ninth conductive ions, and the tenth conductive ions are all N-type doping ions, and the N-type doping ions can be phosphorus, arsenic, etc.

[0117] In another embodiment, for the third conductive ions, the fourth conductive ions, the eighth conductive ions, the ninth conductive ions, and the tenth conductive ions, the P-type doping ions can be boron, indium, gallium, etc.

[0118] Please refer to Figure 9 , a conductive structure is further formed, and the conductive structure includes: a VDMOS gate conductive layer 121 on the surface of the VDMOS gate structure 107, a source conductive layer 122 on the surface of the VDMOS source doping region 115, a first gate conductive layer 123 on the surface of the first gate structure 108, a first source conductive layer 124 on the surface of the first source region 111, a first drain conductive layer 125 on the surface of the first drain region 112, a base conductive layer 126 on the surface of the base region 113, an emitter conductive layer 127 on the surface of the emitter region 116, and a collector conductive layer 128 in the collector region 117; a drain conductive layer 129 is formed on the second surface 106 of the substrate 100.

[0119] In this embodiment, the conductive structure further includes: a second gate conductive layer 130 located on the surface of the second gate structure 109, a second source conductive layer 131 located on the surface of the second source region 118, and a first drain conductive layer 132 located on the surface of the second drain region 119.

[0120] In this embodiment, the conductive structure further includes: a first substrate lead-out layer 133 located on the surface of the first substrate electrode region 114 and a second substrate lead-out layer 134 located on the surface of the second substrate electrode region 120.

[0121] The conductive structure is used for electrical lead-out. Figure 9 The conductive structure in [[ ]] is only for illustration, and its structure is not limited thereto.

[0122] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to [[ ]]. Figure 9, comprising: a substrate 100, the substrate 100 including a plurality of device regions, the plurality of device regions including a VDMOS device region V, a CMOS device region C, and a BJT device region B, the CMOS device region C including a first device region I, the substrate 100 having a first conductivity type and a first doping ion concentration; a buried insulating layer 101 located within the substrate 100, the substrate 100 covering the surface of the buried insulating layer 101; an epitaxial layer 103 located on the surface of the substrate 100, the epitaxial layer 103 having the same conductivity type as the substrate 100, and the epitaxial layer 103 having a second doping ion concentration, the second doping ion concentration being less than the first doping ion concentration; an isolation structure 104 located within the substrate 100 and the epitaxial layer 103, the isolation structure 104 penetrating through the epitaxial layer 103 in a direction perpendicular to the surface of the substrate 100 and being located between adjacent device regions, the bottom of the isolation structure 104 being in contact with the buried insulating layer 101; a plurality of VDMOS gate structures 107 within the epitaxial layer 103 or on the surface of the epitaxial layer 103 located on the VDMOS device region V; a plurality of CMOS gate structures on the surface of the epitaxial layer 103 located on the CMOS device region C, the plurality of CMOS gate structures including a plurality of first gate structures 108 located on the first device region I; a body region 110 within the epitaxial layer 103 located on the VDMOS device region V on one side or both sides of the VDMOS gate structure 107, the body region 110 having a second conductivity type, the second conductivity type being different from the first conductivity type; a first source region 111 within the epitaxial layer 103 located on the first device region I on one side of the first gate structure 108, and a first drain region 112 within the epitaxial layer 103 located on the first device region I on the other side of the first gate structure 108, the first source region 111 and the first drain region 112 having the second conductivity type; a VDMOS source doping region 115 located within the body region 110, the VDMOS source doping region 115 having the first conductivity type; a plurality of BJT devices within the epitaxial layer 103 located on the BJT device region B, the BJT devices including a base region 113, an emitter region 116, and a collector region 117.

[0123] Thus, integrating the VDMOS device with the BCD structure effectively improves the compatibility between the VDMOS device and the BCD process; furthermore, an isolation structure is provided between different devices, and the VDMOS device is physically isolated from the CMOS device and the BJT device in the BCD process through the buried insulating layer 101 and the isolation structure 104, which is beneficial to reducing the influence of system parasitic parameters and improving the process stability of the overall structure.

[0124] In this embodiment, the CMOS device region C further includes a second device region II; and a plurality of the CMOS gate structures further include a plurality of second gate structures 109 located on the second device region II.

[0125] In this embodiment, the isolation structure 104 is further located between the first device region I and the second device region II; a second substrate layer 105 is further provided in the substrate 100, the second substrate layer 105 is located on the buried insulating layer 101 within the second device region II, an epitaxial inversion layer 106 located on the second device region II is further provided in the epitaxial layer 103, the second substrate layer 105 and the epitaxial inversion layer 106 have the second conductivity type, and the second substrate layer 105 has a third doping ion concentration, the epitaxial inversion layer 106 has a fourth doping ion concentration, and the third doping ion concentration is greater than the fourth doping ion concentration.

[0126] In this embodiment, the semiconductor structure further includes: a second source region 118 within the epitaxial inversion layer 106 on one side of the second gate structure 109, a second drain region 119 within the epitaxial inversion layer 106 on the other side of the second gate structure 109, and the second source region 118 and the second drain region 119 have the first conductivity type.

[0127] In this embodiment, the second device region II includes a first region (not shown in the figure) and a second region (not shown in the figure) arranged in a direction parallel to the surface of the substrate 100, the first region and the second region are discrete from each other; the second source region 118 and the second drain region 119 are located on the first region.

[0128] In this embodiment, the semiconductor structure further includes: a first substrate electrode region 114 within the epitaxial inversion layer 106 on the second region, and the first substrate electrode region 114 has the second conductivity type.

[0129] In this embodiment, the first device region I includes a third region (not shown in the figure) and a fourth region (not shown in the figure) arranged in a direction parallel to the surface of the substrate 100, the third region and the fourth region are discrete from each other; the first source region 118 and the first drain region 119 are located on the third region.

[0130] In this embodiment, the semiconductor structure further includes: a second substrate electrode region 120 within the epitaxial layer 103 on the fourth region, and the second substrate electrode region 120 has the first conductivity type.

[0131] In another embodiment, the semiconductor structure further includes: a doped region within the epitaxial layer located on the VDMOS device region, the doped region being in contact with the substrate, the doped region and the epitaxial layer having different conduction types; the doped region having a fifth doping ion concentration, the fifth doping ion concentration being equal to the second doping ion concentration; the body region being located above the doped region and in contact with the doped region.

[0132] In this embodiment, the VDMOS gate structure 107 is located on the surface of the epitaxial layer 103.

[0133] In another embodiment, the VDMOS gate structure is located within the epitaxial layer, and the depth of the VDMOS gate structure is greater than the depth of the body region, and the doped region is separated from the VDMOS gate structure.

[0134] In this embodiment, the body region 110 also extends beneath a portion of the VDMOS gate structure 107.

[0135] In this embodiment, the BJT device region B further includes a fifth region (not shown in the figure), a sixth region (not shown in the figure), and a seventh region (not shown in the figure) arranged parallel to the surface of the substrate 100, the fifth region and the sixth region being adjacent, the fifth region and the seventh region being located on both sides of the sixth region respectively; the base region 113 is located on the sixth region, the emitter region 116 is located on the fifth region, and the collector region 117 is located on the seventh region.

[0136] In this embodiment, the base region 113 is also located within the fifth region, and the depth of the base region 113 is greater than the depth of the emitter region 117.

[0137] In this embodiment, the substrate 100 has opposite first and second surfaces 10a and 10b, and the epitaxial layer 103 is located on the first surface 10a.

[0138] In this embodiment, the semiconductor structure further includes: a VDMOS gate conductive layer 121 located on the surface of the VDMOS gate structure 107, a source conductive layer 122 located on the surface of the VDMOS source doped region 115, a first gate conductive layer 123 located on the surface of the first gate structure 108, a first source conductive layer 124 located on the surface of the first source region 111, a first drain conductive layer 125 located on the surface of the first drain region 112, a base conductive layer 126 located on the surface of the base region 113, an emitter conductive layer 127 located on the surface of the emitter region 116, and a collector conductive layer 128 located on the collector region 117; a drain conductive layer 129 located on the second surface 106 of the substrate 100.

[0139] In this embodiment, the conductive structure further includes: a first substrate lead-out layer 133 located on the surface of the first substrate electrode region 114 and a second substrate lead-out layer 134 located on the surface of the second substrate electrode region 120.

[0140] Figures 10 to 12 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0141] The main difference between this embodiment and the previous embodiment (please refer to Figures 1 to 9 ) is that:

[0142] In this embodiment, a doped region is formed in the epitaxial layer on the VDMOS device region V to form a superjunction VDMOS device.

[0143] In this embodiment, please continue to refer to Figures 1 to 5 , and on the basis of Figure 5 and with reference to Figure 10 , after forming the epitaxial layer 103 and before forming a plurality of VDMOS gate structures, a doped region 201 is further formed in the epitaxial layer 103 on the VDMOS device region V. The doped region 201 is in contact with the substrate 100, and the conductive types of the doped region 201 and the epitaxial layer 103 are different.

[0144] Here, the doped region 201 is used to form a superjunction VDMOS device to improve the breakdown voltage of the device.

[0145] In this embodiment, the doped region 201 has a fifth doping ion concentration, and the fifth doping ion concentration is equal to the second doping ion concentration of the epitaxial layer 103. Here, making the fifth doping ion concentration equal to the second doping ion concentration is to achieve charge balance between the P columns and the N columns.

[0146] Please refer to Figure 11 , a plurality of VDMOS gate structures 207 are formed in or on the surface of the epitaxial layer 103 on the VDMOS device region V; a plurality of CMOS gate structures are formed on the surface of the epitaxial layer 103 on the CMOS device region C, and the plurality of CMOS gate structures include a plurality of first gate structures 208 located on the first device region I.

[0147] In this embodiment, the plurality of CMOS gate structures further include a plurality of second gate structures 209 located on the second device region II.

[0148] In this embodiment, the VDMOS gate structures are formed on the surface of the epitaxial layer 103.

[0149] In another embodiment, the VDMOS gate structure is formed within the epitaxial layer.

[0150] Please refer to Figure 12 , a body region 210 is formed within the epitaxial layer 103 on the VDMOS device region V on one or both sides of the VDMOS gate structure 207. The body region 210 has a second conductivity type, which is different from the first conductivity type. A first source region 211 is formed within the epitaxial layer 103 on the first device region I on one side of the first gate structure 208, and a first drain region 212 is formed within the epitaxial layer 103 on the first device region I on the other side of the first gate structure 208. The first source region 211 and the first drain region 212 have the second conductivity type. A VDMOS source doping region 215 having the first conductivity type is formed within the body region 210. A plurality of BJT devices are formed within the epitaxial layer 103 on the BJT device region B. The BJT devices include a base region 213, an emitter region 216, and a collector region 217.

[0151] In this embodiment, the body region 210 is formed above the doping region 201 and is in contact with the doping region 201.

[0152] The edge of the body region 210 is flush with the edge of the doping region 201, or the edge of the body region 210 is closer to the bottom of the VDMOS gate structure 207 relative to the edge of the doping region 201.

[0153] In this embodiment, the edge of the body region 210 is closer to the bottom of the VDMOS gate structure 207 relative to the edge of the doping region 201.

[0154] It should be noted here that for the formation method of the semiconductor structure outside the doping region 201, please refer to the description of the corresponding formation method from 1 to Figure 9 The corresponding description of the formation method will not be elaborated here.

[0155] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 12 .

[0156] The main difference between this embodiment and the above embodiment (please refer to Figures 1 to 9 ) is that:

[0157] In this embodiment, the epitaxial layer 103 on the VDMOS device region V has a doping region 201 to form a superjunction VDMOS device. The doping region 201 is used to form a superjunction VDMOS device to improve the breakdown voltage of the device.

[0158] It should be noted here that, except for the doped region 201, for the description of the semiconductor structure, please refer to Figures 1 to 9 the corresponding description of the structure therein, which will not be elaborated here.

[0159] Figures 13 to 14 is a schematic structural diagram of each step of the method for forming a semiconductor structure according to another embodiment of the present invention.

[0160] The main difference between this embodiment and the previous embodiment (please refer to Figures 1 to 9 ) is as follows:

[0161] In this embodiment, a plurality of VDMOS gate structures are located in the epitaxial layer on the VDMOS device region V.

[0162] Specifically, please continue to refer to Figures 1 to 5 , and on the basis of Figure 5 refer to Figure 13 to form a plurality of VDMOS gate structures 307 in the epitaxial layer 103 on the VDMOS device region V; form a plurality of CMOS gate structures on the surface of the epitaxial layer 103 on the CMOS device region C, and the plurality of CMOS gate structures include a plurality of first gate structures 308 located on the first device region I.

[0163] In this embodiment, the method for forming the VDMOS gate structure 307 includes: etching a part of the epitaxial layer 103 on the VDMOS device region V to form a gate groove (not shown in the figure) in the epitaxial layer 103; forming a first gate oxide material layer (not shown in the figure) on the bottom and sidewall surfaces of the gate groove; forming a first gate material layer (not shown in the figure) on the surface of the first gate oxide material layer, and the top surface of the first gate material layer is higher than the top surface of the epitaxial layer 103; planarizing the first gate material layer and the first gate oxide material layer until the surface of the epitaxial layer 103 is exposed, and forming the VDMOS gate structure 307 in the gate groove.

[0164] In this embodiment, after forming the epitaxial layer 103 and before forming a plurality of VDMOS gate structures, a doped region 301 is further formed in the epitaxial layer 103 on the VDMOS device region V. The doped region 301 is in contact with the substrate 100. The doped region 301 and the epitaxial layer 103 have different conduction types, and the doped region 301 has a fifth doping ion concentration. Here, the doped region 301 is used to form a superjunction VDMOS device to improve the breakdown voltage of the device.

[0165] In this embodiment, the doping region 301 has a fifth doping ion concentration, and the fifth doping ion concentration is equal to the second doping ion concentration. Here, the fifth doping ion concentration is made equal to the second doping ion concentration to achieve charge balance between the P column and the N column.

[0166] In another embodiment, the doping region may not be formed.

[0167] In this embodiment, several of the CMOS gate structures further include several second gate structures 309 located on the second device region II.

[0168] In this embodiment, the first gate structure 308 and the second gate structure 309 are formed simultaneously and not simultaneously with the VDMOS gate junction 307.

[0169] In this embodiment, the method of forming several of the first gate structures 308 and several of the second gate structures 309 includes: forming a second gate oxide material layer (not shown in the figure) on the surface of the epitaxial layer 103; forming a second gate material layer (not shown in the figure) on the surface of the second gate oxide material layer; patterning the second gate material layer and the second gate oxide material layer to form several of the first gate structures 308 on the first device region I and several of the second gate structures 309 on the second device region II.

[0170] Please refer to Figure 14 , a body region 310 is formed in the epitaxial layer 103 on the VDMOS device region V on one side or both sides of the VDMOS gate structure 307. The body region 310 has a second conductivity type, which is different from the first conductivity type; a first source region 311 is formed in the epitaxial layer 103 on the first device region I on one side of the first gate structure 308, and a first drain region 312 is formed in the epitaxial layer 103 on the first device region I on the other side of the first gate structure 208. The first source region 311 and the first drain region 312 have the second conductivity type; a VDMOS source doping region 315 is formed in the body region 310, and the VDMOS source doping region 315 has the first conductivity type; several BJT devices are formed in the epitaxial layer 103 on the BJT device region B. The BJT devices include a base region 313, an emitter region 316, and a collector region 317.

[0171] In this embodiment, the body region 310 is formed above the doping region 301 and is in contact with the doping region 301.

[0172] In this embodiment, the depth of the VDMOS gate structure 307 is greater than the depth of the body region 310, and the doping region 301 and the VDMOS gate structure 307 are discrete from each other. Making the doping region 301 and the VDMOS gate structure 307 discrete from each other can avoid the influence of the doping region 301 on the doping ions in the channel of the VDMOS device.

[0173] In this embodiment, the body region 310 is in contact with the sidewall of the VDMOS gate structure 307.

[0174] Here, it should be noted that except for the VDMOS gate structure 30, for the formation method of the semiconductor structure, please refer to Figures 1 to 9 the description of the corresponding formation method, which will not be elaborated here.

[0175] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 14 .

[0176] The main difference between this embodiment and the above embodiment (please refer to Figures 1 to 9 ) is that:

[0177] In this embodiment, a plurality of VDMOS gate structures 30 are located in the epitaxial layer 103 on the VDMOS device region V.

[0178] Here, it should be noted that except for the VDMOS gate structure 30, for the semiconductor structure, please refer to Figures 1 to 9 the description corresponding to the structure therein, which will not be elaborated here.

[0179] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a plurality of device regions, the plurality of device regions comprising a VDMOS device region, a CMOS device region and a BJT device region, the CMOS device region comprising a first device region, the substrate having a first conductivity type and a first doping ion concentration; A buried insulating layer located in the substrate, wherein the substrate covers a surface of the buried insulating layer; an epitaxial layer located on the surface of the substrate, the epitaxial layer and the substrate having the same conductivity type, and the epitaxial layer having a second doping ion concentration, which is less than the first doping ion concentration; An isolation structure located in the substrate and the epitaxial layer, the isolation structure penetrates the epitaxial layer in a direction perpendicular to the substrate surface and is located between adjacent device regions, and the bottom of the isolation structure is connected to the buried insulating layer; A plurality of VDMOS gate structures located in the epitaxial layer or on the surface of the epitaxial layer on the VDMOS device region; A plurality of CMOS gate structures located on the surface of the epitaxial layer on the CMOS device region, wherein the plurality of CMOS gate structures include a plurality of first gate structures located on the first device region; a body region in the epitaxial layer on the VDMOS device region on one side or both sides of the VDMOS gate structure, the body region having a second conductivity type, the second conductivity type being different from the first conductivity type; a first source region in the epitaxial layer on the first device region on one side of the first gate structure, and a first drain region in the epitaxial layer on the first device region on the other side of the first gate structure, the first source region and the first drain region having a second conductivity type; a VDMOS source doping region located in the body region, the VDMOS source doping region having the first conductivity type; A plurality of BJT devices are located in the epitaxial layer on the BJT device region, wherein the BJT devices include a base region, an emitter region and a collector region.

2. The semiconductor structure according to claim 1, wherein: The CMOS device area also includes a second device area; the several CMOS gate structures also include several second gate structures located on the second device area; the isolation structure is also located between the first device area and the second device area; the substrate also has a second substrate layer, the second substrate layer is located on the buried insulating layer in the second device area, the epitaxial layer also has an epitaxial inversion layer located on the second device area, the second substrate layer and the epitaxial inversion layer have the second conductivity type, and the second substrate layer has a third doping ion concentration, the epitaxial inversion layer has a fourth doping ion concentration, and the third doping ion concentration is greater than the fourth doping ion concentration.

3. The semiconductor structure according to claim 2, wherein: Also includes: A second source region in the epitaxial inversion layer on one side of the second gate structure and a second drain region in the epitaxial inversion layer on the other side of the second gate structure, the second source region and the second drain region have the first conductivity type.

4. The semiconductor structure according to claim 3, characterized in that The second device region includes a first region and a second region arranged parallel to the substrate surface direction, the first region and the second region are separate from each other, and the second source region and the second drain region are located on the first region; and also includes: a first substrate electrode region within the epitaxial inversion layer located on the second region, and the first substrate electrode region has the second conductivity type.

5. The semiconductor structure according to claim 1, wherein: The first device region includes a third region and a fourth region arranged parallel to the surface direction of the substrate, the third region and the fourth region are separate from each other, and the first source region and the first drain region are located on the third region; and also includes: a second substrate electrode region in the epitaxial layer located on the fourth region, and the second substrate electrode region has the first conductivity type.

6. The semiconductor structure according to claim 1, wherein: Also includes: a doped region in the epitaxial layer located on the VDMOS device region, the doped region being in contact with the substrate, and the doped region and the epitaxial layer having different conductivity types; The doping region has a fifth doping ion concentration, and the fifth doping ion concentration is equal to the second doping ion concentration; the body region is located above the doping region and contacts the doping region.

7. The semiconductor structure according to claim 6, wherein: The VDMOS gate structure is located in the epitaxial layer, and the depth of the VDMOS gate structure is greater than the depth of the body region. The doped region and the VDMOS gate structure are separated from each other.

8. The semiconductor structure according to claim 6, wherein: The VDMOS gate structure is located on the surface of the epitaxial layer; the edge of the body region is flush with the edge of the doped region, or the edge of the body region is closer to the bottom of the VDMOS gate structure than the edge of the doped region.

9. The semiconductor structure according to claim 8, characterized in that The body region also extends below a portion of the VDMOS gate structure.

10. The semiconductor structure according to claim 1, wherein: The BJT device region also includes a fifth region, a sixth region and a seventh region arranged parallel to the surface direction of the substrate, the fifth region and the sixth region are adjacent, and the fifth region and the seventh region are respectively located on both sides of the sixth region; the base region is located on the sixth region, the emitter region is located on the fifth region, and the collector region is located on the seventh region.

11. The semiconductor structure according to claim 10, characterized in that The base region is also located in the fifth region, and a depth of the base region is greater than a depth of the emitter region.

12. The semiconductor structure according to claim 1, wherein: The substrate has a first surface and a second surface relative to each other, and the epitaxial layer is located on the first surface; it also includes: a conductive structure, the conductive structure including a VDMOS gate conductive layer located on the surface of the VDMOS gate structure, a source conductive layer located on the surface of the VDMOS source doping region, a first gate conductive layer located on the surface of the first gate structure, a first source conductive layer located on the surface of the first source region, a first drain conductive layer located on the surface of the first drain region, a base conductive layer located on the surface of the base region, an emitter conductive layer located on the surface of the emitter region, and a collector conductive layer located in the collector region; and a drain conductive layer located on the second surface of the substrate.

13. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of device regions, the plurality of device regions comprising a VDMOS device region, a CMOS device region and a BJT device region, the CMOS device region comprising a first device region, the substrate having a first conductivity type and a first doping ion concentration; Injecting insulating ions into the CMOS device region and the BJT device region to form a buried insulating layer in the substrate, wherein the substrate covers the surface of the buried insulating layer; forming an epitaxial layer on the surface of the substrate, wherein the epitaxial layer and the substrate have the same conductivity type and the epitaxial layer has a second doping ion concentration, which is less than the first doping ion concentration; An isolation structure is formed in the substrate and the epitaxial layer, wherein the isolation structure penetrates the epitaxial layer in a direction perpendicular to the surface of the substrate and is located between adjacent device regions, and the bottom of the isolation structure is connected to the buried insulating layer; forming a plurality of VDMOS gate structures in the epitaxial layer or on the surface of the epitaxial layer on the VDMOS device region; forming a plurality of CMOS gate structures on the surface of the epitaxial layer on the CMOS device region, wherein the plurality of CMOS gate structures include a plurality of first gate structures located on the first device region; forming a body region in the epitaxial layer on the VDMOS device region on one side or both sides of the VDMOS gate structure, the body region having a second conductivity type, the second conductivity type being different from the first conductivity type; forming a first source region in the epitaxial layer on the first device region on one side of the first gate structure, and forming a first drain region in the epitaxial layer on the first device region on the other side of the first gate structure, wherein the first source region and the first drain region have a second conductivity type; forming a VDMOS source doping region in the body region, wherein the VDMOS source doping region has the first conductivity type; A plurality of BJT devices are formed in the epitaxial layer on the BJT device region, wherein the BJT devices include a base region, an emitter region and a collector region.

14. The method for forming a semiconductor structure according to claim 13, wherein: The CMOS device region also includes a second device region; the plurality of CMOS gate structures also include a plurality of second gate structures located on the second device region; the isolation structure is also formed between the first device region and the second device region; the method further includes: after forming the isolation structure and before forming the plurality of VDMOS gate structures and the plurality of CMOS gate structures, injecting first conductive ions into the epitaxial layer on the second device region and its bottom, taking the second device region on the buried insulating layer as the second substrate layer, taking the epitaxial layer on the second device region as the epitaxial inversion layer, the second substrate layer and the epitaxial inversion layer having the second conductivity type, and the second substrate layer having a third doping ion concentration, the epitaxial inversion layer having a fourth doping ion concentration, the third doping ion concentration being greater than the fourth doping ion concentration; forming a second source region in the epitaxial inversion layer on one side of the second gate structure, and forming a second drain region in the epitaxial inversion layer on the other side of the second gate structure, the second source region and the second drain region having the first conductivity type.

15. The method for forming a semiconductor structure according to claim 14, wherein: The second device region includes a first region and a second region arranged parallel to the surface direction of the substrate, the first region and the second region are separate from each other, and the second source region and the second drain region are formed on the first region; the method also includes: forming a first substrate electrode region in the epitaxial inversion layer on the second region, the first substrate electrode region having the second conductivity type.

16. The method for forming a semiconductor structure according to claim 14, wherein: The method of implanting the first conductive ions into the epitaxial layer and the substrate comprises: implanting the first conductive ions into the substrate using a first ion implantation process, and implanting the first conductive ions into the epitaxial layer using a second ion implantation process, wherein the energy of the first conductive ions in the first ion implantation process is greater than the energy of the first conductive ions in the second ion implantation process, and the dosage of the first conductive ions in the first ion implantation process is greater than the dosage of the first conductive ions in the second ion implantation process.

17. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the isolation structure includes: forming a groove in the substrate and the epitaxial layer, the groove penetrating the epitaxial layer in a direction perpendicular to the surface of the substrate and being located between adjacent device areas, and the bottom of the groove exposing the buried insulating layer; filling the groove with insulating material to form the isolation structure.

18. The method for forming a semiconductor structure according to claim 13, wherein: The first device region includes a third region and a fourth region arranged parallel to the surface direction of the substrate, the third region and the fourth region are separate from each other, and the first source region and the first drain region are formed on the third region; the method also includes: forming a second substrate electrode region in the epitaxial layer on the fourth region, the second substrate electrode region having the first conductivity type.

19. The method for forming a semiconductor structure according to claim 13, wherein: After forming the epitaxial layer and before forming the plurality of VDMOS gate structures, the method further includes: forming a doped region in the epitaxial layer on the VDMOS device region, wherein the doped region is in contact with the substrate, and the conductivity types of the doped region and the epitaxial layer are different; the doped region has a fifth doping ion concentration, and the fifth doping ion concentration is equal to the second doping ion concentration; and the body region is formed above the doped region and in contact with the doped region.

20. The method for forming a semiconductor structure according to claim 19, wherein: The VDMOS gate structure is formed in the epitaxial layer, and the depth of the VDMOS gate structure is greater than the depth of the body region. The doped region and the VDMOS gate structure are separated from each other.

21. The method for forming a semiconductor structure according to claim 19, wherein: The VDMOS gate structure is formed on the surface of the epitaxial layer; the edge of the body region is flush with the edge of the doped region, or the edge of the body region is closer to the bottom of the VDMOS gate structure than the edge of the doped region.

22. The method for forming a semiconductor structure according to claim 21, wherein: The body region also extends below a portion of the VDMOS gate structure.

23. The method for forming a semiconductor structure according to claim 13, wherein: The BJT device region also includes a fifth region, a sixth region and a seventh region arranged parallel to the surface direction of the substrate, the fifth region and the sixth region are adjacent, and the fifth region and the seventh region are respectively located on both sides of the sixth region; the method for forming the BJT device includes: injecting second conductive ions into the epitaxial layer on the sixth region to form the base region; injecting third conductive ions into the epitaxial layer on the fifth region to form the emitter region; and injecting fourth conductive ions into the epitaxial layer on the seventh region to form the collector region.

24. The method for forming a semiconductor structure according to claim 23, wherein: The second conductive ions are also implanted into the fifth region, the base region is also located in the fifth region, and the depth of the base region is greater than the depth of the emitter region.

25. The method for forming a semiconductor structure according to claim 13, wherein: The substrate has a first surface and a second surface relative to each other, and the epitaxial layer is formed on the first surface; it also includes: forming a conductive structure, the conductive structure includes a VDMOS gate conductive layer located on the surface of the VDMOS gate structure, a source conductive layer located on the surface of the VDMOS source doping region, a first gate conductive layer located on the surface of the first gate structure, a first source conductive layer located on the surface of the first source region, a first drain conductive layer located on the surface of the first drain region, a base conductive layer located on the surface of the base region, an emitter conductive layer located on the surface of the emitter region, and a collector conductive layer located in the collector region; forming a drain conductive layer on the second surface of the substrate.

Images