Process implementation method of novel 3D nano wall (NWaFET) CMOS integrated circuit structure

Abstract

The invention discloses a process implementation method of a novel 3D nano wall (NWaFET) CMOS integrated circuit structure, and relates to the field of microelectronic technology and integrated circuits (IC). According to the process implementation method of the novel 3D nano-wall CMOS integrated circuit structure provided by the invention, based on a silicon plane process, drift regions are added in a source region and a drain region, the short channel effect is inhibited, and longitudinal stacking is carried out, so that the IC integration degree can be improved, and the chip area is saved. According to the invention, the channel length can be greatly reduced, and the channel length can be less than 12nm by using a plane process in combination with the current domestic mature silicon plane process manufacturing procedure, so that the chip integration level is improved.

Description

Technical Field

[0001] The present invention relates to the fields of microelectronics technology and integrated circuits. Background Art

[0002] With the rapid development of integrated circuit technology, since the proposal of Moore's Law [1] , the development of integrated circuits has always followed the principle of scaling down. [2] . As the device size decreases day by day, the principle of equal scaling down begins to face severe challenges. Therefore, many scientific researchers have started to consider improving integrated circuits from other perspectives to continue Moore's Law.

[0003] As traditional planar transistors (Planar MOSFET) encounter performance and power consumption bottlenecks when reducing the size, FinFET technology emerged. [4] FinFET, that is, fin field-effect transistor, the name of the FinFET transistor comes from its shape similar to a fin. Its conductive channel is surrounded by a vertical fin-like structure, thus increasing the gate's control ability over the channel. This technology was officially proposed in a paper by Professor Zhenming Hu of the University of California, Berkeley in 2000. [3] The main channel region of the FinFET is a fin-shaped semiconductor wrapped by a gate. Compared with traditional planar CMOS, the semi-ring gate fin-shaped structure of the FinFET increases the gate's control area over the channel, greatly enhancing the gate control ability, and thus can effectively suppress the short-channel effect. [5] Intel first commercially introduced FinFET at the 22nm process node.

[0004] When the node is further scaled down, for 3nm, 2nm, 1nm after 5nm, new problems will arise, and even the original 3D FinFET transistors that saved Moore's Law will be unable to meet the requirements of the extreme microscopic world. Replacing the fin with a nanosheet has successfully further reduced the short-channel effect brought by smaller sizes. Thus, a brand-new structure emerged - GAA (Gate-All-Around FET). [6] The gate of the GAA transistor completely surrounds the conductive channel, usually in the form of nanowires or nanosheets. This fully surrounded structure provides more efficient current control. At the 7nm and smaller process nodes, FinFET technology begins to face new challenges, and GAA technology is considered the next-generation solution. [7] Companies such as Samsung and TSMC have started using GAA at the 5nm and 3nm process nodes.

[0005] However, GAA devices are limited by lithography accuracy. Lithography accuracy is crucial for manufacturing the nanowire or nanosheet structure in GAA transistors, which directly affects the device's size control and performance characteristics.[8] It is extremely difficult to further shorten the channel and improve device performance.

[0006] A novel 3D nano-wall (NWaFET) CMOS integrated circuit structure proposed by the present invention can reduce the feature size of the silicon planar process to less than 12 nm, and has a good tolerance range for the feature size of the device. A process implementation method for this circuit structure is given. The channel region can be accurately grown by epitaxial technology, and the channel length is no longer limited by the lithography accuracy. The present invention can improve the IC integration degree and save chip area. This invention can greatly reduce the channel length. Combining with the mature silicon planar process in China, the channel length can also be made less than 12 nm using the planar process, improving the chip integration degree.

[0007] References

[0008] [1]. G.E. Moore, "Cramming More Components Onto Integrated Circuits," in Proceedings of the IEEE, vol. 86, no. 1, pp. 82 - 85, Jan. 1998, doi:10.1109 / JPROC.1998.658762.

[0009] [2]. Thompson S, Packan P, Bohr M. MOS scaling: transistor challenges for the 21st century. Intel Technology Journal, 1998; pp 1 - 18.

[0010] [3]. Chenming Hu, Lee W C, Kedzierski J, et al. FinFET - a self - aligned double - gate MOSFET scalable to 20nm [J]. IEEE Transactions on Electron Devices, 2000, 47(12): 2320 - 2325.

[0011] [4]. D.L. Kencke et al., "FinFET Scaling to 10nm Gate Length," 2005 IEEE International Electron Devices Meeting, Washington, DC, 2005, pp. 4.1.1 - 4.1.4.

[0012] [5]. S. Natarajan et al., "A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588μm 2 SRAM cell size," 2014 IEEE International Electron Devices Meeting, San Francisco, CA, 2014, pp. 3.7.1 - 3.7.3.

[0013] [6]. J.P. Colinge, M.H. Gao, A. Romano, H. Maes, C. Claeys. Silicon-on-insulator “gate-all-around” MOS device[C]. 1990 IEEE SOS / SOI Technology Conference. Proceedings. Key West, FL, USA: IEEE, 1990: 137 - 138.

[0014] [7]. L. Chang et al., "GAA FETs: Opportunities and Challenges for Future Technology Scaling," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 29.1.1 - 29.1.4.

[0015] [8]. C. Chen et al., "Advanced lithography techniques for sub-10nm pitch GAA nanowire array patterning," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 5.3.1 - 5.3.4. Summary of the Invention

[0016] Technical solution 1 of the present invention is a process implementation method for a novel 3D nano-wall (NWaFET) CMOS integrated circuit structure, such asFigure 1 As shown, it is characterized in that at the bottom of the structure is a P-type epitaxial wafer 101, and above the P-type epitaxial wafer 101 is an N well 102; Region 103 is a SiO 2 layer; Region 104 is Si 3 N 4 layer; Region 105 is an oxide layer for filling STI isolation trenches; Region 106 is an insulating layer; Region 107 is a Si 3 N 4 layer for metal layer isolation; Region 108 is a tungsten metal layer; Region 109 is an aluminum metal layer and serves as the source of the PMOS; Region 110 is an aluminum metal layer and serves as the drain of the PMOS; Region 111 is an aluminum metal layer and serves as the source of the NMOS; Region 112 is an aluminum metal layer and serves as the lead electrode of the gate; Region 113 is an aluminum metal layer and serves as the drain of the NMOS; Region 114 is the source region of the NMOS; Region 115 is the channel region of the NMOS; Region 116 is the N-lightly doped drain region of the NMOS; Region 117 is the drain region of the NMOS; Region 118 is the drain region of the PMOS; Region 119 is the P-lightly doped drain region of the PMOS; Region 120 is the channel region of the PMOS; Region 121 is the source region of the PMOS; Region 122 is a polysilicon layer and is used as the gate of the device.

[0017] Furthermore, for the novel 3D nanowall CMOS integrated circuit structure, the length range of the P-type channel semiconductor region 115 of the NMOS is 5 nm to 20 nm, and the length range of the N-type channel semiconductor region 120 of the PMOS is 5 nm to 20 nm.

[0018] Furthermore, for the novel 3D nanowall CMOS integrated circuit structure, it is characterized in that the length range of the N+ source region 114 of the NMOS is 50 nm to 200 nm, the length range of the N+ drain region 117 of the NMOS is 5 nm to 20 nm, the length range of the P+ source region 121 of the PMOS is 50 nm to 200 nm, and the length range of the P+ drain region 118 of the PMOS is 5 nm to 20 nm.

[0019] Furthermore, for the novel 3D nanowall CMOS integrated circuit structure, it is characterized in that the length range of the N-lightly doped drain region 116 of the NMOS is 5 nm to 20 nm, and the length range of the P-lightly doped drain region 119 of the PMOS is 5 nm to 20 nm.

[0020] Further, in the novel 3D nano-wall CMOS integrated circuit structure, the doping concentration of the P-type channel semiconductor region 115 of the NMOS is more than one order of magnitude higher than that of the N-lightly doped drain region 116, and the doping concentration of the N-type channel semiconductor region 120 of the PMOS is more than one order of magnitude higher than that of the P-lightly doped drain region 119.

[0021] Further, in the novel 3D nano-wall CMOS integrated circuit structure, the doping concentration of the N+-type source region 114 and the N+-type drain region 117 of the NMOS is more than one order of magnitude higher than that of the P-type channel semiconductor region 115, and the doping concentration of the P+-type source region 121 and the P+-type drain region 118 of the PMOS is more than one order of magnitude higher than that of the N-type channel semiconductor region 120.

[0022] Further, in the novel 3D nano-wall CMOS integrated circuit structure, the doping concentration range of all layers is 1e14 cm -3 -1e22 cm -3 。

[0023] A process implementation method for the novel 3D nano-wall CMOS integrated circuit structure proposed by the present invention can reduce the feature size of the silicon planar process to less than 12 nm. Based on the silicon planar process, the present invention adds a drift region to the source and drain regions to suppress the short-channel effect, and performs vertical stacking to improve the IC integration density and save chip area. This invention can greatly reduce the channel length. Combining with the mature silicon planar process in China, the channel length can also be made less than 12 nm using the planar process, improving the chip integration density. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a novel 3D nano-wall CMOS integrated circuit structure of the present invention.

[0025] Figures 2(a) to 2(z) is a process implementation method for the novel 3D nano-wall CMOS integrated circuit structure of the present invention, which realizes the structure described in Technical Solution 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Embodiment 1: To clearly understand the process implementation method for the novel 3D nano-wall CMOS integrated circuit structure of the present invention, this embodiment specifically introduces the process flow for realizing the structure described in Technical Solution 1.

[0027] The first step, as shown in Fig. 2(a), is a P-epitaxial wafer, and the surface of the wafer is cleaned;

[0028] The second step, as shown in Fig. 2(b), a layer of SiO 2 is grown as a protective layer during the ion implantation process;

[0029] In the third step, as shown in Fig. 2(c), phosphorus ion implantation is carried out, and annealing is carried out after the ion implantation to form an N well;

[0030] In the fourth step, as shown in Fig. 2(d), boron ion implantation is carried out, and annealing is carried out after the ion implantation to form a P+ source region;

[0031] In the fifth step, as shown in Fig. 2(e), a layer of Si with a thickness of about 100 nm is deposited on the wafer surface by using the LPCVD technology 3 N 4 layer;

[0032] In the sixth step, as shown in Fig. 2(f), by using photolithography and etching technologies, an etched STI trench is formed, and a layer of SiO 2 is grown to repair the etching damage on the sidewall of the STI trench;

[0033] In the seventh step, as shown in Fig. 2(g), a layer of oxide is deposited to fill the STI trench for device isolation;

[0034] In the eighth step, as shown in Fig. 2(h), by using the CMP technology, the excess oxide layer is removed to planarize the wafer surface;

[0035] In the ninth step, as shown in Fig. 2(i), by using photolithography and etching technologies, the Si 3 N 4 , SiO 2 layers are etched;

[0036] In the tenth step, as shown in Fig. 2(j), the channel region, lightly doped drain region, and drain region of the PMOS are grown respectively by using the epitaxial process;

[0037] In the eleventh step, as shown in Fig. 2(k), a layer of Si 3 N 4 is deposited as a marking layer;

[0038] In the twelfth step, as shown in Fig. 2(l), by using photolithography and etching technologies, the Si 3 N 4 is etched to form an etched groove for epitaxial growth of the NMOS drain region;

[0039] In the thirteenth step, as shown in Fig. 2(m), a layer of Si 3 N 4 is deposited as a marking layer;

[0040] In the fourteenth step, as shown in Fig. 2(n), a layer of insulating material is deposited for subsequent isolation;

[0041] In the fifteenth step, as shown in Fig. 2(o), by using photolithography and etching technologies, the insulator and Si are etched3 N 4 layers, and the lightly doped drain region, channel region, and source region of the NMOS are grown separately by using an epitaxial process;

[0042] The sixteenth step, as shown in Figure 2(p), is to remove the excess insulating layer by using CMP technology to planarize the wafer surface;

[0043] The seventeenth step, as shown in Figure 2(q), is to etch to form the gate trench of the device by using photolithography and etching technologies, and then grow a gate oxide with a thickness of 3 nm;

[0044] The eighteenth step, as shown in Figure 2(r), is to deposit a polysilicon layer on the gate trench and fill the gate trench. Then, by using CMP technology, the excess polysilicon is removed to planarize the wafer surface;

[0045] The nineteenth step, as shown in Figure 2(s), is to etch the polysilicon gate trench by using photolithography and etching technologies;

[0046] The twentieth step, as shown in Figure 2(t), is to deposit an insulating layer to fill the polysilicon gate trench;

[0047] The twenty-first step, as shown in Figure 2(u), is to remove the excess insulating layer by using CMP technology to planarize the wafer surface;

[0048] The twenty-second step, as shown in Figure 2(v), is to etch the PMOS drain, source, and N-type device drain lead holes by using photolithography and etching technologies;

[0049] The twenty-third step, as shown in Figure 2(w), is to deposit a composite layer of titanium Ti and titanium nitride TiN, and then deposit a layer of metal tungsten (W) to fill the pole lead hole, so that the drain is led out by a tungsten plug;

[0050] The twenty-fourth step, as shown in Figure 2(x), is to remove the excess metal tungsten (W) layer by using CMP technology to planarize the wafer surface;

[0051] The twenty-fifth step, as shown in Figure 2(y), is to deposit a layer of Si 3 N 4 layer as the isolation of the metal layer;

[0052] The twenty-sixth step, as shown in Figure 2(z), is to fill with metal aluminum (Al) to form a connection line, and remove the excess metal by using CMP technology to planarize the wafer surface.

Claims

1. A novel process implementation method for a 3D nano-wall CMOS integrated circuit structure, characterized in that: At the bottom of the structure is a P-type epitaxial wafer 101, and on the top of the P-type epitaxial wafer 101 is an N well 102; region 103 is a SiO2 layer; region 104 is a Si3N4 layer; region 105 is an oxide layer for filling the STI isolation groove; region 106 is an insulating layer; region 107 is a Si3N4 layer for metal layer isolation; region 108 is a metal tungsten layer; region 109 is a metal aluminum layer, which serves as the source of the PMOS; region 110 is a metal aluminum layer, which serves as the drain of the PMOS; region 111 is a metal aluminum layer, which serves as the NMO Region 111 is the source of S; region 112 is a metal aluminum layer and serves as the lead-out electrode of the gate; region 113 is a metal aluminum layer and serves as the drain of NMOS; region 114 is the source region of NMOS; region 115 is the channel region of NMOS; region 116 is the N-lightly doped drain region of NMOS; region 117 is the drain region of NMOS; region 118 is the drain region of PMOS; region 119 is the P-lightly doped drain region of PMOS; region 120 is the channel region of PMOS; region 121 is the source region of PMOS; region 122 is a polysilicon layer and serves as the gate of the device.

2. A novel 3D nano-wall CMOS integrated circuit structure as claimed in claim 1, characterized in that: The length of the P-type channel semiconductor region 115 of the NMOS is in the range of 5 nm to 20 nm, and the length of the N-type channel semiconductor region 120 of the PMOS is in the range of 5 nm to 20 nm.

3. A novel 3D nano-wall CMOS integrated circuit structure as claimed in claim 1, characterized in that: The length of the N+ source region 114 of the NMOS is in the range of 50nm to 200nm, the length of the N+ drain region 117 of the NMOS is in the range of 5nm to 20nm, the length of the P+ source region 121 of the PMOS is in the range of 50nm to 200nm, and the length of the P+ drain region 113 of the PMOS is in the range of 5nm to 20nm.

4. A novel 3D nano-wall CMOS integrated circuit structure as claimed in claim 1, characterized in that: The length of the N-lightly doped drain region 116 of the NMOS is in the range of 5 nm to 20 nm, and the length of the P-lightly doped drain region 119 of the PMOS is in the range of 5 nm to 20 nm.

5. A novel 3D nano-wall CMOS integrated circuit structure as claimed in claim 1, characterized in that: The doping concentration of the P-type channel semiconductor region 115 of the NMOS is more than one order of magnitude higher than that of the N-lightly doped drain region 116 , and the doping concentration of the N-type channel semiconductor region 120 of the PMOS is more than one order of magnitude higher than that of the P-lightly doped drain region 119 .

6. A novel 3D nano-wall CMOS integrated circuit structure as described in claims 1-5, characterized in that: All layers have a doping concentration range of 1e14 cm -3 -1e22 cm -3 .

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