Robot joint GaN array system chip structure and preparation method thereof

Abstract

The invention discloses a robot joint GaN array system chip structure and a preparation method thereof, and relates to the technical field of robot joint driving control, the chip structure comprises three basic units, and each basic unit comprises two HEMT devices; in each basic unit, the source electrode of the first HEMT device is connected with the drain electrode of the second HEMT device through interconnection metal to form an interconnection metal electrode; the three interconnected metal electrodes are respectively used for being connected with three-phase input ports of a robot joint motor; in each basic unit, a SiNx passivation layer is arranged between the two HEMT devices and is used for insulating isolation; the chip structure is integrated on a single wafer to form a GaN matrix chip formed by six HEMT devices. The size of the chip structure is greatly reduced, the cost of packaging and driving circuit design is reduced, and the chip structure has great advantages in high-voltage and high-temperature environments.

Description

Technical Field

[0001] The present invention relates to the technical field of robot joint drive control, and more particularly, to a GaN array system chip structure for robot joints and a preparation method thereof. Background Art

[0002] In recent years, research on GaN (gallium nitride) array system chips in robot joints has received much attention. Especially due to the significant advantages of GaN materials in high-power density, high-frequency, and high-efficiency devices, it shows broad application prospects in fields such as robot drive systems and servo motor control. GaN power devices have higher conversion efficiency and lower switching losses in the robot drive power module, significantly improving the dynamic response speed and energy efficiency of robot joints. Research shows that GaN-based power management chips have advantages in aspects such as voltage conversion, PWM (pulse width modulation) controllers, and DC motor drives, which can effectively reduce the thermal management requirements and improve the system compactness. GaN devices can achieve higher power density within a smaller size, improving the integration of the robot joint control circuit and facilitating modular design. GaN devices exhibit more stable performance in high-temperature environments, with higher breakdown voltage and withstand voltage capabilities, suitable for high-power density scenarios such as industrial robots and medical robotic arms. In recent years, the maturity of GaN-on-Si (silicon-based GaN) technology has further promoted the development of system-on-chip (SoC), which is suitable for compact joint structures such as robot end effectors.

[0003] The existing technology has the following deficiencies: Although GaN devices have higher thermal conductivity, heat dissipation management is still a key issue under high-power density and continuous operation conditions, and further improvement is still needed in packaging design, heat dissipation material selection, and PCB (printed circuit board) layout optimization; at the same time, GaN devices are prone to an increase in dynamic on-resistance and charge trapping effects under high-frequency switching conditions, which may lead to performance degradation and reliability decline. Optimizing device surface passivation and improving packaging stability are still the focus of current research; in addition, although the cost of GaN technology is gradually decreasing, it is still more expensive compared to traditional Si-MOSFETs. Especially, complex packaging and drive circuit designs may increase the overall cost, and an economical GaN solution for robot joint systems is still being explored. Summary of the Invention

[0004] The present invention aims to provide a GaN array system chip structure for robot joints and a preparation method thereof, which can solve the above problems.

[0005] To solve the above problems, the technical solutions adopted by the present invention are as follows: In a first aspect, the present invention provides a GaN array system chip structure for robot joints, including: Three basic units, each basic unit containing two HEMT devices; In each basic unit, the source electrode of the first HEMT device is connected to the drain electrode of the second HEMT device through an interconnecting metal to form an interconnecting metal electrode; The three interconnecting metal electrodes are respectively used to connect to the three-phase input ports of the robot joint motor. By controlling the level of the gate relative to the source of the HEMT device, the turn-off of the HEMT device is controlled, so that the three-phase input ports of the robot joint motor input corresponding switching waveforms to drive the rotation of the robot joint motor.

[0006] In each basic unit, a SiNx passivation layer is provided between the two HEMT devices for insulation isolation; The chip structure is integrated on a single wafer to form a GaN matrix chip composed of six HEMT devices.

[0007] Specifically, the HEMT device includes an AlGaN barrier layer, an AlN layer, a GaN channel layer, a GaN buffer layer and a substrate; the thickness of the AlGaN barrier layer is 20 nm.

[0008] Specifically, the SiNx passivation layer includes a first passivation layer and a second passivation layer, both with a thickness of 300 nm; the first passivation layer covers the surfaces of the source electrode and the drain electrode, and the second passivation layer covers above the first passivation layer.

[0009] Specifically, the HEMT device further includes a gate dielectric layer with a thickness of 20 nm, which is located above the second passivation layer, and a third passivation layer with a thickness of 200 nm and made of SiNx material is deposited above it.

[0010] Specifically, the interconnecting metal electrode is provided with connection holes for connecting to the robot joint motor cable, and the connection holes are square holes with a side length of 1 mm - 5 mm.

[0011] In a second aspect, the present invention provides a preparation method for a chip structure of a robot joint GaN array system, including: Defining the active area through a positive photoresist lithography process, and realizing device isolation by inductively coupled plasma etching; Defining the source and drain electrodes, removing the surface negative photoresist with a plasma asher, then removing the surface oxide with a hydrochloric acid solution, depositing the source and drain electrode metals by electron beam evaporation, and using an ultrasonic instrument to strip the deposited sample with acetone, isopropyl alcohol and water to form the source and drain electrodes, and forming an ohmic contact through high-temperature annealing; Depositing SiNx on the surfaces of the source and drain electrodes by plasma-enhanced chemical vapor deposition to form a first passivation layer; Etching the first passivation layer to expose the source and drain electrodes; On the surface of the first passivation layer, SiNx is deposited by plasma-enhanced chemical vapor deposition to form the second passivation layer; The gate region is etched, and a ferroelectric thin film material is deposited by magnetron sputtering to form a gate dielectric layer; The negative photoresist on the surface of the gate electrode region is removed by a plasma asher, the gate electrode metal is deposited by electron beam evaporation, and the deposited sample is peeled off using acetone, isopropyl alcohol, and water with an ultrasonic instrument to form the gate; SiNx is deposited by plasma-enhanced chemical vapor deposition to form the third passivation layer; The source, drain, and gate regions are etched, the interconnect metal is deposited by electron beam evaporation, and the sample with the deposited interconnect metal is peeled off using acetone, isopropyl alcohol, and water with an ultrasonic instrument to obtain an interconnect metal electrode with the source and drain connected together.

[0012] Specifically, when depositing the source-drain electrode metal, the metals used from bottom to top are Ti, Al, Ni, and Au in sequence, with thicknesses of 20, 130, 50, and 100 nm respectively, and the deposition rates of the source and drain metals are 0.05 nm / s, 0.1 nm / s, 0.08 nm / s, and 0.11 nm / s respectively.

[0013] Specifically, when depositing the gate electrode metal, the metals used from bottom to top are Ni and Au in sequence, and the thicknesses of Ni and Au are 100 nm and 200 nm respectively, and the deposition rate is 0.1 nm / s for both.

[0014] Specifically, the deposition conditions for the first passivation layer, the second passivation layer, and the third passivation layer are all: the NH3 / SiH4 flow ratio is 100 / 55 sccm, the temperature is 270 °C, the RF power is 60 W, and the chamber pressure is 200 mTorr.

[0015] Specifically, when depositing the interconnect metal, the metals used from bottom to top are Ni and Au in sequence, the deposition thicknesses are 150 nm and 400 nm respectively, and the deposition rates are 11.5 nm / s and 1.5 nm / s respectively.

[0016] Compared with the prior art, the beneficial effects of the present invention are: The present invention generates a GaN matrix chip composed of 6 identical HEMT devices on a single wafer and realizes the connection of the robot joint motor ports. Compared with the traditional single-chip packaging of chips, the chip structure volume of the present invention is reduced by 10 times, reducing the cost of packaging and driving circuit design; at the same time, compared with the traditional Si-based and GaAs-based HEMT devices, the present invention grows a thick SiN insulating material between two different HEMT devices in a single unit. Therefore, there are greater advantages in high-voltage and high-temperature environments.

[0017] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically gives embodiments of the present invention and, in conjunction with the accompanying drawings, provides a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0019] Figure 1 is a top view schematic diagram of the basic unit of the GaN array system chip for a robot joint; Figure 2 is a cross-sectional schematic diagram of the basic unit of the GaN array system chip for a robot joint; Figure 3 is a schematic diagram of the structure of the GaN array system chip for a robot joint.

[0020] In the figure: 1, basic unit; 2, first electrode contact; 3, second electrode contact; 4, first metal electrode; 5, second metal electrode; 6, chip package SiNx passivation layer; 7, semiconductor layer; 8, third passivation layer; 9, AlGaN barrier layer; 10, source of the first HEMT device; 11, gate of the first HEMT device; 12, drain of the first HEMT device; 13, source of the second HEMT device; 14, gate of the second HEMT device; 15, drain of the second HEMT device; 16, via hole; 17, interconnecting metal electrode; 18, first passivation layer; 19, second passivation layer; 20, gate dielectric layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] To make the objects, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention.

[0022] As Figure 3 shown, the embodiments of the present invention describe a structure of a GaN array system chip for a robot joint. The chip includes three basic units 1, and each basic unit 1 has a first electrode contact 2 and a second electrode contact 3. The first electrode contacts 2 of the three basic units 1 are connected together through an interconnecting metal to form a first metal electrode 4, and the second electrode contacts 3 of the three basic units 1 are connected together through an interconnecting metal to form a second metal electrode 5.

[0023] For each basic unit 1, a first HEMT device and a second HEMT device are formed, and three basic units 1 include six identical HEMT devices.

[0024] For each basic unit 1, the drain 12 of its first HEMT device serves as its first electrode contact 2, and the source 13 of its second HEMT device serves as its second electrode contact 3.

[0025] For each basic unit 1, the source 10 of its first HEMT device and the drain 15 of its second HEMT device are interconnected to form an interconnected metal electrode 17.

[0026] When the above chip structure is integrated on a single wafer, a GaN matrix chip composed of six HEMT devices is formed, and a chip package SiNx passivation layer 6 is provided between the basic units 1.

[0027] Three interconnected metal electrodes 17 are all provided with connection holes 16, which are respectively used to connect to the three-phase input U port, V port, and W port of the robot joint motor through cables. By controlling the level of the gate of the HEMT device relative to the source, the turn-off of the HEMT device can be controlled, so that the U, V, and W ports input corresponding switching waveforms to drive the robot joint motor to rotate, realizing the function of the robot joint GaN array system chip.

[0028] The following combines Figure 1 and Figure 2 to make a detailed description of the basic unit 1.

[0029] The basic unit 1 includes a semiconductor layer 7 and a third passivation layer 8.

[0030] As Figure 2 shown, the semiconductor layer 7 is the region where two-dimensional electron gas flows. It includes an AlGaN barrier layer 9, a GaN channel layer, a GaN buffer layer, an AlN layer, and a substrate. The GaN channel layer, GaN buffer layer, AlN layer, and substrate in the semiconductor layer 7 are not separately marked in Figure 2 , and they are located directly below the AlGaN barrier layer 9. From top to bottom, they are the GaN channel layer, GaN buffer layer, AlN layer, and substrate; the thickness of the AlGaN barrier layer 9 in the semiconductor layer 7 is 20 nm.

[0031] The third passivation layer 8 is located at the top of the basic unit 1 (it should be noted that the drain metal, gate metal, and source metal all protrude above the third passivation layer 8), and its thickness is 200 nm, as Figure 2 shown.

[0032] Most of the drain 12 of the first HEMT device, the source 10 of the first HEMT device, the drain 15 of the second HEMT device, and the source 13 of the second HEMT device are located above the AlGaN barrier layer 9, and a small part of the extreme metal diffuses into the AlGaN barrier layer 9 through high-temperature annealing; the metal thickness of the source and the drain is 300 nm each.

[0033] The source 10 of the first HEMT device and the drain 15 of the second HEMT device are interconnected to form an interconnected metal electrode 17, and a connection hole 16 is opened in the interconnected metal electrode 17 for connection with the three-phase input port of the robot joint motor through a cable.

[0034] In this embodiment, the connection hole 16 is a square hole with a side length of 1 mm - 5 mm. Different side lengths correspond to different internal resistances of the interconnected metal electrode 17, as Figure 1 shown.

[0035] To prevent current conduction between the source 10 of the first HEMT device and the drain 15 of the second HEMT device, a first passivation layer 18 (SiNx layer) is grown on the surfaces of the drain 12 of the first HEMT device, the source 10 of the first HEMT device, the drain 15 of the second HEMT device, and the source 13 of the second HEMT device, thereby forming an insulating layer between the source 10 of the first HEMT device and the drain 15 of the second HEMT device, as Figure 2 shown; the thickness of the first passivation layer 18 is the same as the depth of the device isolation etching, both being 300 nm.

[0036] Further insulation treatment is carried out to grow a second passivation layer 19 (SiNx layer); the second passivation layer 19 is located above the first passivation layer 18 and has a thickness of 300 nm, as Figure 2 shown.

[0037] The present invention introduces a gate dielectric layer 20 to form a metal-insulator-semiconductor (MIS) structure. The gate dielectric layer 20 is a ferroelectric thin film material. When a negative polarization voltage is applied to the gate, as the polarization voltage increases, a depolarization field appears in the gate dielectric layer 20, and the electrons in the channel gradually transfer to the ferroelectric thin film interface, that is, the threshold voltage moves in the positive direction, and the two-dimensional electron gas layer channel tends to be completely depleted by the ferroelectric polarization engineering, finally realizing an enhancement-type device.

[0038] The gate dielectric layer 20 is located above the second passivation layer 19 and forms a groove at the gate; the thickness of the gate dielectric layer 20 is 20 nm.

[0039] After the gate metal evaporation, the gate 11 of the first HEMT device and the gate 14 of the second HEMT device are obtained. At the same time, in order to reduce the possible leakage between the gate 11 of the first HEMT device and the gate 14 of the second HEMT device, the third time of the present invention grows a SiNx passivation layer on the outermost periphery to obtain the third passivation layer 8 with a thickness of 200 nm.

[0040] The preparation process of the robot joint GaN array system chip structure described in this embodiment includes the following steps: (1)Device isolation After defining the active region of the device rough sample through positive photolithography, the AlGaN barrier layer 9, GaN channel layer, and GaN buffer layer outside the active region are removed by inductively coupled plasma etching to achieve device isolation, and the etching depth is about 300 nm.

[0041] (2)Source and drain electrode preparation Through negative photolithography, the source and drain electrodes are defined in the device isolation and weak device isolation regions of the device rough sample. The surface negative photoresist is removed by a plasma asher, and then the surface oxide is removed by a hydrochloric acid solution (in this solution, HCL:H2O = 1:10). Finally, the source and drain electrode metals are deposited by electron beam evaporation. The metals used are Ti, Al, Ni, and Au from bottom to top, with thicknesses of 20, 130, 50, and 100 nm respectively, and the deposition rates are 0.05 nm / s, 0.1 nm / s, 0.08 nm / s, and 0.11 nm / s respectively. The deposited sample is peeled off using an ultrasonic instrument (70 °C, 10 min) with acetone, isopropyl alcohol, and water to form the source electrode 10 of the first HEMT device, the drain electrode 12 of the first HEMT device, the source electrode 13 of the second HEMT device, and the drain electrode 15 of the second HEMT device, as Figure 2 shown. Finally, the rough sample is subjected to high-temperature rapid annealing using a high-temperature annealing furnace (875 °C, 30 s) to form an ohmic contact between the source and drain electrodes and the AlGaN barrier layer 9.

[0042] (3)Grow the first passivation layer 18 On the surfaces of the AlGaN barrier layer 9, the source electrode 10 of the first HEMT device, the drain electrode 12 of the first HEMT device, the source electrode 13 of the second HEMT device, and the drain electrode 15 of the second HEMT device of the device rough sample, SiNx is deposited by plasma-enhanced chemical vapor deposition (NH3 / SiH4 is 100 / 55 sccm, temperature is 270 °C, radio frequency power is 60 W, and chamber pressure is 200 mTorr) to form the first passivation layer 18, and the thickness of the first passivation layer 18 is 300 nm.

[0043] (4)RIE etch the first passivation layer 18 on the surface of the source and drain electrodes; On the rough sample of the device, through the positive photoresist lithography process, etch regions for the source electrode 10 of the first HEMT device, the drain electrode 12 of the first HEMT device, the source electrode 13 of the second HEMT device, and the drain electrode 15 of the second HEMT device are defined. The rough sample with the defined etch regions is placed in a reactive ion etching instrument for passivation layer etching (etching time is 300S, etching rate is 1nm / s), so that regions without the passivation layer are exposed for the source electrode 10 of the first HEMT device, the drain electrode 12 of the first HEMT device, the source electrode 13 of the second HEMT device, and the drain electrode 15 of the second HEMT device, as Figure 2 shown.

[0044] (5)Grow the second passivation layer 19 On the surface of the first passivation layer 18 of the rough sample of the device, SiNx is deposited by plasma enhanced chemical vapor deposition method (NH3 / SiH4 is 100 / 55sccm, temperature is 270℃, radio frequency power is 60W, chamber pressure is 200mTorr) to form the second passivation layer 19. The thickness of the second passivation is the same as that of the first passivation layer 18, both are 300nm.

[0045] (6)Open the gate On the rough sample of the device through the positive photoresist lithography process, etch regions for the gate electrode are defined. The rough sample with the defined etch regions is placed in a reactive ion etching instrument for passivation layer etching (etching time is 600S, etching rate is 1nm / s), and a rough sample of the device with an opening at the gate electrode position is obtained.

[0046] (7)Grow the gate dielectric layer On the surface of the rough sample of the device with the gate electrode opening, a ferroelectric thin film material is deposited by magnetron sputtering to form the gate dielectric layer 20. The thickness of the gate dielectric layer 20 is 20nm.

[0047] (8)Fabricate the gate metal In the gate opening region of the rough sample of the device through the negative photoresist lithography process, the gate electrode is defined. The surface negative photoresist is removed by a plasma asher, and then the gate electrode metal is deposited by electron beam evaporation. The metals used are Ni and Au from bottom to top. The thicknesses of Ni and Au are 100 nm and 200nm respectively, and the deposition rates are both 0.1nm / s. The deposited sample is peeled off using an ultrasonic instrument (70℃, 10min) with acetone, isopropyl alcohol and water to form the gate 11 of the first HEMT device and the gate 14 of the second HEMT device, as Figure 2 shown in.

[0048] (9)Grow the third passivation layer 8 On the surface of the device prototype where the gate metal has been prepared, SiNx is deposited by plasma-enhanced chemical vapor deposition (NH3 / SiH4 is 100 / 55 sccm, temperature is 270 °C, radio frequency power is 60 W, and chamber pressure is 200 mTorr) to form the third passivation layer 8. The thickness of the third passivation layer 8 is 100 nm less than that of the first passivation layer 18 and the second passivation layer 19, being 200 nm.

[0049] (10)Source-drain-gate opening On the device prototype, the etching regions of the source, drain, and gate are defined through a positive photoresist lithography process. The sample with the defined etching regions is placed in a reactive ion etching instrument for passivation layer etching. The etching time is 600 s and the etching rate is approximately 1 nm / s, obtaining a device prototype with source-drain-gate openings.

[0050] (11)Field plate fabrication On the device prototype, the source, drain, and gate interconnection regions are defined through a negative photoresist lithography process. Then, the surface negative photoresist is removed using a plasma asher. The interconnection metal electrode 17 is deposited by electron beam evaporation. The metals used are Ni and Au from bottom to top, with thicknesses of 150 nm and 400 nm respectively, and deposition rates of 11.5 nm / s and 1.5 nm / s respectively. Using an ultrasonic instrument (70 °C, 10 min), the sample with the deposited interconnection metal is peeled off using acetone, isopropyl alcohol, and water, obtaining the interconnection metal electrode 17 where the source 10 of the first HEMT device and the drain 15 of the second HEMT device are connected together. The interconnection metal electrode 17 is provided with a connection hole 16 for connection to the robot joint motor through a cable, as Figure 1 and Figure 2 shown.

[0051] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A GaN array system chip structure for robot joints, characterized in that: include: Three basic units, each containing two HEMT devices; In each basic unit, the source of the first HEMT device is connected to the drain of the second HEMT device through an interconnecting metal to form an interconnecting metal electrode; The three interconnected metal electrodes are respectively used to connect to the three-phase input ports of the robot joint motor, so as to control the shutdown of the HEMT device by controlling the level of the gate of the HEMT device relative to the source, so that the three-phase input port of the robot joint motor inputs a corresponding switching waveform to drive the robot joint motor to rotate; In each basic unit, a SiNx passivation layer is provided between two HEMT devices for insulation isolation; The chip structure is integrated on a single wafer to form a GaN matrix chip consisting of six HEMT devices.

2. The GaN array system chip structure for robot joints according to claim 1 is characterized in that: The HEMT device comprises an AlGaN barrier layer, an AlN layer, a GaN channel layer, a GaN buffer layer and a substrate; the thickness of the AlGaN barrier layer is 20 nm.

3. The robot joint GaN array system chip structure according to claim 1 or 2, characterized in that: The SiNx passivation layer includes a first passivation layer and a second passivation layer, both of which have a thickness of 300 nm; the first passivation layer covers the surface of the source and drain electrodes, and the second passivation layer covers the first passivation layer.

4. The GaN array system chip structure for robot joints according to claim 2 is characterized in that: The HEMT device further includes a gate dielectric layer with a thickness of 20 nm, which is located above the second passivation layer, and a third passivation layer deposited from SiNx material with a thickness of 200 nm is disposed above the gate dielectric layer.

5. The GaN array system chip structure for robot joints according to claim 1 is characterized in that: The interconnected metal electrodes are provided with connection holes for connecting to the robot joint motor cables, and the connection holes are square holes with a side length of 1mm-5mm.

6. A method for preparing a GaN array system chip structure for a robot joint, characterized in that: include: The active area is defined by positive photolithography, and device isolation is achieved by inductively coupled plasma etching; Define the source and drain electrodes, remove the surface negative resist with a plasma stripper, then remove the surface oxide with a hydrochloric acid solution, deposit the source and drain electrode metals using electron beam evaporation, use an ultrasonic instrument to peel off the deposited samples with acetone, isopropanol and water to form source and drain electrodes, and form ohmic contacts through high temperature annealing; On the surface of the source and drain, SiNx is deposited by plasma enhanced chemical vapor deposition to form a first passivation layer; Etching the first passivation layer to expose the source and drain electrodes; On the surface of the first passivation layer, SiNx is deposited by a plasma enhanced chemical vapor deposition method to form a second passivation layer; etching the gate region and depositing a ferroelectric thin film material by magnetron sputtering to form a gate dielectric layer; The negative resist on the surface of the gate electrode region is removed by a plasma stripper, the gate electrode metal is deposited by electron beam evaporation, and the deposited sample is stripped by an ultrasonic instrument using acetone, isopropyl alcohol and water to form a gate; Depositing SiNx by plasma enhanced chemical vapor deposition to form a third passivation layer; The source, drain and gate regions are etched, and interconnect metal is deposited using electron beam evaporation. The samples with interconnect metal deposition are stripped using acetone, isopropyl alcohol and water using an ultrasonic instrument to obtain an interconnect metal electrode connecting the source and drain.

7. The preparation method according to claim 6, characterized in that: When depositing the source and drain electrode metals, the metals used are Ti, Al, Ni and Au from bottom to top, with thicknesses of 20, 130, 50 and 100 nm respectively. The source and drain metal deposition rates are 0.05 nm / s, 0.1 nm / s, 0.08 nm / s and 0.11 nm / s respectively.

8. The preparation method according to claim 6, characterized in that: When depositing the gate electrode metal, the metals used are Ni and Au from bottom to top, and the thicknesses of Ni and Au are 100 nm and 200 nm respectively, and the deposition rates are both 0.1 nm / s.

9. The preparation method according to claim 6, characterized in that: The deposition conditions of the first passivation layer, the second passivation layer and the third passivation layer are: NH3 / SiH4 flow ratio of 100 / 55sccm, temperature of 270°C, RF power of 60W, and chamber pressure of 200mTorr.

10. The preparation method according to claim 6, characterized in that: When depositing interconnect metal, the metals used are Ni and Au from bottom to top, with deposition thicknesses of 150 nm and 400 nm, respectively, and deposition rates of 11.5 nm / s and 1.5 nm / s, respectively.

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