Electrostatic discharge protection structure, preparation method thereof and electronic equipment

Abstract

The invention relates to an electrostatic discharge protection structure and a preparation method thereof, and electronic equipment, and the method comprises the steps: providing a substrate which comprises a first type well region which extends along a first direction facing the substrate through a first surface of the substrate; the first type well region comprises isolation structures which are distributed at intervals along a second direction parallel to the first surface; gate structures which are arranged at intervals are formed between any adjacent isolation structures; removing a part of the first type well region to obtain a first groove between the gate structure and the isolation structure and a second groove between the gate structures; performing an ion implantation process on the first type well region to form a first type doped region and a second type doped region; wherein the first type doped region is located between the adjacent isolation structures, and the second type doped region surrounds the surfaces, making contact with the first type well region, of the first groove and the second groove. Under the condition that the layout area is not changed, the source and drain terminal Trench structure is realized, and the junction area of the source and drain terminals and the well region is increased, so that the ESD protection level of the GGNMOS is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to an electrostatic discharge protection structure, a preparation method thereof, and an electronic device. Background Art

[0002] ESD (Electrostatic Discharge) refers to the phenomenon of charge transfer and energy release caused by the mutual approach or direct contact of objects with different electrostatic potentials, which often occurs during the production, assembly, testing, storage, handling, etc. of integrated circuits. When the electrostatic charges accumulated in the human body, instruments, equipment or components are relatively large, transient currents of up to several tens of amperes and voltage surges of kilovolts can be generated, causing damage to electronic components or systems.

[0003] Common ESD devices include Diode, MOS&BJT (Metal-Oxide-Semiconductor Field-Effect Transistor and Bipolar Junction Transistor), SCR (Silicon Controlled Rectifier), etc. Among them, Grounded-gate N-metal-oxide-semiconductor (GGNMOS) is widely used in ESD protection circuits because of its good CMOS process compatibility, relatively simple process, and good Snapback characteristics.

[0004] With the progress of process technology, the reduction of the chip feature size has continuously compressed the design window of ESD protection devices, posing higher requirements for the protection performance of electrostatic discharge protection devices. Therefore, how to effectively improve the ESD protection performance of GGNMOS without increasing the occupied area has become one of the urgent problems to be solved in this field. Summary of the Invention

[0005] Based on this, in view of the technical problems in the prior art, it is necessary to provide an electrostatic discharge protection structure, a preparation method thereof, and an electronic device, which can at least effectively improve the ESD protection performance of GGNMOS without increasing the occupied area.

[0006] In a first aspect, the present application provides a method for preparing an electrostatic discharge protection structure, providing a substrate, the substrate including a first-type well region extending along a first direction toward a first surface of the substrate; the first-type well region includes isolation structures spaced apart along a second direction parallel to the first surface;

[0007] Form gate structures arranged at intervals along the second direction between any adjacent isolation structures;

[0008] Remove a part of the first-type well region to obtain a first trench located between the gate structure and the isolation structure, and a second trench located between adjacent gate structures;

[0009] An ion implantation process is performed on the first-type well region to form a first-type doped region and a second-type doped region; wherein, the first-type doped region is located between adjacent isolation structures, and the second-type doped region surrounds the surfaces of the first trench and the second trench in contact with the first-type well region.

[0010] In the method for manufacturing the electrostatic discharge protection structure in the above embodiments, a first trench and a second trench are added to the traditional GGNMOS structure, and by forming a second-type doped region that surrounds the surfaces of the first trench and the second trench in contact with the first-type well region, the contact area between the second-type doped region and the first-type well region is longitudinally deepened. While increasing its PN junction area, the current is effectively dispersed, preventing the current from concentrating on the device surface, significantly increasing the threshold of the second breakdown current, and enhancing the reliability of the device.

[0011] In some embodiments, the isolation structure extends into the first-type well region via the first surface; the depth of the isolation structure in the first direction is less than the depth of the first-type well region in the first direction.

[0012] In some embodiments, the opening size of the second trench in the second direction is greater than the opening size of the first trench in the second direction.

[0013] In some embodiments, the depth of the first-type doped region in the first direction is less than the depth of the isolation structure in the first direction;

[0014] The depth of the second-type doped region in the first direction is less than the depth of the first-type doped region in the first direction.

[0015] In some embodiments, the gate structure includes sidewall structures arranged at intervals in the second direction, and a gate layer located between adjacent sidewall structures.

[0016] In some embodiments, the second-type doped region includes a source doped region and a drain doped region; wherein, the source doped region is disposed in the first trench, and the drain doped region is disposed in the second trench;

[0017] The size of the drain doped region in the second direction is less than the spacing between adjacent sidewall structures in the first direction.

[0018] In some embodiments, a blocking layer is formed in the second trench; the blocking layer covers the inner sidewalls and part of the bottom surface of the second trench, and extends to the outer surface of the gate structure;

[0019] A self-aligned silicide layer is formed on the exposed top surface of the substrate and the top surface of the gate structure;

[0020] A dielectric layer is formed to cover the substrate, the self-aligned silicide layer, and the blocking layer;

[0021] After forming a contact hole extending in a first direction to a self-aligned silicide layer within a dielectric layer, a contact plug is formed within the contact hole; wherein, the bottom surface of the contact plug is within the top surface of the self-aligned silicide layer.

[0022] In some embodiments, the conduction type of the first type of characterization is different from the conduction type of the second type of characterization.

[0023] In a second aspect, the present application further provides an electrostatic discharge protection structure prepared by using the preparation method of any of the above embodiments.

[0024] In a third aspect, the present application further provides an electronic device, including an electrostatic discharge protection structure prepared by using the preparation method of any of the above embodiments; or including the electrostatic discharge protection device of the above embodiment.

[0025] The electrostatic discharge protection structure, its preparation method, and the electronic device provided by the present application have the following unexpected technical effects:

[0026] By adding a Trench structure, the junction areas of the source doping region, the drain doping region, and the first-type well region, and the base region area of the parasitic lateral NPN are changed, such that the β value of the parasitic lateral NPN increases, the trigger voltage V t1 decreases, and the failure current I t2 increases. Among them, the reduced trigger voltage enables the electrostatic discharge protection structure to respond to ESD pulses faster and start conducting and discharging current at a lower voltage. And the increase in the failure current I t2 means that the device can withstand a larger ESD current and will not easily suffer from thermal breakdown damage. At the same time, the increase in the drain doping region area also increases the heat dissipation area of the electrostatic discharge protection structure.

[0027] Therefore, the electrostatic discharge protection structure prepared based on this preparation method can expand the ESD design window of GGNMOS, enhance the overall ESD protection level of the electronic device, improve the reliability and durability of the circuit, and provide a more flexible and secure option for the design of integrated circuits without sacrificing area efficiency. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1 It is a cross-sectional schematic diagram of an electrostatic discharge protection structure provided in the prior art;

[0030] Figure 2 Flow chart of a method for fabricating an electrostatic discharge protection structure provided in an embodiment;

[0031] Figure 3 Cross-sectional schematic view of the resulting structure after forming the gate structure 30 in step S104 of the method for fabricating an electrostatic discharge protection structure provided in an embodiment;

[0032] Figure 4 Cross-sectional schematic view of the resulting structure after forming the trench in step S106 of the method for fabricating an electrostatic discharge protection structure provided in an embodiment;

[0033] Figure 5 Cross-sectional schematic view of the resulting structure after forming the trench in step S108 of the method for fabricating an electrostatic discharge protection structure provided in an embodiment;

[0034] Figure 6 For Figure 5 Cross-sectional schematic view of the resulting structure after forming the barrier layer;

[0035] Figure 7 For Figure 6 Cross-sectional schematic view of the resulting structure after forming the self-aligned silicide layer;

[0036] Figure 8 For Figure 7 Cross-sectional schematic view of the resulting structure after forming the dielectric layer;

[0037] Figure 9 For Figure 8 Cross-sectional schematic view of the resulting structure after forming the contact hole;

[0038] Figure 10 For Figure 9 Cross-sectional schematic view of the resulting structure after forming the contact plug;

[0039] Figure 11 Cross-sectional schematic view of an electrostatic discharge protection structure provided in an embodiment.

[0040] Explanation of reference numerals:

[0041] 10. Substrate; 101. First-type substrate; 102. First-type well region; 20. Isolation structure; 30. Gate structure; 301. Gate layer; 302. Sidewall structure; 41. First trench; 42. Second trench; 51. First-type doped region; 52. Second-type doped region; 521. Source doped region; 522. Drain doped region; 11. Barrier layer; 12. Self-aligned silicide layer; 13. Dielectric layer; 601. Contact hole; 60. Contact plug. Detailed implementation manners

[0042] To facilitate the understanding of the present application, the present application will be described more comprehensively with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0044] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0045] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also include other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0046] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, and such variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0048] In an embodiment of the present application, the substrate may include a first surface on the front side and a back side opposite the front side, i.e., a second surface. Ignoring the flatness of the first surface and the second surface, a second direction parallel to the first surface is defined, and the direction towards the substrate includes a first direction perpendicular to the first surface of the substrate. For example, the arrangement direction of the isolation structure is the second direction. Among them, the first direction and the second direction are perpendicular to each other. In an embodiment of the present application, the first direction is defined as the X-axis direction, and the second direction is defined as the Y-axis direction.

[0049] Figure 1 For a conventional GGNMOS with a self-aligned silicide layer, in this structure, the gate structure is connected to a low level at the substrate lead-out end, and the drain end is connected to a high level. During ESD protection, the bipolar conduction mode of the internal parasitic NPN transistor is used for discharging.

[0050] To prevent local damage to the metal silicide, a barrier layer is often used to cover the stepped surface formed by the gate structure at the drain end and the substrate. However, this will cause the current to concentrate on the surface, resulting in premature electrostatic protection failure of the device.

[0051] Based on this, please refer to Figure 2 , this application provides a method for preparing an electrostatic discharge protection structure, including: step S102 - step S108.

[0052] Step S102: Provide a substrate 10, the substrate 10 includes a first-type well region 102 extending along the OX direction of the first surface of the substrate 10; the first-type well region 102 includes isolation structures 20 distributed at intervals along the OY direction parallel to the first surface.

[0053] Wherein, the substrate 10 includes a first-type well region 102 and a first-type substrate 101 arranged in sequence along the OX direction. As an example, the first-type substrate 101 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The first-type substrate 101 can be a single-layer structure or a multi-layer structure. For example, the first-type substrate 101 can be a III / V semiconductor or II / VI semiconductor material such as silicon (Si), gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), germanium (Ge), or others. Or, for another example, the first-type substrate 101 can be a layered substrate including, for example, Si / SiGe, Si / SiC, Silicon on Insulator (SOI), or silicon germanium on insulator. Therefore, the type of the first-type substrate 101 should not limit the protection scope of the present disclosure. The material of the first-type well region 102 can be the same as or different from that of the first-type substrate 101. In this application, the material of the first-type well region 102 includes silicon (Si).

[0054] As an example, the material of the isolation structure 20 can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof. It is mainly used to isolate electrons. As an example, the cross-sectional shape of the 20 isolation structure along the OY direction can include a positive trapezoid, an inverted trapezoid, a rectangle, etc., or a combination of shapes such as a positive trapezoid, an inverted trapezoid, a rectangle, etc. In the embodiments of this application, the isolation structure 20 only needs to be able to isolate electrons. In addition, the distance between adjacent isolation structures is not specifically limited and can be set according to actual needs.

[0055] Among them, the first type and the second type are used to characterize the conduction type. In the present application, the conduction type characterized by the first type is the P type, and the conduction type characterized by the second type is the N type. Of course, the conduction types of the first type and the second type can also be exchanged as long as the conduction types of the two are different.

[0056] Further, the first-type substrate 101 is used for mechanical support, denoted as P-sub, and a first-type well region 102 is formed in the substrate 10, denoted as PWL.

[0057] Step S104: Form gate structures 30 arranged at intervals along the OY direction between any adjacent isolation structures 20.

[0058] Step S106: Remove part of the first-type well region 102 to obtain a first trench 41 located between the gate structure 30 and the isolation structure 20, and a second trench 42 located between the gate structures.

[0059] As an example, the gate structure 30 includes a gate layer 301 and a sidewall structure 302. Among them, the material of the gate layer 301 includes, but is not limited to, metal conductive materials such as gold (Au), copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), etc., and heavily doped polysilicon can also be used. The material of the sidewall structure 302 includes, but is not limited to, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), or strontium titanate oxide (SrTiO 3 ), etc.

[0060] Step S108: Perform an ion implantation process on the first-type well region 102 to form a first-type doped region 51 and a second-type doped region 52; among them, the first-type doped region 51 is located between adjacent isolation structures 20, and the second-type doped region 52 surrounds the surfaces of the first trench 41 and the second trench 42 in contact with the first-type well region 102.

[0061] As an example, the second-type doped region 52 includes a drain doped region 522 surrounding the first trench 41 and a source doped region 521 surrounding the second trench 42.

[0062] Among them, the electrostatic discharge protection structure obtained after steps S102 - S108 can be referred to Figure 10 . Of course, for the convenience of understanding the present application, Figure 10Shown is an example of an electrostatic discharge protection structure prepared by the preparation method of the present application. There can be other suitable examples of the electrostatic discharge protection structure prepared by the preparation method of the present application, and the present application does not limit them here.

[0063] It should be understood that although Figure 1 the steps in the flowchart of Figure 1 are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order restriction, and these steps can be executed in other orders. Moreover,

[0064] Please refer to Figure 3 , in some embodiments, executing step S102 includes:

[0065] Step S1022: Form a first-type well region 102 along the OX direction via the first surface in the substrate 10;

[0066] Step S1024: Form an isolation structure 20 extending into the first-type well region 102 along the OX direction via the first surface.

[0067] Specifically, a photoresist can be coated on the first-type well region 102 first, and through a series of steps such as exposure and development, a patterned photoresist layer using the Self-Aligned Double Patterning (abbreviated as SADP) process or the Self-Aligned Quadruple Patterning (abbreviated as SAQP) process can be used to define the position and shape of the trench, and any one of the wet etching method or the dry etching method can be used to form the trench, and then the trench is filled and a planarization process is performed to form the isolation structure 20.

[0068] Among them, the first-type well region 102 is used for isolating and protecting the electrostatic discharge protection structure provided by the application embodiment.

[0069] Please continue to refer to Figure 3 , in some embodiments, executing step S104 further includes: forming a gate structure 30 between any adjacent isolation structures 20, where the gate structure 30 includes sidewall structures 302 arranged at intervals along the OY direction and a gate layer 301 located between the sidewall structures 302.

[0070] Specifically, after forming the gate layer 301, an oxide dielectric layer covering the gate layer 301 is deposited, and an anisotropic dry etching is used to etch back to form the sidewall structure 302. The specific structure is as Figure 1 shown.

[0071] In this embodiment, the sidewall structure 302 is a single-layer structure.

[0072] Please refer to Figure 4 , in some embodiments, performing step S106 further includes:

[0073] Based on the gate structure 30, Figure 1 the semiconductor structure shown is subjected to plasma cleaning and etching (Plasma Cleaning and Etching Technology, PCI-ET). PCI-ET can be extended to LDMOS. In this process, the plasma can be used to remove surface contaminants and unwanted materials, and at the same time, the plasma etching technology is used to precisely control the formation of specific structures - the first trench 41 and the second trench 42.

[0074] Among them, since the electrostatic discharge protection structure provided in this application is symmetric about the center line of the second trench, and the structures on the left and right sides of the center line are both discharged through the parasitic NPN triode, the opening size of the second trench 42 in the OY direction needs to be greater than the opening size of the first trench in the OY direction.

[0075] Please refer to Figure 5 , in some embodiments, performing step S108 further includes:

[0076] Doping ions such as phosphorus (P), arsenic (As), and antimony (Sb) are used to form the second-type doping region 52; doping ions such as boron (B), aluminum (Al), and gallium (Ga) are used to form the first-type doping region 51. Among them, the doping concentration of the first-type doping region 51 is greater than the doping concentration of the first-type well region 102, denoted as P+, and is used to lead out the potential of the substrate 10; the second-type doping region 52 includes a source doping region 521 and a drain doping region 522, both denoted as N+, and are used to form PN junctions with the first-type well region 102 respectively.

[0077] In this embodiment, the body electrode is disposed on the first-type doping region 51, the gate terminal electrode is disposed on the gate structure 30, the source terminal electrode is disposed on the source doping region 521, and the drain terminal electrode is disposed on the drain doping region 522. In its equivalent circuit, the source doping region 521 disposed in the first trench 41 forms the collector of the parasitic triode in the GGNMOS; the drain doping region 522 disposed in the second trench 42 forms the emitter of the parasitic triode in the GGNMOS.

[0078] It should be noted that the depth of the first-type doping region 51 along the OX direction is less than the depth of the isolation structure 20 along the OX direction; the depth of the second-type doping region 52 along the OX direction is less than the depth of the first-type doping region 51 along the OX direction, and the size of the drain doping region 522 along OY is less than the spacing of the adjacent sidewall structure 302 along the OY direction.

[0079] The above structure limitations can ensure that the doping regions (such as the source or drain doping regions) do not extend too deep and break through the isolation structure 20, prevent the formation of additional conductive paths between different functional regions, avoid the mutual influence of electrical characteristics, and damage the normal function of the entire circuit. At the same time, it reduces the leakage risk caused by the drain doping region being too close to the channel region during the electron transport process.

[0080] Please refer to Figures 6 - 10 , in some embodiments, after step S108, it further includes:

[0081] Step S202: Form a barrier layer 11 in the second trench 42; the barrier layer 11 covers the inner sidewall and part of the bottom surface of the second trench 42 and extends to the outer surface of the gate structure 30.

[0082] As an example, the material of the barrier layer 11 includes but is not limited to silicon nitride, silicon oxide, silicon oxynitride, or a combination of the above materials.

[0083] Exemplarily, one or more of the following deposition processes can be used but are not limited to Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High-Density Plasma (HDP) process, Plasma-Enhanced Deposition process, and Spin-on Dielectric (SOD) process to form the barrier material layer. A photoresist layer is coated on the top surface of the barrier material layer, and the photoresist layer is patterned through processes such as exposure, development, and fixing. Using the patterned photoresist layer as a mask, the barrier material layer is etched to form the barrier layer 11.

[0084] Among them, the patterned barrier layer 11 provides a process window for the subsequent self-aligned silicide layer 12, that is, locates its position and the opening size along the OY direction. In this embodiment, no specific limitation is made on the opening size of the barrier layer 11.

[0085] Please refer to Figures 6 - 7 , step S204: Form a self-aligned silicide layer 12 on the top surface of the exposed substrate 10 and the top surface of the gate structure 30.

[0086] Specifically, as Figure 6As shown, the top surface of the exposed substrate 10 includes the top surface 51a of the first-type doped region 51, the inner surface 521a of the source doped region 521, the top surface 30a of the gate layer, and the top surface 522a of the drain doped region 522 that is not covered by the barrier layer 11.

[0087] Exemplarily, but not limited to, a metal layer covering the semiconductor structure shown can be formed by thermal evaporation, electron beam evaporation, furnace tube growth, magnetron sputtering, electroplating, and annealing operations are performed using a rapid thermal annealing process so that the metal layer forms a metal silicide with the contact substrate 10. Finally, the unreacted metal layer is removed by wet etching or dry etching to obtain the structure shown in Figure 6 Figure 7 the figure.

[0088] Among them, the material of the metal layer includes but is not limited to materials such as titanium (Ti), cobalt (Co), platinum (Pt), and nickel (Ni) or a combination thereof.

[0089] Please refer to Figure 8 , step S208: Form a dielectric layer 13 covering the substrate 10, the self-aligned silicide layer 12, and the barrier layer 11.

[0090] Exemplarily, the above structure can also be formed by a deposition process, and the dielectric layer 13 can be formed of a material with a high-k dielectric constant. For example, the materials of the dielectric layer 13 include: aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), or strontium titanate (SrTiO 3 ).

[0091] The dielectric layer 13 is used to provide a process platform for subsequent contact holes and can also be used to isolate adjacent devices.

[0092] Please refer to Figures 9 - 10 , step S210: After forming a contact hole 601 extending in the OX direction to the self-aligned silicide layer 12 in the dielectric layer 13, a contact plug 60 is formed in the contact hole 601; wherein, the bottom surface of the contact plug 60 is within the top surface of the self-aligned silicide layer 12.

[0093] Exemplarily, any one or more etching methods can be used to form the contact hole 601 penetrating the dielectric layer 13 as shown in Figure 9 the figure in the dielectric layer 13, and the contact plug 60 is formed in the contact hole 601 by chemical vapor deposition, sputtering, or electroplating respectively. The specific structure is as shown in Figure 10 ​As shown in the figure. Among them, the materials of the contact plug 60 include, but are not limited to, metal materials such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), tungsten (W), etc.

[0094] Specifically, the top surface of the dielectric layer 13 includes a body electrode end point connecting to the junction surface of the first-type doped region 51, denoted as Bulk; a source end point (Source) connecting to the junction surface of the source doped region 521; a drain end point (Drain) connecting to the junction surface of the drain doped region 522; and a gate end point (Gate) connecting to the junction surface of the gate layer 301.

[0095] Please refer to Figure 11 , this application also provides an electrostatic discharge protection structure, which is made by using the preparation method described in any of the above embodiments.

[0096] It should be noted that, please refer to Figure 11 , in the electrostatic discharge protection structure provided by this application, since the structure is symmetric about the center line A, only the working principle of one side is explained. As described above, during ESD protection, the GGNMOS is equivalent to a parasitic NPN transistor with the gate grounded, the gate-source is grounded, and the source doped region 521 and the drain doped region 522 form a PN junction with the first-type well region 102. When the device is working normally, the PN junction formed by the drain doped region 522 and the first-type well region 102 conducts forwardly to build a discharge path. Under the action of an ESD pulse, this PN junction is broken down, a large number of positive charges are released into the first-type well region 102, and the potential of the first-type well region 102 rises through the parasitic resistance R. When the voltage drop exceeds the conduction voltage of the PN junction formed by the source doped region 521 and the first-type well region 102, the parasitic NPN transistor enters the conduction state to discharge charges.

[0097] In the above electrostatic discharge protection structure, without changing the layout area, by adding source and drain end Trench structures, the junction area between the source and drain ends and the PWELL is increased, and the area of the parasitic lateral NPN base region is reduced. For the parasitic NPN transistor, the number of electrons injected from the emitter region (source end) into the base region (PWELL) will increase, resulting in an increase in the number of carriers that can participate in conduction in the base region. The reduction of the base region area will lead to a relative increase in the electric field strength in the base region, making the electrons injected into the base region easier to be accelerated to the collector region under the action of the electric field, thereby increasing the β value of the parasitic lateral NPN.

[0098] For a given drain current, only a smaller base current is required to turn on the transistor, making it easier to meet the conduction condition of the parasitic NPN, and the V t1 (trigger voltage) is reduced. When the β value increases, the current amplification ability is correspondingly enhanced, and the I t2The increase in (failure current), and the combination of the two expands the ESD design window of the electrostatic discharge protection structure provided by the present application, enabling it to better cope with ESD impacts of various intensities, that is, improving the ESD protection level of the GGNMOS.

[0099] The present application also provides an electronic device, including the electrostatic discharge protection structure prepared by any of the preparation methods in the above embodiments; or including the above electrostatic discharge protection structure.

[0100] In the above electronic device, thanks to the electrostatic discharge protection structure, the maintained layout area ensures that the size and integration of the device are not affected. Through more effective ESD protection, the reliability of the device is effectively enhanced, the service life is extended, and the stable operation of the electronic device in a complex and changeable usage environment is ensured.

[0101] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0102] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it cannot be understood as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing an electrostatic discharge protection structure, characterized in that: include: Providing a substrate, the substrate comprising a first type well region extending along a first direction toward the substrate via a first surface of the substrate; The first-type well region includes isolation structures spaced apart and distributed along a second direction parallel to the first surface; forming gate structures arranged at intervals along the second direction between any adjacent isolation structures; Removing part of the first-type well region to obtain a first trench located between the gate structure and the isolation structure, and a second trench located between adjacent gate structures; An ion implantation process is performed on the first-type well region to form a first-type doping region and a second-type doping region; wherein the first-type doping region is located between adjacent isolation structures, and the second-type doping region surrounds the first trench and the surface of the second trench contacting the first-type well region.

2. The preparation method according to claim 1, characterized in that: The isolation structure extends into the first type well region via the first surface; A depth of the isolation structure along the first direction is less than a depth of the first type well region along the first direction.

3. The preparation method according to claim 2, characterized in that: An opening size of the second groove along the second direction is larger than an opening size of the first groove along the second direction.

4. The preparation method according to claim 2, characterized in that: The depth of the first-type doping region along the first direction is less than the depth of the isolation structure along the first direction; A depth of the second-type doping region along the first direction is less than a depth of the first-type doping region along the first direction.

5. The preparation method according to claim 1, characterized in that: The gate structure includes spacer structures arranged at intervals along the second direction, and a gate layer located between adjacent spacer structures.

6. The preparation method according to claim 5, characterized in that: The second-type doping region includes a source doping region and a drain doping region; wherein the source doping region is disposed in the first trench, and the drain doping region is disposed in the second trench; The dimension of the drain doping region along the second direction is smaller than the spacing between adjacent sidewall structures along the first direction.

7. The preparation method according to any one of claims 1 to 6, characterized in that: forming a barrier layer in the second trench; the barrier layer covers the inner sidewall and a portion of the bottom surface of the second trench and extends to the outer surface of the gate structure; forming a self-aligned silicide layer on the exposed top surface of the substrate and the top surface of the gate structure; forming a dielectric layer covering the substrate, the salicide layer and the barrier layer; After forming a contact hole in the dielectric layer extending along the first direction to the salicide layer, a contact plug is formed in the contact hole; wherein the bottom surface of the contact plug is within the top surface of the salicide layer.

8. The preparation method according to any one of claims 1 to 6, characterized in that: The conductivity type characterized by the first type is different from the conductivity type characterized by the second type.

9. An electrostatic discharge protection structure, characterized in that: The preparation method is described in any one of claims 1 to 8.

10. An electrostatic discharge protection structure, characterized in that: An electrostatic discharge protection structure prepared by the preparation method according to any one of claims 1 to 8; Or including the electrostatic discharge protection structure as described in claim 9.

Images