Image sensor

Abstract

An image sensor is disclosed. The image sensor includes: a semiconductor substrate having a first conductivity type and including a first surface and a second surface facing away from each other; a plurality of photoelectric conversion regions in the semiconductor substrate and having a second conductivity type; and a first pixel isolation structure between the photoelectric conversion regions adjacent to each other in the first direction. The first pixel isolation structure includes: a first conductive pattern adjacent to the semiconductor substrate and having a shape extending from the first surface to the second surface; an internal dielectric pattern on an inside surface of the first conductive pattern; a buried dielectric pattern on the internal dielectric pattern; and an etch stop layer between the internal dielectric pattern and the buried dielectric pattern.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0162593 filed on November 21, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Various example embodiments relate to image sensors and methods of manufacturing the same, and more particularly, to image sensors having improved electrical and / or optical characteristics and / or methods of manufacturing the same. Background Art

[0003] Image sensors convert photon images into electrical signals. Recent advances in the computer and communications industries have led to a strong demand for high-performance image sensors in various consumer electronic devices, such as one or more of digital cameras, camcorders, PCS (personal communication systems), game consoles, security cameras, and medical miniature cameras. Image sensors are classified into charge-coupled devices (CCDs) and CMOS image sensors. CMOS image sensors have a simple operation method, and because the corresponding signal processing circuits are integrated into a single chip, the size of their products can be minimized or reduced. Alternatively or additionally, CMOS image sensors use relatively small power consumption, which is useful in battery-powered applications. Alternatively or additionally, since the process technology for manufacturing CMOS image sensors is compatible with CMOS process technology, CMOS image sensors can reduce manufacturing costs. Therefore, due to technological advances and the realization of high resolution, the use of CMOS image sensors has increased rapidly. Summary of the invention

[0004] Some example embodiments of the inventive concepts provide an image sensor having improved electrical and optical characteristics.

[0005] Alternatively or additionally, some example embodiments of the inventive concepts provide methods of manufacturing an image sensor having improved electrical and optical characteristics.

[0006] The objects of the inventive concept are not limited to the above-mentioned objects, and other objects not mentioned above will be clearly understood by those of ordinary skill in the art from the following description.

[0007] According to some example embodiments, an image sensor may include: a semiconductor substrate having a first conductivity type and including a first surface and a second surface facing away from each other; a plurality of photoelectric conversion regions in the semiconductor substrate and having a second conductivity type; and a first pixel isolation structure located between the photoelectric conversion regions adjacent to each other in a first direction. The first pixel isolation structure may include: a first conductive pattern adjacent to the semiconductor substrate and having a shape extending from the first surface to the second surface; an inner dielectric pattern on an inner side surface of the first conductive pattern; a buried dielectric pattern on the inner dielectric pattern; and an etch stop layer between the inner dielectric pattern and the buried dielectric pattern.

[0008] Alternatively or additionally, according to some example embodiments, an image sensor may include: a semiconductor substrate having a first conductivity type and including a first surface and a second surface facing away from each other; a plurality of photoelectric conversion regions in the semiconductor substrate and having a second conductivity type; a device isolation layer in the semiconductor substrate and adjacent to the first surface; a first pixel isolation structure located between two adjacent photoelectric conversion regions in the photoelectric conversion regions and including a first etch stop layer; and a second pixel isolation structure located between four adjacent photoelectric conversion regions in the photoelectric conversion regions and including a second etch stop layer. The first etch stop layer and the second etch stop layer may be between a bottom surface of the device isolation layer and the second surface of the semiconductor substrate.

[0009] Alternatively or additionally, according to some example embodiments, an image sensor may include: a semiconductor substrate including a light receiving region, a light shielding region, and a pad region and having a first surface and a second surface facing away from each other; a pixel isolation structure, on the light receiving region and the light shielding region in the semiconductor substrate, the pixel isolation structure defining a plurality of pixel regions and including a first conductive pattern; a transmission gate electrode on the first surface of the semiconductor substrate; a plurality of photoelectric conversion regions on the light receiving region and the light shielding region in the semiconductor substrate; a pixel circuit layer on the first surface of the semiconductor substrate; and an optical transmission layer on the second surface of the semiconductor substrate. The pixel isolation structure may include: a plurality of first pixel isolation structures located between pixel regions adjacent to each other in a first direction or in a second direction intersecting the first direction; and a plurality of second pixel isolation structures located between pixel regions adjacent to each other in a third direction obliquely intersecting the first direction and the second direction. The first pixel isolation structure may also include an internal dielectric pattern on an inner side surface of the first conductive pattern. The second pixel isolation structure may also include a second conductive pattern on an inner side surface of the first conductive pattern.

[0010] Alternatively or additionally, according to some example embodiments, a method of manufacturing an image sensor may include: providing a substrate having a first surface and a second surface facing away from each other; forming a first trench and a second trench by removing a portion of the semiconductor substrate; forming a first pixel isolation structure including an etch stop layer in the first trench; and forming a second pixel isolation structure in the second trench. The step of forming the first pixel isolation structure may include: forming the etch stop layer using a first ion implantation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic block diagram illustrating an image sensor is shown according to some example embodiments.

[0012] Figure 2A and Figure 2B A circuit diagram illustrating a pixel of an image sensor according to some example embodiments is illustrated.

[0013] Figure 3 A plan view illustrating an image sensor according to some example embodiments is illustrated.

[0014] Figure 4A and Figure 4B Shown along Figure 3 2 , and a cross-sectional view of an image sensor according to some example embodiments is shown, taken along lines AA′ and BB′.

[0015] FIG. 5A to FIG. 7B An enlarged cross-sectional view illustrating an image sensor is illustrated according to some example embodiments.

[0016] Figure 5A , Fig. 6A and Fig. 7A Show Figure 4A Magnified view of section P1.

[0017] Figure 5B , Figure 6B and Figure 7B Show Figure 4B Magnified view of portion P2.

[0018] Figure 8 A simplified plan view illustrating an image sensor including a semiconductor device according to some example embodiments is illustrated.

[0019] Fig.9A and Fig. 9B Shown along Figure 8 A cross-sectional view of an image sensor according to some example embodiments is shown, taken along line CC'.

[0020] FIG. 10A to FIG. 17B A cross-sectional view illustrating a method of manufacturing an image sensor according to some example embodiments is illustrated.

[0021] Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A Shown along Figure 3 A cross-sectional view taken along line AA'.

[0022] Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B Shown along Figure 3 A cross-sectional view taken along line BB'.

[0023] FIG. 18A to FIG. 21B A cross-sectional view illustrating a method of manufacturing an image sensor according to some example embodiments is illustrated.

[0024] Fig.18A , Fig.19A , Fig. 20A and Fig.21A Shown along Figure 3 A cross-sectional view taken along line AA'.

[0025] Fig.18B , Fig.19B , Fig. 20B and Fig.21B Shown along Figure 3 A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0026] Some example embodiments will now be described below with reference to the accompanying drawings.Throughout the specification, like reference numerals may refer to like components.

[0027] Figure 1 A schematic block diagram illustrating an image sensor is shown according to some example embodiments.

[0028] Reference Figure 1 , the image sensor may include a pixel array (e.g., an active pixel sensor array) 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output (I / O) buffer 8. Figure 1The elements may be connected to each other (e.g., wired (and / or wireless) to each other) to exchange data and / or information (such as analog and / or digital data and / or information such as commands and / or signals) in a serial and / or parallel manner through one-to-one channels and / or many-to-one channels and / or many-to-many channels.

[0029] The active pixel sensor array 1 may include a plurality of two-dimensionally arranged unit pixels, each unit pixel being configured to convert an optical signal into an electrical signal. The active pixel sensor array 1 may be driven by a plurality of driving signals (such as a pixel selection signal, a reset signal, and a charge transfer signal) from a row driver 3. The converted electrical signal may be provided to a correlated double sampler 6. The active pixel sensor array 1 may be arranged in a grid (such as a rectangular (e.g., square) grid). The active pixel sensor array 1 may include a main array and a redundant array; example embodiments are not limited thereto.

[0030] The row driver 3 may provide a number of driving signals for driving a number of unit pixels to the active pixel sensor array 1 according to the decoding result obtained from the row decoder 2. When the unit pixels are arranged in a matrix shape, a driving signal may be provided for each row.

[0031] The timing generator 5 may provide timing signals and control signals to the row decoder 2 and the column decoder 4 .

[0032] The correlated double sampler 6 may receive the electrical signal generated in the active pixel sensor array 1, and hold and sample the received electrical signal. The correlated double sampler 6 may perform a double sampling operation to sample a specific noise level and signal level of the electrical signal, and then output a difference level corresponding to the difference between the noise level and the signal level.

[0033] The analog-to-digital converter 7 may convert an analog signal corresponding to the difference level received from the correlated double sampler 6 into a digital signal and then may output the converted digital signal.

[0034] The input / output buffer 8 may latch the digital signal and may then sequentially output the latched digital signal to an image signal processor (not shown) in response to a decoding result obtained from the column decoder 4 .

[0035] Figure 2A and Figure 2B A circuit diagram illustrating a pixel of an image sensor according to some example embodiments is illustrated.

[0036] Reference Figure 2A, the pixel P may include a first photoelectric conversion element PD1, a second photoelectric conversion element PD2, a first transfer transistor TX1, a second transfer transistor TX2, and four pixel transistors. For example, the four pixel transistors may include a reset transistor RX, a source follower transistor SF, a selection transistor SEL, and a dual conversion gain transistor DCX, but example embodiments are not limited thereto. For example, on each pixel P, the pixel transistors may be arranged in various ways. Each pixel transistor may be an NMOS transistor and / or a PMOS transistor, each transistor having the same and / or different electrical characteristics and / or physical characteristics; however, example embodiments are not limited thereto.

[0037] The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may generate and accumulate charges in proportion to the amount of incident light. For example, the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be one of a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and any combination thereof, either jointly or independently.

[0038] The first transfer transistor TX1 and the second transfer transistor TX2 may provide the charges accumulated in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to the floating diffusion area FD. The first transfer transistor TX1 and the second transfer transistor TX2 may be controlled by a signal applied to the first transfer gate electrode TG1 and the second transfer gate electrode TG2. The first transfer transistor TX1 and the second transfer transistor TX2 may share the floating diffusion area FD, but example embodiments are not limited thereto. For example, the first transfer transistor TX1 and the second transfer transistor TX2 may be connected to different floating diffusion areas FD. The first transfer transistor TX1 and the second transfer transistor TX2 may be NMOS transistors having the same electrical characteristics and physical characteristics; however, example embodiments are not limited thereto.

[0039] The floating diffusion area FD may receive and accumulate charges generated from the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2. The source follower transistor SF may be controlled according to the amount of photocharges accumulated in the floating diffusion area FD.

[0040] The reset transistor RX may periodically reset the charge accumulated in the floating diffusion region FD according to a reset signal applied to the reset gate electrode RG. For example, the reset transistor RX may have a drain terminal connected to the dual conversion gain transistor DCX and a drain terminal connected to the pixel power supply voltage V DD When the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel supply voltage V DD The electric charge accumulated in the floating diffusion area FD may be depleted to initialize the floating diffusion area FD.

[0041] The dual conversion gain transistor DCX may be connected between the floating diffusion region FD and the reset transistor RX. In response to the dual conversion gain control signal, the dual conversion gain transistor DCX may change the capacitance of the floating diffusion region FD to control the conversion gain. For example, different conversion gains may be provided according to the operation of the dual conversion gain transistor DCX. Therefore, the dual conversion gain transistor DCX may be turned on in the high illumination mode and turned off in the low illumination mode.

[0042] The source follower transistor SF may be a source follower buffer amplifier or include a source follower buffer amplifier (or be included in a source follower buffer amplifier) ​​that generates a source-drain current proportional to the amount of charge applied from the floating diffusion region FD to the source follower gate electrode. The source follower transistor SF may amplify the change in the potential of the floating diffusion region FD and may output the amplified signal to the output line V through the selection transistor SEL. out The source follower transistor SF can be connected to the pixel supply voltage V DD and select transistor SEL. For example, source follower transistor SF may be located at pixel power supply voltage V DD and between the selection transistor SEL.

[0043] The selection transistor SEL may select each row of pixels P to be read out. When the selection transistor SEL is turned on in response to a selection signal applied to the selection gate electrode SG, the output line V out An electrical signal output from the drain terminal of the source follower transistor SF may be output.

[0044] Reference Figure 2B , the pixel P may include first, second, third and fourth photoelectric conversion elements PD1, PD2, PD3 and PD4, first, second, third and fourth transfer transistors TX1, TX2, TX3 and TX4, and four pixel transistors.

[0045] The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may share a floating diffusion region FD. The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may be controlled by a signal applied to the first transfer gate electrode TG1, the second transfer gate electrode TG2, the third transfer gate electrode TG3, and the fourth transfer gate electrode TG4. The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may have the same or different electrical characteristics and / or physical characteristics from each other; example embodiments are not limited thereto.

[0046] For example, four pixel transistors may correspond to Figure 2A The reset transistor RX, source follower transistor SF, select transistor SEL and dual conversion gain transistor DCX discussed in.

[0047] Figure 3 A plan view illustrating an image sensor according to some example embodiments is illustrated. Figure 4A and Figure 4B Shown along Figure 3 2 , and a cross-sectional view of an image sensor according to some example embodiments is shown, taken along lines AA′ and BB′.

[0048] Reference Figure 3 , Figure 4A and Figure 4B , an image sensor according to some example embodiments may include a photoelectric conversion layer 10 , a pixel circuit layer 20 , and an optical transmission layer 30 .

[0049] When viewed in cross section, the photoelectric conversion layer 10 may be disposed between the pixel circuit layer 20 and the optical transmission layer 30. The photoelectric conversion layer 10 may convert external incident light into an electrical signal. The photoelectric conversion layer 10 may include a semiconductor substrate 100, and may also include a pixel isolation structure PIS, a barrier region 103, a device isolation layer 105, and a photoelectric conversion region PD located within the semiconductor substrate 100.

[0050] For example, the semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing each other. The semiconductor substrate 100 may be or may include a substrate in which an epitaxial layer having a first conductivity type (e.g., p-type) is formed on a bulk silicon substrate having the first conductivity type. Alternatively or additionally, the semiconductor substrate 100 may be or may include a substrate in which the epitaxial layer remains after the bulk silicon substrate is removed in the manufacture of an image sensor. In some example embodiments, the semiconductor substrate 100 may be a bulk silicon substrate including a well having the first conductivity type. For example, the semiconductor substrate 100 may have a substrate having the first conductivity type.

[0051] The device isolation layer 105 may be adjacent to the first surface 100a of the semiconductor substrate 100 while being located in the semiconductor substrate 100. The device isolation layer 105 may be located in a device isolation trench formed by recessing the first surface 100a of the semiconductor substrate 100. The top surface of the device isolation layer 105 may be coplanar with the first surface 100a of the semiconductor substrate 100. The device isolation layer 105 may include a dielectric material. The device isolation layer 105 may define an active portion on the first surface 100a of the semiconductor substrate 100. For example, the device isolation layer 105 may define a first active portion ACT1 and a second active portion ACT2. The first active portion ACT1 and the second active portion ACT2 may be spaced apart from each other and may have different sizes from each other.

[0052] The pixel isolation structure PIS may be located in the semiconductor substrate 100 and may define a plurality of pixel regions PR. When viewed in a plan view, the pixel isolation structure PIS may surround the plurality of pixel regions PR or the photoelectric conversion region PD. For example, the pixel isolation structure PIS may include a first pixel isolation structure PIS1 located in the first trench T1 and a second pixel isolation structure PIS2 located in the second trench T2.

[0053] Each of the first trenches T1 may be disposed between pixel areas PR or photoelectric conversion areas PD adjacent to each other along the first direction D1 or the second direction D2. Each of the second trenches T2 may be disposed between pixel areas PR or photoelectric conversion areas PD adjacent to each other along the third direction D3. When viewed in a plan view, the first trench T1 may be adjacent to the side surface of the pixel area PR or the photoelectric conversion area PD. When viewed in a plan view, the second trench T2 may be adjacent to the vertex of the pixel area PR or the photoelectric conversion area PD. For example, each of the first trenches T1 may be located between two adjacent pixel areas PR and / or between two adjacent photoelectric conversion areas PD. Each of the second trenches T2 may be located between four adjacent pixel areas PR or between four adjacent photoelectric conversion areas PD.

[0054] The pixel isolation structure PIS may penetrate the semiconductor substrate 100 in a direction from the first surface 100a to the second surface 100b of the semiconductor substrate 100. When viewed in a cross-sectional view, the pixel isolation structure PIS may have a shape extending in the fourth direction D4. The pixel isolation structure PIS may have a length in the fourth direction D4. The length of the pixel isolation structure PIS may be substantially the same as the vertical thickness of the semiconductor substrate 100. The pixel isolation structure PIS may penetrate the device isolation layer 105 and / or penetrate a portion of the device isolation layer 105.

[0055] As described herein, the first direction D1, the second direction D2, and the third direction D3 may be parallel to the first surface 100a and the second surface 100b of the semiconductor substrate 100. The first direction D1, the second direction D2, and the third direction D3 may intersect each other. The first direction D1 and the second direction D2 may be orthogonal to each other. The third direction D3 may be oblique to the first direction D1 or the second direction D2. The fourth direction D4 may intersect with the first direction D1, the second direction D2, and the third direction D3. For example, the fourth direction D4 may be perpendicular to the first surface 100a and the second surface 100b of the semiconductor substrate 100.

[0056] The pixel isolation structure PIS may have an upper width at the first surface 100a of the semiconductor substrate 100 and a lower width at the second surface 100b of the semiconductor substrate 100. The lower width of the pixel isolation structure PIS may be smaller than the upper width of the pixel isolation structure PIS. The pixel isolation structure PIS may have a width that decreases in a direction from the first surface 100a of the semiconductor substrate 100 to the second surface 100b, but example embodiments are not limited thereto. For example, the pixel isolation structure PIS may have a width that increases or is constant in a direction from the first surface 100a of the semiconductor substrate 100 to the second surface 100b.

[0057] Reference FIG. 5A to FIG. 7B , the structure of each of the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 will be described in detail below.

[0058] The barrier region 103 may be disposed in the semiconductor substrate 100 adjacent to the sidewall of the pixel isolation structure PIS. The barrier region 103 may include impurities having the same first conductivity type (e.g., p-type) as the semiconductor substrate 100. When the first trench T1 and the second trench T2 are formed, the barrier region 103 may reduce the occurrence of dark current caused by “electron-hole pairs generated due to surface defects of the first trench T1 and the second trench T2”.

[0059] The photoelectric conversion region PD may be disposed in the semiconductor substrate 100 of the pixel region PR. The photoelectric conversion region PD may generate photocharges proportional to the intensity of the incident light. The photoelectric conversion region PD may have a second conductivity type opposite to the first conductivity type of the semiconductor substrate 100. The junction between the photoelectric conversion region PD having the second conductivity type and the semiconductor substrate 100 having the first conductivity type may constitute a photodiode. The photoelectric conversion region PD may each have an impurity concentration difference between a portion adjacent to the first surface 100a and a portion adjacent to the second surface 100b, so that the semiconductor substrate 100 has a potential gradient between the first surface 100a and the second surface 100b. For example, the photoelectric conversion region PD may include a plurality of doped regions stacked vertically.

[0060] The pixel circuit layer 20 may be located on the first surface 100a of the semiconductor substrate 100. The pixel circuit layer 20 may include a pixel transistor (eg, a MOS transistor) electrically connected to the photoelectric conversion region PD. Figure 2A The reset transistor RX, the select transistor SEL, the dual conversion gain transistor DCX and the source follower transistor SF of the pixel transistor discussed in FIG.

[0061] On each pixel region PR, a transmission gate electrode TG may be disposed on a first active portion ACT1 of the semiconductor substrate 100. The transmission gate electrode TG may be located on a first surface 100a of the semiconductor substrate 100. The transmission gate electrode TG may penetrate a portion of the semiconductor substrate 100. When viewed in a cross-sectional view, the transmission gate electrode TG may have a T-shape. A gate dielectric layer GIL may be disposed between the semiconductor substrate 100 and the transmission gate electrode TG.

[0062] The floating diffusion area FD may be disposed in the first active portion ACT1 on one side of the transfer gate electrode TG. The floating diffusion area FD may be formed by implanting impurities having a second conductivity type opposite to the first conductivity type of the semiconductor substrate 100 into the semiconductor substrate 100. For example, the floating diffusion area FD may have the second conductivity type.

[0063] In each pixel region PR, at least one pixel transistor may be disposed on the second active portion ACT2. The pixel transistor may be a reference Figure 2A and Figure 2B The pixel transistor may include a pixel gate electrode PG across the second active portion ACT2 and a source / drain region disposed in the second active portion ACT2 on the opposite side of the pixel gate electrode PG. The pixel gate electrode PG may have a bottom surface parallel to the top surface of the second active portion ACT2. For example, the pixel gate electrode PG may include doped polysilicon, metal, conductive nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0064] A plurality of interlayer dielectric layers 210 may be located on the first surface 100a of the semiconductor substrate 100. The interlayer dielectric layer 210 may cover the transmission gate electrode TG and a wiring structure connected to the pixel circuit. The wiring structure may include a metal line 223 and a contact plug 221 connecting the metal lines 223 to each other. The number and / or arrangement and / or spacing and / or width and / or interval of the interlayer dielectric layer 210, the metal line 223 and the contact plug 221 are not limited to Figure 4A and / or Figure 4B Those shown in .

[0065] The optical transmission layer 30 may be located on the second surface 100b of the semiconductor substrate 100. The optical transmission layer 30 may include a planarization dielectric layer 310, a grid structure 320, a protective layer 330, a color filter 340, a microlens 350, and a passivation layer 360. The optical transmission layer 30 may focus and filter externally incident light, and the photoelectric conversion layer 10 may be provided with the focused and filtered light.

[0066] For example, the planarization dielectric layer 310 may cover the second surface 100b of the semiconductor substrate 100. The planarization dielectric layer 310 may be formed of a transparent dielectric material and may include a plurality of layers. The planarization dielectric layer 310 may be formed of a dielectric material having a refractive index different from that of the semiconductor substrate 100. The planarization dielectric layer 310 may include one or more of a metal oxide and a silicon oxide. For example, the planarization dielectric layer 310 may include Al 2 O 3 , CeF 3 , HfO 2 、ITO、MgO、Ta 2 O 5 、TiO 2 、ZrO 2 , Si, Ge, ZnSe, ZnS or PbF 2 Alternatively or additionally, the planarization dielectric layer 310 may be formed of a high refractive organic material such as one or more of a siloxane resin, bisbenzocyclobutene (BCB), polyimide, acrylic, polyparaxylene C, poly(methyl methacrylate) (PMMA), or polyethylene terephthalate (PET). In some example embodiments, the planarization dielectric layer 310 may be formed of strontium titanate (SrTiO 3 ), polycarbonate, glass, bromine, sapphire, cubic zirconia, potassium niobate (KNbO 3 ), silicon carbide (SiC), gallium (III) phosphide (GaP) or gallium (III) arsenide (GaAs).

[0067] The grid structure 320 may be disposed on the planarization dielectric layer 310. The grid structure 320 may have a planar grid shape similar to the pixel isolation structure PIS. When viewed in a plan view, the grid structure 320 may overlap the pixel isolation structure PIS. For example, the grid structure 320 may overlap the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2. The width of the grid structure 320 may be substantially the same as or less than the minimum width of the pixel isolation structure PIS.

[0068] The grid structure 320 may include one or more of a light shielding pattern and a low refractive pattern. The light shielding pattern may include a metal material (such as titanium, tantalum, or tungsten). The low refractive pattern may be formed of a material whose refractive index is less than that of the light shielding pattern. The low refractive pattern may be formed of an organic material and may have a refractive index of about 1.1 to about 1.3. For example, the grid structure 320 may be a polymer layer including silicon nanoparticles.

[0069] The protective layer 330 may cover the surfaces of the planarized dielectric layer 310 and the grid structure 320. The protective layer 330 may have a substantially uniform thickness. For example, the protective layer 330 may be a single layer or a multilayer including at least one selected from aluminum oxide and silicon oxycarbide.

[0070] The color filter 340 may be formed on the protective layer 330 to correspond to the pixel region PR. The color filter 340 may fill the space defined by the grid structure 320. Based on the unit pixel, the color filter 340 may include one of a red color filter, a green color filter, and a blue color filter or one of a magenta color filter, a cyan color filter, and a yellow color filter. The color filter 340 may be arranged in a Bayer pattern; example embodiments are not limited thereto.

[0071] The microlenses 350 may be disposed on the color filter 340. The microlenses 350 may each have a convex shape with a certain radius of curvature. For example, the microlenses 350 may include a light-transmitting resin.

[0072] The passivation layer 360 may be positioned on the microlens 350, and may have a uniform thickness covering the surface of the microlens 350. For example, the passivation layer 360 may include an inorganic oxide.

[0073] FIG. 5A to FIG. 7B An enlarged view showing an image sensor is shown according to some example embodiments. Figure 5A , Fig. 6A and Fig. 7A Show Figure 4A Magnified view of section P1. Figure 5B , Figure 6B and Figure 7B Show Figure 4B Magnified view of portion P2.

[0074] Reference Figure 5A and Figure 5B, the first pixel isolation structure PIS1 may be located in a first trench T1 formed by recessing the first surface 100a of the semiconductor substrate 100. The second pixel isolation structure PIS2 may be located in a second trench T2 formed by recessing the first surface 100a of the semiconductor substrate 100. The first trench T1 may have a first width W1 in the first direction D1 at the first surface 100a of the semiconductor substrate 100. The second trench T2 may have a second width W2 in the third direction D3 at the first surface 100a of the semiconductor substrate 100. The first width W1 may be smaller than the second width W2. Therefore, the width of the first pixel isolation structure PIS1 in the first direction D1 may be smaller than the width of the second pixel isolation structure PIS2 in the third direction D3. The first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 may have a tapered profile.

[0075] The first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 may each independently or collectively include a pad dielectric pattern 111, a first conductive pattern 113, and a buried dielectric pattern 119. For example, a bottom surface 119b of the buried dielectric pattern 119 included in the first pixel isolation structure PIS1 and a bottom surface 119b of the buried dielectric pattern 119 included in the second pixel isolation structure PIS2 may be at different levels (or heights). The first pixel isolation structure PIS1 may further include an inner dielectric pattern 115 and an etch stop layer 117. The second pixel isolation structure PIS2 may further include a second conductive pattern 118. For example, the first conductive pattern 113 and the second conductive pattern 118 may include polysilicon.

[0076] The liner dielectric pattern 111 may be located on the inner sidewalls of the first trench T1 and the second trench T2. The liner dielectric pattern 111 may have a uniform thickness covering the inner sidewalls of the first trench T1 and the second trench T2. The liner dielectric pattern 111 may be in direct contact with the semiconductor substrate 100. Since the liner dielectric pattern 111 includes a material having a refractive index less than that of the semiconductor substrate 100, the liner dielectric pattern 111 may have a refractive index less than that of the semiconductor substrate 100. The liner dielectric pattern 111 may include one or more of a silicon-based dielectric material (e.g., one or more of silicon nitride, silicon oxide, and silicon oxynitride), a high-k dielectric material (e.g., one or more of hafnium oxide and aluminum oxide), and a metal oxide. In addition, the liner dielectric pattern 111 may include an impurity having a first conductivity type. For example, the impurity having a first conductivity type may include at least one selected from boron (B), phosphorus (P), arsenic (As), gallium (Ga), indium (In), antimony (Sb), and aluminum (Al).

[0077] In the first trench T1 and the second trench T2, the first conductive pattern 113 may be located on the inner side surface of the pad dielectric pattern 111. The first conductive pattern 113 may cover a portion of the inner side surface of the pad dielectric pattern 111. The first conductive pattern 113 may not cover the remaining portion of the inner side surface of the pad dielectric pattern 111 adjacent to the first surface 100a of the semiconductor substrate 100. For example, the first conductive pattern 113 may include doped polysilicon or undoped polysilicon.

[0078] The first conductive pattern 113 in the first trench T1 may have a top surface parallel to the first direction D1. In contrast, the first conductive pattern 113 in the second trench T2 may include an upper portion having a curved surface. For example, the first conductive pattern 113 in the second trench T2 may have a thickness that decreases as the distance from the bottom surface 119b of the buried dielectric pattern 119 and the first surface 100a of the semiconductor substrate 100 decreases in the third direction D3.

[0079] In the first trench T1, a first height H1 in the fourth direction D4 may be set between the top surface of the first conductive pattern 113 and the bottom surface 105b of the device isolation layer 105. In the second trench T2, a second height H2 in the fourth direction D4 may be set between the top surface of the first conductive pattern 113 and the bottom surface 105b of the device isolation layer 105. The first height H1 may be less than the second height H2, but example embodiments are not limited thereto. For example, the first height H1 may be substantially the same as the second height H2. The first height H1 and the second height H2 may be in the range of about 5 nm to about 1000 nm.

[0080] The internal dielectric pattern 115 may be located on the inner side surface of the first conductive pattern 113. The internal dielectric pattern 115 may be located at the center of the first trench T1 in the first direction D1. For example, when the internal dielectric pattern 115 is located at the center of the first pixel isolation structure PIS1, the first conductive pattern 113 may be placed between the internal dielectric pattern 115 and the pad dielectric pattern 111. The internal dielectric pattern 115 may not be disposed in the second trench T2. Since the internal dielectric pattern 115 includes a material having a refractive index less than that of the first conductive pattern 113, the internal dielectric pattern 115 may have a refractive index less than that of the first conductive pattern 113. For example, the internal dielectric pattern 115 may include a material substantially the same as that of the pad dielectric pattern 111, but example embodiments are not limited thereto.

[0081] The etch stop layer 117 may be located on the inner dielectric pattern 115. In the first trench T1, the etch stop layer 117 may be located between the inner dielectric pattern 115 and a buried dielectric pattern 119 (to be discussed below). In some example embodiments, the etch stop layer 117 may not be disposed in the second trench T2. The top surface of the etch stop layer 117 may be coplanar with the top surface of the first conductive pattern 113. For example, the etch stop layer 117 may be located Figure 4A 1 and the bottom surface 105b of the device isolation layer 105. For example, the first height H1 in the fourth direction D4 may be set between the top surface of the etch stop layer 117 and the bottom surface 105b of the device isolation layer 105.

[0082] The etch stop layer 117 may include a material having an etch selectivity to the etch process. For example, the etch stop layer 117 may include one or more of a silicon-based dielectric material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide) doped with impurities. The impurities doped into the etch stop layer 117 may include at least one selected from boron (B), carbon (C), silicon (Si), and argon (Ar). For example, the etch stop layer 117 may be formed by doping a portion of the inner dielectric pattern 115 with impurities.

[0083] The second conductive pattern 118 may be located on the inner side surface of the first conductive pattern 113. The second conductive pattern 118 may be located at the center of the second trench T2 in the third direction D3. For example, when the second conductive pattern 118 is located at the center of the second pixel isolation structure PIS2, the first conductive pattern 113 may be placed between the second conductive pattern 118 and the pad dielectric pattern 111. The top surface of the second conductive pattern 118 may be coplanar with the top surface of the first conductive pattern 113. For example, the second height H2 in the fourth direction D4 may be set between the top surface of the second conductive pattern 118 and the bottom surface 105b of the device isolation layer 105. The second conductive pattern may include a material substantially the same as that of the first conductive pattern 113, but example embodiments are not limited thereto.

[0084] The buried dielectric pattern 119 may be located in the upper portion of the first trench T1 and the upper portion of the second trench T2. For example, in the first trench T1, the buried dielectric pattern 119 may be located on the etch stop layer 117. In the second trench T2, the buried dielectric pattern 119 may be located on the second conductive pattern 118. The buried dielectric pattern 119 may have a top surface and a bottom surface 119b opposite to the top surface. The top surface of the buried dielectric pattern 119 may be coplanar with the first surface 100a of the semiconductor substrate 100. The bottom surface 119b of the buried dielectric pattern 119 may be lower than the bottom surface 105b of the device isolation layer 105. The thickness of the buried dielectric pattern 119 in the fourth direction D4 may be greater than the thickness of the device isolation layer 105 in the fourth direction D4.

[0085] For example, because the bottom surface 119b of the buried dielectric pattern 119 contacts the etch stop layer 117 in the first trench T1, the first height H1 in the fourth direction D4 may be set between the bottom surface 119b of the buried dielectric pattern 119 and the bottom surface 105b of the device isolation layer 105. Because the bottom surface 119b of the buried dielectric pattern 119 contacts the second conductive pattern 118 in the second trench T2, the second height H2 in the fourth direction D4 may be set between the bottom surface 119b of the buried dielectric pattern 119 and the bottom surface 105b of the device isolation layer 105. For example, the buried dielectric pattern 119 may include a material substantially the same as that of the liner dielectric pattern 111 and / or the inner dielectric pattern 115, but example embodiments are not limited thereto.

[0086] Reference Fig. 6A and Figure 6B , the first pixel isolation structure PIS1 may further include a second conductive pattern 118. In the first trench T1, the second conductive pattern 118 may be located between the etch stop layer 117 and the buried dielectric pattern 119. For example, in the first trench T1, a bottom surface of the second conductive pattern 118 may contact the etch stop layer 117 and the first conductive pattern 113, and a top surface of the second conductive pattern 118 may contact the buried dielectric pattern 119. Therefore, in the first trench T1, a third height H3 in the fourth direction D4 may be set between the top surface of the first conductive pattern 113 and the bottom surface 105b of the device isolation layer 105 and between the top surface of the etch stop layer 117 and the bottom surface 105b of the device isolation layer 105. In the first trench T1, a first height H1 in the fourth direction D4 may be set between the second conductive pattern 118 (e.g., the top surface of the second conductive pattern 118) and the bottom surface 105b of the device isolation layer 105. The first height H1 may be Figure 5A Basically the same as discussed in , the third height H3 may be greater than the first height H1.

[0087] In the second trench T2, the top surface of the first conductive pattern 113 may not be coplanar with the top surface of the second conductive pattern 118. The top surface of the second conductive pattern 118 may be higher than the top surface of the first conductive pattern 113. For example, the second conductive pattern 118 may have a T-shape. In the second trench T2, a second height H2 in the fourth direction D4 may be set between the top surface of the second conductive pattern 118 and the bottom surface 105b of the device isolation layer 105. The second height H2 may be Figure 5B Basically the same as discussed in .

[0088] Reference Fig. 7A and Figure 7B , the first pixel isolation structure PIS1 may include a first etch stop layer 117 a , and the second pixel isolation structure PIS2 may include a second etch stop layer 117 b .

[0089] In the first trench T1, the first etch stop layer 117a may be located between the inner dielectric pattern 115 and the buried dielectric pattern 119 and between the first conductive pattern 113 and the buried dielectric pattern 119. The first etch stop layer 117a may be located Figure 4A The top surface of the first conductive pattern 113 may be coplanar with the top surface of the inner dielectric pattern 115 .

[0090] For example, the first etch stop layer 117a may include one or more of a silicon-based dielectric material (e.g., any one or more of silicon nitride, silicon oxide, and / or silicon oxynitride) containing at least one selected from boron (B), carbon (C), silicon (Si), and argon (Ar) and a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide). According to various example embodiments, the first etch stop layer 117a may be formed with Figure 5A and Fig. 6A The etch stop layer 117 discussed in is substantially the same.

[0091] In the second trench T2, the second etch stop layer 117b may be located between the second conductive pattern 118 and the buried dielectric pattern 119 and between the first conductive pattern 113 and the buried dielectric pattern 119. Similar to the first etch stop layer 117a, the second etch stop layer 117b may be located Figure 4B The top surface of the first conductive pattern 113 may be coplanar with the top surface of the second conductive pattern 118, and the top surface of the second conductive pattern 118 may be parallel to the third direction D3. Figure 5B and Figure 6B, the second conductive pattern 118 may have a constant thickness regardless of the distance from the bottom surface 119b of the buried dielectric pattern 119 and the first surface 100a of the semiconductor substrate 100. For example, the second etch stop layer 117b may include polysilicon doped with impurities including at least one selected from boron (B), carbon (C), silicon (Si), and argon (Ar).

[0092] Return to reference FIG. 5A to FIG. 7B , an image sensor according to some example embodiments may include a first pixel isolation structure PIS1 including an internal dielectric pattern 115. The internal dielectric pattern 115 may be closer to the center of the first pixel isolation structure PIS1 than the first conductive pattern 113, and may have a refractive index less than that of the first conductive pattern 113. Therefore, light incident on the image sensor may be totally reflected or more likely to be totally reflected between the first conductive pattern 113 and the internal dielectric pattern 115, and absorption of the incident light by the first pixel isolation structure PIS1 may be prevented or reduced. Therefore, the image sensor may have improved electrical and / or optical characteristics.

[0093] In addition, the image sensor according to some example embodiments may include a first pixel isolation structure PIS1 including an etch stop layer 117. When manufacturing the image sensor, the etch stop layer 117 may determine the level (or height) of the top surface of the first conductive pattern 113. For example, the top surface of the first conductive pattern 113 may be at substantially the same level as the bottom surface 105b of the device isolation layer 105. The vertical length of the first conductive pattern 113 may be substantially equal to the vertical length of the semiconductor substrate 100 adjacent to the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2. When viewed in a cross-sectional view, the semiconductor substrate 100 may completely overlap the first conductive pattern 113. Therefore, the negative bias applied to the first conductive pattern 113 may sufficiently reduce the dark current occurring between the semiconductor substrate 100 and the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2. Therefore, the image sensor may improve electrical characteristics and optical characteristics.

[0094] Figure 8 A simplified plan view illustrating an image sensor including a semiconductor device according to some example embodiments is illustrated. Fig.9A and Fig. 9B Shown along Figure 8 A cross-sectional view of an image sensor according to some example embodiments is shown, taken along line CC'.

[0095] Reference Figure 8 and Fig.9A , the image sensor may include a sensor chip S1 and a logic chip S2. The sensor chip S1 may include a pixel array area R1 and a pad area R2.

[0096] The pixel array region R1 may include a plurality of pixels P arranged two-dimensionally along a first direction D1 and a second direction D2 crossing each other. Each pixel P may include a photoelectric conversion element and a readout element. Each pixel P on the pixel array region R1 may output an electrical signal converted from incident light.

[0097] The pixel array region R1 may include a light receiving region AR and a light shielding region OB. When viewed in a plan view, the light shielding region OB may surround the light receiving region AR. For example, when viewed in a plan view, the light shielding region OB may be disposed on the upper side, the lower side, the left side, and the right side of the light receiving region AR. The light shielding region OB may include a reference pixel Pa onto which no light is incident, and the amount of charge sensed in the unit pixel Pb on the light receiving region AR may be compared with the reference amount of charge generated from the reference pixel Pa, which may result in obtaining the amplitude of the electrical signal sensed in the unit pixel Pb.

[0098] The pad region R2 may include a plurality of conductive pads CP for inputting and outputting control signals and photoelectric conversion signals. When viewed in a plan view, the pad region R2 may surround the pixel array region R1. Therefore, the pad region R2 may be easily electrically connected to an external device. The conductive pad CP may transmit an electrical signal between the unit pixel Pb and the external device.

[0099] In the light receiving area AR, the sensor chip S1 may have the same technical characteristics (such as electrical characteristics and / or physical characteristics) as those of the image sensor discussed above. For example, the sensor chip S1 may include a photoelectric conversion layer 10 between the pixel circuit layer 20 and the optical transmission layer 30.

[0100] The first pixel isolation structure PIS1 may be disposed between pixels P adjacent to each other in the first direction D1 or the second direction D2. The second pixel isolation structure PIS2 may be disposed between pixels P adjacent to each other in a diagonal direction (e.g., a third direction D3). For example, each of the first pixel isolation structures PIS1 may be located between two adjacent pixels P, and each of the second pixel isolation structures PIS2 may be located between four adjacent pixels P. The first pixel isolation structure PIS1 may be disposed between the pixels P adjacent to each other in the diagonal direction (e.g., a third direction D3). Figure 5A , Fig. 6A and Fig. 7A The first pixel isolation structure PIS1 discussed in the above is substantially the same, and the second pixel isolation structure PIS2 may be the same as Figure 5B , Figure 6B and Figure 7B The second pixel isolation structure PIS2 discussed in is basically the same.

[0101] On the light blocking area OB, the optical transmission layer 30 may include a light blocking pattern OBP, a backside contact plug PLG, a contact pattern CT, an organic layer 355 , and a passivation layer 360 .

[0102] The contact pattern CT may be buried in the contact hole in which the backside contact plug PLG is formed. The contact pattern CT may include a material different from that of the backside contact plug PLG. For example, the backside contact plug PLG may include one or more of titanium and titanium nitride, and the contact pattern CT may include aluminum (Al).

[0103] On the light shielding area OB, one or more of the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 may be electrically connected to the back contact plug PLG and the contact pattern CT. A negative bias may be applied to the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 through the contact pattern CT and the back contact plug PLG. The negative bias may be transferred from the light shielding area OB to the light receiving area AR through the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2. Therefore, dark current occurring between the semiconductor substrate 100 and the first pixel isolation structure PIS1 and between the semiconductor substrate 100 and the second pixel isolation structure PIS2 may be reduced.

[0104] On the light shielding region OB, the light shielding pattern OBP may extend continuously from the backside contact plug PLG to be placed on the top surface of the planarization dielectric layer 310. For example, the light shielding pattern OBP may include the same material as that of the backside contact plug PLG. The light shielding pattern OBP may include at least one of a metal and a metal nitride. For example, the light shielding pattern OBP may include at least one of titanium and titanium nitride. The light shielding pattern OBP may not extend to the light receiving region AR of the pixel array region R1.

[0105] The light blocking pattern OBP may not allow light to travel toward the photoelectric conversion region PD disposed on the light blocking region OB. On the reference pixel Pa of the light blocking region OB, the photoelectric conversion region PD may output a noise signal instead of a photoelectric signal. The noise signal may be generated from electrons generated due to heat or dark current.

[0106] On the light blocking area OB, an organic layer 355 and a passivation layer 360 may be disposed on the light blocking pattern OBP. The organic layer 355 may include the same material as that of the microlens 350.

[0107] On the light shielding area OB, the first through conductive pattern 511 may penetrate the semiconductor substrate 100 to be electrically connected to the metal wire 223 of the pixel circuit layer 20 and the wiring structure 1111 of the logic chip S2. The first through conductive pattern 511 may have a bottom surface located at different levels. The first buried pattern 521 may be disposed in the first through conductive pattern 511. The first buried pattern 521 may include a low refractive material and may have dielectric properties.

[0108] In the pad region R2, the conductive pad CP may be disposed on the second surface 100b of the semiconductor substrate 100. The conductive pad CP may be buried in the second surface 100b of the semiconductor substrate 100. For example, in the pad region R2, the conductive pad CP may be disposed in a pad groove formed in the second surface 100b of the semiconductor substrate 100. The conductive pad CP may include a metal (such as one or more of aluminum, copper, tungsten, titanium, tantalum, or any alloy thereof (such as a homogeneous alloy)). In the mounting process of the image sensor, a plurality of bonding wires may be bonded to the conductive pad CP. The conductive pad CP may be electrically connected to an external device through the bonding wires.

[0109] On the pad region R2, the second through conductive pattern 513 may penetrate the semiconductor substrate 100 to be electrically connected to the wiring structure 1111. The second through conductive pattern 513 may extend to the second surface 100b of the semiconductor substrate 100 to be electrically connected to the conductive pad CP. A portion of the second through conductive pattern 513 may cover the bottom surface and sidewall of the conductive pad CP. The second buried pattern 523 may be disposed in the second through conductive pattern 513. The second buried pattern 523 may include a low refractive material and may have dielectric properties. On the pad region R2, a second pixel isolation structure PIS2 may be disposed around the second through conductive pattern 513.

[0110] The logic chip S2 may include a logic semiconductor substrate 1000, a logic circuit TR, a wiring structure 1111 connected to the logic circuit TR, and a logic interlayer dielectric layer 1100. The uppermost logic interlayer dielectric layer 1100 among the logic interlayer dielectric layers 1100 may be bonded to the pixel circuit layer 20 of the sensor chip S1. The logic chip S2 may be electrically connected to the sensor chip S1 through the first through conductive pattern 511 and the second through conductive pattern 513.

[0111] Reference Figure 8 and Fig. 9B , can be omitted Fig.9A The first and second through conductive patterns 511 and 513 and the first and second buried patterns 521 and 523 are formed. The bonding pads of the sensor chip S1 and the logic chip S2 may be bonded to each other to achieve electrical connection between the sensor chip S1 and the logic chip S2.

[0112] For example, the sensor chip S1 of the image sensor may include a first bonding pad BP1 located on top of the pixel circuit layer 20. The logic chip S2 may include a second bonding pad BP2 located on top of the logic interlayer dielectric layer 1100. For example, the first bonding pad BP1 located on the top surface of the sensor chip S1 and the second bonding pad BP2 located on the top surface of the logic chip S2 may be bonded to each other. The first bonding pad BP1 and the second bonding pad BP2 may include, for example, at least one selected from tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0113] The first bonding pad BP1 of the sensor chip S1 may be directly electrically connected to the second bonding pad BP2 of the logic chip S2 by hybrid bonding. The term "hybrid bonding" may mean that two components of the same type are merged at the interface between them. For example, when the first bonding pad BP1 and the second bonding pad BP2 are formed of copper, copper-to-copper bonding may be used to physically and electrically connect the first bonding pad BP1 and the second bonding pad BP2 to each other.

[0114] FIG. 10A to FIG. 17B A cross-sectional view illustrating a method of manufacturing an image sensor according to some example embodiments is illustrated. Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A Shown along Figure 3 A cross-sectional view taken along line AA'. Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B Shown along Figure 3 A cross-sectional view taken along line BB'.

[0115] Reference Fig. 10A and Fig. 10B, a semiconductor substrate 100 having a first conductivity type (e.g., p-type) may be provided, and in some cases the semiconductor substrate 100 may be doped (e.g., lightly doped) with, for example, boron (B). The semiconductor substrate 100 may have a first surface 100a and a second surface 100b facing away from each other. The semiconductor substrate 100 may include an epitaxial layer having a first conductivity type formed on a bulk silicon substrate having a first conductivity type. For example, the epitaxial layer may be formed by performing a selective epitaxial growth (SEG) process in which a bulk silicon substrate is used as a seed, and an impurity having a first conductivity type may be doped during and / or after the selective epitaxial growth process (e.g., by an ion implantation process after the selective epitaxial growth process).

[0116] According to some example embodiments, the semiconductor substrate 100 may be or include a bulk silicon substrate including a well having a first conductivity type, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, or a silicon germanium substrate.

[0117] The first surface 100a of the semiconductor substrate 100 may be patterned to form a device isolation trench. The device isolation trench may define Figure 3 The device isolation trench may be formed by forming a buffer layer BFL and a mask pattern MP on the first surface 100a of the semiconductor substrate 100 and performing an anisotropic etching process using the mask pattern MP as an etching mask.

[0118] The buffer layer BFL may be formed by performing a deposition process or a thermal oxidation process on the first surface 100a of the semiconductor substrate 100. For example, the buffer layer BFL may include a silicon oxide layer, and the mask pattern MP may include a silicon nitride layer or a silicon oxynitride layer.

[0119] Afterwards, a device isolation dielectric layer 105a may be formed to fill the device isolation trench. The device isolation dielectric layer 105a may be formed by depositing a thick dielectric material on the semiconductor substrate 100 having the device isolation trench. The device isolation dielectric layer 105a may cover the mask pattern MP while filling the device isolation trench.

[0120] Reference Fig.11A and Fig. 11B A first trench T1 and a second trench T2 may be formed on the semiconductor substrate 100 to define Figure 3The pixel region PR of the semiconductor substrate 100 is formed by patterning the device isolation dielectric layer 105a and the first surface 100a of the semiconductor substrate 100. For example, the first trench T1 and the second trench T2 may be formed by forming a second mask pattern (not shown) on the device isolation dielectric layer 105a and performing an anisotropic etching process using the second mask pattern as an etching mask to remove a portion of the semiconductor substrate 100.

[0121] The first trench T1 and the second trench T2 may vertically extend from the first surface 100a of the semiconductor substrate 100 to the second surface 100b of the semiconductor substrate 100 to partially expose the sidewall of the semiconductor substrate 100. The first trench T1 and the second trench T2 may be formed to be deeper than the device isolation trench and may penetrate a portion of the device isolation trench. For example, each of the first trench T1 and the second trench T2 may be a deep trench having an aspect ratio (or height-to-width ratio) of about 10:1 to about 15:1, but example embodiments are not limited thereto.

[0122] Each of the first trench T1 and the second trench T2 may have a width that gradually decreases in a direction from the first surface 100a to the second surface 100b of the semiconductor substrate 100. For example, each of the first trench T1 and the second trench T2 may have an inclined sidewall. The first trench T1 and the second trench T2 may have a bottom surface that is spaced apart from the second surface 100b of the semiconductor substrate 100 in the fourth direction D4. However, example embodiments are not limited thereto, and each of the first trench T1 and the second trench T2 may have a constant width along the fourth direction D4.

[0123] Each of the first trench T1 and the second trench T2 may have a vertical length in the fourth direction D4. The vertical length of the first trench T1 may be substantially the same as the vertical length of the second trench T2. The first trench T1 may have a horizontal width in the first direction D1. The second trench T2 may have a horizontal width in the third direction D3. The horizontal width of the first trench T1 may be smaller than the horizontal width of the second trench T2. Therefore, the same components formed in the first trench T1 and the second trench T2 may have shapes different from each other.

[0124] According to some example embodiments, a doping process may be performed on the semiconductor substrate 100. The doping process may include doping impurities having a first conductivity type into the sidewalls of the semiconductor substrate 100 exposed by the first trench T1 and the second trench T2. For example, the doping process may include one or more of a beam line ion implantation (BLII) process, a gas phase doping (GPD) process, and a plasma doping (PLAD) process. In the case of a plasma doping process, a gaseous source material may be supplied to a process chamber. After plasma ionization of the source material, a high voltage bias may be applied to an electrostatic chuck (not shown) loaded with the semiconductor substrate 100, and the ionized source material may be injected into the sidewalls of the semiconductor substrate 100. Therefore, the sidewalls of the semiconductor substrate 100 may have a uniform impurity concentration regardless of the position (or height).

[0125] Then, a liner dielectric layer 111a, a first conductive layer 113a, and an inner dielectric layer 115a may be sequentially formed on the inner sidewalls of the first trench T1 and the second trench T2. The liner dielectric layer 111a may have a uniform thickness covering the inner sidewalls of the first trench T1 and the second trench T2. The liner dielectric layer 111a may be deposited by using a deposition process with excellent step coverage. For example, the liner dielectric layer 111a may include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. Alternatively or additionally, the liner dielectric layer 111a may include a multilayer formed of at least two selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0126] The first conductive layer 113a may have a uniform thickness covering the pad dielectric layer 111a. The first conductive layer 113a may be formed by a deposition method using a precursor. For example, the first conductive layer 113a may include polysilicon doped with impurities. In this case, one or both of diisopropylaminosilane (DIPAS) and hexachlorodisilane (HCDS) may be used as precursors. The thickness of the first conductive layer 113a may be less than the thickness of the pad dielectric layer 111a, but example embodiments are not limited thereto. For example, a doping process may be performed on the first conductive layer 113a. The doping process may include doping impurities having a first conductivity type or a second conductivity type. For example, the doping process may be performed while or after the first conductive layer 113a is formed.

[0127] The inner dielectric layer 115a may have a uniform thickness covering the first conductive layer 113a. Similar to the liner dielectric layer 111a, the inner dielectric layer 115a may be deposited by using a deposition process with excellent step coverage. The inner dielectric layer 115a may be formed at a low point within the first trench T1 and the second trench T2. For example, the inner dielectric layer 115a may completely fill the lower portion of the first trench T1. On the contrary, the inner dielectric layer 115a may partially fill the lower portion of the second trench T2. Since the horizontal width of the first trench T1 is smaller than the horizontal width of the second trench T2, the inner dielectric layer 115a in the first trench T1 may have a different shape from the inner dielectric layer 115a in the second trench T2.

[0128] Reference Fig. 12A and Fig. 12B , a first impurity layer I1 may be formed on the semiconductor substrate 100. The first impurity layer I1 may be formed by a first ion implantation process IMP1 in which a first impurity is doped. The first impurity may be implanted into the internal dielectric layer 115a to stay between atoms included in the internal dielectric layer 115a. Therefore, in an etching process subsequently performed to remove the internal dielectric layer 115a, the first impurity layer I1 may be etched at an etching rate relatively smaller than an etching rate of the internal dielectric layer 115a in which the first impurity is not doped. In this case, the first impurity layer I1 may be used as an etching stop layer in the etching process. The first impurity used in the first ion implantation process IMP1 may include, for example, at least one selected from boron (B), carbon (C), silicon (Si), and argon (Ar). For example, the first impurity in the first impurity layer I1 may have a carbon content equal to or greater than about 1×10 14 ions / cm 2 concentration.

[0129] According to various example embodiments, the first ion implantation process IMP1 may be performed in a state where the semiconductor substrate 100 is tilted (eg, tilted relative to the ion beam). In this case, the tilt angle of the semiconductor substrate 100 may be in a range of about 1° to about 4°.

[0130] Since each of the first trench T1 and the second trench T2 corresponds to a deep trench having a high aspect ratio, the first impurity layer I1 formed by the first ion implantation process IMP1 may be located at different levels inside and outside the first trench T1 and the second trench T2. For example, outside the first trench T1 and the second trench T2, the first impurity layer I1 may be formed to be higher than the first surface 100a of the semiconductor substrate 100. In the first trench T1 and the second trench T2, the first impurity layer I1 may be formed to be lower than the first surface 100a of the semiconductor substrate 100.

[0131] For example, in the first trench T1, the first impurity layer I1 may be formed adjacent to the first surface 100a of the semiconductor substrate 100, and in the second trench T2, the first impurity layer I1 may be formed adjacent to the second surface 100b of the semiconductor substrate 100. The first impurity layer I1 may be formed in the inner dielectric layer 115a. The first impurity layer I1 in the first trench T1 may be formed to be lower than the bottom surface 105b of the device isolation dielectric layer 105a. The first height H1 in the fourth direction D4 may be set between the top surface of the first impurity layer I1 in the first trench T1 and the bottom surface 105b of the device isolation dielectric layer 105a. The formation position of the first impurity layer I1 may depend on the doping depth (corresponding to the doping energy) of the first impurity implanted by the first ion implantation process IMP1. For example, the first height H1 may be in the range of about 5nm to about 1000nm.

[0132] Reference Fig.13A and Fig. 13B , a second impurity layer I2 may be formed on the semiconductor substrate 100. The second impurity layer I2 may be formed by a second ion implantation process IMP2 doped with a second impurity. The second impurity may be implanted into the internal dielectric layer 115a to break the bonds of atoms included in the internal dielectric layer 115a. Therefore, in an etching process subsequently performed to remove the internal dielectric layer 115a, the second impurity layer I2 may be etched at a relatively greater etching rate than the etching rate of the internal dielectric layer 115a in which the second impurity is not doped. In this case, the second impurity layer I2 may be used as an etching promoting layer in the etching process. Therefore, there may be a large etching rate difference between the first impurity layer I1 and the second impurity layer I2. The second impurity used in the second ion implantation process IMP2 may include a second impurity layer from BF 3 , arsenic (As) and phosphorus (P).

[0133] The doping depth of the second impurity implanted by the second ion implantation process IMP2 may be less than the doping depth of the first impurity implanted by the first ion implantation process IMP1. The doping depth corresponding to the first ion implantation process IMP1 and the doping depth corresponding to the second ion implantation process IMP2 may be determined, for example, based on the corresponding energy associated with the corresponding ion beam. For example, a higher energy may correspond to a deeper implantation profile. Alternatively or additionally, the doping depth may correspond to the atomic mass of the corresponding substance used in the implantation. Therefore, the second impurity layer I2 may be located on the first impurity layer I1. In this case, the second impurity layer I2 may be formed in the upper portion of the first trench T1 and the second trench T2. For example, the second impurity layer I2 may be formed to be higher than the bottom surface 105b of the device isolation dielectric layer 105a. The second impurity layer I2 and the first impurity layer I1 may partially overlap each other. However, example embodiments are not limited thereto.

[0134] Reference Fig.14A and Fig. 14B , an inner dielectric pattern 115 may be formed in the first trench T1. The inner dielectric pattern 115 may be formed by a wet etching process using an etching selectivity between the inner dielectric layer 115a, the first impurity layer I1, and the second impurity layer I2. The second impurity layer I2 may have a greater etching rate than the inner dielectric layer 115a, and the first impurity layer I1 may have a smaller etching rate than the inner dielectric layer 115a. For example, in the wet etching process, the second impurity layer I2 may be used as an etching promotion layer, and the first impurity layer I1 may be used as an etching stop layer. Therefore, in the wet etching process, the second impurity layer I2 may be removed, and the first impurity layer I1 may not be removed.

[0135] In the first trench T1, the first impurity layer I1 may close the upper portion of the first trench T1, and thus the inner dielectric layer 115a below the first impurity layer I1 may not be removed. Therefore, a portion of the inner dielectric layer 115a in the first trench T1 may be formed as the inner dielectric pattern 115. In contrast, in the second trench T2, the first impurity layer I1 may not close the upper portion of the second trench T2, and thus the inner dielectric layer 115a may be removed.

[0136] For example, the formation of the inner dielectric pattern 115 may include: forming a first impurity layer I1 serving as an etch stop layer; forming a second impurity layer I2 serving as an etch promoting layer; and removing a portion of the inner dielectric layer 115 a including the second impurity layer I2 .

[0137] Then, the first conductive pattern 113 may be formed in the lower portion of the first trench T1 and the lower portion of the second trench T2. The first conductive pattern 113 may be formed by an etching process that removes a portion of the first conductive layer 113a. For example, an etch-back process may be used as the etching process that removes a portion of the first conductive layer 113a.

[0138] The etching process may continue until the top surface of the first conductive pattern 113 becomes coplanar with the top surface of the first impurity layer I1 in the first trench T1. The first height H1 in the fourth direction D4 may be set between the top surface of the first conductive pattern 113 in the first trench T1 and the bottom surface 105b of the device isolation dielectric layer 105a. The second height H2 in the fourth direction D4 may be set between the top surface of the first conductive pattern 113 in the second trench T2 and the bottom surface 105b of the device isolation dielectric layer 105a. When the horizontal width of the second trench T2 is greater than the horizontal width of the first trench T1, the first conductive layer 113a in the second trench T2 may be etched more than the first conductive layer 113a in the first trench T1. In this case, the second height H2 may be substantially equal to or greater than the first height H1.

[0139] Reference Fig.15A and Fig. 15B , a second conductive layer 118a may be formed on the semiconductor substrate 100. In the first trench T1, the second conductive layer 118a may be located on the first impurity layer I1. In the second trench T2, the second conductive layer 118a may be located on the first conductive pattern 113. For example, the second conductive layer 118a may fill the upper portion of the first trench T1 and the upper and lower portions of the second trench T2.

[0140] The second conductive layer 118a may be deposited by using a deposition method having excellent step coverage, and the deposition method may include low pressure chemical vapor deposition (LPCVD) and / or plasma enhanced chemical vapor deposition (PECVD). The second conductive layer 118a may include polysilicon doped with impurities. For example, the second conductive layer 118a may include a material substantially the same as that of the first conductive pattern 113, but example embodiments are not limited thereto.

[0141] Reference Fig.16A and Fig. 16B , a first pixel isolation structure PIS1 may be formed in the first trench T1, and a second pixel isolation structure PIS2 may be formed in the second trench T2. For example, the second conductive pattern 118 may be formed by an etching process that removes a portion of the second conductive layer 118a. The etching process may be continued until the top surface of the second conductive pattern 118 becomes coplanar with the top surface of the first conductive pattern 113 in the second trench T2. For example, the formation of the second conductive pattern 118 may be substantially the same as the formation of the first conductive pattern 113. Therefore, the second conductive layer 118a formed in the upper portion of the first trench T1 and the upper portion of the second trench T2 may be removed. Therefore, the second conductive pattern 118 may be formed only in the second trench T2.

[0142] According to some example embodiments, a portion of the second conductive pattern 118 may remain in the first trench T1. Fig. 6A and Figure 6B As shown in FIG. 1 , the second conductive pattern 118 may be formed in the first trench T1 and the second trench T2 . In this case, the top surface of the second conductive pattern 118 may be higher than the top surface of the first conductive pattern 113 .

[0143] Afterwards, a buried dielectric layer (not shown) may be formed to fill the first trench T1 and the second trench T2. The buried dielectric layer may be formed by using a film forming technique with excellent step coverage, such as chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). For example, the buried dielectric layer may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0144] The mask pattern MP may be removed, and a planarization process may be performed to expose the first surface 100a of the semiconductor substrate 100. The planarization process may remove a portion of the first impurity layer I1, a portion of the device isolation dielectric layer 105a, a portion of the pad dielectric layer 111a, and a portion of the buried dielectric layer. As a result, the device isolation dielectric layer 105a may be formed as a device isolation layer 105, the pad dielectric layer 111a may be formed as a pad dielectric pattern 111, and the buried dielectric layer may be formed as a buried dielectric pattern 119. The first impurity layer I1 in the first trench T1 may be formed as an etch stop layer 117. The top surface of the device isolation layer 105 and the top surface of the buried dielectric pattern 119 may be coplanar with the first surface 100a of the semiconductor substrate 100.

[0145] For example, the formation of the first pixel isolation structure PIS1 may include: forming a liner dielectric pattern 111, a first conductive pattern 113, an inner dielectric pattern 115, an etch stop layer 117, and a buried dielectric pattern 119 on the inner sidewall of the first trench T1. The formation of the second pixel isolation structure PIS2 may include: forming a liner dielectric pattern 111, a first conductive pattern 113, a second conductive pattern 118, and a buried dielectric pattern 119 on the inner sidewall of the second trench T2.

[0146] Reference Fig.17A and Fig. 17B , a photoelectric conversion region PD having a second conductivity type may be formed in the semiconductor substrate 100. The photoelectric conversion region PD may be formed by doping the semiconductor substrate 100 with impurities having a second conductivity type (e.g., n-type). The photoelectric conversion region PD may be spaced apart from the first surface 100a and the second surface 100b of the semiconductor substrate 100. Thus, the photoelectric conversion layer 10 of the image sensor may be formed. According to an embodiment, the photoelectric conversion region PD may be formed before forming the first pixel isolation structure PIS1 and the second pixel isolation structure PIS2.

[0147] The pixel circuit layer 20 may be formed on the first surface 100a of the semiconductor substrate 100. The formation of the pixel circuit layer 20 may include forming a transfer gate electrode TG, forming a floating diffusion region FD, and forming an interlayer dielectric layer 210 and a wiring structure.

[0148] The formation of the transmission gate electrode TG may include: patterning the semiconductor substrate 100 to form a gate recessed region; forming a gate dielectric layer GIL conformally covering the inner wall of the gate recessed region; forming a gate conductive layer filling the gate recessed region; and patterning the gate conductive layer. For example, the formation of the transmission gate electrode TG may include forming Figure 3 The pixel gate electrode PG.

[0149] The formation of the floating diffusion region FD may include implanting impurities having the second conductivity type into one side of the transfer gate electrode TG in the semiconductor substrate 100. When the floating diffusion region FD is formed, source / drain regions of the pixel transistor may be simultaneously formed.

[0150] The formation of the interlayer dielectric layer 210 and the wiring structure may include: forming the interlayer dielectric layer 210 covering the first surface 100a of the semiconductor substrate 100; and forming the wiring structure connected to the floating diffusion region FD and the pixel transistor in the interlayer dielectric layer 210. The interlayer dielectric layer 210 may cover the MOS transistor constituting (or corresponding to) the pixel circuit. The interlayer dielectric layer 210 may be formed of a material having excellent gap filling characteristics and may have a planarized upper portion. A contact plug 221 may be formed in the interlayer dielectric layer 210. A plurality of metal lines 223 may be formed in the interlayer dielectric layer 210. The contact plug 221 and the metal line 223 may be formed of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), or any alloy thereof.

[0151] Return to reference Figure 4A and Figure 4B , a thinning process may be performed to remove a portion of the semiconductor substrate 100, thereby reducing the vertical thickness of the semiconductor substrate 100. The thinning process may include grinding or polishing the second surface 100b of the semiconductor substrate 100, and anisotropically and / or isotropically etching the second surface 100b of the semiconductor substrate 100. The semiconductor substrate 100 may be inverted to perform the thinning process thereon.

[0152] A planarization dielectric layer 310, a grid structure 320, a protective layer 330, a color filter 340, a microlens 350, and a passivation layer 360 may be sequentially formed on the second surface 100b of the semiconductor substrate 100. Thus, the optical transmission layer 30 of the image sensor may be formed.

[0153] The planarization dielectric layer 310 may cover the second surface 100b of the semiconductor substrate 100. For example, the planarization dielectric layer 310 may be formed by depositing a metal oxide such as one or more of aluminum oxide and hafnium oxide.

[0154] The grid structure 320 may include one or more of a light shielding pattern and a low refractive pattern. For example, the light shielding pattern may include a metal material (such as titanium, tantalum, or tungsten). The low refractive pattern may be formed of a material with a refractive index less than that of the light shielding pattern. The low refractive pattern may be formed of an organic material and may have a refractive index of about 1.1 to about 1.3. For example, the grid structure 320 may be a polymer layer including silicon nanoparticles.

[0155] A protective layer 330 may be disposed on the planarization dielectric layer 310, the protective layer 330 having a substantially uniform thickness covering the surface of the grid structure 320. For example, the protective layer 330 may include a single layer or multiple layers of at least one selected from an aluminum oxide layer and a silicon oxycarbide layer.

[0156] The color filter 340 may be formed on the protective layer 330 to correspond to the pixel region PR. For example, the color filter 340 may include a blue color filter, a red color filter, and a green color filter.

[0157] Microlenses 350 may be correspondingly formed on the color filter 340. The microlenses 350 may each have a convex shape with a certain radius of curvature. The microlenses 350 may be formed of a light-transmitting resin.

[0158] The passivation layer 360 may conformally cover the top surface of the microlens 350. For example, the passivation layer 360 may include an inorganic oxide.

[0159] FIG. 18A to FIG. 21B A cross-sectional view illustrating a method of manufacturing an image sensor according to some example embodiments is illustrated. Fig.18A , Fig.19A , Fig. 20A and Fig.21A Shown along Figure 3 A cross-sectional view taken along line AA'. Fig.18B , Fig.19B , Fig. 20B and Fig.21B Shown along Figure 3 A cross-sectional view taken along line BB'.

[0160] Reference Fig.18A and Fig.18B , a buffer layer BFL, a mask pattern MP, and a device isolation dielectric layer 105a may be formed on the semiconductor substrate 100. The formation of the buffer layer BFL, the mask pattern MP, and the device isolation dielectric layer 105a may be similar to Fig. 10A and Fig. 10B Basically the same as discussed in .

[0161] A first trench T1 and a second trench T2 may be formed in the semiconductor substrate 100. Fig.11A and Fig. 11B Basically the same as discussed in , a liner dielectric layer 111 a , a first conductive layer 113 a , and an inner dielectric layer 115 a may be formed on the inner sidewalls of the first trench T1 and the second trench T2 .

[0162] A preliminary inner dielectric pattern 115b may be formed in the first trench T1. The preliminary inner dielectric pattern 115b may be formed by a wet etching process that removes a portion of the inner dielectric layer 115a. The horizontal width of the second trench T2 may be greater than the horizontal width of the first trench T1, and thus the inner dielectric layer 115a in the second trench T2 may have a relatively large surface area exposed to the etching solution. Therefore, the inner dielectric layer 115a in the second trench T2 may be removed, but the inner dielectric layer 115a in the first trench T1 may be only partially removed. The preliminary inner dielectric pattern 115b may be formed to have a top surface that is higher than the bottom surface 105b of the device isolation dielectric layer 105a.

[0163] The preliminary first conductive pattern 113b may be formed in the first trench T1 and the second trench T2. The preliminary first conductive pattern 113b may be formed by an etching process that removes a portion of the first conductive layer 113a. The etching process that removes a portion of the first conductive layer 113a may be similar to the etching process that removes a portion of the first conductive layer 113a. Fig.14A and Fig. 14B Since the top surface of the preliminary first conductive pattern 113b is coplanar with the top surface of the preliminary inner dielectric pattern 115b, the top surface of the preliminary first conductive pattern 113b may be higher than the bottom surface 105b of the device isolation dielectric layer 105a.

[0164] A second conductive layer 118a may be formed on the preliminary inner dielectric pattern 115b and the preliminary first conductive pattern 113b. The second conductive layer 118a may be formed in the same manner as described above. Fig.15A and Fig. 15B Basically the same as discussed in .

[0165] Reference Fig.19A and Fig.19B , a preliminary second conductive pattern 118b may be formed in the second trench T2. The preliminary second conductive pattern 118b may be formed by an etching process that removes a portion of the second conductive layer 118a. The etching process that removes a portion of the second conductive layer 118a may be similar to the etching process that removes a portion of the second conductive layer 118a. Fig.16A and Fig. 16B For example, the second conductive layer 118a in the first trench T1 may be completely removed, and the preliminary second conductive pattern 118b may be formed only in the second trench T2. The preliminary second conductive pattern 118b may be formed to have a top surface higher than the bottom surface 105b of the device isolation dielectric layer 105a.

[0166] A first impurity layer I1 may be formed on the semiconductor substrate 100. The first impurity layer I1 may be formed by a first ion implantation process IMP1 doping the first impurity. The first ion implantation process IMP1 may be performed in conjunction with Fig. 12A and Fig. 12B Basically the same as discussed in .

[0167] In the first trench T1, the first impurity layer I1 may be formed in the preliminary first conductive pattern 113b and the preliminary inner dielectric pattern 115b. In the second trench T2, the first impurity layer I1 may be formed in the preliminary first conductive pattern 113b and the preliminary second conductive pattern 118b. For example, the first impurity layer I1 may be formed as an etch stop layer even in the second trench T2. In the first trench T1 and the second trench T2, the first impurity layer I1 may be formed to be lower than the bottom surface 105b of the device isolation dielectric layer 105a.

[0168] Reference Fig. 20A and Fig. 20B , a second impurity layer I2 may be formed on the semiconductor substrate 100. The second impurity layer I2 may be formed by a second ion implantation process IMP2 doping a second impurity. The second ion implantation process IMP2 may be Fig.13A and Fig. 13B Basically the same as discussed in .

[0169] The second impurity layer I2 may be formed on the first impurity layer I1. In the first trench T1 and the second trench T2, the second impurity layer I2 may be formed on the preliminary second conductive pattern 118b, the preliminary first conductive pattern 113b, and the preliminary inner dielectric pattern 115b.

[0170] Reference Fig.21A and Fig.21B , a first pixel isolation structure PIS1 may be formed in the first trench T1. A second pixel isolation structure PIS2 may be formed in the second trench T2. The first pixel isolation structure PIS1 may include a first etch stop layer 117a, and the second pixel isolation structure PIS2 may include a second etch stop layer 117b. The first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 may be connected to Fig. 7A and Figure 7B Basically the same as discussed in .

[0171] The second impurity layer I2 may be removed by a wet etching process. The wet etching process may be Fig.13A and Fig. 13B For example, the difference in etching rate between the first impurity layer I1 and the second impurity layer I2 can be used to remove the second impurity layer I2 and retain the first impurity layer I1. Therefore, the first impurity layer I1 in the first trench T1 can be formed as the first etch stop layer 117a, and the first impurity layer I1 in the second trench T2 can be formed as the second etch stop layer 117b.

[0172] The mask pattern MP may be removed, and a planarization process may be performed to expose the first surface 100a of the semiconductor substrate 100. The planarization process may be performed at the same time as Fig.16A and Fig. 16B Basically the same as discussed in .

[0173] The semiconductor substrate 100 may be formed on the first surface 100a and the second surface 100b of the semiconductor substrate 100. Figure 4A and Figure 4B The pixel circuit layer 20 and the optical transmission layer 30 are formed, and this step may be substantially the same as discussed above.

[0174] An image sensor according to some example embodiments may include a pixel isolation structure including an etch stop layer. When manufacturing the image sensor, the etch stop layer may determine the level (or height) of the top surface of the first conductive pattern. Therefore, the horizontal overlapping area between the semiconductor substrate and the first conductive pattern may be increased. Therefore, the negative bias voltage applied to the first conductive pattern may sufficiently reduce the dark current of the image sensor, and thus the electrical and optical characteristics of the image sensor may be improved.

[0175] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the disclosed range. In addition, when the words "generally" and "substantially" are used in conjunction with a material composition, it is intended that the accuracy of the material is not required, but the tolerance of the material is within the disclosed range.

[0176] In addition, regardless of whether a value or shape is modified to "about (approximately)" or "substantially (substantially)", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated value or shape. Therefore, although the terms "same", "equivalent" or "equal" are used in the description of example embodiments, it should be understood that there may be some imprecision. Therefore, when an element or a value is referred to as being the same as another element or being equal to another value, it should be understood that the element or value is the same as the other element or the other value within the desired manufacturing or operating tolerance range (e.g., ±10%).

[0177] Although the inventive concept has been described in conjunction with the example embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the example embodiments. Therefore, it will be understood that the embodiments described above are merely illustrative and non-restrictive in all respects. In addition, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more drawings, and may also include one or more other features described with reference to one or more other drawings.

Claims

1. An image sensor, comprising: a semiconductor substrate having a first conductivity type and including a first surface and a second surface facing away from each other; a plurality of photoelectric conversion regions in the semiconductor substrate and having a second conductivity type; as well as A first pixel isolation structure is located between photoelectric conversion regions adjacent to each other in a first direction, Wherein, the first pixel isolation structure includes: a first conductive pattern spaced apart from the first surface and extending in a direction perpendicular to the first surface, an inner dielectric pattern, on an inner side surface of the first conductive pattern, a buried dielectric pattern, on the inner dielectric pattern, and An etch stop layer is between the inner dielectric pattern and the buried dielectric pattern.

2. The image sensor according to claim 1, further comprising: A second pixel isolation structure is located between photoelectric conversion regions adjacent to each other in a second direction oblique to the first direction, Wherein, the second pixel isolation structure includes: a first conductive pattern, a second conductive pattern on an inner side surface of the first conductive pattern in the second pixel isolation structure, and The dielectric pattern is buried on the second conductive pattern.

3. The image sensor according to claim 2, wherein: The first conductive pattern of the second pixel isolation structure has a thickness that decreases as the distance from the first surface of the semiconductor substrate decreases.

4. The image sensor according to claim 2, wherein: A top surface of the first conductive pattern included in the second pixel isolation structure is coplanar with a top surface of the second conductive pattern.

5. The image sensor according to claim 2, wherein: A top surface of the first conductive pattern included in the second pixel isolation structure is lower than a top surface of the second conductive pattern.

6. The image sensor according to claim 2, wherein: A bottom surface of the buried dielectric pattern included in the first pixel isolation structure and a bottom surface of the buried dielectric pattern included in the second pixel isolation structure are at different levels.

7. The image sensor according to claim 2, wherein: The width of the first pixel isolation structure in the first direction is smaller than the width of the second pixel isolation structure in the second direction.

8. The image sensor according to claim 2, wherein: The first pixel isolation structure further includes a second conductive pattern, wherein the second conductive pattern in the first pixel isolation structure is between the etch stop layer and the buried dielectric pattern.

9. The image sensor according to claim 2, wherein: The first conductive pattern and the second conductive pattern in the first pixel isolation structure and the second pixel isolation structure include polysilicon.

10. The image sensor according to claim 2, wherein: The first direction and the second direction are parallel to the first surface and the second surface of the semiconductor substrate.

11. The image sensor according to claim 1, wherein: The etch stop layer includes at least one selected from carbon, silicon, argon, and boron.

12. The image sensor according to any one of claims 1 to 11, further comprising: a device isolation layer in the semiconductor substrate and adjacent to the first surface, wherein The first pixel isolation structure penetrates the device isolation layer, and The bottom surface of the device isolation layer is higher than the etch stop layer.

13. The image sensor according to claim 12, wherein: A distance between a bottom surface of the device isolation layer and a top surface of the etch stop layer is in a range of 5 nm to 1000 nm.

14. An image sensor, comprising: a semiconductor substrate having a first conductivity type and including a first surface and a second surface facing away from each other; a plurality of photoelectric conversion regions in the semiconductor substrate and having a second conductivity type; a device isolation layer in the semiconductor substrate and adjacent to the first surface; a first pixel isolation structure located between two adjacent photoelectric conversion regions among the plurality of photoelectric conversion regions and comprising a first etch stop layer; as well as a second pixel isolation structure located between adjacent four photoelectric conversion regions among the plurality of photoelectric conversion regions and including a second etch stop layer, The first etch stop layer and the second etch stop layer are between the bottom surface of the device isolation layer and the second surface of the semiconductor substrate.

15. The image sensor according to claim 14, wherein: The first etch stop layer and the second etch stop layer independently include at least one selected from carbon, silicon, argon, and boron.

16. The image sensor according to claim 14, in, The first pixel isolation structure includes: an inner dielectric pattern between the first etch stop layer and the second surface, and a first conductive pattern, on an opposite side of the inner dielectric pattern, Wherein, the second pixel isolation structure includes: a second conductive pattern between the second etch stop layer and the second surface, and The first conductive pattern is on an opposite side of the second conductive pattern.

17. The image sensor according to any one of claims 14 to 16, wherein: Each of the first pixel isolation structure and the second pixel isolation structure has a width that decreases in a direction from the first surface to the second surface.

18. An image sensor, comprising: a semiconductor substrate including a light receiving region, a light shielding region, and a pad region and having a first surface and a second surface facing away from each other; a pixel isolation structure, in the semiconductor substrate on the light receiving region and the light shielding region, the pixel isolation structure defining a plurality of pixel regions and including a first conductive pattern; a transfer gate electrode on the first surface of the semiconductor substrate; a plurality of photoelectric conversion regions in the semiconductor substrate on the light receiving region and the light shielding region; A pixel circuit layer, on the first surface of the semiconductor substrate; as well as an optical transmission layer on the second surface of the semiconductor substrate, Wherein, the pixel isolation structure includes: a plurality of first pixel isolation structures located between pixel regions adjacent to each other in a first direction or in a second direction intersecting the first direction, and A plurality of second pixel isolation structures are located between pixel regions adjacent to each other in a third direction obliquely intersecting the first direction and the second direction, wherein: A first pixel isolation structure of the plurality of first pixel isolation structures further includes an inner dielectric pattern on an inner side surface of the first conductive pattern, and A second pixel isolation structure among the plurality of second pixel isolation structures further includes a second conductive pattern on an inner side surface of the first conductive pattern.

19. The image sensor according to claim 18, wherein: The first direction, the second direction, and the third direction are parallel to the first surface and the second surface.

20. The image sensor according to claim 18, wherein: The first pixel isolation structure also includes: a buried dielectric pattern adjacent to the first surface; and an etch stop layer between the inner dielectric pattern and the buried dielectric pattern, The etching stop layer includes at least one selected from carbon, silicon, argon and boron.

Images