Display panel and method for manufacturing same

Abstract

The invention relates to a display panel and a method for manufacturing the same. The display panel includes: a base layer; a pixel defining film on the base layer and having a light emitting opening; a partition wall on the pixel defining film and having a partition wall opening overlapping the light emitting opening; a light emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall and in the partition wall opening; and an inorganic encapsulation pattern including a first inorganic encapsulation pattern and a second inorganic encapsulation pattern sequentially arranged on the cathode. The first inorganic encapsulation pattern includes a plurality of inorganic patterns stacked repeatedly.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0165700, filed on November 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Herein, embodiments of the present disclosure relate to a display panel and a method for manufacturing the same, and, for example, to a display panel having improved display quality. Background Art

[0004] Display devices such as televisions, monitors, smart phones, and tablet computers that provide images to users include display panels that display images. Various display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and / or electrophoretic display panels are being developed.

[0005] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern (eg, between the anode and the cathode). The light emitting pattern may be separated from each other in one or more suitable light emitting regions, and the cathode may provide a common voltage in each of the light emitting regions.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] Aspects of one or more embodiments of the present disclosure are directed to a display panel having improved display quality and on which a light emitting element is formed without using a metal mask, and a method for manufacturing the display panel.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] One or more embodiments of the present disclosure provide a display panel, comprising: a base layer; a pixel defining film on the base layer and having a light-emitting opening; a partition wall on the pixel defining film and having a partition wall opening overlapping the light-emitting opening; a light-emitting element, comprising an anode, an intermediate layer and a cathode, (the cathode) being in contact with the partition wall and (the cathode) being in the partition wall opening; and an inorganic encapsulation pattern, comprising a first inorganic encapsulation pattern and a second inorganic encapsulation pattern sequentially arranged on the cathode, wherein the first inorganic encapsulation pattern comprises a plurality of inorganic patterns repeatedly stacked.

[0010] In one or more embodiments, the plurality of inorganic patterns may each include silicon nitride (SiN x ) and / or silicon oxynitride (SiON).

[0011] In one or more embodiments, the plurality of inorganic patterns may each include a first sub-pattern and a second sub-pattern, and the first sub-pattern and the second sub-pattern may be sequentially and repeatedly stacked.

[0012] In one or more embodiments, the second sub-pattern may be rich in nitrogen (N) compared to the first sub-pattern.

[0013] In one or more embodiments, the first sub-pattern may be richer in silicon (Si) than the second sub-pattern.

[0014] In one or more embodiments, a thickness of the first sub-pattern may be smaller than a thickness of the second sub-pattern.

[0015] In one or more embodiments, the plurality of inorganic patterns may include five or more inorganic patterns.

[0016] In one or more embodiments, the partition wall may include a first partition wall layer on the pixel defining film and a second partition wall layer on the first partition wall layer, and the first partition wall layer may have an undercut shape with respect to the second partition wall layer.

[0017] In one or more embodiments of the present disclosure, a display panel includes: a substrate layer; a pixel defining film on the substrate layer and having a light-emitting opening; a partition wall on the pixel defining film and having a partition wall opening overlapping the light-emitting opening; a light-emitting element including an anode, an intermediate layer, and a cathode, the cathode contacting the partition wall and in the partition wall opening; and a first inorganic encapsulation pattern including a first inorganic pattern and a second inorganic pattern sequentially arranged on the cathode. The first inorganic pattern includes a 1-1 sub-pattern on the cathode and a 2-1 sub-pattern on the 1-1 sub-pattern, and the second inorganic pattern includes a 1-2 sub-pattern on the 2-1 sub-pattern and a 2-2 sub-pattern on the 1-2 sub-pattern.

[0018] In one or more embodiments, the first inorganic pattern and the second inorganic pattern may each include silicon nitride (SiN x ) and / or silicon oxynitride (SiON).

[0019] In one or more embodiments, the first inorganic encapsulation pattern may include a first sub-pattern and a second sub-pattern, the first sub-pattern may include a 1-1th sub-pattern and a 1-2th sub-pattern, and the second sub-pattern may include a 2-1th sub-pattern and a 2-2th sub-pattern.

[0020] In one or more embodiments, the second sub-pattern may be rich in nitrogen (N) compared to the first sub-pattern.

[0021] In one or more embodiments, the first sub-pattern may be richer in silicon (Si) than the second sub-pattern.

[0022] In one or more embodiments, a thickness of the first sub-pattern may be smaller than a thickness of the second sub-pattern.

[0023] In one or more embodiments, the display panel may further include a second inorganic encapsulation pattern disposed on the 2-2 th sub-pattern.

[0024] In one or more embodiments of the present disclosure, a method for manufacturing a display panel includes: providing a preliminary display panel, the preliminary display panel including a substrate layer, a pixel defining film on the substrate layer, a first preliminary partition wall layer on the pixel defining film, and a second preliminary partition wall layer on the first preliminary partition wall layer; forming a first partition wall layer and a second partition wall layer having a partition wall opening by etching the first preliminary partition wall layer and the second preliminary partition wall layer; forming a light emitting pattern and a cathode inside the partition wall opening; and forming an inorganic encapsulation pattern on the cathode. The formation of the inorganic encapsulation pattern includes depositing a first inorganic encapsulation layer on the cathode, depositing a second inorganic encapsulation layer on the first inorganic encapsulation layer, and forming the first inorganic encapsulation pattern and the second inorganic encapsulation pattern by etching the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0025] In one or more embodiments, the deposition of the first inorganic encapsulation layer on the cathode may include: depositing a 1-1 sublayer on the cathode; and depositing a 2-1 sublayer on the 1-1 sublayer, wherein the first inorganic layer includes a 1-1 sublayer and a 2-1 sublayer, and the 1-1 sublayer is rich in silicon (Si), and the 2-1 sublayer is rich in nitrogen (N).

[0026] In one or more embodiments, the deposition of the first inorganic encapsulation layer on the cathode may further include: depositing a 1-2 sublayer on the first inorganic layer; and depositing a 2-2 sublayer on the 1-2 sublayer, wherein the second inorganic layer includes the 1-2 sublayer and the 2-2 sublayer, and the 1-2 sublayer is rich in silicon (Si), and the 2-2 sublayer is rich in nitrogen (N).

[0027] In one or more embodiments, the deposition of the 1-1 sub-layer on the cathode may include: introducing a silicon-containing gas and an argon gas; and introducing a nitrogen-containing gas and an argon gas.

[0028] In one or more embodiments, the deposition of the 2-1 sub-layer on the 1-1 sub-layer may include: introducing a silicon-containing gas, a nitrogen-containing gas, and an argon gas; and introducing a nitrogen-containing gas and an argon gas. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0030] Figure 1A is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0031] Figure 1B is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0032] Figure 2 is a cross-sectional view of a display module according to one or more embodiments of the present disclosure;

[0033] Figure 3 is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0034] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to one or more embodiments of the present disclosure;

[0035] Figure 5 According to one or more embodiments of the present disclosure, Figure 3 A cross-sectional view of the display panel taken along line II';

[0036] Figure 6 According to one or more embodiments of the present disclosure Figure 5 an enlarged view of area AA'; and

[0037] FIG. 7A to FIG. 7M is a cross-sectional view or schematic diagram illustrating some steps (eg, actions or tasks) of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] The present disclosure can be modified in many alternative forms, and therefore, specific embodiments will be illustrated in the drawings and will be described in more detail. However, it should be understood that this is not intended to limit the present disclosure to the particular form disclosed, but is intended to cover all modifications, equivalents and substitutes falling within the spirit and scope of the present disclosure.

[0039] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings. However, the present disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments illustrated herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0040] In this specification, it will be understood that when an element such as a region, layer, film, area or portion is referred to as being on, "connected to" or "coupled to" another element, it can be directly on, directly connected to or directly coupled to the other element, or one or more intervening elements may be present. Additionally, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0041] Unless otherwise specified, the same reference numerals or symbols refer to the same elements throughout the drawings and written descriptions, and therefore, repeated descriptions thereof may not be provided. In addition, in the drawings, the thickness, ratio, size, and dimensions of the elements may be exaggerated in order to effectively describe the technical content.

[0042] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0044] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] For ease of explanation, spatially relative terms such as "above", "below", "lower", "below", "above", and "upper" may be used herein to describe the relationship between an element or feature illustrated in the various figures and another (some) element or feature. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or in operation. For example, if the device in the various figures is turned over, the elements described as being "below" or "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the example terms "below" and "below" can cover both the orientation above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly.

[0046] It will be further understood that when used in this specification, the terms "comprises," "comprising," "having," and "containing" and variations thereof specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0047] As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0048] Unless otherwise apparent from the present disclosure, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases when preceding / following a list of elements should be understood to include disjuncts if written as a conjunction list, and vice versa. For example, the expressions “at least one of a, b, and c,” “at least one selected from the group consisting of a, b, and c,” “at least one selected from a, b, and c,” “at least one of a, b, and c,” “at least one of a to c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1A is a perspective view of a display device DD according to one or more embodiments of the present disclosure, and Figure 1B is an exploded perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0052] In one or more embodiments, the display device DD may be a large electronic device such as a television, a monitor, or an outdoor billboard. In one or more embodiments, the display device DD may be a medium or small device such as a personal computer, a laptop computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet computer, or a camera. However, these are presented as examples, and the display device DD may also be used as other display devices without departing from the present disclosure. Figure 1A and Figure 1B , the display device DD is illustrated as a smart phone as an example.

[0053] refer to Figure 1A and Figure 1B , the display device DD can display an image IM in a third direction DR3 on a display surface FS parallel to each of the first direction DR1 and the second direction DR2 (for example, display an image in a plan view of the display device DD). The image IM may include not only a dynamic image but also a static image. Figure 1A , as an example, a clock display and application icons are illustrated as an image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0054] In one or more embodiments, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined based on the direction of displaying the image IM. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal (e.g., vertical) direction of each of the front surface and the rear surface may be parallel to the third direction DR3. In one or more embodiments, the directions indicated by the first direction DR1 to the third direction DR3 may be relative, and therefore, may be changed to other directions. In this specification, the words "when viewed on a plane" or "in a plan view" may refer to the situation when viewed in the third direction DR3.

[0055] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to constitute an appearance of the display device DD.

[0056] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0057] The frame area BZA may be an area having a transmittance relatively lower than that of the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and may be around the transmission area TA (e.g., may surround the transmission area TA). However, this is an example, and the frame area BZA of the window WP may not be provided. The window WP may include at least one functional layer (selected from among the anti-fingerprint layer, the hard coating layer, and the anti-reflection layer) of the anti-fingerprint layer, the hard coating layer, and the anti-reflection layer, but the present disclosure is not limited thereto.

[0058] The display module DM may be arranged under the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated in the display module DM may be displayed on a display surface IS of the display module DM and viewed from the outside by a user through the transmission area TA.

[0059] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may be around the display area DA (e.g., surrounding the display area DA). The non-display area NDA may be an area covered by a bezel area BZA and may not be visible from the outside.

[0060] The housing HAU may be coupled to the window WP and may provide a set or predetermined inner space. The display module DM may be accommodated in the inner space.

[0061] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include glass, plastic, or metal, or include a plurality of frames and / or plates formed of a combination thereof. The housing HAU may stably protect the components of the display device DD accommodated in the internal space from external impacts.

[0062] Figure 2 is a cross-sectional view of a display module DM according to one or more embodiments of the present disclosure.

[0063] refer to Figure 2 , the display module DM may include a display panel DP and an input sensor INS. In one or more embodiments, the display device DD (eg, see Figure 1A ) may further include a protection member disposed on the lower surface of the display panel DP, and / or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0064] The display panel DP may be a light-emitting display panel. However, this is presented as an example, and the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0065] The display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be directly arranged on the thin film encapsulation layer TFE. In this specification, the phrase "part A is directly arranged on part B" means that no adhesive layer is arranged between part A and part B (for example, no other layer is arranged between part A and part B).

[0066] The base layer BL may include at least one plastic film, a flexible substrate, a plastic substrate, a glass substrate, a metal substrate, and / or an organic / inorganic composite material substrate, etc. Figure 1B The display area DA and the non-display area NDA described in illustrative examples may be similarly defined in the base layer BL (eg, the base layer BL may be continuous throughout both the display area DA and the non-display area NDA).

[0067] The circuit element layer DP-CL may include at least one insulating layer or a circuit element. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit element includes a signal line and / or a pixel driving circuit, etc.

[0068] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0069] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be arranged to improve optical efficiency, and other thin films may be arranged to protect the organic light emitting diode.

[0070] The input sensor INS can obtain coordinate information about the external input. The input sensor INS can have a multi-layer structure. The input sensor INS can have a single-layer or multi-layer structure. In addition, the input sensor INS can include a single-layer or multi-layer conductive layer. The input sensor INS can detect the external input in a capacitive manner. However, this is presented as an example, and the present disclosure is not limited thereto. For example, in one or more embodiments, the input sensor INS can detect the external input in an electromagnetic induction manner or a pressure-sensitive manner. In one or more embodiments of the present disclosure, the input sensor INS may not be provided.

[0071] Figure 3 is a plan view of a display panel DP according to one or more embodiments of the present disclosure.

[0072] refer to Figure 3 , a display area DA and a non-display area NDA around the display area DA may be defined in the display panel DP. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished according to whether the pixel PX exists. The pixel PX is arranged in the display area DA. The drive circuit GDC and the pad portion PLD may be arranged in the non-display area NDA.

[0073] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and aligned in the second direction DR2, and a plurality of pixel columns extending in the second direction DR2 and aligned in the first direction DR1.

[0074] The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. The gate line GL may be connected to corresponding pixels PX among the pixels PX, respectively, and the data line DL may be connected to corresponding pixels PX among the pixels PX, respectively. The power line PL may be electrically connected to the pixel PX. The control signal line CSL may be connected to the drive circuit GDC and provide a control signal to the drive circuit GDC.

[0075] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate line GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0076] The pad portion PLD may be a portion to which the flexible circuit board is connected. The pad portion PLD may include a pixel pad D-PD, which may be a pad for connecting the flexible circuit board to the display panel DP. The pixel pads D-PD may be respectively connected to corresponding signal lines SGL among the signal lines SGL. The pixel pads D-PD may be connected to corresponding pixels PX via the signal lines SGL. In one or more embodiments, one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0077] In one or more embodiments, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (see, for example, Figure 2 However, the present disclosure is not limited thereto, and the input pad may be arranged on the input sensor INS (for example, see Figure 2 ) and connected to a circuit board separate from the pixel pad D-PD. In one or more embodiments, the input sensor INS may not be provided (for example, see Figure 2 ), and may further not include an input pad. Figure 4 is a display panel DP according to one or more embodiments of the present disclosure (for example, see Figure 2 ) of the display area DA (see, for example, Figure 2 ) is an enlarged plan view of a portion of the ). Figure 4 is a diagram showing the display module DM (see, for example, Figure 1B ) of the display surface IS (see, for example, Figure 1B ) is a plan view of the display module DM viewed from above, and illustrates the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B.

[0078] refer to Figure 4 , the display area DA may include the first to third light emitting areas PXA-R, PXA-G, and PXA-B and a peripheral area NPXA around the first to third light emitting areas PXA-R, PXA-G, and PXA-B (e.g., surrounding the first to third light emitting areas PXA-R, PXA-G, and PXA-B). The first to third light emitting areas PXA-R, PXA-G, and PXA-B may respectively correspond to areas where light provided from the light emitting element is emitted. The first to third light emitting areas PXA-R, PXA-G, and PXA-B may be arranged according to the direction toward the display module DM (e.g., see Figure 2 ) is distinguished by the color of the externally emitted light.

[0079] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may respectively provide first to third color lights having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color lights are not necessarily limited to the above examples.

[0080] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may be respectively defined as regions in each of which the upper surface of the anode is exposed by a light emitting opening to be described in more detail later. The peripheral region NPXA may define a boundary between the first to third light emitting regions PXA-R, PXA-G, and PXA-B, and prevent or reduce color mixing between the first to third light emitting regions PXA-R, PXA-G, and PXA-B.

[0081] Each of the first to third light emitting areas PXA-R, PXA-G, and PXA-B may be provided in plurality and may be repeatedly arranged in a set or predetermined arrangement within the display area DA. For example, the first light emitting area PXA-R and the third light emitting area PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light emitting area PXA-G may be arranged along the first direction DR1 to form a "second group". The "first group" and the "second group" may each be provided in plurality, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0082] One second light emitting region PXA-G may be arranged to be spaced and / or separated (eg, spaced apart or separated) from one first light emitting region PXA-R or one third light emitting region PXA-B in a fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0083] In one or more embodiments, Figure 4 The arrangement of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B is shown, and the light-emitting regions may be arranged in one or more suitable forms without limitation thereto. In one or more embodiments, as Figure 4 As shown in FIG. 1 , the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be Form layout ( is an officially registered trademark of Samsung Display Co., Ltd.). In one or more embodiments, the first to third light emitting areas PXA-R, PXA-G, and PXA-B may be arranged in a stripe form or a diamond form. Form (DIAMOND is an officially registered trademark of Samsung Display Co., Ltd.).

[0084] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have one or more suitable shapes on a plane (e.g., in a plan view). For example, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may each have a polygonal, circular, and / or elliptical shape, etc. Figure 4 It is illustrated that on a plane (eg, in a plan view), the first light emitting region PXA-R and the third light emitting region PXA-B may each have a quadrangular shape (or a diamond shape), and the second light emitting region PXA-G may each have an octagonal shape.

[0085] On a plane (eg, in a plan view), the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have substantially the same or similar shapes, or may have at least partially different shapes. Figure 4 It is illustrated that on a plane (e.g., in a plan view), the first light-emitting region PXA-R and the third light-emitting region PXA-B may have substantially the same shape, and the second light-emitting region PXA-G may have a shape different from the corresponding shapes of the first light-emitting region PXA-R and the third light-emitting region PXA-B.

[0086] At least some of the light-emitting areas selected from the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have different areas on a plane (e.g., in a plan view). In one or more embodiments, the area of ​​each of the first light-emitting areas PXA-R that emits red light may be greater than the area of ​​each of the second light-emitting areas PXA-G that emits green light, and may be smaller than the area of ​​each of the third light-emitting areas PXA-B that emits blue light. However, depending on the color of the emitted light, the area size relationship between the first to third light-emitting areas PXA-R, PXA-G, and PXA-B (selected from the first to third light-emitting areas PXA-R, PXA-G, and PXA-B) is not limited thereto, and may be determined according to the display module DM (e.g., see Figure 2 ). In addition, the present disclosure is not limited thereto, and the first to third light emitting regions PXA-R, PXA-G, and PXA-B may each have the same area on a plane (eg, in a plan view).

[0087] In one or more embodiments, the display module DM according to one or more embodiments of the present disclosure (for example, see Figure 2The shapes, areas, and arrangements of the first to third light emitting regions PXA-R, PXA-G, and PXA-B of the display module DM can be determined according to the color of the emitted light or the display module DM (see, for example, Figure 2 ) size or configuration, and is not limited to Figure 4 One or more embodiments illustrated in .

[0088] Figure 5 According to one or more embodiments of the present disclosure, Figure 3 The cross-sectional view of the display panel DP taken along the line II' will be referred to as Figure 2 describe Figure 5 , and descriptions of the same figure numerals or symbols may not be provided.

[0089] Figure 5 is a diagrammatic display area DA (see, for example, Figure 4 ) is an enlarged view of a light emitting area PXA within the Figure 5 The light emitting area PXA can be Figure 4 The first to third light emitting regions PXA-R, PXA-G and PXA-B correspond to any one of them. Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0090] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns and / or signal lines, etc. The insulating layers, semiconductor layers and conductive layers are formed by coating and / or deposition, etc. Thereafter, the insulating layers, semiconductor layers and conductive layers may be selectively patterned by performing photolithography and / or etching. In this way, semiconductor patterns, conductive patterns and / or signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED are formed.

[0091] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40 and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0092] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0093] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the semiconductor pattern is not limited thereto and may include amorphous silicon or metal oxide. Figure 5 , only a portion of the semiconductor pattern is illustrated as an example, and the semiconductor pattern is further arranged in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (eg, see Figure 4 ) (e.g., in each of the plurality of light emitting regions PXA-R, PXA-G, and PXA-B). According to a specific rule, the semiconductor pattern may be arranged across the plurality of light emitting regions PXA-R, PXA-G, and PXA-B. The electrical characteristics of the semiconductor pattern may vary depending on whether it is doped. The semiconductor pattern may include a first region having a higher doping concentration and a second region having a lower doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0094] The first region has a higher conductivity than that of the second region and is basically used as an electrode or a signal line. The second region may basically correspond to an active region (or channel) of a transistor. For example, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and another portion may be a conductive region.

[0095] The source S, the active portion A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 5 A portion of a signal transmission region SCL formed of a semiconductor pattern is illustrated. In one or more embodiments, the signal transmission region SCL may be connected to the drain D of the transistor TR1 on a plane (eg, in a plan view).

[0096] The first to fifth insulating layers 10, 20, 30, 40, and 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, and 50 may be inorganic layers and / or organic layers.

[0097] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active portion A, the drain D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 and cover the electrode EE.

[0098] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL via a contact hole CNT-1 passing through the first to third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 and cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0099] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0100] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, and a partition wall PW.

[0101] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode).

[0102] The anode AE ​​may be arranged on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive and semi-reflective electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 via a contact hole CNT-3 defined through the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL via the first connection electrode CNE1 and the second connection electrode CNE2, and may be electrically connected to the corresponding circuit element. The anode AE ​​may have a single-layer or multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, the anode AE ​​may include an ITO-containing layer (hereinafter, a lower ITO layer), an Ag-containing layer (hereinafter, an Ag layer) disposed on the lower ITO layer, and an ITO-containing layer (hereinafter, an upper ITO layer) disposed on the Ag layer.

[0103] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel definition film PDL. In the sacrificial pattern SP, a sacrificial opening OP-S exposing a portion of the upper surface of the anode AE ​​may be defined (or the sacrificial pattern SP may have the sacrificial opening OP-S). The sacrificial opening OP-S may overlap with the light emitting opening OP-E which will be described in more detail later.

[0104] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. In the pixel defining film PDL, a light emitting opening OP-E may be defined (or the pixel defining film PDL may have the light emitting opening OP-E). The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0105] In one or more embodiments, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to one or more embodiments, since the upper surface of the anode AE ​​may be spaced and / or separated (e.g., spaced apart or separated) from the pixel defining film PDL in a cross-sectional view and the sacrificial pattern SP is between the upper surface of the anode AE ​​and the pixel defining film PDL, the anode AE ​​may be protected from damage during a process of forming the light emitting opening OP-E.

[0106] On a plane (e.g., in a plan view), the area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. For example, the inner side surface of the pixel defining film PDL that defines the light-emitting opening OP-E may extend closer to the center of the anode AE ​​than the inner side surface of the sacrificial pattern SP that defines the sacrificial opening OP-S. However, the present disclosure is not limited thereto, and the inner side surface of the sacrificial pattern SP that defines the sacrificial opening OP-S may also be substantially aligned with the inner side surface of the pixel defining film PDL that defines the light-emitting opening OP-E. In such an embodiment, the light-emitting area PXA may be considered to be an area of ​​the anode AE ​​exposed by the corresponding sacrificial opening OP-S.

[0107] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include SiN x (or silicon nitride). The pixel defining film PDL may be disposed between the anode AE ​​and the partition wall PW, and thus, prevent the anode AE ​​and the partition wall PW from being electrically connected to each other.

[0108] The light emitting pattern EP may be arranged on the anode AE. The light emitting pattern EP may further include a light emitting layer including a light emitting material. The light emitting pattern EP may further include a hole injection layer (HIL) and / or a hole transport layer (HTL) arranged between the anode AE ​​and the light emitting layer, or may further include an electron transport layer (ETL) and / or an electron injection layer (EIL) arranged on the light emitting layer. The light emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0109] The light emitting pattern EP may be patterned by a tip portion defined in the partition wall PW. The light emitting pattern EP may be arranged inside the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL exposed by the partition wall opening OP-P.

[0110] The cathode CE may be arranged on the light emitting pattern EP. The cathode CE may be patterned by a tip portion defined in the partition wall PW (wherein the tip portion may be a portion of the partition wall PW extending closer to the center of the anode AE ​​than other portions of the partition wall PW). At least a portion of the cathode CE may be arranged in the partition wall opening OP-P. The cathode CE may be aligned with the first inner side surface S-L1 of the first partition wall layer L1 (e.g., see Fig.7D ) contact. The cathode CE may have electrical conductivity (e.g., be an electronic conductor). The cathode CE may be formed of one or more suitable materials such as metal, transparent conductive oxide (TCO), or conductive polymer material, as long as these materials have electrical conductivity. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or one or more compounds thereof.

[0111] In one or more embodiments of the present disclosure, the display element layer DP-OLED may further include a capping pattern. The capping pattern may be arranged inside the partition wall opening OP-P and arranged on the cathode CE. The capping pattern may be patterned by a tip portion formed in the partition wall PW.

[0112] The partition wall PW may be disposed on the pixel definition film PDL. In the partition wall PW, a partition wall opening OP-P may be defined (or the partition wall PW may have a partition wall opening OP-P). The partition wall opening OP-P may correspond to the light emission opening OP-E and may expose at least a portion of the anode AE.

[0113] The partition wall PW may have an undercut shape in a cross-sectional view. The partition wall PW may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be further recessed from the center of the anode AE ​​than the other layers. Therefore, the partition wall PW may include a tip portion (e.g., a portion of the partition wall PW extending closer to the center of the anode AE ​​relative to other recessed portions of the partition wall PW).

[0114] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition film PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 5 As illustrated in FIG. 1 , the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2 , but the present disclosure is not limited thereto.

[0115] The first partition wall layer L1 may be further recessed than the second partition wall layer L2 relative to the light emitting region PXA. The first partition wall layer L1 may be formed to be undercut relative to the second partition wall layer L2. A portion of the second partition wall layer L2 protruding from the first partition wall layer L1 toward the light emitting region PXA may be defined as a tip portion of the partition wall PW.

[0116] The partition wall opening OP-P defined in the partition wall PW may include a first area A1 and a second area A2. The first partition wall layer L1 may include a first inner surface of the first area A1 defining the partition wall opening OP-P, and the second partition wall layer L2 may include a second inner surface defining the second area A2. In a cross-sectional view, the second inner surface of the second partition wall layer L2 may extend closer to the center of the anode AE ​​than the first inner surface of the first partition wall layer L1. The first inner surface may be further recessed than the second inner surface in a direction extending away from the center of the anode AE. Therefore, the second partition wall layer L2 protruding toward the light emitting area PXA may include a tip portion.

[0117] The width of the first area A1 may be different from the width of the second area A2. The width of the first area A1 may be greater than the width of the second area A2. In one or more embodiments, the second area A2 of the partition wall opening OP-P may be an area defining a tip portion.

[0118] The first partition wall layer L1 and the second partition wall layer L2 may each include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), and / or a combination thereof (e.g., any suitable combination). For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), and / or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), and / or aluminum zinc oxide.

[0119] Figure 5 It is illustrated that the first inner side surface and the second inner side surface are each orthogonal (eg, perpendicular) to the upper surface of the pixel defining film PDL, but the present disclosure is not limited thereto. For example, the partition wall PW may have a tapered shape or an inverse tapered shape.

[0120] The partition wall PW may receive the second driving voltage. Therefore, the cathode CE may be electrically connected to the partition wall PW to receive the second driving voltage.

[0121] The dummy area DMA may be formed on the partition wall PW. For example, in the cross-sectional view, the dummy area DMA may be formed between the partition wall PW and the inorganic encapsulation pattern LIL (or the lower inorganic encapsulation pattern LIL). The dummy area DMA may be defined as a dummy pattern DMP (for example, see FIG. 1 ) during a manufacturing process of the display panel described later. Figure 7K )areas formed and removed.

[0122] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL. The lower inorganic encapsulation pattern LIL may be referred to as an inorganic encapsulation pattern LIL.

[0123] The lower inorganic encapsulation pattern LIL may correspond to the light emitting opening OP-E. The lower inorganic encapsulation pattern LIL may be arranged on the cathode CE. For example, a portion of the lower inorganic encapsulation pattern LIL may be formed inside the partition wall opening OP-P, and another portion of the lower inorganic encapsulation pattern LIL may be formed on the partition wall PW. The lower inorganic encapsulation pattern LIL may include a first lower inorganic encapsulation pattern LIL1 (or a first inorganic encapsulation pattern) and a second lower inorganic encapsulation pattern LIL2 (or a second inorganic encapsulation pattern). The first lower inorganic encapsulation pattern LIL1 and the second lower inorganic encapsulation pattern LIL2 may be sequentially arranged on the cathode CE. The first lower inorganic encapsulation pattern LIL1 may be referred to as a first inorganic encapsulation pattern LIL1, and the second lower inorganic encapsulation pattern LIL2 may be referred to as a second inorganic encapsulation pattern LIL2.

[0124] The organic encapsulation film OL may cover the lower inorganic encapsulation pattern LIL and provide a flat upper surface. The dummy area DMA may be filled with a portion of the organic encapsulation film OL. The upper inorganic encapsulation film UIL may be disposed on the organic encapsulation film OL.

[0125] The lower inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL may protect the display element layer DP-OLED from moisture and / or oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0126] Figure 6 is a diagram illustrating one or more embodiments of the present disclosure Figure 5 Magnified view of area AA'.

[0127] refer to Figure 5 and Figure 6 The first lower inorganic encapsulation pattern LIL1 may include a plurality of inorganic patterns S1, S2, S3, S4, and S5 that are repeatedly stacked. The plurality of inorganic patterns S1, S2, S3, S4, and S5 may each include silicon nitride (SiNx ) and / or silicon oxynitride (SiON (e.g., SiO x N y )). The plurality of inorganic patterns S1, S2, S3, S4, and S5 may each include a first sub-pattern SB1 and a second sub-pattern SB2. The first sub-pattern SB1 may include first sub-patterns SB11, SB12, SB13, SB14, and SB15, and the second sub-pattern SB2 may include second sub-patterns SB21, SB22, SB23, SB24, and SB25. The first sub-patterns SB11, SB12, SB13, SB14, and SB15 and the second sub-patterns SB21, SB22, SB23, SB24, and SB25 may be sequentially and repeatedly stacked.

[0128] For example, the plurality of inorganic patterns S1, S2, S3, S4, and S5 may include a first inorganic pattern S1, a second inorganic pattern S2, a third inorganic pattern S3, a fourth inorganic pattern S4, and a fifth inorganic pattern S5. The first inorganic pattern S1 may include a 1-1st sub-pattern SB11 as a first sub-pattern SB1 and a 2-1st sub-pattern SB21 as a second sub-pattern SB2. The second inorganic pattern S2 may include a 1-2nd sub-pattern SB12 as a first sub-pattern SB1 and a 2-2nd sub-pattern SB22 as a second sub-pattern SB2. The third inorganic pattern S3 may include a 1-3rd sub-pattern SB13 as a first sub-pattern SB1 and a 2-3rd sub-pattern SB23 as a second sub-pattern SB2. The fourth inorganic pattern S4 may include a 1-4th sub-pattern SB14 as a first sub-pattern SB1 and a 2-4th sub-pattern SB24 as a second sub-pattern SB2. The fifth inorganic pattern S5 may include 1-5th sub-pattern SB15 as the first sub-pattern SB1 and 2-5th sub-pattern SB25 as the second sub-pattern SB2.

[0129] The 1-1st sub-pattern SB11, the 2-1st sub-pattern SB21, the 1-2nd sub-pattern SB12, the 2-2nd sub-pattern SB22, the 1-3rd sub-pattern SB13, the 2-3rd sub-pattern SB23, the 1-4th sub-pattern SB14, the 2-4th sub-pattern SB24, the 1-5th sub-pattern SB15, and the 2-5th sub-pattern SB25 may be sequentially stacked on the cathode CE. In this case, one of the first sub-patterns SB11, SB12, SB13, SB14, and SB15 and one of the second sub-patterns SB21, SB22, SB23, SB24, and SB25 may be sequentially and alternately stacked.

[0130] The first sub-pattern SB1 and the second sub-pattern SB2 may each include silicon nitride (SiN x) and / or silicon oxynitride (SiON). The first sub-pattern SB1 may be rich in silicon (Si) compared to the second sub-pattern SB2, and the second sub-pattern SB2 may be rich in nitrogen (N) compared to the first sub-pattern SB1. For example, the first sub-pattern SB1 may be silicon nitride (SiN) rich in silicon (Si). x ) and / or a silicon oxynitride (SiON) layer, and the second sub-pattern SB2 may be a silicon nitride (SiN) layer rich in nitrogen (N). x ) or a silicon oxynitride (SiON) layer. The thickness TT1 of the first sub-pattern SB1 may be less than the thickness TT2 of the second sub-pattern SB2. However, this is illustrated as an example, and the thickness TT1 of the first sub-pattern SB1 and the thickness TT2 of the second sub-pattern SB2 are not limited thereto. In addition, as a non-limiting example, in Si 3 N 4 Silicon-rich refers to a composition having a greater than stoichiometric amount of Si 3 N 4 In contrast, as a non-limiting example, in the case of Si 3 N 4 In the present invention, nitrogen-rich refers to the case where the Si / N ratio is lower than the stoichiometric compound. 3 N 4 With excess silicon, while nitrogen-rich Si 3 N 4 With excess nitrogen.

[0131] Figure 6 The plurality of inorganic patterns S1, S2, S3, S4, and S5 are illustrated to include five inorganic patterns S1, S2, S3, S4, and S5, but the present disclosure is not limited thereto. For example, the plurality of inorganic patterns may include two to four inorganic patterns, or six or more inorganic patterns.

[0132] The second lower inorganic encapsulation pattern LIL2 may be arranged on the first lower inorganic encapsulation pattern LIL1. The thickness of the second lower inorganic encapsulation pattern LIL2 may be greater than the thickness of the first lower inorganic encapsulation pattern LIL1. However, the present disclosure is not limited thereto, and the thickness of the second lower inorganic encapsulation pattern LIL2 may be the same as the thickness of the first lower inorganic encapsulation pattern LIL1, or less than the thickness of the first lower inorganic encapsulation pattern LIL1.

[0133] According to one or more embodiments of the present disclosure, the lower inorganic encapsulation pattern LIL may include a plurality of inorganic patterns S1, S2, S3, S4, and S5, and the plurality of inorganic patterns S1, S2, S3, S4, and S5 may each include silicon nitride (SiN x ) and / or silicon nitride oxide (SiON). x) and / or silicon oxynitride (SiON) can cover the partition wall PW, thereby reducing or eliminating the phenomenon in which the lower inorganic encapsulation pattern LIL is oxidized due to foreign matter introduced from the side surface of the first partition wall layer L1, the lower surface of the second partition wall layer L2, and / or the side surface of the second partition wall layer L2. Therefore, pixel defects (dark spots and / or pixel shrinkage, etc.) of the display panel DP caused by foreign matter can be reduced or eliminated.

[0134] FIG. 7A to FIG. 7M 1 is a cross-sectional view or schematic diagram illustrating some steps (eg, actions or tasks) of a method for manufacturing a display panel according to one or more embodiments of the present disclosure. FIG. 7A to FIG. 7M In the description of FIG. 1 to FIG. 2 , the same / similar reference numerals or symbols are used to describe the same Figure 6 The components described are the same / similar components, and repeated description thereof may not be provided.

[0135] According to one or more embodiments of the present disclosure, the method for manufacturing a display panel may include the following steps: providing a preliminary display panel, the preliminary display panel including a substrate layer, a pixel defining film arranged on the substrate layer, a first preliminary partition wall layer arranged on the pixel defining film, and a second preliminary partition wall layer arranged on the first preliminary partition wall layer; forming a first partition wall layer and a second partition wall layer having a partition wall opening by etching the first preliminary partition wall layer and the second preliminary partition wall layer; forming a light emitting pattern and a cathode inside the partition wall opening; and forming an inorganic encapsulation pattern on the cathode. The step (e.g., action or task) of forming the inorganic encapsulation pattern may include: depositing a first inorganic encapsulation layer on the cathode, depositing a second inorganic encapsulation layer on the first inorganic encapsulation layer, and forming the first inorganic encapsulation pattern and the second inorganic encapsulation pattern by etching the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0136] In the following, reference FIG. 7A to FIG. 7M , a method of forming a light emitting element ED, a lower inorganic encapsulation pattern LIL covering the light emitting element ED, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL will be described. According to one or more embodiments of the present disclosure, by FIG. 7A to FIG. 7M The display panel formed by the steps can be Figure 5 Corresponding to the display panel DP.

[0137] refer to Fig. 7A , the method for manufacturing a display panel according to one or more embodiments may include providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in one or more embodiments may include a base layer BL, a circuit element layer DP-CL, an anode AE, a sacrificial layer SP-I, a pixel defining film PDL, a first preliminary partition wall layer L1-I, and a second preliminary partition wall layer L2-I.

[0138] The circuit element layer DP-CL can be formed by a suitable circuit element manufacturing process, which includes forming an insulating layer, a semiconductor layer and a conductive layer by coating and / or deposition, selectively patterning the insulating layer, the semiconductor layer and the conductive layer by performing a photolithography and / or etching process, and then forming a semiconductor pattern, a conductive pattern and a signal line.

[0139] The anode AE ​​and the sacrificial layer SP-I may be formed by the same patterning process. The pixel defining film PDL may be disposed on the base layer BL. The pixel defining film PDL may cover both the anode AE ​​and the sacrificial layer SP-I.

[0140] The first preliminary partition wall layer L1-I may be arranged on the pixel definition film PDL. The first preliminary partition wall layer L1-I may be formed by a process of depositing a conductive material. The second preliminary partition wall layer L2-I may be arranged on the first preliminary partition wall layer L1-I. The second preliminary partition wall layer L2-I may also be formed by a process of depositing a conductive material. In one or more embodiments, the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may each include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO) and / or a combination thereof (e.g., any suitable combination). For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) and / or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO) and / or aluminum zinc oxide. However, the materials of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I are not limited thereto. The first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may form a preliminary partition wall PW-I.

[0141] Afterwards, refer to Figure 7B , the method for manufacturing a display panel according to one or more embodiments may include forming a first photoresist layer PR1 on the preliminary partition wall PW-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary partition wall PW-I and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first optical opening OP-PR overlapping the anode AE ​​may be formed in the first photoresist layer PR1.

[0142] Afterwards, refer to Figure 7C and Fig.7D, the method for manufacturing a display panel according to one or more embodiments may include forming a first partition wall layer L1 and a second partition wall layer L2 having a partition wall opening OP-P by etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I so that a first partition wall PW-I (for example, see Figure 7B ) forms a partition wall PW.

[0143] First, if Figure 7C As illustrated in the figure, the step (e.g., action or task) of initially etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include forming a preliminary partition wall opening OP-PI in the preliminary partition wall PW-I by dry etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I using the first photoresist layer PR1 as a mask.

[0144] In one or more embodiments, the preliminary dry etching process may be performed under etching conditions in which the etching selectivity between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I (e.g., the etching rates of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I) is substantially the same. Therefore, the inner side surface of the first preliminary partition wall layer L1-I and the inner side surface of the second preliminary partition wall layer L2-I, which define the preliminary partition wall opening OP-PI, may be substantially aligned.

[0145] Afterwards, if Fig.7D As shown in FIG. 1 , the step (e.g., action or task) of second-etching the first preliminary partition wall layer L1-I may include wet-etching the first preliminary partition wall layer L1-I using the first photoresist layer PR1 as a mask to form a first partition wall opening OP-PI (e.g., see Figure 7C ) forms a partition wall opening OP-P.

[0146] The partition wall opening OP-P may include a first area A1 and a second area A2 sequentially formed in the thickness direction (i.e., the third direction DR3). The first partition wall layer L1 may include a first inner side surface S-L1 defining the first area A1 of the partition wall opening OP-P, and the second partition wall layer L2 may include a second inner side surface S-L2 defining the second area A2.

[0147] In one or more embodiments, the second wet etching process may be performed under etching conditions in which the etching selectivity (e.g., the difference in etching rate) between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is large. Therefore, the inner surface of the partition wall PW defining the partition wall opening OP-P may have an undercut shape in a cross-sectional view. For example, in an etching solution, the etching rate of the first partition wall layer L1 is greater than the etching rate of the second partition wall layer L2, and therefore, the first partition wall layer L1 may be mainly etched. Therefore, the first inner surface S-L1 of the first partition wall layer L1 may be formed to be further recessed than the second inner surface S-L2 of the second partition wall layer L2. A portion of the second partition wall layer L2 that protrudes further than the first partition wall layer L1 may form a tip portion in the partition wall PW.

[0148] In one or more embodiments, forming Figure 7C and Fig.7D The step (e.g., action or task) of forming the partition wall opening OP-P may include concurrently (e.g., simultaneously) forming the partition wall opening OP-P with the first to third light emitting regions PXA-R, PXA-G and PXA-B (e.g., see Figure 4 ). However, the present disclosure is not limited thereto, and in one or more embodiments of the present disclosure, the step (e.g., action or task) of forming the partition wall opening OP-P may include forming only the partition wall opening OP-P corresponding to the first light emitting region PXA-R. For example, after forming the partition wall opening OP-P corresponding to the first light emitting region PXA-R and then forming the first light emitting element by a subsequent process, the partition wall opening OP-P corresponding to the second light emitting region PXA-G may be formed. In addition, the second light emitting element is formed by a subsequent process, and then the partition wall opening OP-P corresponding to the third light emitting region PXA-B may be formed.

[0149] Afterwards, refer to Fig. 7E The method for manufacturing a display panel according to one or more embodiments may include etching a pixel definition film PDL and etching a sacrificial layer SP-I (eg, see Fig.7D ). The etching process of the pixel defining film PDL may be performed by dry etching, and the pixel defining film PDL may be etched using the first photoresist layer PR1 and the partition wall PW (eg, the second partition wall layer L2) as a mask. A light emitting opening OP-E corresponding to the partition wall opening OP-P may be formed in the pixel defining film PDL.

[0150] The etching process of the sacrificial layer SP-I may be performed by wet etching, and the sacrificial layer SP-I may be etched using the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) as a mask. A sacrificial opening OP-S overlapping the light emitting opening OP-E may be formed in the sacrificial pattern SP formed by etching the sacrificial layer SP-I. Due to the sacrificial opening OP-S and the light emitting opening OP-E, at least a portion of the anode AE ​​may be exposed from the sacrificial pattern SP and the pixel defining film PDL.

[0151] The etching process of the sacrificial pattern SP may be performed under a condition in which the etching selectivity (e.g., the difference in etching rate) between the sacrificial pattern SP and the anode AE ​​is large, and thus, the possibility of the anode AE ​​being etched together with the sacrificial pattern SP may be prevented or reduced. For example, the sacrificial pattern SP having an etching rate greater than that of the anode AE ​​is arranged between the pixel defining film PDL and the anode AE, and thus, during the etching process, the possibility of the anode AE ​​being etched together with the sacrificial pattern SP and the anode AE ​​being damaged may be prevented or reduced.

[0152] Afterwards, refer to Figure 7F The method for manufacturing a display panel according to one or more embodiments may include removing the first photoresist layer PR1 (eg, see Fig. 7E ), and then a light emitting pattern EP and a cathode CE are formed inside the partition wall opening OP-P.

[0153] The steps (e.g., actions or tasks) of forming the light emitting pattern EP and the cathode CE may each be performed by a deposition process. In one or more embodiments, the step (e.g., action or task) of forming the light emitting pattern EP may include a thermal evaporation process, and the step (e.g., action or task) of forming the cathode CE may include a sputtering process.

[0154] The light emitting pattern EP may be formed on the anode AE. In the step (eg, action or task) of forming the light emitting pattern EP, the light emitting pattern EP may be separated from the tip portion formed in the partition wall PW and may be arranged inside the light emitting opening OP-E and the partition wall opening OP-P.

[0155] In the step (e.g., action or task) of forming the light emitting pattern EP, a first dummy layer D1-I separated and / or separated (e.g., spaced apart or separated) from the light emitting pattern EP may be formed together on the partition wall PW. The first dummy layer D1-I may include an organic material. For example, the first dummy layer D1-I may include the same material as that of the light emitting pattern EP. The first dummy layer D1-I may be formed concurrently (e.g., simultaneously) with the light emitting pattern EP through a single process, and may be formed to be separated from the light emitting pattern EP due to the undercut shape of the partition wall PW.

[0156] The cathode CE may be formed on the light emitting pattern EP. In the step (e.g., action or task) of forming the cathode CE, the cathode CE may be separated by a tip portion formed in the partition wall PW and may be arranged inside the partition wall opening OP-P. Since the cathode CE may be provided to have an incident angle greater than that of the light emitting pattern EP, the cathode CE may be formed to contact the first inner side surface S-L1 of the first partition wall layer L1. The anode AE, the light emitting pattern EP, and the cathode CE may constitute a light emitting element ED.

[0157] In the step (e.g., action or task) of forming the cathode CE, a second dummy layer D2-I separated and / or separated (e.g., spaced or separated) from the cathode CE may be formed together on the partition wall PW. The second dummy layer D2-I may include a conductive material. For example, the second dummy layer D2-I may include the same material as that of the cathode CE. The second dummy layer D2-I may be formed concurrently (e.g., simultaneously) with the cathode CE through a single process and is formed to be separated from the cathode CE due to the undercut shape of the partition wall PW.

[0158] The first dummy layer D1-I and the second dummy layer D2-I may be sequentially stacked on the upper surface of the partition wall PW along the third direction DR3. The first dummy layer D1-I and the second dummy layer D2-I form a dummy layer DMP-I, and a dummy opening OP-D may be formed in the dummy layer DMP-I. The dummy opening OP-D may include a first area AA1 and a second area AA2 sequentially formed in a thickness direction (e.g., the third direction DR3). The first area AA1 of the dummy opening OP-D may be defined by the inner side surface of the first dummy layer D1-I, and the second area AA2 may be defined by the inner side surface of the second dummy layer D2-I.

[0159] In one or more embodiments of the present disclosure, a method for manufacturing a display panel may include forming a capping pattern. The step (e.g., action or task) of forming the capping pattern may include a thermal evaporation process. The capping pattern may be formed on the cathode CE. In the step (e.g., action or task) of forming the capping pattern, the capping pattern may be separated by a tip portion formed in the partition wall PW and may be arranged inside the partition wall opening OP-P.

[0160] In the step (e.g., action or task) of forming the capping pattern, a third dummy layer separated and / or separated (e.g., spaced apart or separated) from the capping pattern can be formed together on the partition wall PW. The third dummy layer may include a conductive material. For example, the third dummy layer may include the same material as the material of the capping pattern. The third dummy layer may be formed concurrently (e.g., simultaneously) with the capping pattern by a single process, and is formed to be separated from the capping pattern due to the undercut shape of the partition wall PW. In such an embodiment, the dummy layer DMP-I may include a first dummy layer D1-I, a second dummy layer D2-I, and a third dummy layer.

[0161] Afterwards, refer to Figure 7G to Figure 7K , the method for manufacturing a display panel according to one or more embodiments may include forming a lower inorganic encapsulation pattern LIL on a cathode CE. The step (e.g., action or task) of forming the lower inorganic encapsulation pattern LIL may include: depositing a first lower inorganic encapsulation layer LIL1_1 (or a first inorganic encapsulation layer) on the cathode CE, depositing a second lower inorganic encapsulation layer LIL2_I (or a second inorganic encapsulation layer) on the first lower inorganic encapsulation layer LIL1_1, and forming a first lower inorganic encapsulation pattern LIL1 and a second lower inorganic encapsulation pattern LIL2 by etching the first lower inorganic encapsulation layer LIL1_I and the second lower inorganic encapsulation layer LIL2_I. The first lower inorganic encapsulation layer LIL1_I may be referred to as a first inorganic encapsulation layer LIL1_I, and the second lower inorganic encapsulation layer LIL2_I may be referred to as a second inorganic encapsulation layer LIL2_I.

[0162] In the following, reference will be made to FIG. 7G to FIG. 7I To describe the steps (eg, actions or tasks) of depositing the first lower inorganic encapsulation layer LIL1_I, reference will be made to Figure 7J Describe the steps (eg, actions or tasks) of depositing the second lower inorganic encapsulation layer LIL2_I, and refer to Figure 7K Steps (eg, actions or tasks) of forming the first and second lower inorganic encapsulation patterns LIL1 and LIL2 are described.

[0163] Figure 7G 1 is a schematic diagram illustrating gases (Ar, G_Si, and G_N) injected over time during a process of depositing a first lower inorganic encapsulation layer LIL1_I. The process of depositing the first lower inorganic encapsulation layer LIL1_I may be to inject a reaction gas onto a substrate (e.g., a preliminary display panel DP-I (e.g., see FIG. 1 ) in which a partition wall PW is formed. Fig. 7A )) is a process for forming a thin film on a substrate. Figure 7GThe first reaction stage TS1, the second reaction stage TS2, the third reaction stage TS3 and the fourth reaction stage TS4 are illustrated. The first reaction stage TS1 may be related to a step (eg, action or task) of depositing the 1-1 sub-layer SB11_I, which will be described in more detail later (eg, see Figure 7H ), and the second reaction stage TS2 may correspond to the step (eg, action or task) of depositing the 2-1st sub-layer SB21_I (eg, see Figure 7H The third reaction stage TS3 may correspond to the step (eg, action or task) of depositing the 1-2 sub-layer SB12_I (eg, see Fig.7I ), and the fourth reaction stage TS4 may correspond to the step (eg, action or task) of depositing the 2-2 sub-layer SB22_I (eg, see Fig.7I ) corresponding to.

[0164] The third reaction stage TS3 and the fourth reaction stage TS4 may be substantially the same as the corresponding first reaction stage TS1 and the second reaction stage TS2. The third reaction stage TS3 may be substantially the same as the first reaction stage TS1, and the fourth reaction stage TS4 may be substantially the same as the second reaction stage TS2. For example, the process of depositing the first lower inorganic encapsulation layer LIL1_I may be a process in which the first reaction stage TS1 and the second reaction stage TS2 are repeated and performed alternately.

[0165] First, refer to Figure 7G and Figure 7H , the step (e.g., action or task) of depositing the first lower inorganic encapsulation layer LIL1_I on the cathode CE may include: depositing the 1-1 sublayer SB11_I on the cathode CE, depositing the 2-1 sublayer SB21_I on the 1-1 sublayer SB11_I, and thereby forming a first inorganic layer S1_I including the 1-1 sublayer SB11_I and the 2-1 sublayer SB12_I.

[0166] The step (e.g., action or task) of depositing the 1-1 sub-layer SB11_I on the cathode CE may include: introducing a silicon-containing gas (G_Si) and an argon gas (Ar), and then introducing a nitrogen-containing gas (G_N) and an argon gas (Ar). For example, the silicon-containing gas (G_Si) may be silane (SiH 4 ), and the nitrogen-containing gas (G_N) may be ammonia (NH 3 ).

[0167] For example, the first reaction stage TS1 may include an early stage T1-1 and a late stage T1-2. After the early stage T1-1, the late stage T1-2 may be performed. The early stage T1-1 of the first reaction stage TS1 may include introducing a silicon-containing gas (G_Si) and an argon gas (Ar). Due to the early stage T1-1, amorphous silicon may be formed on the cathode CE. The late stage T1-2 of the first reaction stage TS1 may include introducing a nitrogen-containing gas (G_N) and an argon gas (Ar). Due to the late stage T1-2, nitridation of the amorphous silicon formed in the early stage T1-1 may be performed. As a result, a 1-1 sub-layer SB11_I may be formed on the cathode CE, and the 1-1 sub-layer SB11_I may be a silicon nitride (SiN) rich in silicon (Si). x ) and / or silicon oxynitride (SiON) layers.

[0168] The step (e.g., action or task) of depositing the 2-1 sub-layer SB21_I on the 1-1 sub-layer SB11_I may include: introducing a silicon-containing gas (G_Si), a nitrogen-containing gas (G_N), and an argon gas (Ar), and then introducing a nitrogen-containing gas (G_N) and an argon gas (Ar). For example, the silicon-containing gas (G_Si) may be silane (SiH 4 ), and the nitrogen-containing gas (G_N) may be ammonia (NH 3 ).

[0169] For example, the second reaction stage TS2 may include an early stage T2-1 and a late stage T2-2. After the early stage T2-1, the late stage T2-2 may be performed. The early stage T2-1 of the second reaction stage TS2 may include introducing a silicon-containing gas (G_Si), a nitrogen-containing gas (G_N), and an argon gas (Ar). Due to the early stage T2-1, silicon nitride (SiN x ) and / or silicon oxynitride (SiON) may be formed on the 1-1 sub-layer SB11_I. The later stage T2-2 of the second reaction stage TS2 may include introducing nitrogen-containing gas (G_N) and argon gas (Ar). Due to the later stage T2-2, the silicon nitride (SiN) formed in the earlier stage T2-1 may be performed. x ) and / or nitridation of silicon oxynitride (SiON). As a result, the 2-1st sub-layer SB21_I may be formed on the 1-1st sub-layer SB11_I, and the 2-1st sub-layer SB21_I may be silicon nitride (SiN) rich in nitrogen (N). x ) and / or silicon oxynitride (SiON) layers.

[0170] The 1-1th sub-layer SB11_I and the 2-1th sub-layer SB21_I may form a first inorganic layer S1_I.

[0171] refer to Figure 7Gand Fig.7I , the step (e.g., action or task) of depositing the first lower inorganic encapsulation layer LIL1_I on the cathode CE may further include depositing a 1-2 sublayer SB12_I on the first inorganic layer S1_I, depositing a 2-2 sublayer SB22_I on the 1-2 sublayer SB12_I, and thereby forming a second inorganic layer S2_I including the 1-2 sublayer SB12_I and the 2-2 sublayer SB22_I.

[0172] The step (e.g., action or task) of depositing the 1-2 sub-layer SB12_I on the first inorganic layer S1_I may include: introducing a silicon-containing gas (G_Si) and an argon gas (Ar), and then introducing a nitrogen-containing gas (G_N) and an argon gas (Ar). For example, the silicon-containing gas (G_Si) may be silane (SiH 4 ), and the nitrogen-containing gas (G_N) may be ammonia (NH 3 ).

[0173] For example, the third reaction stage TS3 may include an early stage T3-1 and a late stage T3-2. After the early stage T3-1, the late stage T3-2 may be performed. The early stage T3-1 of the first reaction stage TS3 may include the introduction of a silicon-containing gas (G_Si) and an argon gas (Ar). Due to the early stage T3-1, amorphous silicon may be formed on the 2-1 sub-layer SB21_I. The late stage T3-2 of the third reaction stage TS3 may include the introduction of a nitrogen-containing gas (G_N) and an argon gas (Ar). Due to the late stage T3-2, nitridation of the amorphous silicon formed in the early stage T3-1 may be performed. As a result, the 1-2 sub-layer SB12_I may be formed on the first inorganic layer S1_I, and the 1-2 sub-layer SB12_I may be a silicon nitride (SiNx) and / or silicon nitride oxide (SiON) layer rich in silicon (Si).

[0174] The step (e.g., action or task) of depositing the 2-2 sub-layer SB22_I on the 1-2 sub-layer SB12_I may include: introducing a silicon-containing gas (G_Si), a nitrogen-containing gas (G_N), and an argon gas (Ar), and then introducing a nitrogen-containing gas (G_N) and an argon gas (Ar). For example, the silicon-containing gas (G_Si) may be silane (SiH 4 ), and the nitrogen-containing gas (G_N) may be ammonia (NH 3 ).

[0175] For example, the fourth reaction stage TS4 may include an early stage T4-1 and a late stage T4-2. After the early stage T4-1, the late stage T4-2 may be performed. The early stage T4-1 of the fourth reaction stage TS4 may include introducing a silicon-containing gas (G_Si), a nitrogen-containing gas (G_N), and an argon gas (Ar). Due to the early stage T4-1, silicon nitride (SiN x ) and / or silicon oxynitride (SiON) may be formed on the 1-2 sub-layer SB12_I. The later stage T4-2 of the fourth reaction stage TS4 may include introducing nitrogen-containing gas (G_N) and argon gas (Ar). Due to the later stage T4-2, the silicon nitride (SiN) formed in the earlier stage T4-1 may be performed. x ) and / or nitridation of silicon oxynitride (SiON). As a result, the 2-2 sub-layer SB22_I may be formed on the 1-2 sub-layer SB12_I, and the 2-2 sub-layer SB22_I may be silicon nitride (SiN) rich in nitrogen (N). x ) and / or silicon oxynitride (SiON) layers.

[0176] The 1-2 sub-layer SB12_I and the 2-2 sub-layer SB22_I may form a second inorganic layer S2_I.

[0177] The 1-1 sublayer SB11_I of the first inorganic layer S1_I and the 1-2 sublayer SB12_I of the second inorganic layer S2_I may be referred to as the first sublayer SB11_I and SB12_I, and the 2-1 sublayer SB21_I of the first inorganic layer S1_I and the 2-2 sublayer SB22_I of the second inorganic layer S2_I may be referred to as the second sublayer SB21_I and SB22_I. The first sublayers SB11_I and SB12_I and the second sublayers SB21_I and SB22_I may each include silicon nitride (SiN x ) and / or silicon oxynitride (SiON). The first sub-layers SB11_I and SB12_I may be rich in silicon (Si) compared to the second sub-layers SB21_I and SB22_I, and the second sub-layers SB21_I and SB22_I may be rich in nitrogen (N) compared to the first sub-layers SB11_I and SB12_I.

[0178] FIG. 7G to FIG. 7I It is illustrated that two inorganic layers S1_I and S2_I are deposited, but the present disclosure is not limited thereto. For example, the method for manufacturing a display panel according to one or more embodiments may include depositing three or more inorganic layers. For example, Figure 6 1 and 2. The display panel DP (see, for example, FIG. 1 ) including first to fifth inorganic patterns S1, S2, S3, S4, and S5 formed by depositing and then etching five inorganic layers is illustrated. Figure 5 ).

[0179] Afterwards, refer to Figure 7J , the method for manufacturing a display panel according to one or more embodiments of the present disclosure may include depositing a second lower inorganic encapsulation layer LIL2_I on the first lower inorganic encapsulation layer LIL1_I. Fig.7I The first inorganic layer S1_I and the second inorganic layer S2_I illustrated in FIG. 5 may form a first lower inorganic encapsulation layer LIL_I.

[0180] The second lower inorganic encapsulation layer LIL2_I may be formed by a deposition process. In one or more embodiments, the second lower inorganic encapsulation layer LIL2_I may be formed by a chemical vapor deposition (CVD process). The second lower inorganic encapsulation layer LIL2_I may be formed to cover the first lower inorganic encapsulation layer LIL1_I.

[0181] Afterwards, refer to Figure 7K , the method for manufacturing a display panel according to one or more embodiments may include forming a second photoresist layer PR2 and forming first and second lower inorganic encapsulation patterns LIL1 and LIL2.

[0182] In the step (e.g., action or task) of forming the second photoresist layer PR2, the second photoresist layer PR2 can be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a mask. Through the patterning process, the second photoresist layer PR2 can be formed to have a pattern corresponding to the light emitting opening OP-E.

[0183] In the step (e.g., action or task) of forming the first lower inorganic encapsulation pattern LIL1 and the second lower inorganic encapsulation pattern LIL2, the first lower inorganic encapsulation pattern LIL1 and the second lower inorganic encapsulation pattern LIL2 (corresponding to the first lower inorganic encapsulation layer LIL1_I and the second lower inorganic encapsulation layer LIL2_I, respectively) may be patterned by dry etching so as to remove a portion other than a portion overlapping with the anode AE. The first lower inorganic encapsulation pattern LIL1 and the second lower inorganic encapsulation pattern LIL2 overlapping with the corresponding light emitting opening OP-E may be formed by patterning the first lower inorganic encapsulation layer LIL1_I and the second lower inorganic encapsulation layer LIL2_I.

[0184] The method for manufacturing a display panel according to one or more embodiments may further include patterning the dummy layer DMP-I (eg, see Figure 7J ) to form a dummy pattern DMP. In the step (eg, action or task) of patterning the dummy layer DMP-I, the first dummy layer D1-I and the second dummy layer D2-I (eg, see Figure 7J) can be patterned by dry etching so as to remove portions except for the portion overlapping with the anode AE.

[0185] The first dummy pattern D1 and the second dummy pattern D2 overlapping the corresponding light emitting opening OP-E are formed by the patterned first dummy layer D1-I and the second dummy layer D2-I, and then the dummy pattern DMP including the first dummy pattern D1 and the second dummy pattern D2 may be formed. The first dummy pattern D1 and the second dummy pattern D2 may have a plurality of dummy patterns on a plane (e.g., in a plan view) in the corresponding light emitting regions PXA-R, PXA-G, and PXA-B (e.g., see Figure 4 ) around (e.g., around the corresponding light emitting regions PXA-R, PXA-G and PXA-B (e.g., see Figure 4 ))’s closed line shape.

[0186] Afterwards, refer to Figure 7L The method for manufacturing a display panel according to one or more embodiments of the present disclosure may include removing the dummy pattern DMP (eg, see Figure 7K ). In the step (eg, action or task) of removing the dummy pattern DMP, the dummy pattern DMP formed on the partition wall PW may be removed by wet etching. The region where the dummy pattern DMP is removed may be defined as a dummy region DMA (eg, see Figure 7L ). For example, in a cross-sectional view, the dummy area DMA may be formed between the partition wall PW and the lower inorganic encapsulation pattern LIL.

[0187] In one or more embodiments, a step (eg, action or task) of removing the dummy pattern DMP may not be provided. In such an embodiment, in a state where the dummy pattern DMP remains, for example, Figure 7M The organic encapsulation film OL and the upper inorganic encapsulation film UIL are shown in FIG.

[0188] Afterwards, refer to Figure 7M The method for manufacturing a display panel according to one or more embodiments may include removing the second photoresist layer PR2 (eg, see Figure 7L ) and then forming an organic encapsulation film OL and an upper inorganic encapsulation film UIL to obtain a final display panel DP. The organic encapsulation film OL can be formed by coating an organic material by an inkjet method, but the present disclosure is not limited thereto. The organic encapsulation film OL provides a planarized upper surface. Thereafter, an upper inorganic encapsulation film UIL can be formed by depositing an inorganic material. In this way, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE can be formed.

[0189] Between the step (e.g., action or task) of forming the lower inorganic encapsulation pattern LIL and the step (e.g., action or task) of obtaining the final display panel DP, the method may further include forming a partition wall opening and a light emitting opening corresponding to a light emitting area having another color in the partition wall PW and the pixel defining film PDL, forming a light emitting element providing the other color, and forming a lower inorganic encapsulation pattern covering the light emitting element providing the other color. Thus, a lower inorganic encapsulation pattern including, for example, Figure 4 The display panel DP includes first to third light emitting elements corresponding to the plurality of light emitting areas PXA-R, PXA-G, and PXA-B illustrated in the figure and lower inorganic encapsulation patterns corresponding to the first to third light emitting elements.

[0190] According to the above description, the lower inorganic encapsulation pattern may include a plurality of inorganic patterns, and the plurality of inorganic patterns may include silicon nitride (SiN x ) and / or silicon nitride oxide (SiON). x ) and / or a plurality of inorganic patterns of silicon oxide nitride (SiON) can cover the partition wall, thereby reducing or eliminating a phenomenon in which the lower inorganic encapsulation pattern is oxidized due to foreign matter introduced from the side surface of the first partition wall layer, the lower surface of the second partition wall layer, and / or the side surface of the second partition wall layer. Therefore, pixel defects (dark spots and / or pixel shrinkage, etc.) of the display panel caused by foreign matter can be reduced or eliminated.

[0191] As used herein, the terms "substantially", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "substantially" as used herein includes the stated value and means within the acceptable deviation range of the particular value determined by those of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0192] In addition, any numerical range disclosed and / or recorded in this article is intended to include all sub-ranges of the same numerical precision contained in the recorded range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the recorded minimum value of 1.0 and the recorded maximum value of 10.0 (and including the recorded minimum value of 1.0 and the recorded maximum value of 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit recorded in this article is intended to include all lower numerical limits contained therein, and any minimum numerical limit recorded in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly record any sub-ranges contained in the range explicitly recorded in this article.

[0193] Furthermore, when describing embodiments of the present disclosure, the use of “may” refers to “one or more embodiments of the present disclosure.”

[0194] Any suitable hardware, firmware (e.g., a dedicated integrated circuit), software, or a combination of software, firmware, and hardware may be utilized to implement the light-emitting device, electronic device, or any other related device or component according to the embodiments of the present disclosure described herein. For example, the various components of the device may be formed on an integrated circuit (IC) chip or on a separate IC chip. Further, the various components of the device may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. Further, the various components of the device may be processes or threads for executing the various functions described herein on one or more processors that execute computer program instructions and interact with other system components in one or more computing devices. The computer program instructions are stored in a memory that may be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). The computer program instructions may also be stored in other non-temporary computer-readable media (such as, for example, a CD-ROM or a flash drive, etc.). In addition, those skilled in the art should recognize that, without departing from the scope of the embodiments of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed on one or more other computing devices.

[0195] It will be understood that the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments, unless otherwise described. Therefore, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. It should be understood that the foregoing is an illustration of various example embodiments and should not be construed as limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments as well as other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined by the claims and their equivalents.

Claims

1. A display panel, comprising: basal layer; A pixel definition film, on the base layer and having a light emitting opening; a partition wall on the pixel definition film and having a partition wall opening overlapping the light emitting opening; a light emitting element including an anode, an intermediate layer, and a cathode, the cathode being in contact with the partition wall and in the partition wall opening; as well as an inorganic encapsulation pattern, comprising a first inorganic encapsulation pattern and a second inorganic encapsulation pattern sequentially arranged on the cathode, The first inorganic encapsulation pattern includes a plurality of inorganic patterns that are repeatedly stacked.

2. The display panel according to claim 1, wherein: Each of the plurality of inorganic patterns includes silicon nitride and / or silicon oxynitride.

3. The display panel according to claim 1, wherein: The plurality of inorganic patterns each include a first sub-pattern and a second sub-pattern, and The first sub-pattern and the second sub-pattern are sequentially and repeatedly stacked.

4. The display panel according to claim 3, wherein: The second sub-pattern is rich in nitrogen compared to the first sub-pattern.

5. The display panel according to claim 3, wherein: The first sub-pattern is richer in silicon than the second sub-pattern.

6. The display panel according to claim 3, wherein: The thickness of the first sub-pattern is smaller than the thickness of the second sub-pattern.

7. The display panel according to claim 1, wherein: The plurality of inorganic patterns include five or more inorganic patterns.

8. The display panel according to any one of claims 1 to 7, wherein: The partition wall includes a first partition wall layer on the pixel definition film and a second partition wall layer on the first partition wall layer, and The first partition wall layer has an undercut shape with respect to the second partition wall layer.

9. A display panel, comprising: basal layer; a pixel defining film on the base layer and having a light emitting opening; a partition wall on the pixel definition film and having a partition wall opening overlapping the light emitting opening; a light emitting element including an anode, an intermediate layer, and a cathode, the cathode being in contact with the partition wall and in the partition wall opening; as well as a first inorganic encapsulation pattern, comprising a first inorganic pattern and a second inorganic pattern sequentially arranged on the cathode, wherein the first inorganic pattern includes a 1-1th sub-pattern on the cathode and a 2-1th sub-pattern on the 1-1th sub-pattern, and The second inorganic pattern includes a 1-2 sub-pattern on the 2-1 sub-pattern and a 2-2 sub-pattern on the 1-2 sub-pattern.

10. The display panel according to claim 9, wherein: The first inorganic pattern and the second inorganic pattern each include silicon nitride and / or silicon oxynitride.

11. The display panel according to claim 9, wherein: The first inorganic encapsulation pattern includes a first sub-pattern and a second sub-pattern, The first sub-pattern includes the 1-1 sub-pattern and the 1-2 sub-pattern, and The second sub-pattern includes the 2-1st sub-pattern and the 2-2nd sub-pattern.

12. The display panel according to claim 11, wherein: The second sub-pattern is rich in nitrogen compared to the first sub-pattern.

13. The display panel according to claim 11, wherein: The first sub-pattern is richer in silicon than the second sub-pattern.

14. The display panel according to claim 11, wherein: The thickness of the first sub-pattern is smaller than the thickness of the second sub-pattern. 15 . The display panel according to claim 9 , further comprising a second inorganic encapsulation pattern on the 2-2 sub-pattern.

16. A method for manufacturing a display panel, the method comprising: Providing a preliminary display panel, the preliminary display panel comprising a base layer, a pixel definition film on the base layer, a first preliminary partition wall layer on the pixel definition film, and a second preliminary partition wall layer on the first preliminary partition wall layer; forming a first partition wall layer and a second partition wall layer having a partition wall opening by etching the first preliminary partition wall layer and the second preliminary partition wall layer; forming a light emitting pattern and a cathode inside the partition wall opening; as well as forming an inorganic encapsulation pattern on the cathode, The forming of the inorganic encapsulation pattern includes: depositing a first inorganic encapsulation layer on the cathode, depositing a second inorganic encapsulation layer on the first inorganic encapsulation layer, and forming a first inorganic encapsulation pattern and a second inorganic encapsulation pattern by etching the first inorganic encapsulation layer and the second inorganic encapsulation layer.

17. The method according to claim 16, wherein: The depositing of the first inorganic encapsulating layer on the cathode comprises: depositing a 1-1 sublayer on the cathode; and depositing a 2-1 sub-layer on the 1-1 sub-layer, The first inorganic layer includes the 1-1 sublayer and the 2-1 sublayer, and The 1-1 sub-layer is rich in silicon, and the 2-1 sub-layer is rich in nitrogen.

18. The method according to claim 17, wherein: The depositing of the first inorganic encapsulating layer on the cathode further comprises: depositing a 1-2 sub-layer on the first inorganic layer; and depositing a 2-2 sub-layer on the 1-2 sub-layer, wherein the second inorganic layer includes the 1-2 sublayer and the 2-2 sublayer, and The 1-2 sub-layer is rich in silicon, and the 2-2 sub-layer is rich in nitrogen.

19. The method according to claim 17, wherein: The depositing of the 1-1 sub-layer on the cathode comprises: introducing a silicon-containing gas and an argon gas; and A nitrogen-containing gas and the argon gas are introduced.

20. The method according to claim 17, wherein: The depositing of the 2-1 sub-layer on the 1-1 sub-layer includes: introducing a silicon-containing gas, a nitrogen-containing gas, and an argon gas; and The nitrogen-containing gas and the argon gas are introduced.

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