Display substrate and display device

Abstract

The invention provides a display substrate and a display device, relates to the technical field of display, and can realize high-frequency touch use and ensure that the characteristics of a transistor are kept stable under the influence of an external electric field and an external magnetic field and in severe environments such as high temperature and high humidity. The display substrate comprises a display area and a peripheral area located on the periphery of the display area, and further comprises a plurality of sub-pixels located in the display area, each sub-pixel comprises a sub-pixel driving circuit, and each sub-pixel driving circuit comprises a transistor structure; the display substrate further comprises a conducting layer and a signal transmission line, the orthographic projection of the conducting layer on the substrate body and the orthographic projection of the transistor structure on the substrate body are at least partially overlapped, and at least part of the conducting layer is located between the transistor structure and the substrate body of the display substrate. The conductive layer and the signal transmission line are coupled in the peripheral area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming more and more extensive, and people's requirements for the performance and application scenarios of display products are also getting higher and higher. For example: for display products with touch functions, high-frequency touch use can be achieved; under the influence of external electric and magnetic fields, as well as in harsh environments such as high temperature and high humidity, the characteristics of transistors in display products remain stable; however, the above requirements cannot be achieved in existing technologies. Summary of the invention

[0003] The object of the present invention is to provide a display substrate and a display device that can realize high-frequency touch control and ensure that the characteristics of the transistor remain stable under the influence of external electric and magnetic fields, and in harsh environments such as high temperature and high humidity.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display substrate, comprising a display area and a peripheral area located around the display area, and also comprising a plurality of sub-pixels located in the display area, wherein the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a transistor structure; the display substrate also includes:

[0006] A conductive layer and a signal transmission line, wherein the orthographic projection of the conductive layer on the base substrate at least partially overlaps with the orthographic projection of the transistor structure on the base substrate, and at least a portion of the conductive layer is located between the transistor structure and the base substrate of the display substrate; the conductive layer and the signal transmission line are coupled in the peripheral area.

[0007] Optionally, the display substrate further includes a first initialization signal line, the signal transmission line includes a first reset signal line, the transistor structure includes a driving transistor and a first reset transistor, a gate of the first reset transistor is coupled to the corresponding first reset signal line, a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first reset transistor includes a first reset active layer;

[0008] The conductive layer includes a first conductive pattern, an orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the first reset active layer on the base substrate, and the first conductive pattern is coupled to the first reset signal line in the peripheral area.

[0009] Optionally, the display substrate further includes a second initialization signal line, the sub-pixel further includes a light-emitting element, the transistor structure further includes a second reset transistor, a gate of the second reset transistor is coupled to a first reset signal line coupled to a first reset transistor in a sub-pixel adjacent to the second direction, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to an anode of the light-emitting element; the second reset transistor includes a second reset active layer;

[0010] An orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the second reset active layer on the base substrate.

[0011] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; and the first conductive pattern includes at least a portion extending along the first direction;

[0012] The orthographic projection of the first conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first reset active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or the orthographic projection of the first conductive pattern on the substrate at least partially overlaps with the orthographic projection of the second reset active layer included in each sub-pixel driving circuit in an adjacent upper row of sub-pixel driving circuits on the substrate.

[0013] Optionally, the peripheral area includes a left frame area and a right frame area which are arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; the display substrate further includes a first conductive connection portion;

[0014] In the left frame area and / or the right frame area, the first conductive connection portion is coupled to the corresponding first reset signal line, and the first conductive connection portion is coupled to the corresponding first conductive pattern through a first via hole;

[0015] The first via hole includes a first sub-via hole and a second sub-via hole that are connected to each other. The first sub-via hole is located between the second sub-via hole and the base substrate. The orthographic projection of the hole wall of the first sub-via hole on the base substrate is surrounded by the orthographic projection of the second sub-via hole on the base substrate.

[0016] Optionally, the signal transmission line includes a scan line, the transistor structure includes a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor includes a compensation active layer;

[0017] The conductive layer includes a second conductive pattern, an orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the second conductive pattern is coupled to the scan line in the peripheral area.

[0018] Optionally, the compensation transistor includes a dual-gate transistor, the compensation active layer includes a first channel portion, a second channel portion and a conductor portion, the conductor portion is coupled to the first channel portion and the second channel portion respectively, the orthographic projection of the second conductive pattern on the substrate substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate substrate, and / or the orthographic projection of the second conductive pattern on the substrate substrate at least partially overlaps with the orthographic projection of the second channel portion on the substrate substrate.

[0019] Optionally, the display substrate further includes a data line, the transistor structure further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding scanning line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; the data writing transistor includes a data writing active layer;

[0020] The orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the data writing active layer on the base substrate.

[0021] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; and the second conductive pattern includes at least a portion extending along the first direction;

[0022] The orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the compensation active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the data writing active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0023] Optionally, the peripheral area includes a left frame area and a right frame area which are arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; and the display substrate further includes a second conductive connection portion;

[0024] In the left frame area and / or the right frame area, the second conductive connection portion is coupled to the corresponding scan line, and the second conductive connection portion is coupled to the corresponding second conductive pattern through a second via hole;

[0025] The second via hole includes a third sub-via hole and a fourth sub-via hole that are connected to each other. The third sub-via hole is located between the fourth sub-via hole and the base substrate. The orthographic projection of the hole wall of the third sub-via hole on the base substrate is surrounded by the orthographic projection of the fourth sub-via hole on the base substrate.

[0026] Optionally, the display substrate further includes a scan line, the signal transmission line includes a first initialization signal line, the transistor structure includes a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor includes a compensation active layer;

[0027] The conductive layer includes a third conductive pattern, an orthographic projection of the third conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the third conductive pattern is coupled to the first initialization signal line in the peripheral area.

[0028] Optionally, the compensation active layer includes a first channel portion, a second channel portion and a conductor portion, and the conductor portion is coupled to the first channel portion and the second channel portion respectively;

[0029] The orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate; and / or, the orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the second channel portion on the substrate; and / or, the orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the conductor portion on the substrate.

[0030] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the third conductive pattern includes at least a portion extending along the first direction; the third conductive pattern includes a main body portion, and a plurality of protrusions respectively coupled to the main body portion;

[0031] The main body portion includes at least a portion extending along a first direction, the main body portion is coupled to the first initialization signal line in the peripheral region, and an orthographic projection of the main body portion on the base substrate does not overlap with an orthographic projection of at least one of the first channel portion, the second channel portion, and the conductor portion on the base substrate;

[0032] The multiple protrusions correspond one-to-one to each compensation active layer in a corresponding row of sub-pixel driving circuits; the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the first channel portion included in the corresponding compensation active layer on the substrate; and / or the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the second channel portion included in the corresponding compensation active layer on the substrate; and / or the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the conductor portion included in the corresponding compensation active layer on the substrate.

[0033] Optionally, the peripheral area includes a left border area and a right border area relatively arranged along a first direction, and the display area is located between the left border area and the right border area; the display substrate also includes a first initialization bus located in the left border area and / or the right border area, the first initialization bus includes at least a portion extending along the second direction, and in the left border area and / or the right border area, the main body and the first initialization signal line are respectively coupled to the first initialization bus.

[0034] Optionally, the main body is coupled to the first initialization bus through a third via, the third via includes a fifth sub-via and a sixth sub-via that are connected, the fifth sub-via is located between the sixth sub-via and the base substrate, and the orthographic projection of the hole wall of the fifth sub-via on the base substrate is surrounded by the orthographic projection of the sixth sub-via on the base substrate.

[0035] Optionally, the conductive layer further includes a first connection line, the first connection line is at least partially arranged around the display area, and the first connection line is respectively coupled to two ends of each of the main parts in the display substrate.

[0036] Optionally, an orthographic projection of the first connection line on the substrate at least partially overlaps with an orthographic projection of the first initialization bus on the substrate.

[0037] Optionally, the transmission signal line includes a power connection line located in the peripheral area, the transistor structure includes a driving transistor, and the driving transistor includes a driving active layer; the conductive layer includes a fourth conductive pattern, the orthographic projection of the fourth conductive pattern on the substrate at least partially overlaps with the orthographic projection of the driving active layer on the substrate, and the fourth conductive pattern is coupled to the power connection line.

[0038] Optionally, the peripheral area includes an upper frame area and a lower frame area that are arranged opposite to each other along the second direction, and the display area is located between the upper frame area and the lower frame area;

[0039] The power connection line is located in the upper frame area and / or the lower frame area; the conductive layer also includes a second connection line, at least part of the second connection line is arranged around the display area, the second connection line is coupled to the power connection line in the upper frame area and / or the lower frame area, and the second connection line is respectively coupled to both ends of each of the fourth conductive patterns in the display substrate.

[0040] Optionally, the second connecting line is coupled to the power connecting line in the upper frame area and / or the lower frame area through a fourth via, the fourth via includes a seventh sub-via and an eighth sub-via coupled, the seventh sub-via is located between the eighth sub-via and the substrate, and the orthographic projection of the hole wall of the seventh sub-via on the substrate is surrounded by the orthographic projection of the hole wall of the eighth sub-via on the substrate.

[0041] Optionally, the peripheral area further includes a first fan-out area and a second fan-out area, the first fan-out area is located between the display area and the second fan-out area; the display substrate further includes a plurality of data lines and a plurality of data fan-out lines, the data fan-out lines are coupled to the corresponding data lines, at least part of the data lines are located in the display area, at least part of the data fan-out lines are located in the first fan-out area and the second fan-out area, and the data fan-out line density of the first fan-out area is less than the fan-out line density of the second fan-out area;

[0042] The first connection line is located between the second fan-out area and the display area; or the second connection line is located between the second fan-out area and the display area.

[0043] Optionally, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; and the second conductive pattern includes at least a portion extending along the first direction;

[0044] The orthographic projection of the fourth conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the driving active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate.

[0045] Optionally, the display substrate further includes an interlayer insulating layer having a plurality of connection holes; an orthographic projection of the conductive layer on the base substrate does not overlap with an orthographic projection of hole walls of the connection holes on the base substrate.

[0046] Optionally, the interlayer insulating layer further includes a plurality of virtual compensation holes, the virtual compensation holes are located in the display area and / or the peripheral area, and the orthographic projection of the conductive layer on the substrate does not overlap with the orthographic projection of the hole wall of the virtual compensation hole on the substrate.

[0047] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present invention provides a display device, comprising the above-mentioned display substrate.

[0048] In the technical solution provided by the present invention, the orthographic projection of the conductive layer on the substrate substrate is set to overlap at least partially with the orthographic projection of the transistor structure on the substrate substrate, at least part of the conductive layer is located between the transistor structure and the substrate substrate of the display substrate, and the conductive layer is coupled to the signal transmission line in the peripheral area. In the case where the signal transmission line transmits a DC voltage signal with a stable potential, the conductive layer also transmits a DC voltage signal with a stable potential, so that the conductive layer can have a shielding effect on the transistor structure overlapped with it, and can shield the influence of the magnetic field and electric field generated by the touch control on the transistor structure when the display product is used for high-frequency touch control, and can also shield the influence of the magnetic field and electric field formed by the conductive structure inside the display substrate on the transistor structure. In the case where the signal transmission line is coupled to the gate of the transistor structure, the signal transmitted by the conductive layer is the same as the signal transmitted by the signal transmission line coupled to the gate of the transistor structure overlapped with it, so that the transistor structure and the conductive layer can form a dual-gate structure together, so that the characteristics of the transistor structure are more stable, so that the reliability yield of the display product in harsh environments such as high temperature and high humidity can be better met. Therefore, the display substrate provided by the embodiment of the present invention can achieve better display quality and avoid problems such as green display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0050] Figure 1A schematic diagram of the circuit principle of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0051] Figure 2 A schematic cross-sectional view of a film layer of a display substrate provided by an embodiment of the present invention;

[0052] Figure 3 A first schematic layout diagram of a conductive layer, an active layer and a first gate metal layer in a display substrate provided by an embodiment of the present invention;

[0053] Figure 4 A schematic diagram of the layout of an active layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer in a display substrate provided by an embodiment of the present invention;

[0054] Figure 5 A schematic diagram of the layout of a first source-drain metal layer in a display substrate provided by an embodiment of the present invention;

[0055] Figure 6 For Figure 4 A schematic diagram of a layout in which a second source / drain metal layer is added on the basis of the invention;

[0056] Figure 7 A schematic diagram of the layout of a second source-drain metal layer in a display substrate provided by an embodiment of the present invention;

[0057] Figure 8 is Figure 6 A schematic diagram of a layout of adding a second source / drain metal layer on the basis of FIG.

[0058] Fig. 9 A schematic diagram of connection between a third conductive pattern and a first connecting line provided by an embodiment of the present invention;

[0059] Fig.10 A second schematic layout diagram of a conductive layer, an active layer and a first gate metal layer in a display substrate provided by an embodiment of the present invention;

[0060] Fig.11 Another schematic diagram of the layout from the conductive layer to the second source-drain metal layer in the display substrate provided by an embodiment of the present invention;

[0061] Fig.12 A schematic diagram of the connection between the third conductive pattern and the first connecting line in the left frame provided by an embodiment of the present invention;

[0062] Fig.13 A schematic diagram of connection between a fourth conductive pattern and a second connecting line provided by an embodiment of the present invention;

[0063] Fig.14 A schematic diagram of the connection between the second connection line of the lower frame and the power connection line provided by an embodiment of the present invention;

[0064] Fig.15 A schematic diagram of the connection between the second connection line of the upper frame and the power connection line provided by an embodiment of the present invention;

[0065] Fig.16 A schematic diagram of the connection between the fourth conductive pattern and the second connecting line in the left frame provided by an embodiment of the present invention;

[0066] Fig.17 A schematic cross-sectional view of a casing hole provided in an embodiment of the present invention;

[0067] Fig.18 A schematic diagram of the layout of the second connection line in the lower left corner and the fan-out area provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0068] In order to further illustrate the display substrate and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0069] See also Figures 1 to 3 , Fig.10 , Fig.12 and Fig.16 The embodiment of the present invention provides a display substrate, comprising a display area 10 and a peripheral area 20 located around the display area 10, and also comprising a plurality of sub-pixels located in the display area 10, wherein the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a transistor structure; the display substrate also includes:

[0070] A conductive layer BSM and a signal transmission line 30, wherein the orthographic projection of the conductive layer BSM on the substrate at least partially overlaps with the orthographic projection of the transistor structure (such as: a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a data writing transistor T4 and a driving transistor T5, etc.) on the substrate, and at least a portion of the conductive layer BSM is located between the transistor structure and the substrate of the display substrate; the conductive layer BSM and the signal transmission line 30 are coupled in the peripheral area 20.

[0071] Exemplarily, the peripheral area 20 surrounds the display area 10 , but is not limited thereto.

[0072] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0073] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0074] Exemplarily, the specific structure of the sub-pixel driving circuit is various, for example: 6T1C (i.e., 6 transistors and 1 capacitor), 7T1C (i.e., 7 transistors and 1 capacitor), 8T1C (i.e., 8 transistors and 1 capacitor), 9T1C (i.e., 9 transistors and 1 capacitor), etc., but not limited thereto. The transistor structure includes at least one transistor in the sub-pixel driving circuit of any of the above structures.

[0075] Exemplarily, at least part of the conductive layer BSM is located between the transistor structure and the base substrate of the display substrate. When the transistor structure includes a low-temperature polysilicon transistor, at least part of the conductive layer BSM is located between the active layer included in the transistor structure and the base substrate.

[0076] Exemplarily, the conductive layer BSM is made of a conductive metal material, such as Mo (molybdenum), but is not limited thereto.

[0077] Exemplarily, the conductive layer BSM can extend from the display area 10 to the peripheral area 20 , but is not limited thereto.

[0078] Exemplarily, the signal transmission line 30 may include a portion located in the display area 10 and a portion located in the peripheral area 20; the signal transmission line 30 may also only include a portion located in the peripheral area 20; but is not limited to the above two methods.

[0079] Exemplarily, the signal transmission line 30 is used to transmit a DC voltage signal with a stable potential; and / or the signal transmission line 30 is coupled to the gate of the transistor structure to provide a corresponding signal to the gate of the transistor structure to control the conduction and cutoff of the transistor structure. The conductive layer BSM is coupled to the signal transmission line 30 so that the conductive layer BSM and the signal transmission line 30 transmit the same signal.

[0080] Exemplarily, the peripheral area 20 includes a left border area and a right border area relatively arranged along a first direction, and an upper border area and a lower border area relatively arranged along a second direction, and the display area 10 is located between the upper border area and the lower border area, and between the left border area and the right border area; the conductive layer BSM is coupled to the signal transmission line 30 in at least one of the upper border area, the lower border area, the left border area and the right border area.

[0081] Exemplarily, the transistor structure includes a corresponding transistor active layer, and the orthographic projection of the conductive layer BSM on the substrate substrate overlaps at least partially with the orthographic projection of the transistor active layer on the substrate substrate. Further, the transistor active layer includes a channel portion, and the orthographic projection of the conductive layer BSM on the substrate substrate may be arranged to overlap at least partially with the orthographic projection of the channel portion on the substrate substrate. It is worth noting that the orthographic projection of the channel portion on the substrate substrate is covered by the orthographic projection of the gate on the substrate substrate.

[0082] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present invention, the orthographic projection of the conductive layer BSM on the base substrate is set to at least partially overlap with the orthographic projection of the transistor structure on the base substrate, at least a portion of the conductive layer BSM is located between the transistor structure and the base substrate of the display substrate, and the conductive layer BSM is coupled to the signal transmission line 30 in the peripheral area 20. In the case where the signal transmission line 30 transmits a DC voltage signal with a stable potential, the conductive layer BSM also transmits a DC voltage signal with a stable potential, so that the conductive layer BSM can shield the transistor structure overlapping with it, and can shield the influence of the magnetic field and electric field generated by the touch control on the transistor structure when the display product is used for high-frequency touch control, and can also shield the influence of the magnetic field and electric field formed by the conductive structure inside the display substrate on the transistor structure. When the signal transmission line 30 is coupled to the gate of the transistor structure, the signal transmitted by the conductive layer BSM is the same as the signal transmitted by the signal transmission line 30 coupled to the gate of the overlapping transistor structure, so that the transistor structure and the conductive layer BSM can form a dual-gate structure together, making the characteristics of the transistor structure more stable, so as to better meet the reliability yield of display products in harsh environments such as high temperature and high humidity. Therefore, the display substrate provided by the embodiment of the present invention can achieve better display quality and avoid problems such as green display screen.

[0083] like Figures 3 to 8 As shown, in some embodiments, the display substrate further includes a first initialization signal line Vinit1, the signal transmission line 30 includes a first reset signal line Rst, the transistor structure includes a driving transistor T3 and a first reset transistor T1, the gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate of the driving transistor T3; the first reset transistor T1 includes a first reset active layer 41;

[0084] The conductive layer BSM includes a first conductive pattern BSM1, the orthographic projection of the first conductive pattern BSM1 on the base substrate at least partially overlaps with the orthographic projection of the first reset active layer 41 on the base substrate, and the first conductive pattern BSM1 is coupled to the first reset signal line Rst in the peripheral area 20.

[0085] Exemplarily, the display substrate includes a plurality of first initialization signal lines Vinit1, the first initialization signal line Vinit1 includes at least a portion extending along the first direction, the first initialization signal line Vinit1 corresponds one-to-one to a plurality of rows of sub-pixel driving circuits, and the first initialization signal line Vinit1 is respectively coupled to the first electrode of the first reset transistor T1 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0086] Exemplarily, the display substrate includes a plurality of first reset signal lines Rst, the first reset signal lines Rst include at least a portion extending along the first direction, the first reset signal lines Rst correspond one-to-one to a plurality of rows of sub-pixel driving circuits, and the first reset signal lines Rst are respectively coupled to the gates of the first reset transistors T1 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0087] Exemplarily, the conductive layer BSM includes a plurality of first conductive patterns BSM1, the first conductive patterns BSM1 including at least a portion extending along the first direction, the first conductive patterns BSM1 corresponding one-to-one to a plurality of rows of sub-pixel driving circuits, and an orthographic projection of the first conductive pattern BSM1 on the substrate at least partially overlaps with an orthographic projection of the first reset active layer 41 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0088] Exemplarily, the plurality of first conductive patterns BSM1 correspond one-to-one to the plurality of first reset signal lines Rst, and the first conductive patterns BSM1 are coupled to the corresponding first reset signal lines Rst in the peripheral region 20 .

[0089] In the display substrate provided in the above embodiment, the orthographic projection of the first conductive pattern BSM1 on the base substrate is set to at least partially overlap with the orthographic projection of the first reset active layer 41 on the base substrate, and the first conductive pattern BSM1 is coupled to the first reset signal line Rst in the peripheral area 20. In this way, the signal transmitted by the first conductive pattern BSM1 is the same as the signal transmitted by the first reset signal line Rst coupled to the gate of the first reset transistor T1 overlapped with it, so that the first reset transistor T1 and the first conductive pattern BSM1 can be formed into a double-gate structure together, so that the characteristics of the first reset transistor T1 are more stable, so that the reliability yield of the display product in harsh environments such as high temperature and high humidity can be better met.

[0090] like Figures 3 to 8As shown, in some embodiments, the display substrate further includes a second initialization signal line Vinit2, the sub-pixel further includes a light-emitting element, the transistor structure further includes a second reset transistor T7, the gate of the second reset transistor T7 is coupled to the first reset signal line Rst coupled to the first reset transistor T1 in the adjacent sub-pixel along the second direction, the first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is coupled to the anode of the light-emitting element; the second reset transistor T7 includes a second reset active layer 47;

[0091] An orthographic projection of the first conductive pattern BSM1 on the base substrate at least partially overlaps with an orthographic projection of the second reset active layer 47 on the base substrate.

[0092] Exemplarily, the display substrate includes a plurality of second initialization signal lines, the second initialization signal lines include at least a portion extending along the first direction, the second initialization signal lines correspond one-to-one to a plurality of rows of sub-pixel driving circuits, and the second initialization signal lines are respectively coupled to the first electrodes of the second reset transistors included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0093] Exemplarily, the first reset signal line Rst corresponds to a plurality of rows of sub-pixel driving circuits one by one, and the first reset signal line Rst is respectively coupled to the gate of the first reset transistor T1 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits. The gate of the second reset transistor T7 in each row of sub-pixel driving circuits is coupled to the first reset signal line Rst corresponding to the next row of sub-pixel driving circuits adjacent to the second direction.

[0094] Exemplarily, the second reset transistor T7 in each row of sub-pixel driving circuits includes an orthographic projection of the second reset active layer 47 on the substrate, which at least partially overlaps with an orthographic projection of the first conductive pattern BSM1 corresponding to the next row of sub-pixel driving circuits adjacent to the second direction on the substrate.

[0095] In the display substrate provided in the above embodiment, the orthographic projection of the first conductive pattern BSM1 on the base substrate is set to at least partially overlap with the orthographic projection of the second reset active layer on the base substrate, and the first conductive pattern BSM1 is coupled to the first reset signal line Rst in the peripheral area 20. In this way, the signal transmitted by the first conductive pattern BSM1 is the same as the signal transmitted by the first reset signal line Rst coupled to the gate of the second reset transistor overlapped therewith, so that the second reset transistor and the first conductive pattern BSM1 can form a dual-gate structure together, so that the characteristics of the second reset transistor are more stable, so as to better meet the reliability yield of the display product in harsh environments such as high temperature and high humidity.

[0096] like Figures 3 to 8 As shown, in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the first conductive pattern BSM1 includes at least a portion extending along the first direction;

[0097] The orthographic projection of the first conductive pattern BSM1 on the substrate at least partially overlaps with the orthographic projection of the first reset active layer 41 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or, the orthographic projection of the first conductive pattern BSM1 on the substrate at least partially overlaps with the orthographic projection of the second reset active layer 47 included in each sub-pixel driving circuit in an adjacent upper row of sub-pixel driving circuits on the substrate.

[0098] The above configuration improves the characteristics of the first reset transistor T1 and the second reset transistor T7 in the display substrate, while being helpful in simplifying the structure of the display substrate and reducing the difficulty of layout of the display substrate.

[0099] like Fig.16 As shown, in some embodiments, the peripheral area 20 includes a left frame area and a right frame area that are arranged opposite to each other along the first direction, and the display area 10 is located between the left frame area and the right frame area; the display substrate further includes a first conductive connection portion 51;

[0100] In the left frame area and / or the right frame area, the first conductive connection portion 51 is coupled to the corresponding first reset signal line Rst, and the first conductive connection portion 51 is coupled to the corresponding first conductive pattern BSM1 through a first via hole Via1;

[0101] like Fig.17As shown, the first via hole Via1 includes a first sub-via hole Via11 and a second sub-via hole Via12 that are connected to each other. The first sub-via hole Via11 is located between the second sub-via hole Via12 and the base substrate. The orthographic projection of the hole wall of the first sub-via hole Via11 on the base substrate is surrounded by the orthographic projection of the second sub-via hole Via12 on the base substrate.

[0102] It should be noted that Fig.12 and Fig.16 The dotted frame in the figure represents that a conductive connection portion made of a second source-drain metal layer will be provided here to electrically connect the corresponding structures.

[0103] like Figure 2 As shown, exemplarily, the display substrate includes a conductive layer BSM, a barrier layer Bar, a buffer layer BUF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source-drain metal layer SD1, a first flat layer PLN1, a second source-drain metal layer SD2, a second flat layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may also include a passivation layer PVX, but is not limited to it.

[0104] like Fig.17 As shown, exemplarily, the first via Via1 is manufactured by the ILD&EBB via process, including two process flows; after the interlayer insulating layer ILD is manufactured, an ILD via process is performed to form the second sub-via Via12, the second sub-via Via12 can at least penetrate the interlayer insulating layer ILD, the second sub-via Via12 can further penetrate the second gate insulating layer GI2, at least one layer of the first gate insulating layer GI1 and the buffer layer BUF, the second sub-via Via12 can also partially penetrate the barrier layer Bar; then an EBB via process is performed to completely penetrate the remaining film layers until the conductive layer BSM is exposed to form the first sub-via Via11.

[0105] Exemplarily, the first sub-via Via11 and the second sub-via Via12 are jointly formed into a stepped sleeve hole design, the aperture of the second sub-via Via12 is larger than the aperture of the first sub-via Via11, and the specific opening size is subject to the process capability. For example: in the direction parallel to the base substrate, on at least one side of the first via Via1, the distance between the orthographic projection of the hole wall of the second sub-via Via12 on the base substrate and the orthographic projection of the hole wall of the first sub-via Via11 on the base substrate is greater than or equal to 1 micron, ensuring that the orthographic projection of the hole wall of the first sub-via Via11 on the base substrate is surrounded by the orthographic projection of the second sub-via Via12 on the base substrate.

[0106] The above-mentioned arrangement is in the left frame area and / or the right frame area, and the first conductive connection part 51 is coupled to the corresponding first reset signal line Rst, and the first conductive connection part 51 is coupled to the corresponding first conductive pattern BSM1 through the first via Via1; so that the first conductive pattern BSM1 can be coupled to the first reset signal line Rst on the left and right sides of the display area 10, and the first conductive pattern BSM1 can penetrate the display area 10 along the first direction, thereby ensuring the signal transmission uniformity of the first conductive pattern BSM1 and the characteristic stability of its overlapping transistor structures.

[0107] The above setting that the first via hole Via1 adopts a sleeve hole structure not only ensures the manufacturing yield of the first via hole Via1, but also ensures the connection performance between the first conductive pattern BSM1 and the first conductive connecting portion 51.

[0108] like Figures 3 to 8 As shown, in some embodiments, the signal transmission line 30 includes a scan line GA, the transistor structure includes a driving transistor T3 and a compensation transistor T2, the gate of the compensation transistor T2 is coupled to the corresponding scan line GA, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3; the compensation transistor T2 includes a compensation active layer 42;

[0109] like Fig.16 As shown, the conductive layer BSM includes a second conductive pattern BSM2, the orthographic projection of the second conductive pattern BSM2 on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 on the base substrate, and the second conductive pattern BSM2 is coupled to the scan line GA in the peripheral area 20.

[0110] Exemplarily, the display substrate includes a plurality of scan lines GA, the scan lines GA include at least a portion extending along the first direction, the scan lines GA correspond one-to-one to a plurality of rows of sub-pixel driving circuits, and the scan lines GA are respectively coupled to the gate of the compensation transistor T2 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0111] Exemplarily, the conductive layer BSM includes a plurality of second conductive patterns BSM2, the second conductive patterns BSM2 including at least a portion extending along the first direction, the second conductive patterns BSM2 corresponding one-to-one to a plurality of rows of sub-pixel driving circuits, and the orthographic projection of the second conductive pattern BSM2 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0112] Exemplarily, the plurality of second conductive patterns BSM2 correspond to the plurality of scan lines GA one by one, and the second conductive patterns BSM2 are coupled to the corresponding scan lines GA in the peripheral region 20 .

[0113] Exemplarily, the first reset signal line Rst coupled to the current row of sub-pixel driving circuits is coupled to the scan line GA coupled to the adjacent previous row of sub-pixel driving circuits in the peripheral area 20. The coupling can be achieved through the first conductive connection portion 51, but is not limited thereto.

[0114] It is worth noting that if the signal lines coupling the first row of sub-pixel driving circuits and the last row of sub-pixel driving circuits in the display substrate do not have corresponding signal lines in the previous row or the next row to provide signals for them, corresponding shift register units can be directly added in the peripheral area 20 to provide corresponding signals for them.

[0115] In the display substrate provided in the above embodiment, the orthographic projection of the second conductive pattern BSM2 on the base substrate is set to at least partially overlap with the orthographic projection of the compensation active layer 42 on the base substrate, and the second conductive pattern BSM2 is coupled to the scan line GA in the peripheral area 20. In this way, the signal transmitted by the second conductive pattern BSM2 is the same as the signal transmitted by the scan line GA coupled to the gate of the compensation transistor T2 overlapped with it, so that the compensation transistor T2 and the second conductive pattern BSM2 can be formed into a dual-gate structure together, so that the characteristics of the compensation transistor T2 are more stable, so that the reliability yield of the display product in harsh environments such as high temperature and high humidity can be better met.

[0116] like Figures 3 to 8As shown, in some embodiments, the compensation transistor T2 includes a dual-gate transistor, the compensation active layer 42 includes a first channel portion 421, a second channel portion 422 and a conductor portion 423, the conductor portion 423 is coupled to the first channel portion 421 and the second channel portion 422 respectively, the orthographic projection of the second conductive pattern BSM2 on the substrate substrate at least partially overlaps with the orthographic projection of the first channel portion 421 on the substrate substrate, and / or, the orthographic projection of the second conductive pattern BSM2 on the substrate substrate at least partially overlaps with the orthographic projection of the second channel portion 422 on the substrate substrate.

[0117] Exemplarily, the orthographic projection of the first channel portion 421 on the substrate at least partially overlaps with the orthographic projection of the gate of the compensation transistor T2 on the substrate. The orthographic projection of the second channel portion 422 on the substrate at least partially overlaps with the orthographic projection of the gate of the compensation transistor T2 on the substrate.

[0118] The above configuration enables the compensation transistor T2 and the second conductive pattern BSM2 to further form a dual-gate structure, so that the characteristics of the compensation transistor T2 are more stable, thereby better meeting the reliability yield of display products in harsh environments such as high temperature and high humidity.

[0119] like Figures 3 to 8 As shown, in some embodiments, the display substrate further includes a data line DA, the transistor structure further includes a data writing transistor T4, the gate of the data writing transistor T4 is coupled to the corresponding scanning line GA, the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3; the data writing transistor T4 includes a data writing active layer 44;

[0120] The orthographic projection of the second conductive pattern BSM2 on the base substrate at least partially overlaps with the orthographic projection of the data writing active layer 44 on the base substrate.

[0121] Exemplarily, the display substrate includes a plurality of data lines DA, the data lines DA include at least a portion extending along the second direction, the data lines DA correspond one-to-one to a plurality of columns of sub-pixel driving circuits, and the data lines DA are respectively coupled to the first electrodes of the data writing transistors T4 included in each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuits.

[0122] Exemplarily, the scan line GA corresponds one-to-one to multiple rows of sub-pixel driving circuits, and the scan line GA is respectively coupled to the gate of the compensation transistor T2 and the gate of the data writing transistor T4 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0123] In the display substrate provided by the above embodiment, the orthographic projection of the second conductive pattern BSM2 on the base substrate is set to at least partially overlap with the orthographic projection of the data writing active layer 44 on the base substrate, and the second conductive pattern BSM2 is coupled to the scanning line GA in the peripheral area 20. In this way, the signal transmitted by the second conductive pattern BSM2 is the same as the signal transmitted by the scanning line GA coupled to the gate of the data writing transistor T4 overlapped with it, so that the data writing transistor T4 and the second conductive pattern BSM2 can be formed into a dual-gate structure together, so that the characteristics of the data writing transistor T4 are more stable, so that the reliability yield of the display product in harsh environments such as high temperature and high humidity can be better met.

[0124] like Figures 3 to 8 As shown, in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern BSM2 includes at least a portion extending along the first direction;

[0125] The orthographic projection of the second conductive pattern BSM2 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or, the orthographic projection of the second conductive pattern BSM2 on the substrate at least partially overlaps with the orthographic projection of the data writing active layer 44 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

[0126] The above configuration improves the characteristics of the compensation transistor T2 and the data writing transistor T4 in the display substrate, while being helpful in simplifying the structure of the display substrate and reducing the difficulty of layout of the display substrate.

[0127] like Fig.16 As shown, in some embodiments, the peripheral area 20 includes a left frame area and a right frame area that are arranged opposite to each other along the first direction, and the display area 10 is located between the left frame area and the right frame area; the display substrate further includes a second conductive connection portion 52;

[0128] In the left frame area and / or the right frame area, the second conductive connection portion 52 is coupled to the corresponding scan line GA, and the second conductive connection portion 52 is coupled to the corresponding second conductive pattern BSM2 through a second via hole Via2;

[0129] The second via hole Via2 includes a third sub-via and a fourth sub-via that are connected to each other. The third sub-via is located between the fourth sub-via and the base substrate. The orthographic projection of the hole wall of the third sub-via on the base substrate is surrounded by the orthographic projection of the fourth sub-via on the base substrate.

[0130] Exemplarily, the second via Via2 is manufactured by an ILD&EBB via process, which includes two process flows; after the interlayer insulating layer ILD is manufactured, an ILD via process is performed to form the fourth sub-via, and the fourth sub-via can at least penetrate the interlayer insulating layer ILD, and the fourth sub-via can further penetrate the second gate insulating layer GI2, the first gate insulating layer GI1 and at least one layer of the buffer layer BUF, and the fourth sub-via can also partially penetrate the barrier layer Bar; then an EBB via process is performed to completely penetrate the remaining film layers until the conductive layer BSM is exposed to form the third sub-via.

[0131] Exemplarily, the third sub-via and the fourth sub-via are jointly formed into a stepped sleeve hole design, the aperture of the fourth sub-via is larger than the aperture of the third sub-via, and the specific opening size is subject to the process capability. For example: in the direction parallel to the substrate, on at least one side of the second via Via2, the distance between the orthographic projection of the hole wall of the fourth sub-via on the substrate and the orthographic projection of the hole wall of the third sub-via on the substrate is greater than or equal to 1 micron, ensuring that the orthographic projection of the hole wall of the third sub-via on the substrate is surrounded by the orthographic projection of the fourth sub-via on the substrate.

[0132] The above-mentioned arrangement is in the left frame area and / or the right frame area, and the second conductive connection part 52 is coupled to the corresponding scanning line GA, and the second conductive connection part 52 is coupled to the corresponding second conductive graphic BSM2 through the second via Via2; so that the second conductive graphic BSM2 can be coupled to the scanning line GA on the left and right sides of the display area 10, and the second conductive graphic BSM2 can penetrate the display area 10 along the first direction, thereby ensuring the signal transmission uniformity of the second conductive graphic BSM2 and the characteristic stability of its overlapping transistor structures.

[0133] The above-mentioned arrangement of the second via hole Via2 using a sleeve hole structure not only ensures the manufacturing yield of the second via hole Via2, but also ensures the connection performance between the second conductive pattern BSM2 and the second conductive connecting portion 52.

[0134] like Figures 10 to 12 As shown, in some embodiments, the display substrate further includes a scan line GA, the signal transmission line 30 includes a first initialization signal line Vinit1, the transistor structure includes a driving transistor T3 and a compensation transistor T2, the gate of the compensation transistor T2 is coupled to the corresponding scan line GA, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3; the compensation transistor T2 includes a compensation active layer 42;

[0135] The conductive layer BSM includes a third conductive pattern BSM3 , the orthographic projection of the third conductive pattern BSM3 on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer 42 on the base substrate, and the third conductive pattern BSM3 is coupled to the first initialization signal line Vinit1 in the peripheral area 20 .

[0136] Exemplarily, the compensation active layer 42 includes a first channel portion 421, a second channel portion 422 and a conductor portion 423, and the conductor portion 423 is coupled to the first channel portion 421 and the second channel portion 422 respectively;

[0137] The orthographic projection of the third conductive pattern BSM3 on the substrate at least partially overlaps with the orthographic projection of the first channel portion 421 on the substrate; and / or, the orthographic projection of the third conductive pattern BSM3 on the substrate at least partially overlaps with the orthographic projection of the second channel portion 422 on the substrate; and / or, the orthographic projection of the third conductive pattern BSM3 on the substrate at least partially overlaps with the orthographic projection of the conductor portion 423 on the substrate.

[0138] The above-mentioned setting method enables the third conductive pattern BSM3 to also transmit the first initialization signal with a stable potential, so that the third conductive pattern BSM3 can shield the compensation transistor T2 overlapping with it, and can shield the influence of the magnetic field and electric field generated by the touch when the display product is used for high-frequency touch on the compensation transistor T2, and at the same time can shield the influence of the magnetic field and electric field formed by the conductive structure inside the display substrate on the compensation transistor T2.

[0139] like Figures 10 to 12As shown, in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the third conductive pattern BSM3 includes at least a portion extending along the first direction; the third conductive pattern BSM3 includes a main body portion BSM31, and a plurality of protrusions BSM32 respectively coupled to the main body portion BSM31;

[0140] The main body portion BSM31 includes at least a portion extending along the first direction, the main body portion BSM31 is coupled to the first initialization signal line Vinit1 in the peripheral area 20, and the orthographic projection of the main body portion BSM31 on the substrate does not overlap with the orthographic projection of at least one of the first channel portion 421, the second channel portion 422 and the conductor portion 423 on the substrate;

[0141] The multiple protrusions BSM32 correspond one by one to each compensation active layer 42 in a corresponding row of sub-pixel driving circuits; the orthographic projection of the protrusion BSM32 on the substrate at least partially overlaps with the orthographic projection of the first channel portion 421 included in the corresponding compensation active layer 42 on the substrate; and / or, the orthographic projection of the protrusion BSM32 on the substrate at least partially overlaps with the orthographic projection of the second channel portion 422 included in the corresponding compensation active layer 42 on the substrate; and / or, the orthographic projection of the protrusion BSM32 on the substrate at least partially overlaps with the orthographic projection of the conductor portion 423 included in the corresponding compensation active layer 42 on the substrate.

[0142] Exemplarily, the main body BSM31 and the plurality of protrusions BSM32 respectively coupled to the main body BSM31 form an integrated structure, but is not limited thereto.

[0143] The above configuration is conducive to reducing the layout difficulty of the third conductive pattern BSM3, reducing the overlapping area between the main body BSM31 and other conductive structures in the display area 10, and reducing the parasitic capacitance generated by the third conductive pattern BSM3.

[0144] like Fig.12As shown, in some embodiments, the peripheral area 20 includes a left border area and a right border area relatively arranged along a first direction, and the display area 10 is located between the left border area and the right border area; the display substrate also includes a first initialization bus 61 located in the left border area and / or the right border area, and the first initialization bus 61 includes at least a portion extending along the second direction, and in the left border area and / or the right border area, the main body BSM31 and the first initialization signal line Vinit1 are respectively coupled to the first initialization bus 61.

[0145] Need to explain, Fig.12 The second initialization bus 62 is also illustrated in FIG. 6 , and the second initialization bus 62 is coupled to the second initialization signal line Vinit2.

[0146] Exemplarily, the display substrate includes the first initialization bus 61 located in the left frame area, and also includes the first initialization bus 61 located in the right frame area.

[0147] Exemplarily, the main body BSM31 is coupled to the first initialization bus 61 through the third via Via3, the third via Via3 includes a fifth sub-via and a sixth sub-via that are connected, the fifth sub-via is located between the sixth sub-via and the base substrate, and the orthographic projection of the hole wall of the fifth sub-via on the base substrate is surrounded by the orthographic projection of the sixth sub-via on the base substrate. It is worth noting that the specific manufacturing process of the third via Via3 is the same as that of the first via Via1 and the second via Via2, which will not be repeated here.

[0148] The above-mentioned arrangement is in the left frame area and / or the right frame area, and the main body BSM31 and the first initialization signal line Vinit1 are respectively coupled to the first initialization bus 61; so that the third conductive pattern BSM3 can be coupled to the first initialization bus 61 on the left and right sides of the display area 10, and the third conductive pattern BSM3 can penetrate the display area 10 along the first direction, thereby ensuring the signal transmission uniformity of the third conductive pattern BSM3 and the characteristic stability of its overlapping transistor structures.

[0149] The third via hole is configured to adopt a sleeve hole structure, which not only ensures the manufacturing yield of the third via hole, but also ensures the connection performance between the third conductive pattern BSM3 and the first initialization bus 61.

[0150] like Fig. 9 and Fig.12As shown, in some embodiments, the conductive layer BSM also includes a first connecting line BSM-L1, which is at least partially arranged around the display area 10, and the first connecting line BSM-L1 is respectively coupled to both ends of each of the main parts BSM31 in the display substrate.

[0151] Exemplarily, the orthographic projection of the first connection line BSM-L1 on the base substrate at least partially overlaps with the orthographic projection of the first initialization bus 61 on the base substrate. This arrangement is conducive to narrowing the frame of the display substrate.

[0152] Exemplarily, the first connection line BSM-L1 surrounds the display area 10 , but is not limited thereto.

[0153] The above-mentioned arrangement of coupling the first connecting line BSM-L1 to the two ends of each of the main parts BSM31 in the display substrate is respectively conducive to further improving the uniformity of signal transmission of each of the third conductive patterns BSM3, thereby better improving the display quality of the display substrate.

[0154] It is worth noting that Fig.12 and Fig.16 Corresponding to two different implementation plans, in order to better achieve the compatibility of the solutions, Fig.12 The meeting will retain Fig.16 The adapter used in Fig.16 The meeting will retain Fig.12 The adapter is in the same layer as the first source-drain metal layer SD1 or the same layer as the conductive layer BSM, but is not limited thereto.

[0155] In some embodiments, the peripheral area 20 also includes a first fan-out area Fan1 and a second fan-out area Fan2, the first fan-out area Fan1 is located between the display area and the second fan-out area Fan2; the display substrate also includes a plurality of data lines DA and a plurality of data fan-out lines DAS, the data fan-out lines DAS are coupled to the corresponding data lines DA, at least a portion of the data lines DA is located in the display area 10, at least a portion of the data fan-out lines DAS is located in the first fan-out area Fan1 and the second fan-out area Fan2, the density of the data fan-out lines DAS in the first fan-out area Fan1 is less than the fan-out line density in the second fan-out area Fan2, and the first connecting line BSM-L1 is located between the second fan-out area Fan2 and the display area 10.

[0156] The above configuration is conducive to reducing the overlapping area between the first connecting line BSM-L1 and the fan-out line, reducing the parasitic capacitance generated between the first connecting line BSM-L1 and the fan-out line, and improving the uniformity of the signal transmitted by the third conductive pattern BSM3.

[0157] like Figures 3 to 8 As shown, Figures 13 to 16 As shown, in some embodiments, the transmission signal line includes a power connection line VDDL located in the peripheral area 20, the transistor structure includes a driving transistor T3, and the driving transistor T3 includes a driving active layer 43; the conductive layer BSM includes a fourth conductive pattern BSM4, and the orthographic projection of the fourth conductive pattern BSM4 on the substrate at least partially overlaps with the orthographic projection of the driving active layer 43 on the substrate, and the fourth conductive pattern BSM4 is coupled to the power connection line VDDL.

[0158] Exemplarily, the driving active layer 43 includes a driving channel portion, and an orthographic projection of the fourth conductive pattern BSM4 on the base substrate at least partially overlaps with an orthographic projection of the driving channel portion on the base substrate.

[0159] The above-mentioned setting method enables the fourth conductive pattern BSM4 to also transmit a power signal with a stable potential, so that the fourth conductive pattern BSM4 can shield the driving transistor T3 overlapping with it, and can shield the influence of the magnetic field and electric field generated by the touch when the display product is used for high-frequency touch on the driving transistor T3, and at the same time can shield the influence of the magnetic field and electric field formed by the conductive structure inside the display substrate on the driving transistor T3.

[0160] like Figures 13 to 16 As shown, in some embodiments, the peripheral area 20 includes an upper frame area and a lower frame area that are arranged opposite to each other along the second direction, and the display area 10 is located between the upper frame area and the lower frame area;

[0161] The power connection line VDDL is located in the upper frame area and / or the lower frame area; the conductive layer BSM also includes a second connection line BSM-L2, at least part of the second connection line BSM-L2 is arranged around the display area 10, the second connection line BSM-L2 is coupled to the power connection line VDDL in the upper frame area and / or the lower frame area, and the second connection line BSM-L2 is respectively coupled to both ends of each of the fourth conductive patterns BSM4 in the display substrate.

[0162] For example, Fig.14 As shown, the second connection line BSM-L2 is coupled to the power line VDD in the lower frame area.

[0163] Exemplarily, the second connection line BSM-L2 surrounds the display area 10 , but is not limited thereto.

[0164] Exemplarily, the display substrate includes two power connection lines VDDL, one power connection line VDDL is located in the upper frame area, and the other power connection line VDDL is located in the lower frame area, and the two power connection lines VDDL are arranged opposite to each other along the second direction.

[0165] Exemplarily, the second connection line BSM-L2 is coupled to the power connection line VDDL in the upper frame area and / or the lower frame area through the fourth via Via4, the fourth via Via4 includes a seventh sub-via and an eighth sub-via coupled, the seventh sub-via is located between the eighth sub-via and the base substrate, and the orthographic projection of the hole wall of the seventh sub-via on the base substrate is surrounded by the orthographic projection of the hole wall of the eighth sub-via on the base substrate. It is worth noting that the specific manufacturing process of the fourth via Via4 is the same as that of the first via Via1 and the second via Via2 mentioned above, and will not be repeated here.

[0166] The above-mentioned second connection line BSM-L2 is at least partially arranged around the display area 10, and the second connection line BSM-L2 is coupled to the power connection line VDDL in the upper frame area and / or the lower frame area, and the second connection line BSM-L2 is respectively coupled to the two ends of each of the fourth conductive graphics BSM4 in the display substrate, so that the second connection line BSM-L2 can be connected to the power connection line VDDL in the upper frame area and / or the lower frame area, receive the power signal transmitted by the power connection line VDDL, and the second connection line BSM-L2 goes around the left frame area and the right frame area to achieve coupling with each of the fourth conductive graphics BSM4, and transmits the power signal to the fourth conductive graphics BSM4, so as to better improve the uniformity of the signal transmitted by each of the fourth conductive graphics BSM4, thereby better improving the display quality of the display substrate.

[0167] The fourth via hole is configured to adopt a sleeve hole structure, which not only ensures the manufacturing yield of the fourth via hole, but also ensures the connection performance between the second connecting line BSM-L2 and the power connecting line VDDL.

[0168] like Fig.18As shown, in some embodiments, the peripheral area 20 also includes a first fan-out area Fan1 and a second fan-out area Fan2, and the first fan-out area Fan1 is located between the display area 10 and the second fan-out area Fan2; the display substrate also includes a plurality of data lines DA and a plurality of data fan-out lines DAS, the data fan-out lines DAS are coupled to the corresponding data lines DA, at least a portion of the data lines DA is located in the display area 10, at least a portion of the data fan-out lines DAS is located in the first fan-out area Fan1 and the second fan-out area Fan2, and the density of the data fan-out lines DAS in the first fan-out area Fan1 is less than the fan-out line density in the second fan-out area Fan2; the second connecting line BSM-L2 is located between the second fan-out area Fan2 and the display area 10.

[0169] The above configuration is conducive to reducing the overlapping area between the second connecting line BSM-L2 and the data fan-out line DAS, reducing the parasitic capacitance generated between the second connecting line and the fan-out line, and improving the uniformity of the signal transmitted by the fourth conductive pattern.

[0170] like Figures 3 to 8 As shown, Figures 13 to 16 As shown, in some embodiments, the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern BSM2 includes at least a portion extending along the first direction;

[0171] The orthographic projection of the fourth conductive pattern BSM4 on the base substrate at least partially overlaps with the orthographic projection of the driving active layer 43 included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate.

[0172] Exemplarily, the fourth conductive pattern BSM4 penetrates the display area 10 along the first direction, but is not limited thereto.

[0173] The above configuration improves the stability of the driving transistor T3 in the display substrate while being helpful in simplifying the structure of the display substrate and reducing the difficulty of the layout of the display substrate.

[0174] like Figure 2 , Figure 3 and Fig.10 As shown, in some embodiments, the display substrate further includes an interlayer insulating layer ILD, and the interlayer insulating layer ILD has a plurality of connecting holes LVia; the orthographic projection of the conductive layer BSM on the base substrate does not overlap with the orthographic projection of the hole wall of the connecting hole LVia on the base substrate.

[0175] Exemplarily, the plurality of connection holes LVia include vias for connecting the active layer poly and the first source-drain metal layer SD1, vias for connecting the first gate insulating layer GI1 and the first source-drain metal layer SD1, and vias for connecting the second gate insulating layer GI2 and the first source-drain metal layer SD1.

[0176] Since the conductive layer BSM is manufactured first and the connecting hole LVia is manufactured later, in the process of forming the connecting hole LVia, the accumulated static electricity may be directed to the conductive layer BSM, causing damage to the conductive layer BSM. The above-mentioned setting makes the orthographic projection of the conductive layer BSM on the substrate and the orthographic projection of the hole wall of the connecting hole LVia on the substrate not overlap, so that the distance between the conductive layer BSM and the connecting hole LVia is relatively far, which can effectively avoid the above-mentioned problem.

[0177] like Fig.18 As shown, in some embodiments, the interlayer insulating layer also includes a plurality of virtual compensation holes XVia, and the virtual compensation holes XVia are located in the display area 10 and / or the peripheral area 20, and the orthographic projection of the conductive layer BSM on the substrate does not overlap with the orthographic projection of the hole wall of the virtual compensation hole XVia on the substrate.

[0178] Exemplarily, the virtual compensation hole XVia is generally designed to ensure the uniformity of the display substrate layout, and the layout position of the virtual compensation hole XVia is varied, for example: arranged in the display area 10 at the corner of the display substrate and / or in the peripheral area 20 at the corner, but not limited to this. The corner includes the upper left corner, the upper right corner, the lower left corner and the lower right corner, but not limited to this.

[0179] The above-mentioned setting makes the orthographic projection of the conductive layer BSM on the substrate not overlap with the orthographic projection of the hole wall of the virtual compensation hole XVia on the substrate, so that the distance between the conductive layer BSM and the virtual compensation hole XVia is relatively far. In this way, when making the virtual compensation hole XVia, it is possible to avoid the accumulated static electricity from being directed to the conductive layer BSM, thereby avoiding damaging the conductive layer BSM.

[0180] like Figure 1 As shown, in some embodiments, the display substrate includes a power line VDD, a data line DA, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a first reset signal line Rst, a scan line GA, and a light emission control signal line EM. The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emission control transistor T6 and a storage capacitor Cst.

[0181] The gate of the first reset transistor T1 is coupled to the corresponding first reset signal line Rst, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3 - g of the driving transistor T3 .

[0182] The gate of the compensation transistor T2 is coupled to the corresponding scan line GA, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0183] The gate of the data writing transistor T4 is coupled to the corresponding scanning line GA1 , the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 .

[0184] The gate of the power control transistor T5 is coupled to the corresponding light emitting control signal line EM, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0185] The gate of the light emitting control transistor T6 is coupled to the corresponding light emitting control signal line EM, the first electrode of the light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light emitting control transistor T6 is coupled to the anode of the corresponding light emitting element. The cathode of the light emitting element transmits a VSS signal.

[0186] A gate of the second reset transistor T7 is coupled to a first reset signal line Rst′ connected to a sub-pixel driving circuit adjacent to the second direction.

[0187] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the driving transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the power line VDD.

[0188] like Figure 3 and Fig.10 As shown, the figure also illustrates a power control active layer 45 included in the power control transistor T5 and a light emission control active layer 46 included in the light emission control transistor T6.

[0189] like Figure 4As shown, the figure illustrates the second initialization connection line Vinit2' and the first initialization connection line Vinit1'. The second initialization connection line Vinit2' is coupled to each second initialization signal line Vinit2 respectively to form a grid structure. The first initialization connection line Vinit1' is coupled to each first initialization signal line Vinit1 respectively to form a grid structure.

[0190] like Figure 5 As shown, the figure schematically shows a third conductive connection portion 53, a fourth conductive connection portion 54, a fifth conductive connection portion 55, a sixth conductive connection portion 56 and a seventh conductive connection portion 57. Figure 6 and Figure 7 As shown, the eighth conductive connection portion 58 is illustrated in the figure.

[0191] like Figures 4 to 7 As shown, the third conductive connection portion 53 is respectively coupled to the second electrode of the light emitting control transistor T6 and the eighth conductive connection portion 58, and the eighth conductive connection portion 58 is coupled to the anode of the light emitting element. The fourth conductive connection portion 54 is respectively coupled to the first electrode of the data writing transistor T4 and the data line DA. The fifth conductive connection portion 55 is respectively coupled to the gate of the driving transistor T3, the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2. The sixth conductive connection portion 56 is respectively coupled to the second initialization signal line Vinit2 and the first electrode of the second reset transistor T7. The seventh conductive connection portion 57 is respectively coupled to the first initialization signal line Vinit1 and the first electrode of the first reset transistor T1.

[0192] like Figure 6 and Figure 7 As shown in the figure, a compensation power line VDD' is illustrated, and the compensation power line VDD' is coupled to the corresponding power line VDD through a via hole (such as a larger square hole in the figure) penetrating the second planar layer.

[0193] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0194] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0195] Exemplarily, the display device includes an active matrix organic light emitting diode display device, but is not limited thereto.

[0196] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present invention, the orthographic projection of the conductive layer on the base substrate is set to overlap at least partially with the orthographic projection of the transistor structure on the base substrate, at least part of the conductive layer is located between the transistor structure and the base substrate of the display substrate, and the conductive layer is coupled to the signal transmission line in the peripheral area. In the case where the signal transmission line transmits a DC voltage signal with a stable potential, the conductive layer also transmits a DC voltage signal with a stable potential, so that the conductive layer can have a shielding effect on the transistor structure overlapped with it, and can shield the influence of the magnetic field and electric field generated by the touch control on the transistor structure when the display product is used for high-frequency touch control, and can also shield the influence of the magnetic field and electric field formed by the conductive structure inside the display substrate on the transistor structure. In the case where the signal transmission line is coupled to the gate of the transistor structure, the signal transmitted by the conductive layer is the same as the signal transmitted by the signal transmission line coupled to the gate of the transistor structure overlapped with it, so that the transistor structure and the conductive layer can form a dual-gate structure together, so that the characteristics of the transistor structure are more stable, so that the reliability yield of the display product in harsh environments such as high temperature and high humidity can be better met. Therefore, the display substrate provided by the embodiment of the present invention can achieve better display quality and avoid problems such as green display screen.

[0197] It should be noted that the signal line extends along the X direction means that the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending along other directions.

[0198] It should be noted that the layout area occupied by each sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0199] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0200] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0201] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0202] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0203] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0204] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0205] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display substrate, It is characterized in that The display substrate includes a display area and a peripheral area located around the display area, and also includes a plurality of sub-pixels located in the display area, wherein the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a transistor structure; the display substrate also includes: A conductive layer and a signal transmission line, wherein the orthographic projection of the conductive layer on the base substrate at least partially overlaps with the orthographic projection of the transistor structure on the base substrate, and at least a portion of the conductive layer is located between the transistor structure and the base substrate of the display substrate; the conductive layer and the signal transmission line are coupled in the peripheral area.

2. The display substrate according to claim 1, It is characterized in that The display substrate further includes a first initialization signal line, the signal transmission line includes a first reset signal line, the transistor structure includes a driving transistor and a first reset transistor, a gate of the first reset transistor is coupled to the corresponding first reset signal line, a first electrode of the first reset transistor is coupled to the corresponding first initialization signal line, and a second electrode of the first reset transistor is coupled to the gate of the driving transistor; the first reset transistor includes a first reset active layer; The conductive layer includes a first conductive pattern, an orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the first reset active layer on the base substrate, and the first conductive pattern is coupled to the first reset signal line in the peripheral area.

3. The display substrate according to claim 2, It is characterized in that The display substrate further includes a second initialization signal line, the sub-pixel further includes a light-emitting element, the transistor structure further includes a second reset transistor, a gate of the second reset transistor is coupled to a first reset signal line coupled to a first reset transistor in a sub-pixel adjacent to the second direction, a first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to an anode of the light-emitting element; the second reset transistor includes a second reset active layer; An orthographic projection of the first conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the second reset active layer on the base substrate.

4. The display substrate according to claim 3, It is characterized in that The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the first conductive pattern includes at least a portion extending along the first direction; The orthographic projection of the first conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first reset active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or the orthographic projection of the first conductive pattern on the substrate at least partially overlaps with the orthographic projection of the second reset active layer included in each sub-pixel driving circuit in an adjacent upper row of sub-pixel driving circuits on the substrate.

5. The display substrate according to claim 4, It is characterized in that The peripheral area includes a left frame area and a right frame area which are arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; the display substrate also includes a first conductive connection portion; In the left frame area and / or the right frame area, the first conductive connection portion is coupled to the corresponding first reset signal line, and the first conductive connection portion is coupled to the corresponding first conductive pattern through a first via hole; The first via hole includes a first sub-via hole and a second sub-via hole that are connected to each other. The first sub-via hole is located between the second sub-via hole and the base substrate. The orthographic projection of the hole wall of the first sub-via hole on the base substrate is surrounded by the orthographic projection of the second sub-via hole on the base substrate.

6. The display substrate according to claim 1, It is characterized in that The signal transmission line includes a scan line, the transistor structure includes a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor includes a compensation active layer; The conductive layer includes a second conductive pattern, an orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the second conductive pattern is coupled to the scan line in the peripheral area.

7. The display substrate according to claim 6, It is characterized in that The compensation transistor comprises a dual-gate transistor, the compensation active layer comprises a first channel portion, a second channel portion and a conductor portion, the conductor portion is coupled to the first channel portion and the second channel portion respectively, the orthographic projection of the second conductive pattern on the substrate substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate substrate, and / or the orthographic projection of the second conductive pattern on the substrate substrate at least partially overlaps with the orthographic projection of the second channel portion on the substrate substrate.

8. The display substrate according to claim 6, It is characterized in that The display substrate further includes a data line, the transistor structure further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding scanning line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; the data writing transistor includes a data writing active layer; The orthographic projection of the second conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the data writing active layer on the base substrate.

9. The display substrate according to claim 8, It is characterized in that The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern includes at least a portion extending along the first direction; The orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the compensation active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate; and / or the orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the data writing active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the substrate.

10. The display substrate according to claim 9, It is characterized in that The peripheral area includes a left frame area and a right frame area which are arranged opposite to each other along the first direction, and the display area is located between the left frame area and the right frame area; the display substrate also includes a second conductive connection portion; In the left frame area and / or the right frame area, the second conductive connection portion is coupled to the corresponding scan line, and the second conductive connection portion is coupled to the corresponding second conductive pattern through a second via hole; The second via hole includes a third sub-via hole and a fourth sub-via hole that are connected to each other. The third sub-via hole is located between the fourth sub-via hole and the base substrate. The orthographic projection of the hole wall of the third sub-via hole on the base substrate is surrounded by the orthographic projection of the fourth sub-via hole on the base substrate.

11. The display substrate according to claim 1, It is characterized in that The display substrate further comprises a scan line, the signal transmission line comprises a first initialization signal line, the transistor structure comprises a driving transistor and a compensation transistor, the gate of the compensation transistor is coupled to the corresponding scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; the compensation transistor comprises a compensation active layer; The conductive layer includes a third conductive pattern, an orthographic projection of the third conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the compensation active layer on the base substrate, and the third conductive pattern is coupled to the first initialization signal line in the peripheral area.

12. The display substrate according to claim 11, It is characterized in that The compensation active layer includes a first channel portion, a second channel portion and a conductor portion, and the conductor portion is coupled to the first channel portion and the second channel portion respectively; The orthographic projection of the third conductive pattern on the substrate at least partially overlaps with the orthographic projection of the first channel portion on the substrate; And / or, an orthographic projection of the third conductive pattern on the substrate at least partially overlaps with an orthographic projection of the second channel portion on the substrate; And / or, an orthographic projection of the third conductive pattern on the base substrate at least partially overlaps with an orthographic projection of the conductor portion on the base substrate.

13. The display substrate according to claim 12, It is characterized in that The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the third conductive pattern includes at least a portion extending along the first direction; the third conductive pattern includes a main body portion, and a plurality of protrusions respectively coupled to the main body portion; The main body portion includes at least a portion extending along a first direction, the main body portion is coupled to the first initialization signal line in the peripheral region, and an orthographic projection of the main body portion on the base substrate does not overlap with an orthographic projection of at least one of the first channel portion, the second channel portion, and the conductor portion on the base substrate; The plurality of protrusions correspond one-to-one to each compensation active layer in a corresponding row of sub-pixel driving circuits; an orthographic projection of the protrusion on the substrate at least partially overlaps with an orthographic projection of the first channel portion included in the corresponding compensation active layer on the substrate; And / or, an orthographic projection of the protrusion on the substrate at least partially overlaps with an orthographic projection of the second channel portion included in the corresponding compensation active layer on the substrate; And / or, an orthographic projection of the protrusion on the substrate at least partially overlaps with an orthographic projection of the conductor portion included in the corresponding compensation active layer on the substrate.

14. The display substrate according to claim 13, It is characterized in that The peripheral area includes a left frame area and a right frame area arranged relatively to each other along a first direction, and the display area is located between the left frame area and the right frame area; the display substrate also includes a first initialization bus located in the left frame area and / or the right frame area, the first initialization bus includes at least a portion extending along the second direction, and in the left frame area and / or the right frame area, the main body and the first initialization signal line are respectively coupled to the first initialization bus.

15. The display substrate according to claim 14, It is characterized in that The main body is coupled to the first initialization bus through a third via, the third via includes a fifth sub-via and a sixth sub-via that are connected, the fifth sub-via is located between the sixth sub-via and the base substrate, and the orthographic projection of the hole wall of the fifth sub-via on the base substrate is surrounded by the orthographic projection of the sixth sub-via on the base substrate.

16. The display substrate according to claim 14, It is characterized in that The conductive layer further includes a first connection line, which is at least partially arranged around the display area, and the first connection line is respectively coupled to two ends of each of the main body parts in the display substrate.

17. The display substrate according to claim 16, It is characterized in that An orthographic projection of the first connection line on the substrate at least partially overlaps with an orthographic projection of the first initialization bus on the substrate.

18. The display substrate according to claim 1, It is characterized in that The transmission signal line includes a power connection line located in the peripheral area, the transistor structure includes a driving transistor, and the driving transistor includes a driving active layer; the conductive layer includes a fourth conductive pattern, the orthographic projection of the fourth conductive pattern on the substrate at least partially overlaps with the orthographic projection of the driving active layer on the substrate, and the fourth conductive pattern is coupled to the power connection line.

19. The display substrate according to claim 18, It is characterized in that The peripheral area includes an upper frame area and a lower frame area that are arranged opposite to each other along the second direction, and the display area is located between the upper frame area and the lower frame area; The power connection line is located in the upper frame area and / or the lower frame area; the conductive layer also includes a second connection line, at least part of the second connection line is arranged around the display area, the second connection line is coupled to the power connection line in the upper frame area and / or the lower frame area, and the second connection line is respectively coupled to both ends of each of the fourth conductive patterns in the display substrate.

20. The display substrate according to claim 19, It is characterized in that The second connecting line is coupled to the power connecting line in the upper frame area and / or the lower frame area through a fourth via, the fourth via includes a seventh sub-via and an eighth sub-via coupled, the seventh sub-via is located between the eighth sub-via and the base substrate, and the orthographic projection of the hole wall of the seventh sub-via on the base substrate is surrounded by the orthographic projection of the hole wall of the eighth sub-via on the base substrate.

21. The display substrate according to claim 16 or 19, It is characterized in that The peripheral area further includes a first fan-out area and a second fan-out area, the first fan-out area is located between the display area and the second fan-out area; the display substrate further includes a plurality of data lines and a plurality of data fan-out lines, the data fan-out lines are coupled to the corresponding data lines, at least a portion of the data lines is located in the display area, at least a portion of the data fan-out lines is located in the first fan-out area and the second fan-out area, and a data fan-out line density in the first fan-out area is less than a fan-out line density in the second fan-out area; The first connection line is located between the second fan-out area and the display area; or the second connection line is located between the second fan-out area and the display area.

22. The display substrate according to claim 18, It is characterized in that The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction; the second conductive pattern includes at least a portion extending along the first direction; The orthographic projection of the fourth conductive pattern on the base substrate at least partially overlaps with the orthographic projection of the driving active layer included in each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits on the base substrate.

23. The display substrate according to any one of claims 1 to 20, It is characterized in that The display substrate further comprises an interlayer insulating layer having a plurality of connection holes; the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the hole wall of the connection hole on the base substrate.

24. The display substrate according to claim 23, It is characterized in that The interlayer insulating layer also includes a plurality of virtual compensation holes, the virtual compensation holes are located in the display area and / or the peripheral area, and the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the hole wall of the virtual compensation hole on the base substrate.

25. A display device, It is characterized in that The invention comprises the display substrate according to any one of claims 1 to 24.

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