Display panel

Abstract

A display panel includes: a driving element layer including a first pixel driver including a first conductive pattern and a second pixel driver including a second conductive pattern; a light emitting element on the driving element layer and including a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connection electrode on the driving element layer and electrically connected with the first pixel driver and the second electrode; and a metal layer between the second conductive pattern and the connection electrode in a cross-sectional view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0166461 filed in the Korean Intellectual Property Office on November 27, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display panel, and more particularly, to a display panel with reduced afterimage. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, computers (such as tablet computers), navigators or game consoles are provided with display panels for displaying images. The display panel includes a light-emitting element and a circuit for controlling the light-emitting element. The light-emitting element included in the display panel emits light according to a voltage applied from the circuit to generate an image. In order to improve the reliability of the display panel, it may be desirable to improve the connection between the light-emitting element and the circuit.

[0005] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] One or more embodiments of the present disclosure may be directed to a display panel with reduced afterimage.

[0007] According to one or more embodiments of the present disclosure, a display panel includes: a driving element layer, including a first pixel driver including a first conductive pattern and a second pixel driver including a second conductive pattern; a light-emitting element, on the driving element layer, and including a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connecting electrode, on the driving element layer, and electrically connected to the first pixel driver and the second electrode; and a metal layer, between the second conductive pattern and the connecting electrode in a cross-sectional view.

[0008] In an embodiment, the first conductive pattern may include: a 1-1th pattern; and a 2-1th pattern electrically connected to the connection electrode.

[0009] In an embodiment, the second conductive pattern may include a 1-2th pattern and a 2-2th pattern.

[0010] In an embodiment, the 1-2th pattern and the 2-2th pattern may overlap the metal layer in a plan view.

[0011] In an embodiment, the 1-2 pattern and the 2-2 pattern may overlap with the connection electrode in a plan view.

[0012] In an embodiment, the 1-1th pattern and the 1-2th pattern may include a source electrode pattern.

[0013] In an embodiment, the 2-1th pattern and the 2-2th pattern may include a drain electrode pattern.

[0014] In an embodiment, the display panel may further include: an intermediate connection electrode electrically connecting the first pixel driver and the connection electrode to each other.

[0015] In an embodiment, the metal layer may include the same material as that of the intermediate connection electrode, and the metal layer may be positioned at the same layer as that of the intermediate connection electrode.

[0016] In an embodiment, the metal layer may include the same material as that of the first electrode, and the metal layer may be connected to the first electrode.

[0017] In an embodiment, the display panel may further include: a pixel defining layer on the driving element layer and having an emission opening passing through the pixel defining layer, the emission opening exposing at least a portion of the first electrode. The connection electrode may have a ring shape surrounding the emission opening.

[0018] In an embodiment, a bottom surface of the second electrode may contact a top surface of the connection electrode.

[0019] In an embodiment, the display panel may further include: a spacer on the connection electrode, and the second electrode and the connection electrode may be connected to each other at a region adjacent to the spacer.

[0020] In an embodiment, the connection electrode may include: a first edge; and a second edge surrounding the first edge and overlapping the spacer.

[0021] According to one or more embodiments of the present disclosure, a display panel includes: a driving element layer, including a pixel driver including a conductive pattern; a light-emitting element, which is on the driving element layer and includes a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connecting electrode, which is on the driving element layer and is electrically connected to the pixel driver and the second electrode; and a metal layer, which overlaps with the connecting electrode and the conductive pattern in a plan view.

[0022] In an embodiment, the conductive pattern may include: a first pattern; and a second pattern electrically connected to the connection electrode.

[0023] In an embodiment, the first pattern may include a source electrode pattern, and the second pattern may include a drain electrode pattern.

[0024] In an embodiment, the display panel may further include: an intermediate connection electrode electrically connecting the pixel driver and the connection electrode to each other.

[0025] In an embodiment, the metal layer may include the same material as that of the intermediate connecting electrode, and the metal layer may be positioned on the same layer as that of the intermediate connecting electrode.

[0026] In an embodiment, the metal layer may include the same material as that of the first electrode, and the metal layer may be connected to the first electrode.

[0027] However, the present disclosure is not limited to the above-mentioned aspects and features, and the above-mentioned and other aspects and features of the present disclosure will be partially set forth in the following detailed description with reference to the accompanying drawings, and in part may be obvious from the detailed description, or may be understood by practicing one or more of the multiple presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0029] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure;

[0030] FIG. 2A to FIG. 2C is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0031] Figure 3A and Figure 3B is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0032] FIG. 4A to FIG. 4D is an enlarged plan view of a partial area of ​​a display panel according to one or more embodiments of the present disclosure;

[0033] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0034] Figure 6 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure;

[0035] Figure 7 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0036] Figure 8 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0037] Fig. 9 is an enlarged cross-sectional view of a partial area of ​​a display panel according to an embodiment of the present disclosure; and

[0038] Fig.10 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for fully understanding the various aspects and features of the present disclosure for those of ordinary skill in the art may not be described. Unless otherwise noted, in the entire drawings and written description, the same reference numerals represent the same elements, and therefore, their redundant descriptions may not be repeated.

[0040] When a specific embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described successively may be performed at the same time or substantially at the same time, or may be performed in the reverse order of the described order.

[0041] In addition, as will be understood by those skilled in the art, in view of the entire content of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and may be technically interconnected and operated in various suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable manner, unless otherwise stated or implied.

[0042] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and zones may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "under ... ", "under ... ", "under ... ", "above ... " and "on " can be used in this article to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the element described as "under" or "under" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the example terms "under ... " and "under ... " can cover two orientations above and below. The device can be oriented in addition (for example, rotated 90 degrees or at other orientations), and the spatial relative terms used in this article should be interpreted accordingly.

[0043] In the drawings, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the directions indicated by the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular to each other or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0044] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as the second element, component, region, layer or part.

[0045] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to the other layer, region, or element with one or more intervening layers, regions, or elements between the layer, region, or element and the other layer, region, or element. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0046] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "one" and "one (kind / person)" are also intended to include plural forms. It will also be understood that when used in this specification, the terms "comprises, comprising", "includes, including" and "has, have, having" illustrate the existence of stated features, integrals, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integrals, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. For example, the statement "A and / or B" means A, B or A and B. Statements such as "at least one (kind / person) in ... " modify the entire list of elements when after the list of elements and do not modify the individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0047] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, rather than terms of degree, and are intended to account for the inherent variations in measurements or calculations that will be recognized by one of ordinary skill in the art. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. In addition, the term "exemplary" is intended to refer to an example or illustration.

[0048] As used herein, various terms including "component" or "unit" may refer to software components or hardware components that perform specific functions. Hardware components may include, for example, field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Software components may refer to executable code in an addressable storage medium and / or data used by the executable code. Therefore, software components may be, for example, object-oriented software components, class components, and task components, and may include processes, functions, attributes, programs, subroutines, program code segments, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, and / or variables, etc.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their context in the relevant art and / or the meaning in this specification, and should not be interpreted in an idealized or overly formal sense.

[0050] Figure 1 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0051] Reference Figure 1 , the display device DD may include a display panel DP, a panel driver SDC, an EDC and a DDC, a power supply component (e.g., a power supply or an electric power source) PWS, and a timing controller TC. In an embodiment, the display panel DP may be described in more detail in the context of a light-emitting display panel. The light-emitting display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In an embodiment, an organic light-emitting display panel may be described in more detail later as a representative example of a display panel DP. The panel drivers SDC, EDC and DDC may include a scan driver SDC, an emission driver EDC and a data driver DDC.

[0052] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm, where n and m are integers greater than 1. The display panel DP may include a plurality of pixels connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm.

[0053] For example, a pixel PXij (where i is greater than or equal to 1 and less than or equal to n, and j is greater than or equal to 1 and less than or equal to m) located at the i-th horizontal line (e.g., the i-th pixel row) and the j-th vertical line (e.g., the j-th pixel column) can be connected to the i-th first scan line (e.g., write scan line) GWLi, the i-th second scan line (e.g., compensation scan line) GCLi, the i-th third scan line (e.g., first initialization scan line) GILi, the i-th fourth scan line (e.g., second initialization scan line) GBLi, the i-th fifth scan line (e.g., reset scan line) GRLi, the j-th data line DLj and the i-th emission line ESLi.

[0054] The pixel PXij may include at least one light emitting element, a plurality of transistors, and at least one capacitor. The pixel PXij may receive a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (e.g., a reference voltage) VREF, a fourth power supply voltage (e.g., a first initialization voltage) VINT1, a fifth power supply voltage (e.g., a second initialization voltage) VINT2, and a sixth power supply voltage (e.g., a compensation voltage) VCOMP through a power supply component PWS.

[0055] The values ​​(eg, voltage values) of the first power supply voltage VDD and the second power supply voltage VSS may be determined (eg, may be set) so that current flows through the light emitting element to emit light. For example, the first power supply voltage VDD may be higher than the second power supply voltage VSS.

[0056] The third power supply voltage VREF can be used to initialize the gate of the driving transistor included in the pixel PXij. The third power supply voltage VREF can be used to achieve a predetermined grayscale using a difference from the voltage of the data signal. Therefore, the third power supply voltage VREF can have a predetermined voltage within a suitable voltage range of the data signal.

[0057] The fourth power supply voltage VINT1 may be used to initialize a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may have a voltage lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the present disclosure is not limited thereto.

[0058] The fifth power supply voltage VINT2 may be used to initialize the cathode of the light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 may have a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or may have a voltage similar to or the same as the third power supply voltage VREF, but the present disclosure is not limited thereto. The fifth power supply voltage VINT2 may have a voltage similar to or the same as the first power supply voltage VDD.

[0059] When the threshold voltage of the driving transistor is compensated, the sixth power supply voltage VCOMP may supply a predetermined current to the driving transistor.

[0060] exist Figure 1 , the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP are shown as being supplied from the power supply part PWS, but the present disclosure is not limited thereto. For example, the first power supply voltage VDD and the second power supply voltage VSS may be supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied corresponding to the structure of the pixel PXij.

[0061] In the embodiments of the present disclosure, the signal lines connected to the pixels PXij may be designed in various suitable ways corresponding to the circuit structure of the pixels PXij.

[0062] The scan driver SDC may receive a first control signal SCS from the timing controller TC and may supply respective scan signals to the first, second, third, fourth, or fifth scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, or GRL1 to GRLn based on the first control signal SCS.

[0063] Each of the plurality of scan signals may have a voltage by which the transistor supplied with the scan signal may be turned on. For example, the scan signal supplied to the P-type transistor may have a logic low level, and the scan signal supplied to the N-type transistor may have a logic high level. As used herein, the phrase "scan signal is supplied" may be understood as the scan signal being supplied to have a logic level (e.g., a conduction level) for turning on the transistor controlled by the scan signal.

[0064] For ease of explanation, Figure 1 The scan driver SDC is shown as having a single component, but the present disclosure is not limited thereto. According to an embodiment, a plurality of scan drivers may be included to supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, or the fifth scan lines GRL1 to GRLn.

[0065] The emission driver EDC may output an emission control signal to the plurality of emission lines ESL1 to ESLn based on the second control signal ECS. For example, the plurality of emission control signals may be sequentially supplied to the emission lines ESL1 to ESLn.

[0066] According to an embodiment of the present disclosure, the transistors connected to the emission lines ESL1 to ESLn may be composed of N-type transistors. The emission signals supplied to the emission lines ESL1 to ESLn may have a gate cutoff voltage. The transistors configured to receive the emission signals may be cut off when the emission signals are supplied, and may be in a conducting state in other cases.

[0067] The second control signal ECS may include an emission start signal and a clock signal. The emission driver EDC may be implemented with a shift register configured to sequentially shift the pulse type emission start signal using the clock signal to sequentially generate and output emission signals having a pulse type.

[0068] The data driver DDC may receive the third control signal DCS and the image data RGB from the timing controller TC. The data driver DDC may convert the digital image data RGB into analog data signals (eg, data signals). The data driver DDC may supply the data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0069] The third control signal DCS may include a data enable signal for indicating output of a valid data signal, a horizontal start signal, or a data clock signal, etc. For example, the data driver DDC may include a shift register for shifting a data clock signal in synchronization with the horizontal start signal to generate a sampling signal, a latch for latching the image data RGB in response to the sampling signal, a digital-to-analog converter (e.g., a decoder) for converting the latched image data (e.g., digital data) into an analog data signal, and a buffer (e.g., an amplifier) ​​for outputting the data signal to the data lines DL1 to DLm.

[0070] The power supply part PWS may supply the first power supply voltage VDD, the second power supply voltage VSS or the third power supply voltage VREF for driving the pixel PXij to the display panel DP. In addition, the power supply part PWS may supply at least one of the fourth power supply voltage VINT1, the fifth power supply voltage VINT2 and the sixth power supply voltage VCOMP to the display panel DP.

[0071] For example, the power supply component PWS can be connected via the first power line VDL (see, for example, Figure 2A ), the second power line VSL (see, for example, Figure 2A ), a third power line (eg, a reference voltage line) VRL (eg, see Figure 2A ), a fourth power line (eg, a first initialization voltage line) VIL1 (eg, see Figure 2A ), a fifth power line (eg, a second initialization voltage line) VIL2 (eg, see Figure 2A ) and a sixth power line (eg, voltage compensation line) VCL (eg, see Figure 2A ) supplies the first power voltage VDD, the second power voltage VSS, the third power voltage VREF, the fourth power voltage VINT1, the fifth power voltage VINT2 or the sixth power voltage VCOMP to the display panel DP.

[0072] The power supply part PWS may be implemented as a power management integrated circuit, but the present disclosure is not limited thereto.

[0073] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal and a horizontal synchronization signal, etc.), a data enable signal DE or a clock signal, etc. The first control signal SCS may be supplied to the scan driver SDC, the second control signal ECS may be supplied to the emission driver EDC, the third control signal DCS may be supplied to the data driver DDC, and the fourth control signal PCS may be supplied to the power supply part PWS. The timing controller TC may rearrange the input image data IRGB in response to the pixels PXij (e.g., the arrangement of the pixels PXij) in the display panel DP to generate image data RGB (e.g., frame data).

[0074] The scan driver SDC, the emission driver EDC, the data driver DDC, the power supply component PWS and / or the timing controller TC may be directly provided in the display panel DP, or may be provided in a separate driver chip to be connected to the display panel DP. In addition, at least two of the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply component PWS and the timing controller TC may be provided together in one driver chip. For example, the data driver DDC and the timing controller TC may be provided together as one driver chip.

[0075] Although referenced Figure 1 The display device DD according to the embodiment is described, but the present disclosure is not limited thereto. For example, a signal line may be further added or omitted according to the composition of the pixel PXij. In addition, various modifications may be made to the connection relationship between a pixel and a signal line as needed or desired. When any one of the plurality of signal lines is omitted, another signal line may replace the omitted signal line.

[0076] FIG. 2A to FIG. 2C is an equivalent circuit diagram of pixels PXij, PXij-1, and PXij-2 according to one or more embodiments of the present disclosure. FIG. 2A to FIG. 2C Some example equivalent circuit diagrams of pixels PXij, PXij-1, and PXij-2 connected to an i-th first scan line (hereinafter, a write scan line) GWLi and a j-th data line (hereinafter, a data line) DLj are shown.

[0077] like Figure 2A As shown in FIG. 1 , the pixel PXij includes a light emitting element LD and a pixel driver PDC. The light emitting element LD is connected to the first power line VDL and the pixel driver PDC.

[0078] The pixel driver PDC may be connected to a plurality of scan lines GWLi, GCLi, GBLi, GILi, GRLi, a data line DLj, an i-th emission line ESLi, and a plurality of power lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The pixel driver PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a first capacitor C1, and a second capacitor C2. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be, for example, an N-type transistor. However, the present disclosure is not limited thereto, and some of the first transistor T1 to the eighth transistor T8 may be N-type transistors, and the remaining part of the first transistor T1 to the eighth transistor T8 may be P-type transistors. As another example, each of the first transistor T1 to the eighth transistor T8 may be a P-type transistor, but the present disclosure is not limited to any particular embodiment.

[0079] The gate of the first transistor T1 may be connected to the first node N1. The first electrode of the first transistor T1 may be connected to the second node N2, and the second electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL to the second power line VSL via the light emitting element LD in response to the voltage of the first node N1. For example, the first power supply voltage VDD may have a potential higher than that of the second power supply voltage VSS.

[0080] As used herein, the expression “electrically connected between a transistor and a signal line or between transistors” may mean “a source, a drain, and a gate of the transistor have a shape integral with the signal line or are connected through a connecting electrode”.

[0081] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply the data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi. When the write scan signal GW is supplied to the write scan line GWLi, the second transistor T2 may be turned on to connect the data line DLj and the first node N1 to each other.

[0082] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and the second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, the gate of the third transistor T3 may receive the reset scan signal GR through the i-th fifth scan line (hereinafter, the reset scan line) GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to supply the reference voltage VREF to the first node N1.

[0083] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 may be connected to the third node N3, and the second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 through which the first initialization voltage VINT1 is supplied. The fourth transistor T4 may be referred to as a first initialization transistor. The gate of the fourth transistor T4 may receive the first initialization scan signal GI through the i-th third scan line (hereinafter, the first initialization scan line) GILi. When the first initialization scan signal GI is supplied to the first initialization scan line GILi, the fourth transistor T4 may be turned on to supply the first initialization voltage VINT1 to the third node N3.

[0084] The fifth transistor T5 may be connected between the voltage compensation line VCL and the second node N2. The first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP through the voltage compensation line VCL, and the second electrode of the fifth transistor T5 may be connected to the second node N2 to be electrically connected to the first electrode of the first transistor T1. The gate of the fifth transistor T5 may receive the compensation scan signal GC through the i-th second scan line (hereinafter, the compensation scan line) GCLi. When the compensation scan signal GC is supplied to the compensation scan line GCLi, the fifth transistor T5 may be turned on to provide the compensation voltage VCOMP to the second node N2, and during the compensation period, the threshold voltage of the first transistor T1 may be compensated.

[0085] The sixth transistor T6 may be connected between the first electrode of the first transistor T1 and the light emitting element LD. In more detail, the gate of the sixth transistor T6 may receive the emission signal EM through the i-th emission line (hereinafter, the emission line) ESLi. The first electrode of the sixth transistor T6 may be connected to the cathode of the light emitting element LD through the fourth node N4, and the second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1 through the second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. When the emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 may be turned on to electrically connect the light emitting element LD and the first transistor T1 to each other.

[0086] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. The first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the seventh transistor T7 may receive the second power supply voltage VSS through the second power line VSL. The gate of the seventh transistor T7 may be electrically connected to the emission line ESLi. The seventh transistor T7 may be referred to as a second emission control transistor. When the emission signal EM is supplied to the emission line ESLi, the seventh transistor T7 may be turned on to electrically connect the second electrode of the first transistor T1 and the second power line VSL to each other.

[0087] In the embodiment, the sixth transistor T6 and the seventh transistor T7 are shown as being connected to the same emission line ESLi to be turned on by the same emission signal EM, but the present disclosure is not limited thereto. The sixth transistor T6 and the seventh transistor T7 can be turned on independently by different signals. In addition, in the pixel driver PDC according to the embodiment of the present disclosure, any one of the sixth transistor T6 and the seventh transistor T7 can be omitted as needed or desired.

[0088] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. In other words, the eighth transistor T8 may include a gate connected to the i-th fourth scan line (hereinafter, the second initialization scan line) GBLi, a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0089] In an embodiment, some of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be turned on concurrently or substantially simultaneously with each other by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be turned on concurrently or substantially simultaneously with each other by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be turned on / off concurrently or substantially simultaneously with each other by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be provided as the same signal line (for example, provided as a substantially single scan line). Therefore, the initialization of the cathode of the light emitting element LD may be implemented at the same time or substantially at the same time with the threshold voltage compensation of the first transistor T1. However, the present disclosure is not limited thereto.

[0090] In addition, according to an embodiment of the present disclosure, applying the same power supply voltage can result in initialization of the cathode of the light emitting element LD and compensation of the threshold voltage of the first transistor T1. For example, the voltage compensation line VCL and the second initialization voltage line VIL2 can be provided as the same power supply line (for example, provided as a substantially single power supply voltage line). In this case, cathode initialization and compensation of the driving transistor can be implemented with one power supply voltage, and therefore, the design of the pixel driver PDC can be simplified. However, the present disclosure is not limited thereto.

[0091] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store charges corresponding to a voltage difference between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0092] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. In other words, one electrode of the second capacitor C2 may be connected to the second power line VSL to which the second power supply voltage VSS is supplied, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power supply voltage VSS and the third node N3. The second capacitor C2 may be referred to as a holding capacitor. The second capacitor C2 may have a high storage capacitance compared to the storage capacitance of the first capacitor C1. Therefore, the second capacitor C2 may minimize or reduce a voltage change in the third node N3 in response to a voltage change in the first node N1.

[0093] In an embodiment, the light emitting element LD may be connected to the pixel driver PDC via a fourth node N4. The light emitting element LD may include an anode connected to the first power line VDL and a cathode opposite to the anode. In an embodiment, the light emitting element LD may be connected to the pixel driver PDC via a cathode. In other words, in the pixel PXij according to an embodiment of the present disclosure, the connection node at which the light emitting element LD is connected to the pixel driver PDC may be a fourth node N4, and the fourth node N4 may correspond to a connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Therefore, the potential of the fourth node N4 may correspond to or substantially correspond to the cathode potential of the light emitting element LD.

[0094] In more detail, the anode of the light emitting element LD may be connected to the first power line VDL to receive the first power supply voltage VDD as a constant or substantially constant voltage, and the cathode of the light emitting element LD may be connected to the first transistor T1 through the sixth transistor T6. In other words, in an embodiment in which the first transistor T1 to the eighth transistor T8 are N-type transistors, the potential of the third node N3 corresponding to the second electrode (e.g., source) of the first transistor T1 as a driving transistor may not be directly affected by the characteristics of the light emitting element LD. Therefore, even when the light emitting element LD deteriorates, the gate-source voltage (Vgs) of the driving transistor from among the plurality of transistors constituting the pixel driver PDC may be less affected. In other words, the amount of change in the driving current ILD due to the degradation of the light emitting element LD may be reduced, and therefore, the afterimage defect of the display panel due to the increase in the utilization time may be reduced and the lifespan may be improved.

[0095] In another embodiment, if Figure 2B As shown in , the pixel PXij-1 may include a light emitting element LD and a pixel driver PDC-1, the pixel driver PDC-1 includes two transistors T1 and T2 and a first capacitor C1. The pixel driver PDC-1 may be connected to the light emitting element LD, the write scan line GWLi, the data line DLj, the first power line VDL and the second power line VSL. Figure 2B The pixel driver PDC-1 shown in FIG. Figure 2A Corresponding to the pixel driver PDC described above, the third to eighth transistors T3 to T8 and the second capacitor C2 are omitted from the pixel driver PDC.

[0096] Each of the first transistor T1 and the second transistor T2 may be an N-type transistor or a P-type transistor. Figure 2B An example case in which each of the first transistor T1 and the second transistor T2 is an N-type transistor is shown in FIG.

[0097] The first transistor T1 includes a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to the first power line VDL side, and the third node N3 may be a node connected to the second power line VSL side. The first transistor T1 is connected to the light emitting element LD through the second node N2, and is connected to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0098] The second transistor T2 may include a gate configured to receive a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0099] The first capacitor C1 may include an electrode connected to the first node N1 and an electrode connected to the third node N3. The first capacitor C1 may store charges corresponding to a voltage difference between the first node N1 and the third node N3.

[0100] The light emitting element LD may include an anode and a cathode. In an embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode of the light emitting element LD is connected to the pixel driver PDC-1 through the second node N2. In an embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light in response to the amount of current ILD flowing through the first transistor T1 of the pixel driver PDC-1.

[0101] In an embodiment where the first transistor T1 and the second transistor T2 are N-type transistors, the second node N2 at which the light emitting element LD is connected to the pixel driver PDC-1 may correspond to the drain of the first transistor T1. In other words, a change in the gate-source voltage (Vgs) of the first transistor T1 due to the light emitting element LD may be prevented or substantially prevented. In other words, the amount of change in the drive current ILD due to degradation of the light emitting element LD may be reduced, and therefore, afterimage defects of the display panel due to an increase in utilization time may be reduced and the lifespan may be improved.

[0102] In another embodiment, if Figure 2C As shown in FIG, the pixel PXij-2 may include a light emitting element LD and a pixel driver PDC-2 including six transistors T1, T2, T3, T4a, T5a and T6a and two capacitors C1 and C2.

[0103] The pixel driver PDC-2 can be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first emission line (hereinafter, the first emission line) ESL1i, the i-th second emission line (hereinafter, the second emission line) ESL2i, the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL and the initialization voltage line VIL.

[0104] Figure 2C The pixel driver PDC-2 in FIG. 1 may be similar to that in FIG. Figure 2A The pixel driver PDC described herein omits the structure of the fourth transistor T4 and the fifth transistor T5. Figure 2C The area of ​​the pixel driver PDC-2 is smaller than Figure 2A The area of ​​the pixel driver PDC in the image processing unit can be reduced, and thus a high resolution can be achieved (eg, can be easily achieved).

[0105] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a may be an N-type transistor or a P-type transistor. In an embodiment, for convenience, an example case in which the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a are N-type transistors may be described in more detail below.

[0106] The first transistor T1 includes a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to the first power line VDL side, and the third node N3 may be a node connected to the second power line VSL side. The first transistor T1 is connected to the light emitting element LD through the second node N2, and is connected to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0107] The second transistor T2 may include a gate configured to receive a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0108] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through a reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may supply the reference voltage VREF to the first node N1.

[0109] The fourth transistor T4a may be connected between the first electrode of the first transistor T1 and the light emitting element LD. In more detail, the gate of the fourth transistor T4a may receive the first emission signal EM1 through the first emission line ESL1i. The first electrode of the fourth transistor T4a may be connected to the cathode of the light emitting element LD through the fourth node N4, and the second electrode of the fourth transistor T4a may be connected to the first electrode of the first transistor T1 through the second node N2. The fourth transistor T4a may be referred to as a first emission control transistor. When the first emission signal EM1 is supplied to the first emission line ESL1i, the fourth transistor T4a may be turned on to electrically connect the light emitting element LD and the first transistor T1 to each other.

[0110] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. The first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the fifth transistor T5a may receive the second power supply voltage VSS through the second power line VSL. The gate of the fifth transistor T5a may be electrically connected to the second emission line ESL2i. The fifth transistor T5a may be referred to as a second emission control transistor. When the second emission signal EM2 is supplied to the second emission line ESL2i, the fifth transistor T5a may be turned on to electrically connect the second electrode of the first transistor T1 and the second power line VSL to each other.

[0111] In an embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to the first emission line ESL1i and the second emission line ESL2i, respectively, to be turned on by the first emission signal EM1 and the second emission signal EM2. In other words, the fourth transistor T4a and the fifth transistor T5a may be turned on independently. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the fourth transistor T4a and the fifth transistor T5a may be connected to the same emission line and may be controlled by the same emission signal. In addition, in the pixel driver PDC-2 according to an embodiment of the present disclosure, any one of the fourth transistor T4a and the fifth transistor T5a may be omitted as needed or desired.

[0112] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. The sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may supply an initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0113] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store charges corresponding to a voltage difference between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0114] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. In other words, one electrode of the second capacitor C2 may be connected to the second power line VSL to receive the second power supply voltage VSS supplied thereto, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power supply voltage VSS and the third node N3. The second capacitor C2 may be referred to as a holding capacitor.

[0115] The light emitting element LD may include an anode and a cathode. In an embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode of the light emitting element LD is connected to the pixel driver PDC-2 through the fourth node N4. In an embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1 through the fourth transistor T4a. The light emitting element LD may emit light corresponding to the amount of current ILD flowing through the first transistor T1 of the pixel driver PDC-2.

[0116] In an embodiment in which the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a are N-type transistors, the potential of the third node N3 corresponding to the second electrode (e.g., source) of the first transistor T1 as a driving transistor may not be directly affected by the characteristics of the light emitting element LD. Therefore, even when the light emitting element LD deteriorates, the degradation may less affect the gate-source voltage (Vgs) of the driving transistor from among the plurality of transistors constituting the pixel driver PDC-2. In other words, the amount of change in the driving current ILD caused by the degradation of the light emitting element LD may be reduced, and therefore, the afterimage defect of the display panel caused by the increase in the utilization time may be reduced and the lifespan may be improved.

[0117] Figure 2A , Figure 2B and Figure 2C Pixel drivers PDC, PDC-1 and PDC-2 according to some embodiments of the present disclosure are shown, and the display panel according to the embodiments of the present disclosure can be designed in various suitable ways in terms of the number or arrangement relationship of transistors or capacitors, and is therefore not limited to any specific embodiment as long as the pixel driver is connected to the cathode of the light-emitting element LD.

[0118] Figure 3A and Figure 3B is a plan view of a display panel according to one or more embodiments of the present disclosure. Figure 3A and Figure 3B In each of the embodiments, some components are not shown for ease of explanation. Figure 3A and Figure 3B Some embodiments of the present disclosure are described in more detail.

[0119] Reference Figure 3A , the display panel DP according to the embodiment may be divided into a display area DA and a peripheral area (eg, non-display area) NDA. The display area DA includes a plurality of light emitting parts EP.

[0120] The light emitting portion EP may be a corresponding pixel PXij (eg, see Figure 1 ) an area where light is emitted. In more detail, each of the plurality of light emitting portions EP may correspond to a corresponding emission opening OP-PDL (eg, see Figure 5 ).

[0121] The peripheral area NDA may be disposed adjacent to the display area DA. In an embodiment, the peripheral area NDA may surround an edge of the display area DA (e.g., around the periphery of the edge of the display area DA). However, the present disclosure is not limited thereto, and the peripheral area NDA may be disposed on one side of the display area DA (e.g., disposed only on one side of the display area DA), or may be omitted as needed or desired.

[0122] In an embodiment, the scan driver SDC and the data driver DDC may be installed in the display panel DP. In an embodiment, the scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the peripheral area NDA. The scan driver SDC may overlap at least some of the plurality of light emitting portions EP disposed in the display area DA in a plan view. Because the scan driver SDC is disposed in the display area DA, the area of ​​the peripheral area NDA may be reduced compared to the area of ​​the peripheral area of ​​a comparative display panel in which the scan driver is disposed in the peripheral area, and therefore, a display device having a thinner frame may be implemented (e.g., may be easily implemented).

[0123] However, the present disclosure is not limited thereto and is Figure 3A , the scan driver SDC may include two separate parts. The two scan drivers SDC may be spaced apart from each other in the horizontal direction with the center of the display area DA between the two scan drivers SDC. As another example, the scan driver SDC may have more than two parts distinguishable from each other, and the present disclosure is not limited to any particular embodiment.

[0124] Although Figure 3A An example of a display panel DP in which the data driver DDC is disposed in the peripheral area NDA is shown, but the present disclosure is not limited thereto, and the data driver DDC may be disposed in the display area DA. In this case, some of the plurality of light emitting parts EP disposed in the display area DA may overlap with the data driver DDC in a plan view.

[0125] In an embodiment, the data driver DDC may be provided as a driving chip separate from the display panel DP to be connected to the display panel DP. However, the present disclosure is not limited thereto, and the data driver DDC may be provided in the same process as the scan driver SDC to constitute the display panel DP, and the present disclosure is not limited to any specific embodiment.

[0126] Reference Figure 3B , the display panel DP may have a shape in which a length of the display panel DP in the first direction DR1 is longer than a length of the display panel DP in the second direction DR2. As an example, a plurality of pixels PX11 to PXnm may be arranged in n rows and m columns in the display area DA, where n and m are integers greater than 1. In an embodiment, the display panel DP may include a plurality of scan drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 may include a first scan driver SDC1 and a second scan driver SDC2 spaced apart from each other in the first direction DR1.

[0127] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to the others of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines from among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines from among the scan lines GL1 to GLn.

[0128] For ease of explanation, Figure 3B 1 and 2 show pads PD of the data lines DL1 to DLm. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to a data driver DDC (eg, see Figure 3A ).

[0129] According to an embodiment of the present disclosure, some of the plurality of pads PD may be disposed in the peripheral area NDA, at a position where the plurality of pads PD are spaced apart from each other and the display area DA is interposed between the plurality of pads PD. For example, some of the plurality of pads PD may be disposed on the upper side (such as a side adjacent to the first scan line GL1 from among the scan lines GL1 to GLn), and the others of the plurality of pads PD may be disposed on the lower side (such as a side adjacent to the last scan line GLn from among the scan lines GL1 to GLn). In an embodiment, the pads PD connected to the odd-numbered data lines from among the data lines DL1 to DLm may be disposed on the upper side, and the pads PD connected to the even-numbered data lines from among the data lines DL1 to DLm may be disposed on the lower side.

[0130] The display panel DP may include a plurality of upper data drivers connected to the pads PD disposed on the upper side and / or a plurality of lower data drivers connected to the pads PD disposed on the lower side. However, the present disclosure is not limited thereto, and the display panel DP may include one upper data driver connected to the pads PD disposed on the upper side and / or one lower data driver connected to the pads PD disposed on the lower side. The pads PD according to an embodiment of the present disclosure may also be disposed at one side of the display panel DP (for example, disposed at only one side of the display panel DP) to be connected to a single data driver, and the present disclosure is not limited to any particular embodiment.

[0131] In addition, as mentioned above Figure 3A As described, Figure 3B The display panel DP may further include a scan driver and / or a data driver disposed in the display area DA, and thus, some of the plurality of light emitting portions disposed in the display area DA may overlap with the scan driver and / or the data driver in a plan view.

[0132] FIG. 4A to FIG. 4Dis an enlarged plan view of a partial area of ​​a display panel according to one or more embodiments of the present disclosure.

[0133] Figure 4A An example of light emitting units (eg, light emitting unit regions) UT11, UT12, UT21, and UT22 arranged in two rows and two columns is shown. Each of the light emitting units UT11, UT12, UT21, and UT22 may be a region where a plurality of light emitting portions EP1, EP2, and EP3 are disposed. Figure 4A , the light emitting parts EP1, EP2 and EP3 in the first row Rk constitute the light emitting unit UT11 in the first row Rk and the first column and the light emitting unit UT12 in the first row Rk and the second column. The light emitting parts EP1, EP2 and EP3 in the second row Rk+1 constitute the light emitting unit UT21 in the second row Rk+1 and the first column and the light emitting unit UT22 in the second row Rk+1 and the second column.

[0134] The light emitting portions EP1, EP2, and EP3 may respectively correspond to emission openings OP-PDL (eg, see Figure 5 ). In more detail, each of the light emitting parts EP1, EP2, and EP3 may be a region in which light is emitted by a corresponding light emitting element. The light emitting parts EP1, EP2, and EP3 may correspond to a region for constituting a display on the display panel DP (for example, see Figure 1 ) is a unit (eg, a minimum unit) of an image in the image. In more detail, the light emitting portions EP1, EP2, and EP3 may correspond to an area defined by the emission opening OP-PDL, and may correspond to an area defined by a bottom surface of the emission opening OP-PDL.

[0135] The light-emitting parts EP1, EP2 and EP3 may include a first light-emitting part EP1, a second light-emitting part EP2 and a third light-emitting part EP3. The first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3 may emit light of different colors from each other. For example, the first light-emitting part EP1 may emit red light, the second light-emitting part EP2 may emit green light, and the third light-emitting part EP3 may emit blue light, but the present disclosure is not limited thereto, and the color combination of the light emitted from the light-emitting parts EP1, EP2 and EP3 may be variously modified as needed or desired. In some embodiments, at least two of the light-emitting parts EP1, EP2 and EP3 may emit light of the same color as each other. For example, all of the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3 may emit blue light or white light.

[0136] The third light emitting portion EP3 from among the light emitting portions EP1, EP2, and EP3 may emit light emitted by a third light emitting element, and may include two sub-light emitting portions EP31 and EP32 spaced apart from each other in the second direction DR2. However, the present disclosure is not limited thereto, and the third light emitting portion EP3 may be provided with a pattern of an integral shape similar to the patterns of the first light emitting portion EP1 and the second light emitting portion EP2. As another example, at least one of the first light emitting portion EP1 and the second light emitting portion EP2 may also include sub-light emitting portions spaced apart from each other, and the present disclosure is not limited to any particular embodiment.

[0137] The light-emitting portion in the first row Rk may include the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 constituting the light-emitting unit UT11 in the first row Rk and the first column, and the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 (for example, the third light-emitting portion EP3a) constituting the light-emitting unit UT12 in the first row Rk and the second column. The light-emitting portion in the second row Rk+1 may include the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 (for example, the third light-emitting portion EP3a) constituting the light-emitting unit UT21 in the second row Rk+1 and the first column, and the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 constituting the light-emitting unit UT22 in the second row Rk+1 and the second column.

[0138] In an embodiment of the present disclosure, the light-emitting portion of the light-emitting unit UT11 configured in the first row Rk and the first column may have the same or substantially the same shape as the light-emitting portion of the light-emitting unit UT22 configured in the second row Rk+1 and the second column. In addition, the light-emitting portion of the light-emitting unit UT12 configured in the first row Rk and the second column may have the same or substantially the same shape as the light-emitting portion of the light-emitting unit UT21 configured in the second row Rk+1 and the first column. The light-emitting portion of the light-emitting unit UT11 configured in the first row Rk and the first column may have a different shape from the light-emitting portion of the light-emitting unit UT12 configured in the first row Rk and the second column. For example, a portion of the light-emitting portion in the first row Rk may have a symmetrical shape relative to the light-emitting portion in the second row Rk+1.

[0139] In an embodiment of the present disclosure, the third light emitting portion EP3a of the light emitting unit UT21 in the second row Rk+1 and the first column and the third light emitting portion EP3 of the light emitting unit UT11 in the first row Rk and the first column may have a linearly symmetrical shape and arrangement form with respect to an axis parallel to the first direction DR1. The third light emitting portion EP3a of the light emitting unit UT12 in the first row Rk and the second column and the third light emitting portion EP3 of the light emitting unit UT22 in the second row Rk+1 and the second column may have a linearly symmetrical shape and arrangement form with respect to an axis parallel to the first direction DR1. However, the present disclosure is not limited thereto.

[0140] Figure 4B The light emitting parts are arranged in a row. Figure 4B A plurality of second electrodes EL2_1 , EL2_2 , and EL2_3 , a plurality of pixel drivers PDC1 , PDC2 , and PDC3 , first, second, and third connection electrodes CNE1 , CNE2 , and CNE3 , and a spacer SPR are shown. Figure 4C A spacer SPR, a plurality of light emitting parts EP1 , EP2 , and EP3 disposed in a region divided by the spacer SPR, and a plurality of connection electrodes CNE1 , CNE2 , and CNE3 are shown from among a plurality of components of the display panel DP.

[0141] Reference Figure 4B and Figure 4C , the second electrodes EL2_1, EL2_2 and EL2_3 may be separated from each other by a separator SPR and may be electrically disconnected from each other. In an embodiment, one light emitting unit UT11 may include three light emitting portions EP1, EP2 and EP3. Therefore, the light emitting unit UT11 may include three second electrodes (hereinafter referred to as a first cathode, a second cathode and a third cathode) EL2_1, EL2_2 and EL2_3, three pixel drivers PDC1, PDC2 and PDC3, and three connection electrodes CNE1, CNE2 and CNE3. However, the present disclosure is not limited thereto, and the number and arrangement of the light emitting portions included in the light emitting unit UT11 may be variously modified as needed or desired.

[0142] The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be electrically connected to the light emitting elements LD1, LD2, and LD3 including the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3, respectively. As used herein, the term "connection" may include a case where they are directly physically connected to each other through contact as well as a case where they are electrically connected to each other.

[0143] In addition, if Figure 4BAs shown in FIG. 1 , a plurality of regions respectively defining a first pixel driver PDC1, a second pixel driver PDC2, and a third pixel driver PDC3 in a plan view may correspond to a pixel driver (pixel circuit) PDC (for example, see FIG. 1 ) constituting a light emitting element for driving a pixel. Figure 2A ) is a unit in which transistors and capacitors are repeatedly arranged.

[0144] The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be sequentially arranged along the first direction DR1. However, the arrangement positions of the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be designed regardless of the positions and shapes of the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3.

[0145] For example, the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be arranged in an area divided and defined by the partition SPR. The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be arranged at a position different from the position where the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are set, or may have an area and shape different from the area and shape of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3. As another example, the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be arranged to overlap with the positions where the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 exist, respectively, and may also have an area / area similar to the area / area divided and defined by the partition SPR (such as the area / area of ​​the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 as an example).

[0146] In an embodiment, each of the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 is shown to have a rectangular shape, and each of the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 is shown to be arranged to have an area smaller than that of the first pixel driver PDC1 to the third pixel driver PDC3 and a type different from the types of the first pixel driver PDC1 to the third pixel driver PDC3. The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be provided to overlap with the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3, respectively, and may have an irregular shape.

[0147] Therefore, if Figure 4BAs shown in , the first pixel driver PDC1 can be arranged to overlap with the first light-emitting portion EP1, the second light-emitting portion EP2 and another adjacent light-emitting portion. The second pixel driver PDC2 can be arranged to overlap with the first light-emitting portion EP1, the second light-emitting portion EP2 and the third cathode EL2_3. The third pixel driver PDC3 can be arranged to overlap with the third light-emitting portion EP3. However, the present disclosure is not limited thereto, and the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 can have various suitable shapes and arrangements, regardless of the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3.

[0148] The light emitting unit UT11 may include a first connection electrode CNE1, a second connection electrode CNE2, and a third connection electrode CNE3. The first connection electrode CNE1 may electrically connect the first light emitting element LD1 constituting (e.g., defining) the first light emitting portion EP1 and the first pixel driver PDC1 to each other. The second connection electrode CNE2 may connect the second light emitting element LD2 constituting (e.g., defining) the second light emitting portion EP2 and the second pixel driver PDC2 to each other. The third connection electrode CNE3 may connect the third light emitting element LD3 constituting (e.g., defining) the third light emitting portion EP3 and the third pixel driver PDC3 to each other. Each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may include a first electrode EL1 (e.g., see Figure 5 ), an intermediate layer IML (for example, see Figure 5 ) and a second electrode EL2 disposed on the intermediate layer IML (see, for example, Figure 5 ).

[0149] In more detail, the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may be connected to the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 in one-to-one correspondence with the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3. For example, the first connection electrode CNE1 may be electrically connected to the first pixel driver PDC1 and the first cathode EL2_1, the second connection electrode CNE2 may be electrically connected to the second pixel driver PDC2 and the second cathode EL2_2, and the third connection electrode CNE3 may be electrically connected to the third pixel driver PDC3 and the third cathode EL2_3.

[0150] The first link electrode CNE1, the second link electrode CNE2, and the third link electrode CNE3 may be disposed on a pixel defining layer PDL (eg, see Figure 5). The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may have a ring shape surrounding the corresponding first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 (for example, around the periphery of the corresponding first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3). In the embodiment of the present disclosure, each of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 is shown as having a ring shape formed by a closed line, but the present disclosure is not limited thereto. For example, at least a portion of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may have an open loop shape with a portion thereof disconnected.

[0151] Since the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 have a ring shape, the degree of freedom at the positions where the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 are respectively connected to the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 can be improved. For example, the first connection electrode CNE1 may be connected to the first pixel driver PDC1 through the first connection portion CE1, the second connection electrode CNE2 may be connected to the second pixel driver PDC2 through the second connection portion CE2, and the third connection electrode CNE3 may be connected to the third pixel driver PDC3 through the connection line CN3. However, there may be no connection line additionally connected to the first connection electrode CNE1 and the second connection electrode CNE2.

[0152] One connection line CN3 may electrically connect the third pixel driver PDC3 and the third light emitting element LD3 constituting the third light emitting portion EP3 to each other. In more detail, the connection line CN3 may correspond to the light emitting element LD (eg, see FIG. 2A to FIG. 2C ) is connected to a pixel driver (e.g., Figure 2A The pixel driver PDC in Figure 2B The pixel driver PDC-1 or Figure 2C The node where the pixel driver PDC-2 in the Figure 2A The fourth node N4 in Figure 2B The second node N2 in Figure 2C The fourth node N4 in the.

[0153] The connection line CN3 may include a third connection portion CE3 and a driving connection portion CD3. The third connection portion CE3 may be provided to one side of the connection line CN3, and the driving connection portion CD3 may be provided to the other side (eg, opposite side) of the connection line CN3.

[0154] The driving connection portion CD3 may be a portion of the connection line CN3 connected to the third pixel driver PDC3. In an embodiment, the driving connection portion CD3 may be connected to one electrode of a transistor constituting the third pixel driver PDC3. In more detail, the driving connection portion CD3 may be connected to Figure 2A The drain of the sixth transistor T6 or Figure 2C The drain of the fourth transistor T4a in the third pixel driver PDC3. Therefore, the position of the driving connection part CD3 may correspond to the position of the transistor physically connected to the connection line CN3 in the corresponding third pixel driver PDC3. The third connection part CE3 may be a portion of the connection line CN3 connected to the third light emitting element LD3. In an embodiment, the third connection part CE3 may be connected to the third connection electrode CNE3.

[0155] The first connection electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light emitting portion EP1 (e.g., around the periphery of at least a portion of the first light emitting portion EP1) and a second edge EG12 surrounding the first edge EG11 (e.g., around the periphery of the first edge EG11). The second connection electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light emitting portion EP2 (e.g., around the periphery of at least a portion of the second light emitting portion EP2) and a second edge EG22 surrounding the first edge EG21 (e.g., around the periphery of the first edge EG21). The third connection electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light emitting portion EP3 (e.g., around the periphery of at least a portion of the third light emitting portion EP3) and a second edge EG32 surrounding the first edge EG31 (e.g., around the periphery of the first edge EG31).

[0156] The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may be spaced apart from each other. For example, the gaps GP1, GP2, and GP3 between a plurality of adjacent connection electrodes from among the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may overlap with the separator SPR. For example, the first edges EG11, EG21, and EG31 of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may not be covered by the separator SPR, and the second edges EG12, EG22, and EG32 of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may overlap with the separator SPR. As another example, the second edges EG12, EG22, and EG32 of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may be covered by the separator SPR.

[0157] In the embodiment of the present disclosure, the first connection portion CE1, the second connection portion CE2 and the third connection portion CE3 may be disposed at a position that does not overlap with the light emitting portions EP1, EP2 and EP3 in a plan view. Figure 5 ) and a through hole OP-P spaced apart from the emission opening OP-PDL may be defined in the pixel defining layer PDL.

[0158] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be arranged to correspond to the first through hole OP-P1, the second through hole OP-P2, and the third through hole OP-P3, respectively. The emission opening OP-PDL may include a first emission opening OP-PDL1, a second emission opening OP-PDL2, and a third emission opening OP-PDL3. The first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may be defined to correspond to the first emission opening OP-PDL1, the second emission opening OP-PDL2, and the third emission opening OP-PDL3, respectively. Therefore, the first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be spaced apart from the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3.

[0159] The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may be disposed on the pixel defining layer PDL (eg, see Figure 5 In a plan view, the first connection electrode CNE1 may surround the first emission opening OP-PDL1 (e.g., around the periphery of the first emission opening OP-PDL1), the second connection electrode CNE2 may surround the second emission opening OP-PDL2 (e.g., around the periphery of the second emission opening OP-PDL2), and the third connection electrode CNE3 may surround the third emission opening OP-PDL3 (e.g., around the periphery of the third emission opening OP-PDL3).

[0160] According to an embodiment of the present disclosure, the connection line CN3 is connected to the transistor TR1 of the third pixel driver PDC3 (eg, see Fig.10 ) The driving connection part CD3 where the connection is located can be defined in a plan view at a position that does not overlap with the third connection part CE3, and can be arranged in a plan view at a position that overlaps with the third light emitting part EP3. For example, the connection line CN3 can correspond to the reference line CN3 described later. Fig.10 The connection line CN-ad described in more detail, the driving connection CD3 may correspond to Fig.10 The third connection portion CE3 may correspond to the portion in contact with the intermediate connection electrode CN. Fig.10Since the third cathode EL2_3 is connected to the third pixel driver PDC3 through the connection line CN3, the restriction on the position or shape of the third light emitting portion EP3 can be reduced to improve the freedom of design thereof.

[0161] The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively. For example, the bottom surfaces of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to the top surfaces of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively (e.g., may contact the top surfaces of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3). Therefore, the contact reliability (e.g., connection stability) between the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 and the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may be further improved.

[0162] In addition, the connection area in which the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are respectively connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may surround at least a portion of the first emission opening OP-PDL1, the second emission opening OP-PDL2, and the third emission opening OP-PDL3, respectively (for example, around the periphery of at least a portion of the first emission opening OP-PDL1, the second emission opening OP-PDL2, and the third emission opening OP-PDL3). The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be respectively connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 in an area adjacent to the separator SPR, and each of the plurality of connection areas may be defined adjacent to the separator SPR. For example, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively, not at a specific point but in a relatively wide area (such as across an area having a shape similar to that of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, for example). Therefore, the area of ​​the connection region can be increased to achieve a more stable connection.

[0163] Figure 4D The separator SPR, the light emitting parts EP1 , EP2 , and EP3 , and the first electrode EL1 are shown.

[0164] Reference Figure 4D, the light emitting element LD according to the embodiment of the present disclosure (for example, see Figure 5 ) may be commonly provided to the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3. In other words, the anode EL1 may be provided as a layer that is completely or substantially completely integrated with the display area DA, and therefore, the anode layer of the anode EL1 may be arranged to overlap with the partition SPR. As another example, the anode EL1 of each of the plurality of light emitting elements LD may be provided with a conductive pattern spaced apart from other anodes, and may be electrically connected to the other anodes through another conductive layer. In this case, the anode EL1 does not overlap with the partition SPR.

[0165] As described above, the anode EL1 may be applied with the first power supply voltage VDD (eg, see Figure 2A ), and all of the plurality of light emitting parts EP1, EP2, and EP3 may be applied with a common voltage. The anode EL1 may also be connected in the peripheral area NDA to a first power line VDL (eg, see Figure 2A ) or may be connected to the first power line VDL in the display area DA, and the present disclosure is not limited to any particular embodiment.

[0166] According to an embodiment, a plurality of openings may be defined in the anode EL1, and the openings may penetrate the anode layer of the anode EL1. The openings in the anode layer of the anode EL1 may be disposed at a position adjacent to the light emitting portion EP (eg, see Figure 3A ) at a non-overlapping position and may be defined in a plan view at a position overlapping with the partition SPR. The opening may facilitate the generation of an organic layer that may be disposed below the anode EL1 (such as from a sixth insulating layer 60 (eg, see Figure 5 ) produces the emission of gas such as (for example). Therefore, in the process of manufacturing the display panel, the gas from the organic layer disposed under the light-emitting element can be fully discharged, and after manufacturing, the gas discharged from the organic layer can be reduced to reduce the rate of degradation of the light-emitting element.

[0167] Figure 5 is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 5 Shows the corresponding Figure 4A A cross section of the portion along line II'.

[0168] Reference Figure 5The display panel DP according to the embodiment may include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL. However, the present disclosure is not limited thereto, and in the embodiment, the display panel DP may not include the sensing layer ISL.

[0169] The driving element layer DDL may include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, and 60 to constitute the pixel drivers PDC1 and PDC2. For ease of explanation, Figure 5 An example cross section from any one region among a plurality of regions in which one light emitting section is provided is shown.

[0170] The base layer BS may be a member for providing a base surface on which the pixel drivers PDC1 and PDC2 are disposed. The base layer BS may be a rigid base or a flexible base that is bendable, foldable, or rollable, etc. The base layer BS may be a glass base, a metal base, or a polymer base, etc. However, the present disclosure is not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0171] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiO x ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a matrix barrier layer.

[0172] The first polymer resin layer or the second polymer resin layer may include a polyimide resin. In addition, the first polymer resin layer or the second polymer resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin and perylene resin. As used herein, the expression "~~" resin means a functional group including "~~".

[0173] The insulating layers 10, 20, 30, 40, 50 and 60, the conductive layers or the semiconductor layers disposed on the base layer BS may be provided by a suitable method such as coating or deposition, etc. Then, through a plurality of photolithography processes, the insulating layers 10, 20, 30, 40, 50 and 60, the semiconductor layers and the conductive layers may be selectively patterned to provide holes in the insulating layers 10, 20, 30, 40, 50 and 60 and / or to provide semiconductor patterns, conductive patterns or signal lines, etc. in the insulating layers 10, 20, 30, 40, 50 and 60.

[0174] The driving element layer DDL may include first, second, third, fourth, fifth, and sixth insulating layers 10 , 20 , 30 , 40 , 50 , and 60 and pixel drivers PDC1 and PDC2 sequentially stacked on the base layer BS. Figure 5 Shows Figure 4A and Figure 4B 1 and 2. The first pixel driver PDC1 is shown as including one transistor TR1 and two capacitors C1 and C2, and the second pixel driver PDC2 is shown as including one transistor TR2. The transistor TR2 may be one of a plurality of transistors included in the second pixel driver PDC2.

[0175] The transistor TR1 of the first pixel driver PDC1 may correspond to a transistor connected to the light emitting element LD through the intermediate connection electrode CN and the connection electrode CNE, such as to a node corresponding to the cathode of the light emitting element LD (eg, Figure 2A The fourth node N4 in Figure 2B The second node N2 in Figure 2C For example, transistor TR1 may correspond to Figure 2A The sixth transistor T6 in Figure 2B The first transistor T1 or Figure 2C Hereinafter, the transistor TR1 of the first pixel driver PDC1 may be referred to as the connecting transistor TR1. The light emitting element LD electrically connected to the first pixel driver PDC1 may be the first light emitting element LD1 (eg, see Figure 4C ).

[0176] The second pixel driver PDC2 may be electrically connected to a second light emitting element LD2 adjacent to the first light emitting element LD1 (eg, see Figure 4C For example, the second pixel driver PDC2 may be connected via the middle connection electrode and the second connection electrode CNE2 (see, for example, Figure 4C ) is electrically connected to the second light emitting element LD2.

[0177] The other transistors constituting the pixel driver PDC1 or PDC2 may have the same Figure 5 The structure of the transistor TR1 or TR2 in the pixel driver PDC1 or PDC2 may be the same or substantially the same. However, the present disclosure is not limited thereto, and other transistors constituting the pixel driver PDC1 or PDC2 may have the same structure as the transistor TR1 or TR2 in the pixel driver PDC1 or PDC2. Figure 5 The structure of the transistor TR1 or TR2 may vary in structure and is not limited to any particular embodiment.

[0178] The first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may include an inorganic material and / or an organic material and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be formed on the substrate BS. Figure 5 , is shown as a single silicon oxide layer. The insulating layer, which will be described in more detail later, may include an inorganic layer and / or an organic layer, and have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the present disclosure is not limited thereto.

[0179] The first insulating layer 10 may cover the bottom conductive layer BCL1 or BCL2. The display panel DP may further include a bottom conductive layer BCL1 or BCL2 disposed to overlap the transistor TR1 or TR2. The bottom conductive layer BCL1 or BCL2 may prevent a potential caused by polarization of the base layer BS from affecting the transistor TR1 or TR2. In addition, the bottom conductive layer BCL1 or BCL2 may block light entering the transistor TR1 or TR2 from below. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the bottom conductive layer BCL1 or BCL2 and the base layer BS.

[0180] The bottom conductive layer BCL1 or BCL2 may include a reflective metal. For example, the bottom conductive layer BCL1 or BCL2 may include titanium (Ti), molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), or copper (Cu).

[0181] The bottom conductive layer BCL1 or BCL2 may include a first bottom conductive layer BCL1 or a second bottom conductive layer BCL2. In an embodiment, the first bottom conductive layer BCL1 may be connected to the first source region SR1 connected to the transistor TR1 through a first source electrode pattern S1 (e.g., a 1-1 pattern S1). In this case, the first bottom conductive layer BCL1 may be synchronized with the first source region SR1 of the transistor TR1. The second bottom conductive layer BCL2 may be connected to the second source region SR2 connected to the transistor TR2 through a second source electrode pattern S2 (e.g., a 1-2 pattern S2). In this case, the second bottom conductive layer BCL2 may be synchronized with the second source region SR2 of the transistor TR2.

[0182] However, the present disclosure is not limited thereto, and the bottom conductive layer BCL1 or BCL2 may be connected and synchronized with the first gate electrode GE1 or the second gate electrode GE2 of the transistor TR1 or TR2. As another example, the bottom conductive layer BCL1 or BCL2 may be connected to another electrode to be independently applied with an electrostatic voltage or a pulse signal. As another example, the bottom conductive layer BCL1 or BCL2 may be provided to be isolated from another conductive pattern. The bottom conductive layer BCL1 or BCL2 according to the embodiment may be provided in various suitable forms and is not limited to any particular embodiment.

[0183] The transistor TR1 of the first pixel driver PDC1 and the transistor TR2 of the second pixel driver PDC2 may be disposed on the first insulating layer 10. The transistor TR1 of the first pixel driver PDC1 may include a first semiconductor pattern SP1 and a first gate electrode GE1. The transistor TR2 of the second pixel driver PDC2 may include a second semiconductor pattern SP2 and a second gate electrode GE2. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be disposed on the first insulating layer 10. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include an oxide semiconductor. For example, the oxide semiconductor may include an indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) or the like. However, the present disclosure is not limited thereto, and the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include amorphous silicon, low temperature polysilicon, or polycrystalline silicon.

[0184] Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include a source region, a drain region, and a channel region divided according to the level of their conductivity. For example, the first semiconductor pattern SP1 may include a first source region SR1, a first drain region DR_1, and a first channel region CR1. The first source region SR1 and the first drain region DR_1 may be spaced apart from each other and the first channel region CR1 is between the first source region SR1 and the first drain region DR_1. The first channel region CR1 may overlap with the first gate electrode GE1 in a plan view. The second semiconductor pattern SP2 may include a second source region SR2, a second drain region, and a second channel region CR2. The second source region SR2 and the second drain region may be spaced apart from each other and the second channel region CR2 is between the second source region SR2 and the second drain region. The second channel region CR2 may overlap with the second gate electrode GE2 in a plan view. Corresponding to Figure 5 The line II' of the cross-sectional view of FIG. 1 does not pass through the second drain region of the second semiconductor pattern SP2, and therefore, the second drain region is Figure 5 Not shown.

[0185] When the semiconductor pattern SP1 or SP2 is an oxide semiconductor, each of the first source region SR1 or the second source region SR2 and the first drain region DR_1 or the second drain region may be a reduction region. Therefore, the first source region SR1 or the second source region SR2 and the first drain region DR_1 or the second drain region may have a relatively high content ratio of the reduction metal. As another example, when the semiconductor pattern SP1 or SP2 is polycrystalline silicon, each of the first source region SR1 or the second source region SR2 and the first drain region DR_1 or the second drain region may be doped at a higher concentration.

[0186] The first source region SR1 or the second source region SR2 and the first drain region DR_1 or the second drain region may have a conductivity relatively higher than that of the channel region CR1 or CR2. The first source region SR1 or the second source region SR2 may correspond to a source electrode of the transistor TR1 or TR2, and the first drain region DR_1 or the second drain region may correspond to a drain electrode of the transistor TR1 or TR2. Figure 5 As shown in , a separate source electrode pattern S1 or S2 and a drain electrode pattern D1 or D2 may be further included to be connected to the first source region SR1 or the second source region SR2 and the first drain region DR_1 or the second drain region, respectively. In more detail, the separate source electrode pattern S1 or S2 and the drain electrode pattern D1 or D2 may be connected to the pixel driver (for example, see Figure 2A The pixel driver PDC in Figure 2B The pixel driver PDC-1 or Figure 2C A corresponding one of the multiple lines of the pixel driver PDC-2) in the pixel driver is provided integrally, and is not limited to any particular embodiment.

[0187] The second insulating layer 20 may overlap with a plurality of pixels in common and may cover the semiconductor pattern SP1 or SP2. The second insulating layer 20 may include an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0188] The gate electrodes GE1 and GE2 may be disposed on the second insulating layer 20. The first gate electrode GE1 may correspond to the gate of the transistor TR1 of the first pixel driver PDC1, and the second gate electrode GE2 may correspond to the gate of the transistor TR2 of the second pixel driver PDC2. Each of the gate electrodes GE1 and GE2 may be disposed above the semiconductor patterns SP1 and SP2. However, the present disclosure is not limited thereto, and the gate electrodes GE1 and GE2 may be disposed under the semiconductor patterns SP1 and SP2, respectively, and are not limited to any particular embodiment.

[0189] Each of the gate electrodes GE1 and GE2 may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or suitable alloys thereof, but the present disclosure is not particularly limited thereto.

[0190] The third insulating layer 30 may be disposed on the gate electrodes GE1 and GE2. The third insulating layer 30 may include an inorganic layer and / or an organic layer and have a single layer structure or a multilayer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0191] A first capacitor electrode CPE1 and a second capacitor electrode CPE2 from among a plurality of conductive patterns (e.g., a first source electrode pattern S1, a second source electrode pattern S2, a first drain electrode pattern D1, a second drain electrode pattern D2, a first capacitor electrode CPE1, a second capacitor electrode CPE2, and a third capacitor electrode CPE3) provide a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart from each other with a first insulating layer 10 and a second insulating layer 20 interposed therebetween.

[0192] In an embodiment of the present disclosure, the first capacitor electrode CPE1 and the first bottom conductive layer BCL1 may have an integral shape. In addition, the second capacitor electrode CPE2 may have an integral shape connected to the first gate electrode GE1, and the capacitor electrode CPE may have an integral shape connected to the second gate electrode GE2. However, the present disclosure is not limited thereto. For example, the first capacitor electrode CPE1 and the first bottom conductive layer BCL1 may be disposed at the same layer (e.g., in the middle or on) as each other, and may be spaced apart from each other. The second capacitor electrode CPE2 and the first gate electrode GE1 may be disposed at the same layer (e.g., in the middle or on) as each other, and may be spaced apart from each other. The capacitor electrode CPE and the second gate electrode GE2 may be disposed at the same layer (e.g., in the middle or on) as each other, and may be spaced apart from each other.

[0193] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2 with the third insulating layer 30 interposed therebetween. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 may provide a second capacitor C2.

[0194] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may include an inorganic material and / or an organic material and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0195] On the fourth insulating layer 40 , a first source electrode pattern S1 and a first drain electrode pattern D1 connected to the first semiconductor pattern SP1 , and a second source electrode pattern S2 and a second drain electrode pattern D2 connected to the second semiconductor pattern SP2 may be disposed.

[0196] The first source electrode pattern S1 may be connected to the first source region SR1 of the connection transistor TR1 through the first contact hole CNT1, and the first source electrode pattern S1 and the first source region SR1 of the first semiconductor pattern SP1 may function as the source of the connection transistor TR1. The first drain electrode pattern D1 may be connected to the first drain region DR_1 of the connection transistor TR1 through the second contact hole CNT2, and the first drain electrode pattern D1 and the first drain region DR_1 of the first semiconductor pattern SP1 may function as the drain of the connection transistor TR1.

[0197] The second source electrode pattern S2 may be connected to the second bottom conductive layer BCL2 of the second pixel driver PDC2 and the second source region SR2 of the transistor TR2 through a contact hole. The second source electrode pattern S2 and the second source region SR2 of the second semiconductor pattern SP2 may serve as a source of the transistor TR2. The second drain electrode pattern D2 may be connected to the second gate electrode GE2 through a contact hole, and the second gate electrode GE2 may be connected to the second drain region of the second semiconductor pattern SP2. The second drain electrode pattern D2 may be connected to the second drain region of the transistor TR2, and the second drain electrode pattern D2 and the second drain region may serve as a drain of the transistor TR2.

[0198] A fifth insulating layer 50 may be disposed on the first source electrode pattern S1 , the first drain electrode pattern D1 , the second source electrode pattern S2 , and the second drain electrode pattern D2 .

[0199] The intermediate connection electrode CN may be disposed on the fifth insulating layer 50. The intermediate connection electrode CN may electrically connect the first pixel driver PDC1 and the connection electrode CNE to each other. The intermediate connection electrode CN may electrically connect the light emitting element LD and the connection transistor TR1 of the first pixel driver PDC1 to each other. The intermediate connection electrode CN may be a connection node connecting the first pixel driver PDC1 and the light emitting element LD to each other. The intermediate connection electrode CN may correspond to the fourth node N4 (for example, see Figure 2A ), the second node N2 (for example, see Figure 2B ) or the fourth node N4 (see, for example, Figure 2C ).

[0200] The sixth insulating layer 60 may be disposed on the intermediate connection electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover at least a portion of the intermediate connection electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or a general polymer such as polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer such as polyimide, an aryl ether polymer, an amide polymer, a fluorine-containing polymer, a paraxylene polymer, a vinyl alcohol polymer, or a suitable blend thereof.

[0201] A through hole OP-60 exposing at least a portion of the intermediate connection electrode CN may be provided in the sixth insulating layer 60. The intermediate connection electrode CN may be connected to the connection electrode CNE through a portion exposed from the sixth insulating layer 60, and may be electrically connected to the light emitting element LD. The intermediate connection electrode CN may electrically connect the connection transistor TR1 and the light emitting element LD to each other together with the connection electrode CNE. In the display panel DP according to an embodiment of the present disclosure, the sixth insulating layer 60 may be omitted or provided in plural as needed or desired, and therefore, is not limited to any specific embodiment. When the sixth insulating layer 60 is omitted, the intermediate connection electrode CN may also be omitted.

[0202] The intermediate connection electrode CN may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along a third direction DR3. The second layer L2 may include a material different from that of the first layer L1. In addition, the second layer L2 may include a material different from that of the third layer L3. The second layer L2 may have a thickness relatively thicker than that of the first layer L1. In addition, the second layer L2 may have a thickness relatively thicker than that of the third layer L3. The second layer L2 may include a suitable material having high electrical conductivity. In an embodiment, the second layer L2 may include aluminum (Al).

[0203] The light emitting element layer LDL may be disposed on the driving element layer DDL. The light emitting element layer LDL may include a pixel defining layer PDL, a light emitting element LD, and a spacer SPR.

[0204] The pixel defining layer PDL may be an organic layer. For example, the pixel defining layer PDL may include benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), PMMA or a general polymer such as PS, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer such as polyimide, an aromatic ether polymer, an amide polymer, a fluorine-containing polymer, a paraxylene polymer, a vinyl alcohol polymer, or a suitable blend thereof.

[0205] In an embodiment, the pixel defining layer PDL may have a light absorbing property and, for example, may have a black color. In other words, the pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide of a metal. The pixel defining layer PDL may correspond to a light blocking pattern having a light blocking property.

[0206] An opening (hereinafter, emission opening) OP-PDL exposing at least a portion of the first electrode EL1, which will be described in more detail later, may be defined in the pixel defining layer PDL. The emission opening OP-PDL may be provided in plurality to be respectively arranged corresponding to a plurality of light emitting elements. The emission opening OP-PDL may be a region overlapping all components of the light emitting element LD and where light emitted from the light emitting element LD is emitted or substantially emitted. Thus, the first light emitting portion EP1 (for example, see Figure 4A ) may correspond to or substantially correspond to the shape of the emission opening OP-PDL in a plan view.

[0207] The connection electrode CNE may be disposed on the pixel defining layer PDL. The connection electrode CNE may connect the pixel driver PDC (eg, Figure 2A ) and the light emitting element LD are electrically connected to each other. The pixel driver PDC may be electrically connected to the light emitting element LD via the intermediate connection electrode CN and the connection electrode CNE. The connection electrode CNE may correspond to Figure 4A The first connection electrode CNE1 in the embodiment. The second connection electrode CNE2 (for example, see Figure 4A ) and the third connection electrode CNE3 (see, for example, Figure 4A ) may also have a structure similar to or the same as that of the connecting electrode CNE.

[0208] The connection electrode CNE may include a first edge EG1c adjacent to (eg, facing) the emission opening OP-PDL and a second edge EG2c surrounding (eg, around the periphery of) the first edge EG1c. The second electrode EL2 of the light emitting element LD may contact the connection electrode CNE in a region adjacent to the second edge EG2c.

[0209] The connection electrode CNE may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) etc. However, the material of the connection electrode CNE is not limited thereto.

[0210] A through hole OP-P spaced apart from the emission opening OP-PDL may be defined in the pixel defining layer PDL. The emission opening OP-PDL may be provided in plurality, and each of the plurality of emission openings OP-PDL may correspond to one of the plurality of light emitting elements LD. The size of the through hole OP-P defined in the pixel defining layer PDL may be greater than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connection electrode CNE may be disposed in the through hole OP-P and the through hole OP-60, and may be connected to the intermediate connection electrode CN.

[0211] The light emitting element LD may include a first electrode EL1 , an intermediate layer IML, and a second electrode EL2 .

[0212] The first electrode EL1 may be a semi-transmissive electrode, a transmissive electrode or a reflective electrode. According to an embodiment of the present disclosure, the first electrode EL1 may include a reflective layer and a transparent electrode layer or a semi-transparent electrode layer provided on the reflective layer, wherein the reflective layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or suitable compounds thereof, etc. (for example, composed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or suitable compounds thereof, etc.). The transparent electrode layer or the semi-transparent electrode layer may include a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may include a stacked structure of ITO / Ag / ITO.

[0213] In this embodiment, the first electrode EL1 may be an anode of the light emitting element LD. In other words, the first electrode EL1 may be connected to the first power line VDL (eg, see Figure 2A ) is connected, and may be applied with a first power supply voltage VDD. The first electrode EL1 may be connected in the display area DA (eg, see Figure 3A or Figure 3B ) is connected to the first power line VDL, or is connected to the first power line VDL in the peripheral area NDA. In the latter case, the first power line VDL may be provided in the peripheral area NDA, and the first electrode EL1 may have a shape extending to the peripheral area NDA.

[0214] exist Figure 5 In the cross-sectional view in FIG. 1 , the first electrode EL1 is shown to overlap with the emission opening OP-PDL and not overlap with the partition SPR, but as shown in FIG. Figure 4D As shown in , the first electrode EL1 of the light emitting element may have an integral shape, and may have a grid shape or a lattice shape in which an opening is defined in a partial area. In other words, when the first power supply voltage VDD is applied to the first electrodes EL1 of the plurality of light emitting elements, the shape of each of the plurality of first electrodes EL1 may be provided in various suitable manners and is not limited to any particular embodiment.

[0215] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include a light emitting layer EML and a functional layer FNL. The light emitting element LD may include an intermediate layer IML having various suitable structures, and is not limited to any specific embodiment. For example, the functional layer FNL may be provided in plurality and may include two or more layers spaced apart from each other and the light emitting layer EML is interposed between the two or more layers.

[0216] The light emitting layer EML may include an organic emission material. In addition, the light emitting layer EML may include an inorganic emission material, or may be provided with a mixture layer of an organic emission material and an inorganic emission material. In this embodiment, the light emitting portion EP (eg, Figure 3A ) may include an emission material for emitting light of different colors from each other. For example, the emission layer EML included in each of the plurality of light emitting portions EP may provide light of any one color from blue, red, and green. However, the present disclosure is not limited thereto, and the emission layers EML in all of the plurality of light emitting portions EP may have an emission material for emitting light of the same color as each other. In this case, the emission layer EML may provide blue light or white light.

[0217] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. In more detail, the functional layer FNL may include a first intermediate functional layer FNLa (eg, see Fig. 9 ) and a second intermediate functional layer FNLb (eg, see Fig. 9 ). In the embodiment of the present disclosure, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb can be omitted as needed or desired. In the present embodiment, the light-emitting layer EML is shown as being embedded in the functional layer FNL. For example, it can be understood that the light-emitting layer EML is disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0218] The functional layer FNL may control the charge transfer between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa may include one or more hole injection / transport materials and / or one or more electron injection / transport materials. The second intermediate functional layer FNLb may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0219] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be connected to the connection electrode CNE to be electrically connected to the first pixel driver PDC1. The second electrode EL2 may be electrically connected to the connection transistor TR1 through the connection electrode CNE.

[0220] The spacer SPR may be disposed on the pixel defining layer PDL. In addition, the spacer SPR may be disposed between the connection electrode CNE on the pixel defining layer PDL and the adjacent connection electrode CNEn adjacent to the connection electrode CNE (eg, see Fig. 9 ) between the gap GP (see, for example, Fig. 9 )middle.

[0221] In an embodiment, the second electrode EL2 and the functional layer FNL may be commonly deposited in a plurality of pixels through an open mask. Here, the second electrode EL2 and the functional layer FNL may be divided by a separator SPR. As described above, the separator SPR may have a closed line shape for each of the plurality of light-emitting portions, and therefore, the second electrode EL2 and the functional layer FNL may have a separate shape for each of the plurality of light-emitting portions. In other words, the second electrode EL2 and the intermediate layer IML may be electrically isolated from each adjacent pixel. This will be referred to later. Fig. 9 The separator SPR is described in more detail.

[0222] The encapsulation layer ECL may be disposed on the light emitting element layer LDL. The encapsulation layer ECL may cover the light emitting element layer LD and the partition SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked sequentially. However, the present disclosure is not limited thereto, and the encapsulation layer ECL may also include a plurality of inorganic layers and organic layers. The encapsulation layer ECL may be a glass substrate.

[0223] The first inorganic layer IL1 and the second inorganic layer IL2 may protect the light emitting element LD from moisture and oxygen from outside the display panel DP, and the organic layer OL may protect the light emitting element LD from foreign matter (such as particles) that may remain in the process of providing the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer OL may include an acrylic organic layer, but the present disclosure is not limited to the above materials.

[0224] The sensing layer ISL may sense external input. In an embodiment, the sensing layer ISL may be provided on the encapsulation layer ECL through a continuous process. In this case, the sensing layer ISL may be understood to be directly disposed on the encapsulation layer ECL. As used herein, "directly disposed" may mean that another component is not disposed between the sensing layer ISL and the encapsulation layer ECL. In other words, a separate adhesive member may not be disposed between the input sensing layer ISL and the encapsulation layer ECL. However, the present disclosure is not limited to this. In the display panel DP according to an embodiment of the present disclosure, the sensing layer ISL may be provided separately and may then be combined with the display panel DP through an adhesive member, but the present disclosure is not limited to any particular embodiment.

[0225] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2. The plurality of insulating layers may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, the present disclosure is not limited thereto, and the number of conductive layers and insulating layers is not limited to any particular embodiment.

[0226] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0227] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT provided in the second sensing insulating layer 72. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may each have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0228] The sensing conductive layer of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or a suitable alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). As another example, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, or graphene.

[0229] The sensing conductive layer of the multi-layer structure may include multiple metal layers. For example, the metal layer may have a three-layer structure of titanium / aluminum / titanium. As another example, the sensing conductive layer of the multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0230] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor for sensing external input in the sensing layer ISL. The sensor may be driven in an electrostatic capacitance mode, and in more detail, may be driven in any one of a mutual capacitance mode and a self-capacitance mode. However, the present disclosure is not limited thereto. In addition to the electrostatic capacitance mode, the sensor may be driven in a resistive film mode, an ultrasonic mode, or an infrared mode, and is not limited to any particular embodiment.

[0231] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may further include a transparent conductive oxide, or may have a shape of a metal mesh including (e.g., consisting of) a non-transparent conductive material. As long as visibility of an image displayed on the display panel DP is not reduced, each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include various suitable materials and various suitable shapes, and is not limited to any specific embodiment.

[0232] Figure 6 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure. Figure 6 is a schematic diagram showing some components, such as the connection electrodes CNE1 , CNE2 , and CNE3 and the light emitting parts EP1 , EP2 , and EP3 , and the first, second, and third conductive patterns CP1 , CP2 , and CP3 .

[0233] Reference Figure 5 and Figure 6 The display panel DP may include a first pixel driver PDC1, a second pixel driver PDC2, and a third pixel driver PDC3 (see, for example, Figure 4B). The first pixel driver PDC1 may include a first conductive pattern CP1, the second pixel driver PDC2 may include a second conductive pattern CP2, and the third pixel driver PDC3 may include a third conductive pattern CP3.

[0234] The first conductive pattern CP1 may include a 1-1 pattern S1 and a 2-1 pattern D1 electrically connected to the first connection electrode CNE1. The second conductive pattern CP2 may include a 1-2 pattern S2 and a 2-2 pattern D2 electrically connected to the second connection electrode CNE2. The third conductive pattern CP3 may include a 1-3 pattern S3 and a 2-3 pattern D3 electrically connected to the third connection electrode CNE3. The 1-1 pattern S1, the 1-2 pattern S2, and the 1-3 pattern S3 may correspond to a source electrode pattern of a transistor, and the 2-1 pattern D1, the 2-2 pattern D2, and the 2-3 pattern D3 may correspond to a drain electrode pattern of a transistor.

[0235] The conductive patterns CP1 and CP2 may overlap adjacent connection electrodes CNE1 and CNE2 that are not electrically connected thereto. For example, the 1-1 pattern S1 and the 2-1 pattern D1 of the first conductive pattern CP1 are not electrically connected to the second connection electrode CNE2, but may overlap the second connection electrode CNE2 in a plan view. The 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 are not electrically connected to the first connection electrode CNE1, but may overlap the first connection electrode CNE1 in a plan view. Since the conductive pattern that is not electrically connected to the connection electrode overlaps the connection electrode in a plan view, the electric field may change, and coupling noise may be generated or increased in response to the change in the electric field.

[0236] Refer again Figure 5 , the display panel DP may further include a first metal layer ML1. The first metal layer ML1 may include the same material as that of the first electrode EL1, and is connected to the first electrode EL1. The first metal layer ML1 may be provided in the same process as that of the first electrode EL1. The first metal layer ML1 may be disposed between the connection electrode CNE and the 1-2 pattern S2 and the 2-2 pattern D2 in a cross-sectional view. The 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 may overlap with the first metal layer ML1 in a plan view.

[0237] Figure 5 The connection electrode CNE in the embodiment may not be electrically connected to the 1-2 pattern S2 and the 2-2 pattern D2. Figure 5 and Figure 6The first metal layer ML1 may include the same material as that of the first electrode EL1 of the first light emitting part EP1 and be connected to the first electrode EL1 of the first light emitting part EP1. The first metal layer ML1 may be disposed between the second conductive pattern CP2 and the first connection electrode CNE1 in a cross-sectional view, and may overlap the 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 in a plan view.

[0238] However, the present disclosure is not limited thereto, and the position of the first metal layer ML1 may be variously modified as needed or desired. For example, the first metal layer ML1 may be disposed between the first conductive pattern CP1 and the second connection electrode CNE2 in a cross-sectional view, and may overlap the 1-1 pattern S1 and the 2-1 pattern D1 of the first conductive pattern CP1 in a plan view.

[0239] According to an embodiment of the present disclosure, the first electrode EL1 of the display panel DP may extend to be disposed between the connection electrode CNE and the conductive patterns CP1, CP2, and CP3. The first electrode EL1 may be supplied with a first power supply voltage VDD (eg, see Figure 2A Since the conductive patterns CP1, CP2, and CP3 and the connection electrode CNE are shielded using the first electrode EL1 supplied with a constant voltage, coupling noise generated between the conductive patterns CP1, CP2, and CP3 and the connection electrode CNE may be reduced or removed.

[0240] Figure 7 is a cross-sectional view of a display panel DP-1 according to an embodiment of the present disclosure. Figure 7 Shows the corresponding Figure 4A The cross section of the line I-I' in Figure 7 In the drawings, the same reference numerals are used to indicate Figure 5 The elements described are identical elements (eg, identical or substantially identical elements), and thus, redundant descriptions thereof may not be repeated.

[0241] Reference Figure 7 , the display panel DP-1 may include a second metal layer ML2. The second metal layer ML2 may include the same material as that of the intermediate connection electrode CN, and may be provided at the same layer as that of the intermediate connection electrode CN (e.g., in or on). The second metal layer ML2 may be provided in the same process as that of the intermediate connection electrode CN. The second metal layer ML2 may be provided between the connection electrode CNE and the 1-2nd pattern S2 and the 2-2nd pattern D2. The 1-2nd pattern S2 and the 2-2nd pattern D2 may overlap with the second metal layer ML2 in a plan view.

[0242] Figure 7The connection electrode CNE in the embodiment may not be electrically connected to the 1-2 pattern S2 and the 2-2 pattern D2. Figure 6 and Figure 7 , the second metal layer ML2 may include the same material as that of the intermediate connection electrode CN that electrically connects the first pixel driving part PDC1 and the first connection electrode CNE1 to each other, and may be disposed at the same layer as that of the intermediate connection electrode CN (e.g., in or above). The second metal layer ML2 may be disposed between the second conductive pattern CP2 and the first connection electrode CNE1 in a cross-sectional view, and may overlap the 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 in a plan view.

[0243] However, the present disclosure is not limited thereto, and the position of the second metal layer ML2 may be variously modified as needed or desired. For example, the second metal layer ML2 may be disposed between the first conductive pattern CP1 and the second connection electrode CNE2 in a cross-sectional view, and may overlap the 1-1 pattern S1 and the 2-1 pattern D1 in a plan view.

[0244] According to some embodiments of the present disclosure, the middle connection electrode CN of the display panel DP- 1 may be extended to reduce or remove coupling noise provided between the connection electrode CNE and the conductive patterns CP1 , CP2 , and CP3 .

[0245] Figure 8 is a cross-sectional view of a display panel DP-2 according to an embodiment of the present disclosure. Figure 8 Shows the corresponding Figure 4A The cross section of the line I-I' in Figure 8 In the drawings, the same reference numerals are used to indicate Figure 5 The elements described are identical elements (eg, identical or substantially identical elements), and thus, redundant descriptions thereof may not be repeated.

[0246] Reference Figure 8 , the display panel DP-2 may include both a first metal layer ML1 and a second metal layer ML2. The first metal layer ML1 may include the same material as that of the first electrode EL1, and is connected to the first electrode EL1. The second metal layer ML2 may include the same material as that of the intermediate connection electrode CN, and may be provided at the same layer as that of the intermediate connection electrode CN (e.g., in or above). The first metal layer ML1 may be provided in the same process as that of the first electrode EL1, and the second metal layer ML2 may be provided in the same process as that of the intermediate connection electrode CN.

[0247] The first metal layer ML1 and the second metal layer ML2 may be disposed between the connection electrode CNE and the 1-2nd and 2-2nd patterns S2 and D2. The 1-2nd and 2-2nd patterns S2 and D2 may overlap the first metal layer ML1 and the second metal layer ML2 in a plan view.

[0248] Figure 8 The connection electrode CNE in the embodiment may not be electrically connected to the 1-2 pattern S2 and the 2-2 pattern D2. Figure 6 and Figure 8 , the first metal layer ML1 may include the same material as the first electrode EL1 of the first light emitting portion EP1, and is connected to the first electrode EL1 of the first light emitting portion EP1. The second metal layer ML2 may include the same material as the intermediate connection electrode CN that electrically connects the first pixel driver PDC1 and the first connection electrode CNE1 to each other, and may be disposed at the same layer as (e.g., in or above) that of the intermediate connection electrode CN. The first metal layer ML1 and the second metal layer ML2 may be disposed between the second conductive pattern CP2 and the first connection electrode CNE1 in a cross-sectional view, and may overlap with the 1-2 pattern S2 and the 2-2 pattern D2 in a plan view.

[0249] However, the present disclosure is not limited thereto, and the positions of the first metal layer ML1 and the second metal layer ML2 may be variously modified as needed or desired. For example, the first metal layer ML1 and the second metal layer ML2 may be disposed between the first conductive pattern CP1 and the second connection electrode CNE2 in a cross-sectional view, and may overlap with the 1-1 pattern S1 and the 2-1 pattern D1 in a plan view.

[0250] According to an embodiment of the present disclosure, the middle connection electrode CN and / or the first electrode EL1 of the display panel DP- 2 may be extended to reduce or remove coupling noise provided between the conductive patterns CP1 , CP2 , and CP3 and the connection electrode CNE.

[0251] Fig. 9 is an enlarged cross-sectional view of a partial area of ​​the display panel DP according to an embodiment of the present disclosure. Fig. 9 yes Figure 5 An enlarged plan view of area AA' in FIG.

[0252] Reference Figure 5 and Fig. 9, in an embodiment, the spacer SPR may have a reverse tapered shape. For example, the farther the spacer SPR is from the top surface of the pixel defining layer PDL, the wider the width of the spacer SPR. The side surface TP of the spacer SPR may have a shape in which the tapered angle from the top surface of the pixel defining layer PDL is an obtuse angle. However, the present disclosure is not limited thereto, and when the spacer SPR electrically disconnects the second electrode EL2 for each of a plurality of pixels, the spacer SPR may have a dual structure in which various modifications (e.g., such that the tapered angle changes) may be made to the tapered angle. In addition, the spacer SPR may have a structure that is the same as or substantially the same as that of the tip portion, and is not limited to any particular embodiment.

[0253] The spacer SPR may include a suitable material having insulating properties, such as an organic insulating material. The spacer SPR may also include an inorganic insulating material or a multilayer structure of an organic insulating material and an inorganic insulating material, and in some embodiments, may also include a conductive material. When the second electrode EL2 is electrically disconnected for each of a plurality of pixels, the spacer SPR is not particularly limited to any particular type of material.

[0254] On the separator SPR, a dummy layer UP may be provided. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be provided in the same process as that of the intermediate layer IML and include the same material as that of the intermediate layer IML. The first dummy layer UP1 may include a 1-1st dummy layer UP1a and a 1-2nd dummy layer UP1b. The 1-1st dummy layer UP1a may be provided in the same process as that of the first intermediate functional layer FNLa and may include the same material as that of the first intermediate functional layer FNLa. The 1-2nd dummy layer UP1b may be provided in the same process as that of the second intermediate functional layer FNLb and may include the same material as that of the second intermediate functional layer FNLb. The second dummy layer UP2 may be provided in the same process as that of the second electrode EL2 and may include the same material as that of the second electrode EL2. In other words, the first dummy layer UP1 and the second dummy layer UP2 may be provided concurrently in the manufacturing process of the functional layer FNL and the second electrode EL2. Fig. 9 As shown in , the dummy layer UP may also be provided on a portion of the side surface TP and on the top surface of the spacer SPR. In another embodiment, the display panel DP may not include the dummy layer UP. The dummy layer UP may not contact the connection electrode CNE and the second electrode EL2. The second dummy layer UP2 included in the dummy layer UP may not contact the connection electrode CNE and the second electrode EL2.

[0255] The portion where the second electrode EL2 contacts the connection electrode CNE may be defined as a contact region. The contact region may be provided adjacent to the separator SPR. In the contact region, the top surface CNE-us of the connection electrode CNE contacts the bottom surface EL2-bs of the second electrode EL2. Since the separator SPR has a reverse tapered shape and is provided adjacent to the contact region, at least a portion of the contact region where the second electrode EL2 contacts the connection electrode CNE may be disposed below the side surface TP of the separator SPR.

[0256] In an embodiment, at least a portion of the connection electrode CNE may be disposed under the spacer SPR. The spacer SPR may be disposed in the gap GP between the connection electrode CNE and an adjacent connection electrode CNEn adjacent to the connection electrode CNE, and the second edge EG2c of the second electrode EL2 may be covered by the spacer SPR.

[0257] According to an embodiment of the present disclosure, the connection electrode CNE may have a shape surrounding a portion of the emission region in which the light emitting element LD is disposed (e.g., around the periphery of the portion of the emission region in which the light emitting element LD is disposed). Therefore, the connection position of the connection electrode CNE and the light emitting element LD and the connection position of the connection electrode CNE and the pixel driver PDC (e.g., see FIG. 1 ) may be improved. Figure 2A ) at the connection position. In addition, the top surface CNE-us of the connection electrode CNE can contact the bottom surface EL2-bs of the second electrode EL2 of the light-emitting element LD through a contact area defined adjacent to the partition SPR. Therefore, because the bottom surface of the connection electrode CNE contacts the top surface of the intermediate connection electrode CN, the contact reliability of the connection electrode CNE and the second electrode EL2 can be improved. In the display panel DP according to the embodiment, due to the above-mentioned structure, the size of the through hole OP-P and the size of OP-60 for connecting the connection electrode CNE and the intermediate connection electrode CN can be reduced or minimized, and therefore, the area or resolution of the light-emitting portion of the display panel DP can be improved (for example, it can be easily improved).

[0258] Fig.10 is a cross-sectional view of a display panel DP-3 according to an embodiment of the present disclosure. Fig.10 is shown corresponding to Figure 4B A cross-sectional view of the portion along line II-II'. Fig.10 In the drawings, the same reference numerals are used to indicate Figure 5 The elements described are identical elements (eg, identical or substantially identical elements), and thus, redundant descriptions thereof may not be repeated.

[0259] Reference Fig.10The display panel DP-3 may further include a connection line CN-ad disposed between the sixth insulating layer 60 and the pixel defining layer PDL. The connection line CN-ad may be connected to the intermediate connection electrode CN through a through hole OP-60 exposing at least a portion of the intermediate connection electrode CN.

[0260] In an embodiment of the present disclosure, the connection line CN-ad may be disposed at the same layer as the layer of the first electrode EL1 (e.g., in or above). For example, the connection line CN-ad may have the same material as the material of the first electrode EL1 and the same layer structure as the layer structure of the first electrode EL1. In addition, the connection line CN-ad may be provided in the same process as the process of the first electrode EL1. However, the present disclosure is not limited thereto. For example, the connection line CN-ad may have a material different from that of the first electrode EL1 and may be provided in a process different from that of the first electrode EL1.

[0261] The through hole OP-Pa may be defined in the pixel defining layer PDL. The through hole OP-Pa and the through hole OP-60 may not overlap each other, but the present disclosure is not limited thereto. For example, in some embodiments, the through hole OP-Pa and the through hole OP-60 may overlap each other. The connection electrode CNEa may be disposed in the through hole OP-Pa. The connection electrode CNEa may be connected to a portion of the connection line CN-ad exposed by the through hole OP-Pa.

[0262] According to some embodiments described above, the intermediate connection electrode and / or the first electrode may be extended to reduce or remove coupling noise generated between the conductive pattern and the connection electrode.

[0263] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting it. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that various modifications may be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, unless otherwise specifically stated, as will be apparent to those of ordinary skill in the art, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an explanation of various example embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display panel, wherein: The display panel comprises: Driver component layer, including: A first pixel driver including a first conductive pattern; and A second pixel driver including a second conductive pattern; a light emitting element on the driving element layer, and comprising a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connecting electrode, on the driving element layer, and electrically connected to the first pixel driver and the second electrode; and The metal layer is between the second conductive pattern and the connection electrode in the cross-sectional view.

2. The display panel according to claim 1, wherein: The first conductive pattern comprises: Pattern 1-1; and The 2-1 pattern is electrically connected to the connection electrode.

3. The display panel according to claim 2, wherein: The second conductive pattern includes a 1-2 pattern and a 2-2 pattern.

4. The display panel according to claim 3, wherein: The 1-2 pattern and the 2-2 pattern overlap with the metal layer in a plan view.

5. The display panel according to claim 3, wherein: The 1-2 pattern and the 2-2 pattern overlap with the connection electrode in a plan view.

6. The display panel according to claim 3, wherein: The 1-1 pattern and the 1-2 pattern include source electrode patterns.

7. The display panel according to claim 3, wherein: The 2-1st pattern and the 2-2nd pattern include a drain electrode pattern.

8. The display panel according to claim 1, wherein: The display panel further includes: The intermediate connecting electrode electrically connects the first pixel driver and the connecting electrode to each other.

9. The display panel according to claim 8, wherein: The metal layer includes the same material as that of the intermediate connection electrode, and the metal layer is positioned at the same layer as that of the intermediate connection electrode.

10. The display panel according to claim 1, wherein: The metal layer includes the same material as that of the first electrode, and the metal layer is connected to the first electrode.

11. The display panel according to claim 1, wherein: The display panel further includes: a pixel defining layer on the driving element layer and having an emission opening passing through the pixel defining layer, wherein the emission opening exposes at least a portion of the first electrode, Wherein, the connection electrode has a ring shape surrounding the emission opening.

12. The display panel according to claim 1, wherein: A bottom surface of the second electrode contacts a top surface of the connection electrode.

13. The display panel according to claim 1, wherein: The display panel further includes: a separator, on the connecting electrode, The second electrode and the connection electrode are connected to each other at a region adjacent to the separator.

14. The display panel according to claim 13, wherein: The connecting electrode comprises: first edge; and A second edge surrounds the first edge and overlaps the divider.

15. A display panel, wherein: The display panel comprises: a driving element layer, including a pixel driver including a conductive pattern; a light emitting element on the driving element layer, and comprising a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a connecting electrode on the driving element layer and electrically connected to the pixel driver and the second electrode; and A metal layer overlaps the connection electrode and the conductive pattern in a plan view.

16. The display panel according to claim 15, wherein: The conductive pattern comprises: a first pattern; and The second pattern is electrically connected to the connection electrode.

17. The display panel according to claim 16, wherein: The first pattern includes a source electrode pattern, and the second pattern includes a drain electrode pattern.

18. The display panel according to claim 15, wherein: The display panel further includes: The intermediate connecting electrode electrically connects the pixel driver and the connecting electrode to each other.

19. The display panel according to claim 18, wherein: The metal layer includes the same material as that of the intermediate connecting electrode, and the metal layer is positioned on the same layer as that of the intermediate connecting electrode.

20. The display panel according to claim 15, wherein: The metal layer includes the same material as that of the first electrode, and the metal layer is connected to the first electrode.

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