Current bias circuit, memory and memory system

Abstract

A current bias circuit, a memory (60, 702) and a memory system (701), the current bias circuit comprising: a voltage stabilizing circuit (200) configured to output a second voltage through a second end (203) of the voltage stabilizing circuit (200) based on a first voltage received by a first end (202) of the voltage stabilizing circuit (200); and a main body circuit (100), the first end (101) of the main body circuit (100) is coupled to the second end (203) of the voltage stabilizing circuit (200), and the main body circuit (100) is configured to receive the second voltage output by the second end (203) of the voltage stabilizing circuit (200) and generate a bias current.

Description

Current bias circuit, memory, and memory system Technical Field

[0001] The embodiments of the present disclosure relate to semiconductor technology, and relate to but are not limited to a current bias circuit, a memory, and a memory system. Background Art

[0002] Memory chips are an indispensable component of modern electronic devices. They not only increase storage capacity but also make electronic devices more intelligent. Improving the performance of memory chips has become a pressing issue.

[0003] Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a current bias circuit, a memory, and a memory system.

[0005] In a first aspect, an embodiment of the present disclosure provides a current bias circuit, comprising:

[0006] a voltage stabilizing circuit configured to output a second voltage through a second terminal of the voltage stabilizing circuit based on a first voltage received at a first terminal of the voltage stabilizing circuit;

[0007] A main circuit has a first terminal coupled to the second terminal of the voltage stabilizing circuit, and is configured to receive a second voltage outputted by the second terminal of the voltage stabilizing circuit to generate a bias current.

[0008] In some embodiments, the voltage stabilization circuit includes a clamping circuit,

[0009] The clamp circuit is configured to provide the second voltage to the first end of the body circuit based on the first voltage and a voltage drop across the clamp circuit.

[0010] In some embodiments, the clamp circuit includes a first transistor, and the clamp circuit is configured to provide the second voltage to the first terminal of the body circuit based on the first voltage and a threshold voltage of the first transistor.

[0011] In some embodiments, the third terminal of the voltage stabilization circuit is configured to receive a third voltage, and the third voltage is greater than the first voltage.

[0012] In some embodiments, the first transistor comprises a depletion-mode N-type transistor.

[0013] In some embodiments, the voltage stabilization circuit further includes a first resistor coupled to the clamping circuit.

[0014] In some embodiments, the resistance of the first resistor is related to the magnitude of loop stability loss caused by parasitic capacitance of the voltage stabilization circuit.

[0015] In some embodiments, the resistance of the first resistor is greater than or equal to 1 kΩ and less than or equal to 100 kΩ.

[0016] In some embodiments, the main circuit is configured to provide the first voltage to the first terminal of the voltage regulation circuit based on a reference voltage received at the second terminal of the main circuit.

[0017] In some embodiments, the main circuit is configured to generate a feedback voltage at a first node of the main circuit based on a reference voltage received at a second end of the main circuit, and the feedback voltage is equal to the reference voltage; the first node of the main circuit is connected to the first end of the voltage stabilization circuit.

[0018] In some embodiments, the main circuit includes:

[0019] an operational amplifier circuit, wherein a first terminal of the operational amplifier circuit is configured to receive the reference voltage and provide a bias voltage to the current regulating circuit;

[0020] The current regulating circuit is coupled to the operational amplifier circuit and is configured to output a bias current from a first terminal of the current regulating circuit based on the bias voltage and the second voltage.

[0021] In some embodiments, the first terminal of the voltage stabilizing circuit is connected to the second terminal of the operational amplifier circuit; or, the first terminal of the voltage stabilizing circuit is connected to the feedback terminal of the operational amplifier circuit.

[0022] In some embodiments, the operational amplifier circuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a third P-type transistor, and a second resistor;

[0023] The gate terminal of the first P-type transistor is connected to the gate terminal of the second P-type transistor, the first terminal of the first P-type transistor, the first terminal of the second P-type transistor and the first terminal of the third P-type transistor are connected to the second terminal of the voltage stabilizing circuit, the gate terminal of the second P-type transistor is connected to the second terminal of the second P-type transistor, the first terminal of the first N-type transistor, the second terminal of the first P-type transistor and the gate terminal of the third P-type transistor are connected to the second terminal of the current regulating circuit, the first terminal of the second N-type transistor is connected to the second terminal of the second P-type transistor, the gate terminal of the first N-type transistor is configured to receive the reference voltage, the gate terminal of the second N-type transistor, the first terminal of the second resistor and the second terminal of the third P-type transistor are connected, the second terminal of the second resistor is connected to the ground terminal, the second terminal of the first N-type transistor and the second terminal of the second N-type transistor are connected to the first terminal of the third N-type transistor, and the second terminal of the third N-type transistor is connected to the ground terminal.

[0024] In some embodiments, the current regulating circuit includes a second transistor;

[0025] The first end of the second transistor is connected to the second end of the voltage stabilizing circuit, the gate end of the second transistor is connected to the output end of the operational amplifier circuit, and the second end of the second transistor is configured to output the bias current.

[0026] In a second aspect, an embodiment of the present disclosure provides a memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit comprises the current bias circuit as described in any of the above embodiments.

[0027] In a third aspect, an embodiment of the present disclosure further provides a memory, comprising a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit comprises:

[0028] a first transistor configured to output a second voltage through a first terminal of the first transistor based on a first voltage received at a gate terminal of the first transistor;

[0029] A main circuit has a first terminal coupled to the first terminal of the first transistor, and is configured to generate a bias current based on a second voltage output by the first terminal of the first transistor.

[0030] In some embodiments, the peripheral circuit further includes: a first resistor, wherein a first end of the first resistor is connected to a gate end of the first transistor.

[0031] In some embodiments, the first transistor comprises a depletion-mode N-type transistor.

[0032] In some embodiments, the second end of the main body circuit is configured to receive a reference voltage, and the main body circuit is configured to generate a feedback voltage at a first node of the main body circuit based on the reference voltage, and the feedback voltage is equal to the reference voltage; the second end of the first resistor is connected to the first node of the main body circuit.

[0033] In some embodiments, the main circuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third P-type transistor, a second resistor, and a second transistor;

[0034] The gate terminal of the first P-type transistor is connected to the gate terminal of the second P-type transistor, the first terminal of the first P-type transistor, the first terminal of the second P-type transistor, the first terminal of the third P-type transistor, and the first terminal of the second transistor are connected to the first terminal of the first transistor, the gate terminal of the second P-type transistor is connected to the second terminal of the second P-type transistor, the first terminal of the first N-type transistor, the second terminal of the first P-type transistor, and the gate terminal of the third P-type transistor are connected to the gate terminal of the second transistor, the first terminal of the second N-type transistor is connected to the second terminal of the second P-type transistor, the gate terminal of the first N-type transistor is configured to receive a reference voltage, the gate terminal of the second N-type transistor, the first terminal of the second resistor, and the second terminal of the third P-type transistor are connected, the second terminal of the second resistor is connected to the ground terminal, the second terminal of the first N-type transistor and the second terminal of the second N-type transistor are connected to the ground terminal; the second terminal of the second transistor outputs the bias current.

[0035] In some embodiments, the gate terminal of the first N-type transistor is connected to the gate terminal of the first transistor, or the gate terminal of the second N-type transistor is connected to the gate terminal of the first transistor.

[0036] In a fourth aspect, an embodiment of the present disclosure provides a memory system, comprising a memory as described in any of the above embodiments, and a memory controller coupled to and controlling the memory.

[0037] In the embodiment of the present disclosure, a voltage stabilizing circuit is provided at the first end of the main circuit, the first end of the voltage stabilizing circuit receives a first voltage, and the second end of the voltage stabilizing circuit outputs a second voltage. On the one hand, the second voltage output by the second end of the voltage stabilizing circuit is related to the magnitude of the first voltage and the internal characteristics of the voltage stabilizing circuit. Therefore, it can effectively filter out the influence of power supply noise in the external power supply, improve the ability of the bias current generating circuit to resist power supply noise, and make the bias current generated by the main circuit more stable. On the other hand, the solution provided by the embodiment of the present disclosure utilizes a clamping circuit for power supply, so that the second voltage stabilizes faster and can meet the speed requirements of high-speed circuits. On the other hand, in the embodiment of the present disclosure, a large number of decoupling capacitors and additional high performance are not required, and the area of ​​the voltage stabilizing circuit is small, which is conducive to the miniaturization of memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0039] FIG1 is a schematic diagram of a current bias circuit provided in some embodiments of the present disclosure;

[0040] FIG2A is a schematic diagram of a current bias circuit provided in some other embodiments of the present disclosure;

[0041] FIG2B is a schematic diagram of the PSR of the LDO and the voltage stabilization circuit at different frequencies;

[0042] FIG2C is a schematic diagram showing the response speed of the LDO and voltage stabilization circuit in generating a stable internal power supply voltage;

[0043] 3 to 12 are schematic diagrams of current bias circuits provided in some other embodiments of the present disclosure;

[0044] FIG13 is a first structural diagram of a memory including a memory cell array and peripheral circuits provided by an embodiment of the present disclosure;

[0045] FIG14 is a second structural diagram of a memory including a memory cell array and peripheral circuits provided by an embodiment of the present disclosure;

[0046] FIG15 is a third structural diagram of a memory including a memory cell array and peripheral circuits provided by an embodiment of the present disclosure;

[0047] FIG16 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0048] FIG17 is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0049] FIG. 18 is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] Memory chips are an indispensable component of modern electronic devices. They not only increase a device's storage capacity but also make them more intelligent. With the continuous advancement of technology, memory chips are also constantly evolving. The speed requirements for the input / output (I / O) systems of memory chips are increasing, and consequently, the speed requirements for the I / O buffers within memory chips are also increasing. The I / O buffer requires a bias current. To meet the speed requirements of the I / O system, this bias current must be generated quickly. Furthermore, because the bias current affects the duty cycle of the I / O system, to ensure this duty cycle, it must be stable and have good immunity to power supply rejection (PSR). This bias current can ultimately be converted from current to voltage and used as the input voltage for the I / O system.

[0053] Therefore, how to ensure that the bias current provided by the memory chip has both a fast generation speed and a good ability to resist power supply noise has become an urgent problem to be solved.

[0054] In some embodiments, the main circuit receives an internal power supply voltage and is used to generate a bias current. In some implementations, as shown in FIG1 , the internal power supply voltage received by the main circuit 100 is powered by a high-performance low dropout linear regulator (LDO) 20, which is used to filter the noise in the external power supply to ensure voltage purity. However, the ability of the LDO 20 to resist power supply noise deteriorates at high frequencies, which will affect the bias current generated by the main circuit 100. Moreover, due to the long response time of the LDO 20, the bias current turn-on speed cannot meet the specification requirements of the Open NAND Flash Interface (ONFI), and the area occupied by the LDO 20 is large, which is not conducive to the miniaturization of the chip. In other embodiments, a large number of decoupling capacitors can be added to help turn on the main circuit 100 and filter the noise in the external power supply, but a large number of decoupling capacitors need to occupy a large area of ​​the memory, which is not conducive to the miniaturization of the memory.

[0055] To solve one or more of the above problems, an embodiment of the present disclosure provides a current bias circuit, as shown in FIG2A , comprising:

[0056] The voltage stabilizing circuit 200 is configured to output a second voltage through a second terminal 203 of the voltage stabilizing circuit 200 based on a first voltage received at a first terminal 202 of the voltage stabilizing circuit 200 ;

[0057] The main circuit 100 has a first terminal 101 coupled to a second terminal 203 of the voltage stabilizing circuit 200 . The main circuit 100 is configured to receive a second voltage outputted by the second terminal 203 of the voltage stabilizing circuit 200 and generate a bias current.

[0058] In the embodiment of the present disclosure, the first voltage may come from the main circuit 100 or from other external circuits. It should be noted that the external circuit that generates the first voltage is also part of the memory.

[0059] In the disclosed embodiment, the third terminal of the voltage stabilization circuit is further configured to receive a third voltage, which may be generated by an external power supply. The external power supply may generate power supply noise when in a switching state or while supplying power. It should be noted that the external power supply that generates the third voltage is also part of the memory.

[0060] It is understandable that if the third voltage is directly provided to the main circuit 100, when there is power supply noise in the third voltage, the output bias current cannot be stable. In the embodiment of the present disclosure, a voltage stabilizing circuit 200 is provided at the first end 101 of the main circuit, the third end 201 of the voltage stabilizing circuit receives the third voltage, and the first end 202 of the voltage stabilizing circuit receives the first voltage. Firstly, the second voltage output by the second end 203 of the voltage stabilizing circuit is related to the magnitude of the first voltage and the internal characteristics of the voltage stabilizing circuit 200, and is not related to the interference and state of the third voltage. Therefore, it can effectively filter the influence of power supply noise in the external power supply, improve the ability of the bias current generating circuit to resist power supply noise, and make the bias current generated by the main circuit 100 more stable; secondly, the solution provided by the embodiment of the present disclosure uses a clamping circuit for power supply, so that the second voltage stabilizes quickly and can meet the speed requirements of high-speed circuits; thirdly, the area of ​​the voltage stabilizing circuit is small and does not occupy a large area of ​​the memory, which is conducive to the miniaturization development of the memory.

[0061] FIG2B shows the PSR at different frequencies when the LDO and the voltage stabilizing circuit supply power to the main circuit (the hollow circle line represents the LDO power supply, and the solid circle line represents the voltage stabilizing circuit power supply provided by the embodiment of the present disclosure).

[0062] It can be seen in FIG2B that the highest PSR value is generated when the LDO is supplying power to the main circuit. The higher the PSR value, the worse the circuit's ability to filter noise.

[0063] For the LDO circuit, the highest PSR value occurs at high frequency f1, and the PSR value is y2. For the voltage regulator circuit, the highest PSR value occurs at high frequency f2, and the PSR value is y1, which is significantly smaller than y2.

[0064] Figure 2B also shows that both power supply circuits perform well at low and medium frequencies. Figure 2C shows the response speed of generating a stable second voltage when the LDO and voltage regulator circuit are supplying power to the main circuit (the hollow circle line represents the LDO power supply, and the solid circle line represents the voltage regulator circuit provided by the embodiment of the present disclosure).

[0065] It can be seen that when the LDO is supplying power to the main circuit, the response speed of the second voltage is t2. However, when the voltage stabilizing circuit provided by the embodiment of the present disclosure is supplying power to the main circuit, the response speed of the second voltage is t1, which is much faster. In Figure 2C, both V1 and V2 are voltage levels that meet the requirements of the main circuit.

[0066] In some embodiments, as shown in FIG. 3 , the voltage stabilizing circuit 200 includes a clamping circuit 300 , and the clamping circuit 300 is configured to provide a second voltage to the first terminal 101 of the main circuit based on a first voltage and a voltage drop across the clamping circuit 300 .

[0067] The first terminal 301 of the clamp circuit is configured to receive a third voltage, the second terminal 302 of the clamp circuit is configured to receive the first voltage, and the output terminal 303 of the clamp circuit is connected to the first terminal 101 of the main circuit. The voltage drop of the clamp circuit 300 refers to the voltage difference between the voltage received by the clamp circuit 300 and the voltage output by the clamp circuit 300. The value of this voltage difference is determined by the internal device characteristics of the clamp circuit 300.

[0068] The clamping circuit 300 can implement a positive clamping function or a negative clamping function. Specifically, it can shift the received first voltage upward or downward without changing the waveform of the first voltage.

[0069] In the embodiment of the present disclosure, since the first voltage is a stable voltage, the second voltage generated by shifting the stable voltage upward or downward is also a stable voltage.

[0070] It should be noted that the second voltage must be greater than the voltage margin required by the main circuit 100. The main circuit 100 includes a plurality of transistors.

[0071] The second voltage is required to ensure that the transistors included in the main circuit 100 operate in a normal operating range and maintain a certain voltage margin. Here, the reason for maintaining a certain voltage margin is to ensure that the main circuit 100 can operate normally under different temperature process conditions.

[0072] In some embodiments, as shown in FIG. 4 , the clamp circuit 300 includes a first transistor 400 , and the clamp circuit 300 is configured to provide a second voltage to the first terminal 101 of the body circuit based on the first voltage and a threshold voltage of the first transistor 400 .

[0073] In the disclosed embodiment, the second voltage is primarily determined by the first voltage and the threshold voltage of the first transistor 400, thereby filtering out power supply noise from the external power supply. Furthermore, the first transistor 400 significantly reduces the area of ​​the memory chip occupied by a large number of decoupling capacitors, effectively saving memory chip area and facilitating miniaturization of the memory chip.

[0074] In some embodiments, the third terminal 201 of the voltage stabilization circuit is configured to receive a third voltage, and the first voltage is less than the third voltage.

[0075] In the embodiment of the present disclosure, the third voltage may be generated by an external power supply. The external power supply may generate power supply noise when in a switching state or when supplying power.

[0076] It is understandable that if the first voltage received by the gate terminal of the first transistor 400 is greater than the third voltage received by the second terminal of the first transistor 400, it is equivalent to the first transistor 400 being fully turned on. The third voltage received by the second terminal of the first transistor 400 can be completely transmitted to the first terminal of the first transistor 400. At this time, the voltage at the first terminal of the first transistor 400 is still equal to the third voltage, which cannot achieve a good clamping effect. The first voltage is less than the third voltage to ensure that the first transistor 400 is in a state of just being turned on. At this time, the first transistor 400 can play a clamping role. The voltage at the second terminal of the first transistor 400 is equal to the first voltage minus the threshold voltage of the first transistor 400.

[0077] In some embodiments, the first transistor 400 includes an enhancement-type N-type transistor.

[0078] When the first transistor 400 is an enhancement type N-type transistor, the second voltage is equal to the first voltage minus the threshold voltage of the enhancement type transistor. Since the threshold voltage of the enhancement type transistor is greater than 0, the second voltage is equal to the first voltage minus the threshold voltage of the enhancement type transistor.

[0079] In some embodiments, the first transistor 400 includes a depletion-mode N-type transistor.

[0080] When the first transistor 400 is a depletion-type N-type transistor, the second voltage is equal to the first voltage minus the threshold voltage of the depletion-type transistor. Since the threshold voltage of the depletion-type transistor is less than 0, the second voltage is equal to the first voltage plus the absolute value of the threshold voltage of the depletion-type transistor. Because the second voltage must be greater than the voltage margin required by the main circuit 100, using a depletion-type N-type transistor is more conducive to raising the second voltage so that the magnitude of the second voltage meets the actual voltage requirement and meets the requirements for normal circuit operation.

[0081] In the disclosed embodiment, the second voltage is determined by the first voltage and the threshold voltage of the first transistor 400, thereby filtering out power supply noise from the external power supply. Furthermore, the area of ​​the memory chip occupied by the first transistor 400 is very small, effectively saving the area of ​​the memory chip and facilitating miniaturization of the memory chip.

[0082] 5 , the voltage stabilizing circuit 200 further includes a first resistor 410 coupled to the clamping circuit 300. Specifically, a first terminal 411 of the first resistor is connected to the second terminal 302 of the clamping circuit 300, and a second terminal 412 of the first resistor is configured to receive a first voltage.

[0083] In some embodiments, the resistance of the first resistor 410 is related to the magnitude of the loop stability loss caused by the parasitic capacitance of the voltage stabilization circuit 200 .

[0084] It is understood that the clamping circuit 300 may also have parasitic capacitance. Specifically, the clamping circuit 300 includes a first transistor 400. A parasitic capacitance Cgs may also exist between the first terminal of the first transistor 400 and the gate terminal of the first transistor 400. The parasitic capacitance Cgs may cause loop stability loss. Loop stability loss refers to the parasitic capacitance Cgs introducing a pole. By adding the first resistor 410, a zero point is added, which pushes the pole away and ensures loop stability. Here, the magnitude of the parasitic capacitance Cgs is related to the process and size of the first transistor 410.

[0085] In the embodiment of the present disclosure, the first resistor 410 is provided at the second end 302 of the clamp circuit to compensate for the loop stability loss caused by the parasitic capacitance Cgs, thereby improving the stability of the circuit.

[0086] In some embodiments, the resistance of the first resistor 410 is greater than or equal to 1 kΩ and less than or equal to 100 kΩ.

[0087] It should be noted that the specific range of the first resistance 410 given above is only exemplary and does not limit the size of the first resistor 410. In some specific examples, the size of the first resistance 410 can be set accordingly based on the size of the loop stability loss caused by parasitic capacitance.

[0088] In some embodiments, as shown in FIG. 6 and FIG. 7 , the main circuit 100 is configured to provide a first voltage to the first terminal 202 of the voltage stabilization circuit 200 based on a reference voltage received at the second terminal 102 of the main circuit 100 .

[0089] In some embodiments, as shown in FIG6 , the second terminal 102 of the main circuit 100 receives a reference voltage and outputs a bias current based on the reference voltage. The main circuit 100 is configured to provide a first voltage to the voltage stabilization circuit 200 based on the reference voltage. In the disclosed embodiment, the first voltage is provided by the second terminal 102 of the main circuit 100, eliminating the need for an additional first voltage generation circuit to generate the first voltage. This effectively utilizes existing resources, saves costs, and facilitates miniaturization of memory chips.

[0090] In some embodiments, the second terminal 102 of the main circuit 100 may be connected to a reference voltage source, and the reference voltage source provides a reference voltage to the second terminal 102 of the main circuit 100 .

[0091] In some embodiments, the reference voltage source may be a bandgap reference source in a memory. The reference voltage may be a reference voltage in a memory.

[0092] In some embodiments, as shown in FIG7 , the reference voltage can be directly provided to the second terminal 102 of the main circuit, and the reference voltage can be indirectly provided to the voltage stabilization circuit via the voltage amplifier 500. The first voltage = K * reference voltage, where K is the amplification factor of the voltage amplifier 500. That is, the first voltage can be obtained by scaling the reference voltage by a certain ratio. When the reference voltage is small, increasing the amplification factor K can yield a larger first voltage, for example, 1.2 times the reference voltage. When the reference voltage is large, decreasing the amplification factor K can yield a smaller first voltage, for example, 0.8 times the reference voltage.

[0093] In the embodiment of the present disclosure, the voltage amplifier 500 is added to adjust the magnitude of the first voltage, so that the first voltage is more flexible and applicable to more types of main circuits 100 .

[0094] In some embodiments, as shown in Figure 8, the main circuit 100 is configured to generate a feedback voltage at a first node of the main circuit 100 based on a reference voltage received at the second end 102 of the main circuit, and the feedback voltage is equal to the reference voltage; the first node of the main circuit 100 is connected to the first end 202 of the voltage stabilization circuit.

[0095] In the embodiment of the present disclosure, the first node of the main circuit 100 is connected to the first end 202 of the voltage stabilizing circuit, which can effectively prevent the high-speed switching state of the main circuit 100 (the switch in the main circuit 100 is not shown) from affecting the second end 102 of the main circuit. After the circuit is stable, the feedback voltage of the first node of the main circuit 100 can be equal to the reference voltage of the second end 102 of the main circuit. Here, the first node of the main circuit can be an internal node of the main circuit. It should be noted that due to reasons such as the coupling capacitance inside the main circuit or the internal voltage fluctuation of the main circuit caused by external interference, the feedback voltage here is not necessarily completely equal to the reference voltage, but is approximately equal. Ideally, the feedback voltage is equal to the reference voltage.

[0096] It can be understood that the first node of the main circuit is connected to the first end 202 of the voltage stabilizing circuit (including direct connection and indirect connection), and the first voltage is provided by the main circuit 100. No additional first voltage generating circuit is required to generate the first voltage, which effectively utilizes existing resources, saves costs, and is more conducive to the miniaturization of the memory chip.

[0097] In some embodiments, as shown in FIG9 , the main circuit 100 includes:

[0098] an operational amplifier circuit 210 , wherein a first terminal 211 of the operational amplifier circuit 210 is configured to receive a reference voltage and provide a bias voltage to the current regulating circuit 220 ;

[0099] The current regulating circuit 220 , coupled to the operational amplifier circuit 210 , is configured to output a bias current from the first terminal 103 of the current regulating circuit 220 based on the bias voltage and the second voltage.

[0100] Specifically, the first terminal 211 of the operational amplifier circuit 210 may be the first terminal 101 of the main circuit, and is configured to receive a reference voltage; the second terminal 212 of the operational amplifier circuit 210 and the third terminal 222 of the current regulating circuit 220 are connected to the second terminal 203 of the voltage stabilizing circuit; the output terminal 213 of the operational amplifier circuit 210 is connected to the second terminal 221 of the current regulating circuit 220;

[0101] The operational amplifier circuit 210 is configured to provide a bias voltage to the current regulating circuit 220 . The current regulating circuit 220 is configured to output a bias current from the first terminal 103 of the current regulating circuit 220 based on the bias voltage and a second voltage.

[0102] In some embodiments, the operational amplifier circuit 210 may include but is not limited to a proportional operational amplifier, an adding operational amplifier, a subtracting operational amplifier, and combinations thereof. The operational amplifier 210 receives a reference voltage and outputs a bias voltage, where the bias voltage = g(reference voltage).

[0103] In the embodiment of the present disclosure, different bias voltages can be obtained by changing the type of operational amplifier in the operational amplifier circuit 210 and the type and size of the internal devices of the operational amplifier (including but not limited to transistors and resistors), thereby changing the size of the final bias current.

[0104] In some embodiments, as shown in FIG10 a , the first terminal 202 of the voltage stabilizing circuit is connected to the first terminal 211 of the operational amplifier circuit, and the first voltage is equal to the reference voltage; or, as shown in FIG10 b , the first terminal 202 of the voltage stabilizing circuit is connected to the feedback terminal 214 of the operational amplifier circuit, and the first voltage is equal to the feedback voltage of the feedback terminal 214 of the operational amplifier circuit.

[0105] In the embodiment of the present disclosure, the feedback terminal 214 of the operational amplifier circuit may be the first node of the main circuit.

[0106] In the embodiment of the present disclosure, the first terminal 211 of the operational amplifier circuit and the feedback terminal 214 of the operational amplifier circuit can be regarded as "virtual short", so the voltage at the first terminal 211 of the operational amplifier circuit and the feedback terminal 214 of the operational amplifier circuit 210 is the same.

[0107] It can be understood that since the high-speed switching state of the main circuit 100 (the switch in the main circuit 100 is not shown) will affect the reference voltage of the first end 211 of the operational amplifier circuit, thereby affecting the stability of the first voltage, the first end 202 of the voltage stabilizing circuit in the embodiment of the present disclosure is connected to the feedback end 214 of the operational amplifier circuit, and the feedback voltage of the feedback end 214 of the operational amplifier circuit is more stable than the reference voltage of the first end 211 of the operational amplifier circuit, thereby making the first voltage received by the voltage stabilizing circuit 200 more stable.

[0108] In some embodiments, the operational amplifier circuit 210 may include one or more operational amplifiers, and the output end of the previous stage operational amplifier may be used as the input end of the next stage operational amplifier to achieve multi-stage amplification and improve the operational amplifier capability of the operational amplifier circuit 210.

[0109] In some embodiments, as shown in FIG11 , the operational amplifier circuit 210 includes: a first P-type transistor 601 , a second P-type transistor 602 , a first N-type transistor 611 , a second N-type transistor 612 , a third P-type transistor 603 , and a second resistor 420 ;

[0110] The gate terminal of the first P-type transistor 601 is connected to the gate terminal of the second P-type transistor 602, the first terminal of the first P-type transistor 601, the first terminal of the second P-type transistor 602, and the first terminal of the third P-type transistor 603 are connected to the second terminal 203 of the voltage regulator circuit, the gate terminal of the second P-type transistor 602 is connected to the second terminal of the second P-type transistor 602, the first terminal of the first N-type transistor 611, the second terminal of the first P-type transistor 601, and the gate terminal of the third P-type transistor 603 are connected to the second terminal 221 of the current regulation circuit, the first terminal of the second N-type transistor 612 is connected to the second terminal of the second P-type transistor 602, the gate terminal of the first N-type transistor 611 is configured to receive a reference voltage, the gate terminal of the second N-type transistor 612, the first terminal of the second resistor 420, and the second terminal of the third P-type transistor 603 are connected, the second terminal of the second resistor 420 is connected to the ground terminal, the second terminal of the first N-type transistor 611 and the second terminal of the second N-type transistor 612 are connected to the first terminal of the third N-type transistor 613 and to the ground terminal.

[0111] The embodiment of the present disclosure may further include a third N-type transistor 613 , and the first N-type transistor 611 and the second N-type transistor 612 may be grounded through the third N-type transistor 613 .

[0112] In the embodiments of the present disclosure, the first terminal of each transistor may be a source or a drain, and the second terminal of each transistor may be a drain or a source. For example, when the first terminal of the first P-type transistor 601 is a drain, the second terminal of the first P-type transistor 601 is a source. For another example, when the first terminal of the first P-type transistor 601 is a source, the second terminal of the first P-type transistor 601 is a drain.

[0113] In the disclosed embodiment, the feedback terminal of the operational amplifier circuit 210 is "virtually shorted" to the first terminal of the operational amplifier circuit 210, and the feedback voltage at the feedback terminal of the operational amplifier circuit 210 is equal to the reference voltage at the first terminal of the operational amplifier circuit 210. It should be noted that due to factors such as coupling capacitance within the main circuit or internal voltage fluctuations caused by external interference in the main circuit, the feedback voltage may not be completely equal to the reference voltage, but it is approximately equal. Ideally, the feedback voltage is equal to the reference voltage. A second resistor 420 is located between the feedback terminal and the ground terminal, so the current in the second resistor 420 is equal to the reference voltage / the resistance of the second resistor 420. Since the third P-type transistor 603 and the second resistor 420 are located in the same branch, the current in the third P-type transistor 603 is the same as the current in the second resistor 420, thereby determining the gate voltage of the third P-type transistor 603 and the bias voltage output by the first-stage operational amplifier module.

[0114] In some embodiments, the second resistor 420 may be a variable resistor. By changing the resistance of the second resistor 420 , the current in the third P-type transistor 603 may be changed.

[0115] In some embodiments, the gate terminal of the first transistor 400 can be connected to the gate terminal of the first N-type transistor 611. In other embodiments, the gate terminal of the first transistor can be connected to the gate terminal of the second N-type transistor 612. Here, the gate terminal of the first transistor 400 can be directly connected to the gate terminal of the second N-type transistor 612, or the gate terminal of the first transistor 400 is connected to the first resistor 410 and indirectly connected to the gate terminal of the second N-type transistor 612. Specifically, the second end of the first resistor 410 and the gate terminal of the second N-type transistor 612 are both connected to the first node, and the voltage at the first node is the feedback voltage. In the embodiment of the present disclosure, the parameters of the first N-type transistor 611 and the second N-type transistor 612 are exactly the same, and the parameters of the first P-type transistor and the second P-type transistor are exactly the same. After the circuit is stable, the feedback voltage at the first node is equal to the reference voltage received by the gate terminal of the first N-type transistor 611.

[0116] In the disclosed embodiment, the gate terminal of the first transistor is connected to the gate terminal of the second N-type transistor 612, which can effectively prevent the high-speed switching state of the main circuit 100 (the switch in the main circuit 100 is not shown) from affecting the reference voltage at the gate terminal of the first N-type transistor 611. Because the feedback voltage at the gate terminal of the second N-type transistor 612 is more stable than the reference voltage at the gate terminal of the first N-type transistor 611, the first voltage received by the voltage stabilization circuit is more stable, and the second voltage received by the first terminal of the main circuit 100 is further stable.

[0117] In some embodiments, as shown in FIG11 , the current regulating circuit includes a second transistor 604 ;

[0118] A first terminal of the second transistor 604 is connected to the second terminal 203 of the voltage stabilizing circuit, a gate terminal of the second transistor 604 is connected to the output terminal of the operational amplifier circuit 210 , and a second terminal of the second transistor 604 is configured to output a bias current.

[0119] In some embodiments, the second transistor 604 may be a P-type transistor.

[0120] In some embodiments, the second transistor 604 can be a transistor that is exactly the same as the third P-type transistor 603. The exactly the same transistor here can mean that the second transistor 604 and the third P-type transistor 603 can be transistors from the same batch, or the second transistor 604 and the third P-type transistor 603 have exactly the same tube specifications and manufacturing processes.

[0121] When the second transistor 604 is identical to the third P-type transistor 603 , the second transistor 604 can “copy” the current on the third P-type transistor 603 , that is, the magnitude of the bias current outputted by the second end of the second transistor 604 is equal to the current at the second end of the third P-type transistor 603 .

[0122] In other embodiments, the channel width of the third P-type transistor 603 is M1, and the channel length is L1, and the channel width of the second transistor 604 is M2, and the channel length is L2, then the magnitude of the bias current output by the second end of the second transistor 604 = the current of the second end of the third P-type transistor 603 * (M2 / L2) / (M1 / L1). In some specific examples, the channel length L1 of the third P-type transistor 603 and the channel length L2 of the second transistor 604 can be the same length, because when the channel lengths are the same, the consistency of the device is better. The current can be scaled by adjusting the channel width between different transistors to output the target bias current.

[0123] In some embodiments, the current regulating circuit 220 may include N P-type transistors connected in series. The P-type transistors may be the same as the third P-type transistor. It is understood that the N P-type transistors connected in series amplify the current in the third P-type transistor 603 by N times. N is an integer greater than 1.

[0124] In some embodiments, as shown in FIG12 , the current regulating circuit 220 includes not only a first branch in which the second transistor 604 is located, but also a second branch in which a fifth P-type transistor 605 is located. The channel length L3 of the fifth P-type transistor 605 can be different from the channel length L2 of the second transistor 604. Alternatively, the fifth P-type transistor 605 includes M P-type transistors connected in series. It will be understood that the P-type transistors here can be the same transistor as the third P-type transistor. M is an integer greater than 1, and M is different from N.

[0125] These can output a specified target bias current by selectively turning on the transistors on a specified branch of the current regulating circuit 220.

[0126] The embodiment of the present disclosure enriches the adjustable range of the bias current by providing multiple branches on the current regulating circuit 220 .

[0127] The embodiment of the present disclosure further provides a memory, as shown in FIG13 , including a memory cell array 62 and a peripheral circuit 64 coupled to the memory cell array 62 , wherein the peripheral circuit 64 includes a current bias circuit as described in any of the above embodiments.

[0128] The memory 60 may include a memory cell array 62 and a peripheral circuit 64 coupled to the memory cell array 62. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 66, each NAND memory string 66 extending vertically above the substrate. In some embodiments, each NAND memory string 66 may include a plurality of memory cells coupled in series and stacked vertically. Each memory cell is configured to maintain a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the memory cell area. In addition, each memory cell in the above-mentioned memory cell array 62 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0129] In one embodiment of the present disclosure, the above-mentioned memory cell may be a single-level memory cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, the first storage state "0" may correspond to a first threshold voltage range, and the second storage state "1" may correspond to a second threshold voltage range. In other embodiments, each memory cell may be a multi-level memory cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to a range of possible nominal storage values. For example, if each MLC stores two bits of data, the MLC may be programmed to program the memory cell from an erased state to one of three possible programming levels by writing one of three possible nominal storage values ​​to the memory cell. Among them, the fourth nominal storage value may be used for the erased state.

[0130] In an embodiment of the present disclosure, the above-mentioned peripheral circuit can be coupled to the memory cell array through a bit line (BL), a word line (WL), a source (Source Line), a source select gate (SSG), and a drain select gate (DSG). Here, the peripheral circuit may include any suitable analog, digital, and mixed signal circuits for facilitating the relevant operations of the memory cell array by applying a voltage signal and / or a current signal to each target memory cell via a bit line, a word line, a source, an SSG, or a DSG, and sensing a voltage signal and / or a current signal from each target memory cell. In addition, the peripheral circuit may also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, as shown in FIG14 . The peripheral circuit 70 may include a page buffer (PB) / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a latch circuit 76, an interface 77, a data bus 78, and an input / output buffer 79, wherein the input / output buffer 79 includes a current bias circuit 80. It should be understood that the above-mentioned peripheral circuit 70 may be the same as the peripheral circuit 64 in Figure 13, and in some other embodiments, the peripheral circuit 70 may further include additional peripheral circuits not shown in Figure 14. In the embodiment of the present disclosure, the I / O system may include an interface 77 and an input / output buffer 79. The I / O system is configured to transmit data and commands between an external host and the memory cell array.

[0131] The page buffer / sense amplifier 71 can be configured to read data from the memory cell array and program (write) data to the memory cell array according to a control signal from the control logic unit 75. The column decoder / bit line driver 72 can be configured to be controlled by the control logic unit 75 and select one or more memory strings by applying a bit line voltage generated from the voltage generator 74. The row decoder / word line driver 73 can be configured to be controlled by the control logic unit 75 and select / deselect a memory block of the memory cell array and select / deselect a word line of the memory block. The row decoder / word line driver 73 can also be configured to drive the word line using the word line voltage generated from the voltage generator 74. The voltage generator 74 can be configured to be controlled by the control logic unit 75 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array. The control logic unit 75 can be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The latch circuit 76 can be coupled to the control logic unit 75 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 77 can be coupled to the control logic unit 75 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 75, as well as to buffer status information received from the control logic unit 75 and relay them to the host. The input / output buffer 79 can be coupled to the column decoder / bit line driver 72 and coupled to the interface 77 via the data bus 78 for buffering input / output data. In the embodiment of the present disclosure, the input / output buffer 79 can be connected to the interface 77, and the input / output buffer 79 interacts with the external host through the interface 77, including outputting data in the memory cell array to the external host, or storing data transmitted by the external host in the memory cell array. Specifically, data can be read from the memory cell array, cached in a page buffer, and then output to the input / output buffer 79 via the page buffer. The data is then output to the interface 77 via the input / output buffer 79 and further output to an external host. The input / output buffer 79 requires a stable bias voltage to stably input / output data. The input / output buffer 79 in the disclosed embodiment includes a current bias circuit 80, which provides a stable bias current to the input / output buffer 79. The current-voltage conversion circuit then provides a stable bias voltage to the input / output buffer 79, thereby enabling stable data input or output.

[0132] It should be understood that the current bias circuit in the embodiment of the present disclosure is not limited to being used in the input / output buffer 79 in the peripheral circuit. Any component in the peripheral circuit that requires a stable bias current can adopt the current bias circuit provided by the present disclosure. For example, it can also be applied to the Verify Failbit Count (VFC) circuit.

[0133] The present disclosure also provides another memory, as shown in FIG15 , including a memory cell array 62 and a peripheral circuit 70 coupled to the memory cell array 62. The peripheral circuit 70 includes:

[0134] The first transistor 400 is configured to output a second voltage through a first terminal of the first transistor 400 based on a first voltage received at a gate terminal of the first transistor 400 ;

[0135] The main circuit 100 has a first terminal 101 coupled to a first terminal of the first transistor 400 . The main circuit 100 is configured to generate a bias current based on a second voltage outputted from the first terminal of the first transistor 400 .

[0136] Specifically, the gate terminal of the first transistor 400 is configured to receive a first voltage, and the first terminal of the first transistor 400 is connected to the first terminal 101 of the main circuit 100; the first transistor 400 is configured to provide a second voltage to the first terminal 101 of the main circuit based on the first voltage; the main circuit 100 is configured to generate a bias current based on the second voltage.

[0137] The second end of the first transistor 400 is connected to the external power supply, and the first voltage received by the gate end of the first transistor 400 is less than the third voltage provided by the external power supply. This ensures that the first transistor 400 is in a just-turned-on state, so that the first transistor 400 can act as a clamp. At this time, the voltage at the first end of the first transistor 400, that is, the second voltage, is equal to the first voltage minus the threshold voltage of the first transistor 400.

[0138] The first transistor 400 includes but is not limited to an enhancement-type N-type transistor or a depletion-type N-type transistor.

[0139] In the disclosed embodiment, the peripheral circuit 70 includes an input / output buffer 79, which includes a current bias circuit 80. The current bias circuit 80 includes a first transistor 400 and a main circuit 100. The current bias circuit 80 can provide a stable bias current for the input / output buffer 79, which then passes through the current-to-voltage conversion circuit in the input / output buffer to provide a bias voltage for the input / output buffer. It is understood that the first transistor 400 and the main circuit 100 can also provide a stable bias current for other circuits in the peripheral circuit that require a bias current.

[0140] In the disclosed embodiment, the second voltage required by the main circuit is primarily determined by the first voltage and the threshold voltage of the first transistor 400, thereby filtering out power supply noise on the third voltage and ensuring a relatively stable bias current provided by the first transistor 400 and the main circuit 100. Furthermore, the area of ​​the memory chip occupied by the first transistor 400 is very small, effectively saving memory chip area and facilitating miniaturization of the memory chip.

[0141] In some embodiments, the peripheral circuit further includes: a first resistor; a first end of the first resistor is connected to the gate end of the first transistor.

[0142] In some embodiments, the second end of the first resistor is configured to receive a first voltage, and the first end of the first resistor is connected to the gate terminal of the first transistor to transfer the first voltage to the gate terminal of the first transistor.

[0143] The embodiment of the present disclosure compensates for the loop stability loss caused by parasitic capacitance by providing a first resistor at the second end of the clamping circuit, thereby improving the stability of the circuit.

[0144] In some embodiments, the first transistor comprises a depletion-mode N-type transistor.

[0145] In some embodiments, the main circuit is configured to generate a feedback voltage at a first node of the main circuit based on a reference voltage received at a second end of the main circuit, and the feedback voltage is equal to the reference voltage; the second end of the first resistor is connected to the first node of the main circuit.

[0146] In some embodiments, the main circuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third P-type transistor, a second resistor, and a second transistor;

[0147] The gate terminal of the first P-type transistor is connected to the gate terminal of the second P-type transistor, the first end of the first P-type transistor, the first end of the second P-type transistor, the first end of the third P-type transistor, and the first end of the second transistor are connected to the first end of the first transistor, the gate terminal of the second P-type transistor is connected to the second end of the second P-type transistor, the first end of the first N-type transistor, the second end of the first P-type transistor, and the gate terminal of the third P-type transistor are connected to the gate terminal of the second transistor, the first end of the second N-type transistor is connected to the second end of the second P-type transistor, the gate terminal of the first N-type transistor is configured to receive a reference voltage, the gate terminal of the second N-type transistor, the first end of the second resistor, and the second end of the third P-type transistor are connected, the second end of the second resistor is connected to the ground terminal, the second end of the first N-type transistor and the second end of the second N-type transistor are connected to the ground terminal; the second end of the second transistor outputs a bias current.

[0148] In some embodiments, the main circuit is further configured to provide the first voltage to the gate terminal of the first transistor; the gate terminal of the first N-type transistor is connected to the gate terminal of the first transistor, or the gate terminal of the second N-type transistor is connected to the gate terminal of the first transistor.

[0149] Since the gate terminals of the first N-type transistor and the second N-type transistor are "virtually shorted", the voltage at the gate terminal of the second N-type transistor follows the voltage at the gate terminal of the first N-type transistor. In the embodiment of the present disclosure, the voltage at the gate terminal of the first N-type transistor can be a reference voltage.

[0150] In this way, the first voltage received by the first transistor comes from the main circuit, and no additional first voltage generating circuit is required to generate the first voltage, which is more conducive to the miniaturization of the memory chip.

[0151] In some embodiments, the gate terminal of the first transistor is connected to the gate terminal of the second N-type transistor, which can effectively prevent the high-speed switching state of the main circuit (the switch in the main circuit is not shown) from affecting the reference voltage at the gate terminal of the first N-type transistor. The feedback voltage at the gate terminal of the second N-type transistor is more stable than the reference voltage at the gate terminal of the first N-type transistor, thereby making the first voltage received by the voltage stabilization circuit more stable.

[0152] In some embodiments, the memory provided by the embodiments of the present disclosure includes, but is not limited to, two-dimensional memory (e.g., two-dimensional NAND memory) and three-dimensional memory (e.g., three-dimensional NAND memory). Memory types include, but are not limited to, flash memory, ferroelectric random access memory, magnetic random access memory, phase change random access memory, and resistive random access memory.

[0153] An embodiment of the present disclosure further provides a memory system, comprising the memory according to any one of the above embodiments, and a memory controller coupled to and controlling the memory.

[0154] In some embodiments, the memory system includes but is not limited to a memory card or a solid state drive (SSD).

[0155] The memory and the memory system are further described below with reference to the accompanying drawings.

[0156] As shown in FIG16 , system 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. System 700 may include a host 704 and a memory system 701. Memory system 701 includes one or more memories 702 and a memory controller 703. Host 704 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. Host 704 may be configured to send data to or receive data from memory 702.

[0157] The memory controller 703 and one or more memories 702 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 701 can be implemented and packaged into different types of terminal electronic products. In an example as shown in Figure 17, the memory controller 703 and a single memory 702 can be integrated into a memory card 801. The memory card 801 may include a PC card (Personal Computer Memory Card International Association, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 801 may also include a memory card connector 802 that couples the memory card 801 to a host. 18 , the memory controller 703 and the plurality of memories 702 may be integrated into an SSD 803. The SSD 803 may also include an SSD connector 804 that couples the SSD 803 with a host.

[0158] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0159] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0160] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A current bias circuit, comprising: a voltage stabilizing circuit configured to output a second voltage through a second terminal of the voltage stabilizing circuit based on a first voltage received at a first terminal of the voltage stabilizing circuit; A main body circuit, wherein a first end of the main body circuit is coupled to a second end of the voltage stabilizing circuit, and the main body circuit is configured to receive a second voltage outputted by the second end of the voltage stabilizing circuit to generate a bias current.

2. The current bias circuit according to claim 1, wherein: The voltage stabilizing circuit includes a clamp circuit configured to provide the second voltage to a first end of the main circuit based on a voltage drop between the first voltage and the clamp circuit.

3. The current bias circuit according to claim 2, wherein: The clamp circuit includes a first transistor, and the clamp circuit is configured to provide the second voltage to a first terminal of the body circuit based on the first voltage and a threshold voltage of the first transistor.

4. The current bias circuit according to claim 1, wherein: The third terminal of the voltage stabilizing circuit is configured to receive a third voltage, and the third voltage is greater than the first voltage.

5. The current bias circuit according to claim 3, wherein: The first transistor comprises a depletion-type N-type transistor.

6. The current bias circuit according to claim 2, wherein: The voltage stabilization circuit further includes a first resistor coupled to the clamping circuit.

7. The current bias circuit according to claim 6, wherein: The resistance value of the first resistor is related to the magnitude of loop stability loss caused by the parasitic capacitance of the voltage stabilization circuit.

8. The current bias circuit according to claim 6, wherein: The resistance of the first resistor is greater than or equal to 1 kΩ and less than or equal to 100 kΩ.

9. The current bias circuit according to claim 1, wherein: The main body circuit is configured to provide the first voltage to the first terminal of the voltage regulating circuit based on a reference voltage received at the second terminal of the main body circuit.

10. The current bias circuit according to claim 1, wherein: The main circuit is configured to generate a feedback voltage at a first node of the main circuit based on a reference voltage received at a second end of the main circuit, wherein the feedback voltage is equal to the reference voltage; the first node of the main circuit is connected to a first end of the voltage stabilizing circuit.

11. The current bias circuit according to claim 9, wherein: The main circuit comprises: an operational amplifier circuit, wherein a first terminal of the operational amplifier circuit is configured to receive the reference voltage and provide a bias voltage to the current regulating circuit; The current regulating circuit is coupled to the operational amplifier circuit and is configured to output a bias current from a first terminal of the current regulating circuit based on the bias voltage and the second voltage.

12. The current bias circuit according to claim 11, wherein: The first end of the voltage stabilizing circuit is connected to the second end of the operational amplifier circuit; or, the first end of the voltage stabilizing circuit is connected to the feedback end of the operational amplifier circuit.

13. The current bias circuit according to claim 11, wherein: The operational amplifier circuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a third P-type transistor and a second resistor; The gate terminal of the first P-type transistor is connected to the gate terminal of the second P-type transistor, the first end of the first P-type transistor, the first end of the second P-type transistor and the first end of the third P-type transistor are connected to the second end of the voltage stabilizing circuit, the gate terminal of the second P-type transistor is connected to the second end of the second P-type transistor, the first end of the first N-type transistor, the second end of the first P-type transistor and the gate terminal of the third P-type transistor are connected to the second end of the current regulating circuit, the first end of the second N-type transistor is connected to the second end of the second P-type transistor, the gate terminal of the first N-type transistor is configured to receive the reference voltage, the gate terminal of the second N-type transistor and the first end of the second resistor are connected to the second end of the third P-type transistor, the second end of the second resistor is connected to the ground terminal, the second end of the first N-type transistor and the second end of the second N-type transistor are connected to the first end of the third N-type transistor, and the second end of the third N-type transistor is connected to the ground terminal.

14. The current bias circuit according to claim 11, wherein: The current regulating circuit includes a second transistor; The first end of the second transistor is connected to the second end of the voltage stabilizing circuit, the gate end of the second transistor is connected to the output end of the operational amplifier circuit, and the second end of the second transistor is configured to output the bias current. 15 . A memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit comprises the current bias circuit according to claim 1 .

16. A memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising: a first transistor configured to output a second voltage through a first terminal of the first transistor based on a first voltage received at a gate terminal of the first transistor; A main circuit has a first terminal coupled to the first terminal of the first transistor, and is configured to generate a bias current based on a second voltage output by the first terminal of the first transistor.

17. The memory according to claim 16, wherein: The peripheral circuit further includes: a first resistor, a first end of the first resistor is connected to the gate end of the first transistor.

18. The memory according to claim 16, wherein: The first transistor comprises a depletion-type N-type transistor.

19. The memory according to claim 17, wherein: The main circuit is configured to generate a feedback voltage at a first node of the main circuit based on a reference voltage received at a second end of the main circuit, wherein the feedback voltage is equal to the reference voltage; the second end of the first resistor is connected to the first node of the main circuit.

20. The memory according to claim 16, wherein: The main circuit includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third P-type transistor, a second resistor and a second transistor; The gate terminal of the first P-type transistor is connected to the gate terminal of the second P-type transistor, the first terminal of the first P-type transistor, the first terminal of the second P-type transistor, the first terminal of the third P-type transistor, and the first terminal of the second transistor are connected to the first terminal of the first transistor, The gate terminal of the second P-type transistor is connected to the second terminal of the second P-type transistor, the first terminal of the first N-type transistor, the second terminal of the first P-type transistor and the gate terminal of the third P-type transistor are connected to the gate terminal of the second transistor, the first terminal of the second N-type transistor is connected to the second terminal of the second P-type transistor, the gate terminal of the first N-type transistor is configured to receive a reference voltage, the gate terminal of the second N-type transistor, the first terminal of the second resistor are connected to the second terminal of the third P-type transistor, the second terminal of the second resistor is connected to the ground terminal, the second terminal of the first N-type transistor and the second terminal of the second N-type transistor are connected to the ground terminal; the second terminal of the second transistor outputs the bias current.

21. The memory according to claim 20, wherein: The gate terminal of the first N-type transistor is connected to the gate terminal of the first transistor, or the gate terminal of the second N-type transistor is connected to the gate terminal of the first transistor.

22. A memory system, comprising the memory according to any one of claims 16 to 21, and a memory controller coupled to the memory and controlling the memory.

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